Apparatus and method for split gate NROM memory Number:6,979,857 from the United States Patent and Trademark Office (PTO) owispatent

Title: Apparatus and method for split gate NROM memory

Abstract: A split gate, vertical NROM memory cell is comprised of a plurality of oxide pillars that each has a source/drain region formed in the top of the pillar. A trench is formed between each pair of oxide pillars. A polysilicon control gate is formed in the trench between the pair of oxide pillars. A polysilicon program gate is formed between the control gate and each oxide pillar. The program gates extend along the sidewall of each oxide pillar. A gate insulator layer is formed between each program gate and the adjacent oxide pillar. Each gate insulator layer has a structure for trapping at least one charge. In one embodiment, the gate insulator structure is an oxide-nitride-oxide layer in which the charge is stored at the trench bottom end of the nitride layer. An interpoly insulator is formed between the program gates and the control gate.

Patent Number: 6,979,857 Issued on 12/27/2005 to Forbes

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Inventors:	Forbes; Leonard (Corvallis, OR)
Assignee:	Micron Technology, Inc. (Boise, ID)
Appl. No.:	719772
Filed:	November 21, 2003

Current U.S. Class:	257/314; 257/315; 257/316; 257/317; 257/318; 438/259
Intern'l Class:	H01L 029/76; H01L 029/94; H01L 031/06.2; H01L 031/11.3; H01L 031/11.9
Field of Search:	257/314-326

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References Cited [Referenced By]

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U.S. Patent Documents

4184207	Jan., 1980	McElroy.
4420504	Dec., 1983	Cooper.
4755864	Jul., 1988	Ariizumi.
4881114	Nov., 1989	Mohsen.
4964080	Oct., 1990	Tzeng.
5241496	Aug., 1993	Lowrey.
5330930	Jul., 1994	Chi.
5378647	Jan., 1995	Hong.
5379253	Jan., 1995	Bergemont.
5397725	Mar., 1995	Wolstenholme.
5467305	Nov., 1995	Bertin.
5467308	Nov., 1995	Chang et al.
5576236	Nov., 1996	Chang.
5768192	Jun., 1998	Eitan.
5792697	Aug., 1998	Wen.
5858841	Jan., 1999	Hsu.
5911106	Jun., 1999	Tasaka.
5936274	Aug., 1999	Forbes.
5946558	Aug., 1999	Hsu.
5966603	Oct., 1999	Eitan.
5969384	Oct., 1999	Hong.
5994745	Nov., 1999	Hong.
6011725	Jan., 2000	Eitan.
6028342	Feb., 2000	Chang.
6030871	Feb., 2000	Eitan.
6044022	Mar., 2000	Nachumovsky.
6069042	May., 2000	Chien et al.
6081456	Jun., 2000	Dadashev.
6108240	Aug., 2000	Lavi.
6133102	Oct., 2000	Wu.
6134156	Oct., 2000	Eitan.
6143636	Nov., 2000	Forbes.
6147904	Nov., 2000	Liron.
6157570	Dec., 2000	Nachumovsky.
6172396	Jan., 2001	Chang.
6174758	Jan., 2001	Nachumovsky.
6175523	Jan., 2001	Yang.
6181597	Jan., 2001	Nachumovsky.
6184089	Feb., 2001	Chang.
6191459	Feb., 2001	Hofmann et al.
6201282	Mar., 2001	Eitan.
6201737	Mar., 2001	Hollmer.
6204529	Mar., 2001	Lung.
6207504	Mar., 2001	Hsieh.
6207992	Mar., 2001	Mori.
6208164	Mar., 2001	Noble.
6208557	Mar., 2001	Bergemont.
6215702	Apr., 2001	Derhacobian.
6218695	Apr., 2001	Nachumovsky.
6222768	Apr., 2001	Hollmer.
6238976	May., 2001	Noble.
6240020	May., 2001	Yang.
6243300	Jun., 2001	Sunkavalli.
6249460	Jun., 2001	Forbes.
6251731	Jun., 2001	Wu.
6255166	Jul., 2001	Ogura.
6256231	Jul., 2001	Lavi.
6266281	Jul., 2001	Derhacobian.
6269023	Jul., 2001	Derhacobian.
6272043	Aug., 2001	Hollmer.
6275414	Aug., 2001	Randolph.
6282118	Aug., 2001	Lung.
6291854	Sep., 2001	Peng.
6297096	Oct., 2001	Boaz.
6303436	Oct., 2001	Sung.
6327174	Dec., 2001	Jung.
6337808	Jan., 2002	Forbes.
6348711	Feb., 2002	Eitan.
6383871	May., 2002	Noble.
6384448	May., 2002	Forbes.
6392930	May., 2002	Jung.
6417049	Jul., 2002	Sung.
6417053	Jul., 2002	Kuo.
6421275	Jul., 2002	Chen.
6424001	Jul., 2002	Forbes.
6429063	Aug., 2002	Eitan.
6432778	Aug., 2002	Lai.
6433382	Aug., 2002	Orlowski et al.
6436764	Aug., 2002	Hsieh.
6440801	Aug., 2002	Furukawa et al.
6461949	Oct., 2002	Chang.
6462378	Oct., 2002	Kim.
6462387	Oct., 2002	Lai.
6468864	Oct., 2002	Sung.
6469342	Oct., 2002	Kuo .
6477084	Nov., 2002	Eitan.
6486028	Nov., 2002	Chang.
6487050	Nov., 2002	Liu.
6496034	Dec., 2002	Forbes.
6498377	Dec., 2002	Lin.
6514831	Feb., 2003	Liu.
6531887	Mar., 2003	Sun.
6545309	Apr., 2003	Kuo.
6552287	Apr., 2003	Janniere.
6559013	May., 2003	Pan.
6570213	May., 2003	Wu.
6576511	Jun., 2003	Pan.
6580135	Jun., 2003	Chen.
6580630	Jun., 2003	Liu.
6597037	Jul., 2003	Forbes.
6602805	Aug., 2003	Chang.
6607957	Aug., 2003	Fan.
6610586	Aug., 2003	Liu.
6613632	Sep., 2003	Liu.
6617204	Sep., 2003	Sung.
6639268	Oct., 2003	Forbes.
6762092	Jul., 2004	Yuan et al.
2001/0001075	May., 2001	Ngo.
2001/0004332	Jun., 2001	Eitan.
2001/0011755	Aug., 2001	Tasaka.
2001/0022375	Sep., 2001	Hsieh.
2002/0130356	Sep., 2002	Sung.
2002/0142569	Oct., 2002	Chang.
2002/0146885	Oct., 2002	Chen.
2002/0151138	Oct., 2002	Liu.
2002/0177275	Nov., 2002	Liu.
2002/0182829	Dec., 2002	Chen.
2003/0015752	Jan., 2003	Palm.
2003/0057997	Mar., 2003	Sun.
2003/0067807	Apr., 2003	Lin.
2003/0113969	Jun., 2003	Cho.
2003/0117861	Jun., 2003	Maayan.
2003/0146565	Aug., 2003	Wu.
Foreign Patent Documents
84303740.9	Jan., 1985	EP.
90115805.5	Feb., 1991	EP.
01113179.4	Dec., 2002	EP.

Other References

B. Eitan et al., "Characterization of Channel Hot Electron Injection by the Subthreshold Slope of NROM™ Device," IEEE Electron Devices Lett., vol. 22, No. 11, (Nov. 2001) pp. 556-558, Copyright 2001 IEEE. B. Eitan et al., "Spatial Characterization of Hot Carriers Injected into the Gate Dielectric Stack of a MOFSET Based on Non-Volatile Memory Device," date unknown, pp. 58-60. B. Eitan et al., "NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell," IEEE Electron Device Lett, vol. 21, No. 11, (Nov. 2000), pp. 543-545, Copyright 2000 IEEE. E. Maayan et al., "A 512Mb NROM Flash Data Storage Memory with 8MB/s Data Range," Dig. IEEE Int. Solid-State Circuits Conf., San Francisco, (Feb. 2002), pp. 1-8, Copyright Saifun Semiconductors Ltd. 2002. E. Maayan et al., "A 512Mb NROM Flash Data Storage Memory with 8MB/s Data Range," ISSCC 2002 Visuals Supplement, Session 6, SRAM and Non-Volatile Memories, 6.1 and 6.2, pp. 76-77, 407-408. Copyright 1990 IEEE. M. Janai, "Data Retention, Endurance and Acceleration Factors of NROM Devices," IEEE 41st Annual International Reliability Physics Symposium, Dallas, TX (2003), pp. 502-505, Copyright 1989 IEEE. S. Minami and Y. Kamigaki, "A Novel MONOS Nonvolatile Memory Device Ensuring 10-Year Data Retention after 107 Erase/Write Cycles," IEEE Transactions on Electron Devices, vol. 40, No. 11 (Nov. 1993) pp. 2011-2017, Copyright 1998 IEEE. C. Pan, K. Wu, P. Freiberger, A. Chatterjee, G. Sery, "A Scaling Methodology for Oxide Nitride-Oxide Interpoly Dielectric for EPROM Applications," IEEE Transactions on Electron Devices, vol. 37, No. 6, (Jun. 1990), pp. 1439-1443, Copyright 1990 IEEE. P. Manos and C. Hart, "A Self-Aligned EPROM Structure with Superior Data Retention," IEEE Electron Device Letters, vol. 11, No. 7, (Jul. 1990) pp. 309-311, Copyright 1990 IEEE. W. Owen and W. Tchon, "E2PROM Product Issues and Technology Trends," IEEE 1989, pp. 17-19, Copyright 1989 IEEE. T. Huang, F. Jong, T. Chao, H. Lin, L. Leu, K. Young, C. Lin, K. Chiu, "Improving Radiation Hardness of EEPROM/Flash Cell BY N2O Annealing," IEEE Electron Device Letters, vol. 19, No. 7 (Jul. 1998), pp. 256-258, Copyright 1998 IEEE. B. Eitan et al., "Electrons Retention Model for Localized Charge in Oxide-Nitride-Oxide (ONO) Dielectric," IEEE Device Lett., vol. 23, No. 9, (Sep. 2002), pp. 556-558. Copyright 2002 IEEE. T. Nozaki, T. Tanaka, Y. Kijiya, E. Kinoshita, T. Tsuchiya, Y. Hayashi, "A 1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application," IEEE Journal of Solid-State Circuits, vol. 26, No. 4 (Apr. 1991), pp. 497-501, Copyright 1991 IEEE. F. Vollebregt, R. Cuppens, F. Druyts, G. Lemmen, F. Verberne, J. Solo, "A New E(E)PROM Technology With A TiSi2 Control Gate," IEEE 1989, pp. 25.8.1-25.8.4, Copyright 1989 IEEE. B. Eitan et al., "Impact of Programming Charge Distribution on Threshold Voltage and Subthreshold Slope of NROM Memory cells," IEEE Transactions on Electron Devices, vol. 49, No. 11, (Nov. 2002), pp. 1939-1946, Copyright 2002 IEEE. B. Eitan et al., "Spatial characterization of Channel hot electron injection utilizing subthreshold slope of the localized charge storage NORM™ memory device," Non-Volatile Semiconductor Memory Workshop (NVSMW), Monterey, CA, (Aug. 2001), pp. 1-2. B. Eitan et al., "Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?" Int. Conf. on Solid State Devices and Materials, Tokyo, (1999), pp. 1-3, Copyright 1999 Saifun Semiconductors Ltd. S. Ogura, et al. "Twin MONOS Cell with Dual Control Gates," Halo LSI and New Halo, pp 187-187.3, Date Unknown. T. Sugizaki, et al. "New 2-bit/Tr MONOS Type Flash Memory using AI2O3 as Charge Trapping Layer," Fujitsu Laboratories Ltd, Date Unknown. T. Saito, et al. "Hot Hole Erase Characteristics and Reliability in Twin MONOS Device" Halo LSI, Date Unknown. Saifun Semiconductors, LTD. PowerPoint Presentation, Date Unknown. Y. Roizin, et al. "Novel Techniques for data retention and Leff measurements in two bit MicroFlash® Memory Cells," Characterization and Metrology for ULSI Technology: 200 International Conf., pp. 181-185, Copyright 2001 American Institute of Physics, 1-56396-967-X/01. W. J. Tsai, et al. "Cause of Data Retention Loss in a Nitride-Based Localized Trapping Storage Flassh Memory Cell," IEEE 40th Annual International Reliability Physics Symposium, Dallas, (2002), pp. 34-38. Copyright 2002 IEEE. W.J. Tsai, et al. "Data Retention Behavior of a SONOS Type Two-Bit Storage Flash Memory Cell," IEDM 01-1079-01-722, Copyright 2001 IEEE. A. Shappir, et al., "Subtreshold slope degradation model for localized-charge-trapping based non-volatile memory devices," Solid-State Electronics 47 (2003), pp. 937-941. Copyright 2003 Elsevier Science Ltd. R. Neale, "AMD's MirrorBit—a big step in Flash progress," Electronic Engineering Design, V. 74, No. 906, pp. 47-50. I. Bloom, et al., "NROM™—a new technology for non-volatile memory products" Solid-State Electronics 46 (2002), pp. 1757-1763. Copyright 2002 Elsevier Science Ltd. J. Bu and M. White, "Electrical characterization on ONO triple dielectric in SONOS nonvolatile memory devices," Solid-State Electronics 45 (2001) pp. 47-51. Copyright 2001 Elsevier Science Ltd. Y. Kamigaki and S. Minami, "MNOS Nonvolatile Semiconductor Memory Technology: Present and Future," IEICE Trans. Electron, vol. E84-C, No. 6, pp. 713-723 (Jun. 2001). E. Lusky, et al., "Electron Discharge Model of Locally-Trapped Charge in Oxide-Nitride-Oxide (ONO) Gates for NROM™ Non-Volatile Semiconductor Memory Devices," Extended Abstracts of the 2001 International Conference on Solid State Devices and Materials, Tokyo, 2001 pp. 534-535. A. Nughin, "n-Channel 256kb and 1Mb EEPROMs" ISSCC91, Session 134, Special Session on Technology in the USSR, Paper 13.4, 1991 IEEE InternationalSolid State Circuits Conference, Digest of Technical Papers, pp. 228-229, 319. G. Xue, et al., "Low Voltage Low Cost Nitride Embedded Flash Memory Cell" IMEC., Date Unknown. L. Breuil, et al., "A new 2 isolated-bits/cell flash memory device with self aligned split gate structure using ONO stacks for charge storage," IMEC, Date Unknown. J. Willer, et al., "UMEM: A U-shape Non-Volatile-Memory Cell," Ingentix GmbH &Co. KG., Infineon Technologies and Saifun Semiconductors, Date Unknown. S. Kang, et al., "A Study of SONOS Nonvolatile Memory Cell Controlled Structurally by Localizing Charge-Trapping Layer," Samsung Electrons Co., Ltd., Date Unknown. Y. Roizin, et al., "In-Process Charging in microFLASH® Memory Cells," Tower Semiconductor, Ltd., Date Unknown. A. Shappir, et al., "Subthreshold slope degradation model for localized-charge-trapping based non-volatile memory devices," Solid State Electronics, 47 (2003) pp. 937-941, Copyright 2003 Elsevier Science Ltd. I. Fujiwara, et al., "High speed program/erase sub 100 nm MONOS memory cell," Sony Corporation, Date Unknown. E. Lusky, et al., "Investigation of Spatial Distribution of CHE Injection Utilizing the Subthreshold Slope and the Gate Induced Drain Leakage (GIDL) Characteristics of the NROM™ Device," Saifun Semiconductors, Ltd. and Tel Aviv University, Dept of Physical Electronics, pp. 1-2., Date Unknown. C. C. Yeh, et al., "A Modified Read Scheme to Improve Read Disturb and Second Bit Effect in a Sealed MXVAND Flash Memory Cell," Macronix International Co., Ltd. and Department of Electronics Engineering, National Chiao-Tung University, Date Unknown. Y. K. Lee, et al., "30-nm Twin Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) Memory (TSM) with High Erase Speed and Reliability," School of Electrical Engineering, Seoul National University, C&M, System LSI, ATD, PD, Samsung Electronics Co., Date Unknown. J. H. Kim, et al., "Highly Manufacturable SONOS Non-Volatile Memory for the Embedded SoC Solution," 2003 Symposium on VLSI Technology Digest of Technical Papers, pp. 31-32. Y. Hayashi, et al., "Twin MONOS Cells with Dual Control Gates," 2000 Symposium on VLSI Technology Digest of Technical Papers, 2000 IEEE, pp. 122-123. M. K. Cho and D. M. Kim, "High Performance SONOS Memory Cells Free of Drain Turn-On and Over-Erase: Compatibility Issue with Current Flash Technology," IEEE Electron Device Letters, vol. 21, No. 8, Aug. 2000, pp. 399-401, Copyright 2000 IEEE. T. Y. Chan, K.K. Young and C. Hu, "A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device," IEEE Electron Device Letters, vol. EDL-8, No. 3, Mar. 1987, pp. 93-95., Copyright 1987 IEEE. I. Bloom, et al., "NROM™ NVM technology for Multi-Media Applications," Saifun Semiconductors, Ltd. Ingentix, Ltd. and Infineon Technologies, Date Unknown. E. J. Prinz, et al., "An Embedded 90nm SONOS Flash EEPROM Utilizing Hot Electron Injection Programming and 2-Sided Hot Hole Injection Erase," Motorola Embedded Memory. Center, Date Unknown. Y. Roizin, et al., "Retention Characteristics of microFLASH® Memory (Activation Energy of Traps in the ONO Stack)," Tower Semiconductor, Ltd., Date Unknown. Y. Roizin, et al., "Activation Energy of Traps in the ONO Stack of microFLASH® Memory Cells," Tower Semiconductor, Ltd., Date Unknown. Y. Roizin, et al., "'Dummy' Gox for Optimization of microFLASH® Technology," Tower Semiconductor, Ltd., Date Unknown. Y. K. Lee, et al., "Multi-Level Vertical Channel SONOS Nonvolatile Memory on SOI," 2002 Symposium on VLSI Technology Digest of Technical Papers, Copyright 2002 IEEE. T. Saito, et al., "CHE Program Behavior in MONOS Device," Halo LSI., Date Unknown. J. Bu, et al., "Retention Reliability Enhanced SONOS NVSM with Scaled Programming Voltage," Microelectronics Lab., Date Unknown. H. Tomiye, et al., "A novel 2-bit/cell MONOS memory device with a wrapped-control-gate structure that applies source-side hot-electron injection," 2002 Symposium on VLSI Technology Digest of Technical Papers, Copyright 2002 IEEE. Certified Translation, "Flash cell that seeks to replace current technology introduced enabling both low cost and high performance" Nikkei Microdevices, Nov. 1999, pp. 147-148. Cappelletti, P., et al., "Failure mechanisms of Flash Cell in Program/Erase Cycling", IEEE, 1994, IEDM-94, pp. 291-294. Guan Huinan, et al., "On Scaling of SST Split-Gate Flash Memory Technologies", Department of Electrical and Computer Engineering, University of California, Irvine, Final Report 1998-1999 for MICRO Project 98-080. Pavan, Paolo, et al., "Flash Memory Cells—An Overview", Proceedings of the IEEE, vol. 85, No. 8, Aug. 1997, pp. 1248-1271. Seo, Jin-ho, et al., "Charge-to-Breakdown Characteristics of Thin Gate Oxide and Buried Oxide on SIMOX SOI Wafers", Journal of the Electrochemical Society, vol. 144, No. 1, Jan. 1997, pp. 375-378.

Primary Examiner: Thomas; Tom
Assistant Examiner: Fenty; Jesse A.
Attorney, Agent or Firm: Leffert Jay & Polglaze, P.A.

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Parent Case Text

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RELATED APPLICATIONS

This application is a continuation-in-part of U.S. patent application Ser. No. 10/612,725 filed on Jul. 1, 2003.

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Claims

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1. A vertical NROM memory cell comprising:

a plurality of oxide pillars each having a source/drain region formed at the top, a trench being formed between each pair of oxide pillars;

a control gate formed between each pair of oxide pillars;

a plurality of program gates, each formed between the control gate and each oxide pillar, each program gate extending along the oxide pillar sidewall; and

a plurality of gate insulator layers, each gate insulator layer formed between each program gate and the adjacent oxide pillar, each gate insulator layer having a structure for trapping at least one charge.

2. The memory cell of claim 1 wherein the plurality of gate insulators are comprised of a composite oxide-nitride-oxide structure such that the nitride layer the charge trapping structure.

3. The memory cell of claim 1 and further including a silicon oxide gate insulator formed between the control gate and the adjacent program gates and along the bottom of the trench.

4. The memory cell of claim 1 wherein each gate insulator layer is a composite layer comprised of one of an oxide-nitride-aluminum oxide composite layer, an oxide-aluminum oxide-oxide composite layer, or an oxide-silicon oxycarbide-oxide composite layer.

5. The memory cell of claim 1 wherein each gate insulator layer is a non-composite layer comprised of one of silicon oxides formed by wet oxidation and not annealed, silicon-rich oxides with inclusions of nanoparticles of silicon, silicon oxynitride layers, silicon-rich aluminum oxide insulators, silicon oxycarbide insulators, or silicon oxide insulators with inclusions of nanoparticles of silicon carbide.

6. The memory cell of claim 1 wherein each gate insulator is comprised of non-stoichiometric single layers of two or more of silicon, nitrogen, aluminum, titanium, tantalum, hafnium, lanthanum, or zirconium.

7. A vertical NROM memory cell comprising:

a plurality of oxide pillars each having a source/drain region formed at the top, a trench being formed between each pair of oxide pillars;

a control gate formed between each pair of oxide pillars;

a plurality of program gates, each formed between the control gate and each oxide pillar, each program gate extending along the oxide pillar sidewall;

a plurality of gate insulator layers, each gate insulator layer formed between each program gate and the adjacent oxide pillar sidewall, each gate insulator layer having a structure for trapping at least one charge; and

an oxide interpoly layer formed between the control gate and each adjacent program gate.

8. The memory cell of claim 7 and further including a gate insulator layer formed on the bottom of the trench such that a plurality of charges can be trapped under the control gate in the gate insulator layer.

9. The memory cell of claim 8 wherein the plurality of charges are trapped in a nitride layer of the gate insulator layer under the control gate.

10. An array of vertical NROM memory cells comprising:

a plurality of oxide pillars each having a source/drain region formed at the top, a trench being formed between each pair of oxide pillars;

a plurality of control gates, each control gate formed in the trench between each pair of oxide pillars;

a plurality of program gates, each formed in the trench between a first control gate and each oxide pillar, each program gate extending along the oxide pillar sidewall;

a plurality of gate insulator layers, each gate insulator layer formed between each program gate and the adjacent oxide pillar, each gate insulator layer having a structure for trapping at least one charge; and

a word line coupling the plurality of control gates.

11. The array of claim 10 and further including:

an oxide interpoly material between each control gate and each program gate; and

a gate insulator layer on the bottom of each trench and comprising a structure for storing a plurality of charges under each control gate.

12. The array of claim 10 wherein each source/drain region is comprised of an n-type conductivity semiconductor material.

13. A computer system, comprising:

a central processing unit (CPU); and

an array of vertical NROM memory cells coupled to the CPU, the array including:

a plurality of oxide pillars each having a source/drain region formed at the top, a trench being formed between each pair of oxide pillars;

a plurality of control gates, each control gate formed in the trench between each pair of oxide pillars;

a plurality of program gates, each formed in the trench between a first control gate and each oxide pillar, each program gate extending along the oxide pillar sidewall;

a plurality of gate insulator layers, each gate insulator layer formed between each program gate and the adjacent oxide pillar, each gate insulator layer having a structure for trapping at least one charge; and

a word line coupling the plurality of control gates.

14. The computer system of claim 13 wherein the source/drain region of each oxide pillar acts as either a source connection or a drain connection in response to a direction of operation of the vertical NROM memory cell.

15. The computer system of claim 13 wherein each second source/drain region is comprised of an N+ conductivity silicon material.

16. A method for forming a vertical NROM split gate transistor, the method comprising:

forming a first columnar structure on a substrate, the first columnar structure having a doped region of a first type of conductivity that is different than the substrate, the doped region formed in the top of the first columnar structure;

forming a second columnar structure on the substrate that is spaced apart from the first columnar structure to form a trench between the two columnar structures, the second columnar structure having a doped region of the first type of conductivity formed in the top of the second columnar structure;

forming an oxide material on the bottom of the trench;

forming a polysilicon control gate structure between the first and second columnar structures;

forming a first gate insulator layer in the trench along the sidewall of the first columnar structure and a second gate insulator layer in the trench along the sidewall of the second columnar structure; and

interposing a polysilicon program gate structure between the first gate insulator layer and the control gate structure and between the second gate insulator layer and the control gate structure.

17. The method of claim 16 and further including forming an oxide interpoly region between the control gate structure and the program gate structures.

18. The method of claim 16 wherein the first type of conductivity is N+ and the substrate has a P+ conductivity.

19. The method of claim 16 wherein forming the first and second gate insulator layers comprises forming a composite oxide-nitride-oxide layer.

20. A method for forming a vertical NROM split gate transistor, the method comprising:

forming a first columnar structure on a substrate, the first columnar structure having a doped region of a first type of conductivity that is different than the substrate;

forming a second columnar structure on the substrate that is spaced apart from the first columnar structure to form a trench between the two columnar structures, the second columnar structure having a doped region of the first type of conductivity;

forming a bottom gate insulator layer on the bottom of the trench;

forming a polysilicon control gate structure between the first and second columnar structures;

forming a first gate insulator layer in the trench along the sidewall of the first columnar structure and a second gate insulator layer in the trench along the sidewall of the second columnar structure, wherein the bottom, first, and second gate insulator layers are a composite structure; and

interposing a polysilicon program gate structure between the first gate insulator layer and the control gate structure and between the second gate insulator layer and the control gate structure.

21. The method of claim 20 wherein the composite structure is comprised of one of an oxide-nitride-aluminum oxide composite layer, an oxide-aluminum oxide-oxide composite layer, or an oxide-silicon oxycarbide-oxide composite layer.

22. The method of claim 20 wherein the bottom, first, and second gate insulator layers are comprised of non-stoichiometric single layers of two or more of silicon, nitrogen, aluminum, titanium, tantalum, hafnium, lanthanum, or zirconium.

23. The method of claim 20 wherein the bottom, first, and second gate insulator layers are non-composite layers comprised of one of silicon oxides formed by wet oxidation and not annealed, silicon-rich oxides with inclusions of nanoparticles of silicon, silicon oxynitride layers, silicon-rich aluminum oxide insulators, silicon oxycarbide insulators, or silicon oxide insulators with inclusions of nanoparticles of silicon carbide.

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Description

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TECHNICAL FIELD

The present invention relates generally to semiconductor memory devices, and in particular to nitride read only memory transistor structures.

BACKGROUND OF THE INVENTION

Flash memory devices are high density, non-volatile memory devices having low power consumption, fast access times and low cost. Flash memory devices are thus well suited for use in a variety of portable electronic devices that require high-density storage but cannot support a disk drive, or other mass storage devices due to high power consumption or the additional weight of such devices. An additional advantage of flash memory is that it offers in-circuit programmability. A flash memory device may thus be reprogrammed under software control while the device resides on a circuit board within an electronic device.

FIG. 1 is a flash memory cell 10 according to the prior art. The flash memory cell 10 has a metal oxide semiconductor (MOS) structure that includes a substrate 12, a pair of source/drain regions 14, a floating gate 18 overlying a MOS channel region 16, and a control gate 20 overlying the floating gate 18. An oxide structure 22 separates the floating gate 18 from the channel region 16, and also separates the floating gate 18 from the control gate 20. For the device shown, the substrate 12 is doped with P-type impurities, and the source/drain regions 14 are doped with N-type impurities.

The memory cell 10 may be programmed by applying a sufficiently positive gate voltage V_CG and a positive drain voltage V_D to the device 10, while maintaining the source voltage V_S at a zero, or ground potential. As charge is moved to the floating gate 18 from the source/drain region 14, the device 10 attains a logic state "0". Alternately, if little or no charge is present at the floating gate 18, a logic state corresponding to "1" is stored on the device 10.

To read the state of the device 10, a positive voltage V_CG of predetermined magnitude is applied to the control gate 18, while V_D is maintained positive. If the voltage applied to the control gate 18 is sufficient to turn the device 10 on, a current flows from one source/drain region 14 to the other source/drain region 14 that may be detected by other external circuits, thus indicating the logic state "1". Correspondingly, if sufficient charge exists at the floating gate 18 to prevent the device 10 from turning on, a logic state of "0" is read. A logic state may be erased from the device 10 by applying a positive source voltage V_S to the source/drain region 14 while V_CG is maintained at a negative potential. The device 10 attains a logic state "1" following an erase cycle.

Although the foregoing flash memory cell 10 is highly effective to store a logic state in a memory device, it has been observed that the programming efficiency of the memory cell 10 is degraded as the number of accumulated program/erase cycles increases. As a result, the cell 10 may fail after the number of program/erase cycles exceeds a limiting value, which is termed the endurance limit for the cell 10. Although the endurance limit is relatively unimportant in cases where the cell 10 is programmed only once, it may be a critical concern where the device 10 is erased and reprogrammed numerous times. The degradation of the programming efficiency is believed to result from hot electrons that become trapped in the relatively thin oxide layer separating the floating gate 18 from the substrate 12 during a programming cycle, which permanently damages the oxide layer. In addition, extremely high electric field strengths are generated during erase cycles that cause holes having relatively low momentum to become trapped in the oxide layer separating the floating gate 18 and the substrate 12. As the cell 10 is subjected to repeated program/erase cycles, the trapped holes accumulate in the oxide layer and thus cause the electric fields applied during a read cycle to be degraded.

The qualitative effects of degradation of the flash memory cell 10 are shown in FIGS. 2-4. FIG. 2 compares the performance of a non-cycled flash memory cell 10 with the performance of the cell 10 after it has been subjected to a substantial number of erase and programming cycles. As shown in FIG. 2, the source/drain current I_DS for the cycled cell 10 is significantly lower that that obtained from a non-cycled cell 10 for a comparable fixed control gate voltage V_CG. As a consequence, the determination of a logic state during a read cycle is adversely affected due to the lowered source/drain current in the cycled cell 10. This effect is further shown in FIG. 3, where the source/drain current I_DS of the cell 10 is observed to steadily decrease as the number of cycles accumulates on the cell 10. FIG. 3 also shows that the endurance limit for the cell 10 may occur between approximately 105 and 106 cycles.

FIG. 4 shows the variation of a threshold voltage V_T for the cell 10 as the number of program/erase cycles is increased. The threshold voltage V_T is defined as the minimum required voltage to turn on a cell 10 during a read cycle. In FIG. 4, V_T,1 corresponds to the threshold value required to turn on the cell 10 when the floating gate of the cell 10 is charged (indicating logic state "0"), while V_T,2 corresponds to the threshold value required to turn on the cell 10 when the floating gate 18 is not charged. The difference between the V_T,1 and V_T,2 values thus defines a threshold voltage "window", as shown in FIG. 4. As the cell 10 is subjected to cycling, the "window" becomes progressively smaller, so that it becomes more difficult to distinguish between the two logic states stored in the cell 10.

One prior art solution to the foregoing endurance limit problem is a flash memory cell having a floating gate asymmetrically positioned towards the source, with the control gate overlying the floating gate and also directly overlying the channel region of the cell, as disclosed in detail in an article by P. Pavan, et al., entitled Flash Memories-An Overview, IEEE Proceedings, vol. 85, No. 8, pp. 1248-1271, 1997. Since the programming and erase functions occur in the portion of the channel region ad