Apparatus for reducing the impact of program disturb during read Number:7,426,137 from the United States Patent and Trademark Office (PTO) owispatent

Title: Apparatus for reducing the impact of program disturb during read

Abstract: The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as "program disturb." A system is proposed for programming and/or reading non-volatile storage that reduces the effect of program disturb. In one embodiment, different verify levels are used for a particular word line (or other grouping of storage elements) during a programming process. In another embodiment, different compare levels are used for a particular word (or other grouping of storage elements) during a read process.

Patent Number: 7,426,137 Issued on 09/16/2008 to Hemink

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Inventors:	Hemink; Gerrit Jan (Yokohama, JP)
Assignee:	SanDisk Corporation (Milpitas, CA)
Appl. No.:	11/413,671
Filed:	April 28, 2006

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Related U.S. Patent Documents

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	Application Number	Filing Date	Patent Number	Issue Date
	60791365	Apr., 2006

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Current U.S. Class:	365/185.02 ; 365/185.03
Current International Class:	G11C 11/34 (20060101)
Field of Search:	365/185.02,185.03,185.18

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Primary Examiner: Phung; Anh
Attorney, Agent or Firm: Vierra Magen Marcus & DeNiro LLP

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Parent Case Text

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CLAIM OF PRIORITY

This application claims the benefit of U.S. Provisional Application No. 60/791,365, "Reducing The Impact Of Program Disturb For A Word Line," Inventor Gerrit Jan Hemink, filed on Apr. 12, 2006, incorporated herein by reference in its entirety.

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Claims

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I claim:

1. A non-volatile storage system, comprising: non-volatile storage elements, said non-volatile storage elements include a first set of non-volatile storage elements connected to a first control line and a second set of non-volatile storage elements connected to a second set of control lines different than said first control line, said first control line is next to a source select control line; and a managing circuit in communication with said non-volatile storage elements, said managing circuit causes reading of said first set of non-volatile storage elements using a first set of read compare values and reading of said second set of one or more non-volatile storage elements using a second set of read compare values, at least one of said first set of read compare values is different than a corresponding compare level of said second set of read compare values.

2. A non-volatile storage system according to claim 1, wherein: said first set of one or more non-volatile storage elements and said second set of one or more non-volatile storage elements are multi-state NAND flash memory devices.

3. A non-volatile storage system according to claim 1, wherein: said non-volatile storage elements are arranged in blocks, each block includes a set of pages, said pages define units of programming and blocks define units of erase; said first control line and said second set of control lines are word lines that are part of a common block; said common block includes a set of bit lines; and each of said first set of non-volatile storage elements are connected to a different bit line of said set of bit lines.

4. A non-volatile storage system according to claim 1, wherein: said one of said first set of read compare values is greater than said corresponding compare level of said second set of read compare values.

5. A non-volatile storage system according to claim 1, wherein: said reading said first set of non-volatile storage elements includes reading a first page of data using said first set of read compare values and reading a second page of data using a third set of read compare values.

6. A non-volatile storage system according to claim 1, wherein: said managing circuit reads a third set of non-volatile storage elements using a third set of read compare values, said third set of non-volatile storage elements are connected to said first control line.

7. A non-volatile memory system according to claim 1, wherein: all of said first set of read compare values are greater than corresponding compare levels of said second set of read compare values.

8. A non-volatile memory system according to claim 1, wherein: said managing circuit includes any one or a combination of a controller, a state machine, command circuits, control circuits and decoders.

9. A non-volatile storage system, comprising: non-volatile storage elements, said non-volatile storage elements include a first set of non-volatile storage elements connected to a first control line and a second set of non-volatile storage elements connected to a second set of control lines different than said first control line, said first control line is next to a third control line that is not part of said second set of control lines; and a managing circuit in communication with said non-volatile storage elements, said managing circuit causes programming of said first set of non-volatile storage elements using a set of target levels, said programming of said first set of non-volatile storage elements includes providing a programming signal on said first control line and providing a signal on said third control line requiring non-volatile storage elements connected to said third control line to turn off in response to said signal, said managing circuit causes programming of said second set of non-volatile storage elements using said set of target levels, said managing circuit causes reading of said first set of one or more non-volatile storage elements using a first set of read compare values and reading of said second set of one or more non-volatile storage elements using a second set read compare values, at least one of said first read compare values is different than a corresponding compare level of said second set of read compare values.

10. A non-volatile storage system according to claim 9, wherein: said first set of one or more non-volatile storage elements and said second set of one or more non-volatile storage elements are multi-state NAND flash memory devices.

11. A non-volatile storage system according to claim 10, wherein: said non-volatile storage elements are arranged in blocks, each block includes a set of pages, said pages define units of programming and blocks define units of erase; said first control line and said second set of control lines are word lines are part of a common block; said first control line is next to a source select line for said common block; said common block includes a set of bit lines; and each of said first set of non-volatile storage elements are connected to a different bit line of said set of bit lines.

12. A non-volatile storage system according to claim 11, wherein: said non-volatile storage elements and said managing circuit are mounted in a removable card; and said managing circuit includes a state machine.

13. A non-volatile storage system according to claim 10, wherein: said one of said first set of read compare values is greater than said corresponding compare level of said second set of read compare values.

14. A non-volatile storage system, comprising: non-volatile storage elements, said non-volatile storage elements include a first set of non-volatile storage elements connected to a first word line and a second set of non-volatile storage elements connected to a group of word lines different than said first word line; and a managing circuit in communication with said non-volatile storage elements, said managing circuit programs said first set of non-volatile storage elements using a set of target levels and programs said second set of non-volatile storage elements using said set of target levels, said managing circuit reads said first set of non-volatile storage elements using a first set of read compare values and reads said second set of one or more non-volatile storage elements using a second set of read compare values, at least one of said first set of read compare values is different than a corresponding compare level of said second set of read compare values.

15. A non-volatile storage system according to claim 14, wherein: said first set of one or more non-volatile storage elements and said second set of one or more non-volatile storage elements are multi-state NAND flash memory devices.

16. A non-volatile storage system according to claim 15, wherein: said non-volatile storage elements are arranged in blocks, each block includes a set of pages, said pages define units of programming and blocks define units of erase; said first word line and said group of word lines are part of a common block; said common block includes a set of bit lines; and each of said first set of non-volatile storage elements are connected to a different bit line of said set of bit lines.

17. A non-volatile storage system according to claim 14, wherein: said one of said first set of read compare values is greater than said corresponding compare level of said second set of read compare values.

18. A non-volatile me storage system according to claim 14, wherein: said first set of one or more non-volatile storage elements are adjacent to source select gates.

19. A non-volatile storage system according to claim 14, wherein: said reading said first set of non-volatile storage elements includes reading a first page of data using said first set of read compare values and reading a second page of data using a third set of read compare values.

20. A non-volatile storage system according to claim 14, wherein: said managing circuit includes a controller, a state machine, and decoders.

21. A non-volatile storage system, comprising: non-volatile storage elements, said non-volatile storage elements include a first set of non-volatile storage elements connected to a first set of control lines and a second set of non-volatile storage elements connected to a second set of control lines different than said first set of control lines, said first set of control lines are next to a source select control line; and a managing circuit in communication with said non-volatile storage elements, said managing circuit causes reading of said first set of non-volatile storage elements using a first set of read compare values and reading of said second set of one or more non-volatile storage elements using a second set of read compare values, at least one of said first set of read compare values is different than a corresponding compare level of said second set of read compare values.

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Description

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CROSS-REFERENCE TO RELATED APPLICATIONS

This application is related to the following three United States patent applications, all three of which are incorporated herein by reference in their entirety:

"Reducing The Impact of Program Disturb During Read," Inventor Gerrit Jan Hemink, filed on the same day as the present application;

"Apparatus for Reducing The Impact Of Program Disturb," Inventor Gerrit Jan Hemink, filed on the same day as the present application; and

"Apparatus for Reducing The Impact of Program Disturb During Read," Inventor Gerrit Jan Hemink, filed on the same day as the present application.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a non-volatile memory.

2. Description of the Related Art

Semiconductor memory devices have become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.

Many types of EEPROM and flash memories utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate is positioned between source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.

One example of a flash memory system uses the NAND structure, which includes arranging multiple transistors in series, sandwiched between two select gates. The transistors in series and the select gates are referred to as a NAND string. FIG. 1 is a top view showing one NAND string. FIG. 2 is an equivalent circuit thereof. The NAND string depicted in FIGS. 1 and 2 includes four transistors 100, 102, 104 and 106 in series and sandwiched between a first (or drain) select gate 120 and a second (or source) select gate 122. Select gate 120 connects the NAND string to a bit line via bit line contact 126. Select gate 122 connects the NAND string to source line 128. Select gate 120 is controlled by applying the appropriate voltages to select line SGD. Select gate 122 is controlled by applying the appropriate voltages to select line SGS. Each of the transistors 100, 102, 104 and 106 has a control gate and a floating gate. For example, transistor 100 has control gate 100CG and floating gate 100FG. Transistor 102 includes control gate 102CG and a floating gate 102FG. Transistor 104 includes control gate 104CG and floating gate 104FG. Transistor 106 includes a control gate 106CG and a floating gate 106FG. Control gate 100CG is connected to word line WL3, control gate 102CG is connected to word line WL2, control gate 104CG is connected to word line WL1, and control gate 106CG is connected to word line WL0.

Note that although FIGS. 1 and 2 shows four memory cells in the NAND string, the use of four transistors is only provided as an example. A NAND string can have less than four memory cells or more than four memory cells. For example, some NAND strings will include eight memory cells, 16 memory cells, 32 memory cells, 64 memory cells, etc. The discussion herein is not limited to any particular number of memory cells in a NAND string.

A typical architecture for a flash memory system using a NAND structure will include several NAND strings. For example, FIG. 3 shows three NAND strings 202, 204 and 206 of a memory array having many more NAND strings. Each of the NAND strings of FIG. 3 includes two select transistors (also called gates) and four memory cells. For example, NAND string 202 includes select transistors 220 and 230, and memory cells 222, 224, 226 and 228. NAND string 204 includes select transistors 240 and 250, and memory cells 242, 244, 246 and 248. Each NAND string is connected to the source line by its source select gate (e.g. select transistor 230 and select transistor 250). A selection line SGS is used to control the source select gates (e.g., 230 and 250).

The various NAND strings are connected to respective bit lines by select transistors 220, 240, etc., which are controlled by select line SGD. Each bit line and the respective NAND string(s) that are connected to that bit line via a bit line contact comprise the columns of the array of memory cells. Bit lines are shared with multiple NAND strings. Typically, the bit line runs on top of the NAND strings in a direction perpendicular to the word lines and is connected to one or more sense amplifiers.

The word lines (WL3, WL2, WL1 and WL0) comprise the rows of the array. Word line WL3 is connected to the control gates for memory cell 222 and memory cell 242. Word line WL2 is connected to the control gates for memory cell 224, memory cell 244 and memory cell 252. Word line WL1 is connected to the control gates for memory cell 226 and memory cell 246. Word line WL0 is connected to the control gates for memory cell 228 and memory cell 248.

Each memory cell can store data (analog or digital). When storing one bit of digital data (referred to as a binary memory cell), the range of possible threshold voltages of the memory cell is divided into two ranges which are assigned logical data "1" and "0." In one example of a NAND type flash memory, the voltage threshold is negative after the memory cell is erased, and defined as logic "1." The threshold voltage after programming is positive and defined as logic "0." When the threshold voltage is negative and a read is attempted by applying 0 volts to the control gate, the memory cell will turn on to indicate logic one is being stored. When the threshold voltage is positive and a read operation is attempted by applying 0 volts to the control gate, the memory cell will not turn on, which indicates that logic zero is stored.

A memory cell can also store multiple levels of information (referred to as a multi-state memory cell). In the case of storing multiple levels of data, the range of possible threshold voltages is divided into the number of levels of data. For example, if four levels of information is stored, there will be four threshold voltage ranges assigned to the data values "11", "10", "01", and "00." In one example of a NAND type memory, the threshold voltage after an erase operation is negative and defined as "11". Positive threshold voltages are used for the states of "10", "01", and "00."

Relevant examples of NAND type flash memories and their operation are provided in the following U.S. patents/patent applications, all of which are incorporated herein by reference: U.S. Pat. Nos. 5,570,315; 5,774,397; 6,046,935; 6,456,528; and U.S. Pat. Publication No. US2003/0002348. The discussion herein can also apply to other types of flash memory in addition to NAND as well as other types of non-volatile memory.

When programming a flash memory cell, a program voltage is applied to the control gate and the bit line is grounded. Due to the voltage differential between the channel of the flash memory cell and the floating gate, electrons from the channel area under the floating gate are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised. To apply the program voltage to the control gate of the cell being programmed, that program voltage is applied on the appropriate word line. As discussed above, that word line is also connected to one memory cell in each of the other NAND strings that utilize the same word line. For example, when programming memory cell 224 of FIG. 3, the program voltage will also be applied to the control gate of memory cell 244 because both memory cells share the same word line. A problem arises when it's desired to program one cell on a word line without programming other cells connected to the same word line, for example, when it's desired to program memory cell 224 and not memory cell 244. Because the program voltage is applied to all memory cells connected to a word line, an unselected memory cell (a memory cell that is not to be programmed) on the same word line may become inadvertently programmed. For example, memory cell 244 is adjacent to memory cell 224. When programming memory cell 224, there is a concern that memory cell 244 might unintentionally be programmed. The unintentional programming of the unselected memory cell on the selected word line is referred to as "program disturb."

Several techniques can be employed to prevent program disturb. In one method known as "self boosting," the unselected NAND strings are electrically isolated from the corresponding bit lines and a pass voltage (e.g. 7-10 volts, but not limited to this range) is applied to the unselected word lines during programming. The unselected word lines couple to the channel area of the unselected NAND strings, causing a voltage (e.g., 6-10 volts) to exist in the channel of the unselected NAND strings, thereby reducing program disturb. Self boosting causes a boosted voltage to exist in the channel which lowers the voltage differential across the tunnel oxide and hence reduces program disturb. Note that the boosted channel voltage can vary largely since the boosted channel voltage depends on the value of the pass voltage and also on the state of the memory cells, with boosting being most efficient (highest channel voltage) when all memory cells in the NAND string are in the erased state.

FIGS. 4 and 5 depict NAND strings that are being programmed and inhibited using the self-boosting method. FIG. 4 depicts a NAND string being programmed. The NAND string of FIG. 4 includes eight memory cells 304, 306, 308, 310, 312, 314, 316 and 318. Each of those eight memory cells includes a floating gate (FG) and a control gate (CG). Between each of the floating gates are source/drain regions 330. In some implementations, there is a P-type substrate (e.g., Silicon), an N-well within the substrate and a P-well within the N-well (all of which are not depicted to make the drawings more readable). Note that the P-well may contain a so called channel implantation that is usually a P-type implantation that determines or helps to determine the threshold voltage and other characteristics of the memory cells. The source/drain regions 330 are N+ diffusion regions that are formed in the P-well.

At one end of the NAND string is a drain side select gate 324. The drain select gate 324 connects the NAND string to the corresponding bit line via bit line contact 334. At another end of the NAND string is a source select gate 322. Source select gate 322 connects the NAND string to common source line 332. During programming, the memory cell selected for programming (e.g., memory cell 312) receives a program voltage Vpgm on its associated word line. The program voltage Vpgm can typically vary between 12 to 24 volts. In one embodiment, the program voltage signal is a set of pulses which increase in magnitude with each new pulse. A pass voltage Vpass of approximately 8 volts is applied to the control gates of the memory cells that are not selected for programming. Source select gate 322 is in an isolating state, receiving 0 volts at its gate (G). A low voltage is applied to the common source line 332. This low voltage can be zero volts. However, the source voltage can also be slightly higher than zero volts to provide better isolation characteristics of the source side select gate. A voltage Vsgd, which is typically in the range of the power supply voltage Vdd (e.g., 2.5 volts), is applied to drain side select gate 324. Zero volts is applied to bit line contact 334 via the corresponding bit line to enable programming of the selected memory cell 312. Channel 340 is at or close to zero volts. Because of the voltage differential between the channel and the floating gate of memory cell 314, electrons tunnel through the gate oxide (also commonly referred to as tunnel oxide) into the floating gate by Fowler-Nordheim tunneling.

The NAND string of FIG. 5 depicts a NAND string being inhibited from programming. The NAND string includes eight memory cells 350, 352, 354, 356, 358, 360, 362 and 364. The NAND string also includes drain select gate 366 connecting the NAND string to the corresponding bit line via bit line contact 374, and source select gate for 368 connecting the NAND string to common source line 332. Between each of the floating gate stacks are source/drain regions 370. The NAND string of FIG. 5 has Vsgd applied to the gate of the drain select gate 366, zero volts applied to the gate of the source side select gate 368 and zero volts (or a slightly higher voltage) at the common source line 332. Bit line contact 374 receives the power supply voltage Vdd via the corresponding bit line in order to inhibit the programming of memory cell 358.

When Vdd is applied, the drain select transistor 366 will initially be in a conducting state; therefore, the channel area under the NAND string will partly be charged up to a higher potential (higher than zero volts and typically equal or almost equal to Vdd). This charging is commonly referred to as pre-charging. The pre-charging will stop automatically when the channel potential has reached Vdd or a lower potential given by Vsgd-Vt, where Vt equals the threshold voltage of the drain select gate 366. In general, during pre-charging, Vsgd is chosen in such a way that Vsgd-Vt>Vdd so that the channel area under the NAND string can be pre-charged to Vdd. After the channel has reached that potential, the select gate transistor is non-conducting or made non-conducting by lowering Vsgd to a value similar to Vdd (e.g. 2.5 volts). Subsequently, the voltages Vpass and Vpgm are ramped up from zero volts to their respective final values (not necessarily at the same time), and because the drain side select gate transistor 366 is in a non-conducting state, the channel potential will start to rise because of the capacitive coupling between the word lines and the channel area. This phenomenon is called self boosting. It can be seen from FIG. 5 that channel 380 is boosted, more or less uniformly, to a boosting voltage. Because the voltage differential between the floating gate of memory cell 358 and channel 380 has been reduced, programming is inhibited. More information about programming NAND flash memory, including self boosting techniques, can be found in U.S. Pat. No. 6,859,397, "Source Side Self Boosting Technique for Non-Volatile Memory," Lutze at al., incorporated herein by reference in its entirety.

Another attempt to address program disturb is Erased Area Self Boosting ("EASB"). EASB attempts to isolate the channel of previously programmed cells from the channel of the cell being inhibited. In the EASB method, the channel area of the selected NAND string is divided into two areas. An area at the source side of the selected word line that can contain a number of programmed (or erased cells) memory cells and an area at the drain side of the selected word line in which the cells are still in the erased state, or at least not yet in the final programmed state. The two areas are separated by a word line that is biased to a low voltage, typically zero volts. Because of this separation, the two areas can be boosted to different potentials. In almost all cases, the area at the drain side of the selected word line will be boosted to a higher potential than the area at the source side. Since the highest boosted area is the area with the erased cells, this boosting method is referred to as Erased Area Self Boosting (EASB).

Although the above boosting methods have reduced program disturb, they have not eliminated the problem. One effect that can occur to the memory cell next to the source select gate (e.g., memory cell 350 is next to source select gate 368 of FIG. 5) is Gate Induced Drain Leakage (GIDL), which is also referred to as Band-To-Band-Tunneling. GIDL causes the generation of electrons at the source select gate when the channel under the NAND string is inhibited from programming (boosted to a high voltage). Subsequently, the generated electrons are accelerated in the strong lateral electric field towards the floating gate of the memory cell next to the source select gate. Some of the electrons can gain sufficient energy to be injected into the tunnel oxide under the floating gate or in the floating gate itself and, thus modify the threshold voltage of the corresponding memory cell.

FIG. 6 shows a portion of the NAND string of FIG. 5, with a zooming-in on the drain and a portion of the channel for memory cell 350. Due to boosting of the NAND string during a program inhibit operation (for example when other NAND strings are being programmed), a high voltage is present in the channel area of the boosted NAND string (see boosted channel 380). This high voltage is also present at the junction area between source select gate 368, which is typically biased at 0V, and memory cell 350 next to source select gate 368. This bias condition may cause GIDL, which can result in the creation of electron hole pairs. The holes will go to P-well area 384. The electrons will move to the boosted channel area 380. In general, there is a lateral electric field present in the junction area between the source select gate and the memory cell next to the source side select gate because part of that junction (drain/source) is depleted due to the large voltage difference between channel area under the memory cells and the channel area under the select gate. The electrons can be accelerated in the electric field and may gain enough energy to be injected in the tunnel oxide of the memory cell next to the source side select gate or may even reach the floating gate of that memory cell. In both cases, the threshold voltage of the corresponding memory cell will change due to the presence of the injected electrons, thereby, risking an error when reading the memory cell next to the source select gate.

Thus, there is a need for a new mechanism to reduce the impact of program disturb.

SUMMARY OF THE INVENTION

A system is proposed for programming and/or reading non-volatile storage elements that reduces the effect of program disturb. In one set of implementations, different verify levels are used for a particular word line (or other grouping of storage elements) during a programming process. For one set of examples that use multi-state devices, the target level for one programmed state, two programmed states, another subset of programmed states, or all of the programmed states can be different. In some embodiments, different pages of data associated with the particular word line (or other grouping of storage elements) could use different (one, two, another subset or all) target levels. In other embodiments, different storage elements associated with the particular word line (or other grouping of storage elements) could use different (one, two, another, subset or all) target levels. In one embodiment, the word line that receives the different target levels is chosen based on its position relative to a boosted region.

One embodiment includes programming a group of non-volatile storage elements using a group of target levels and programming a particular set of non-volatile storage elements using a particular set of target levels so that threshold distributions of the particular set of non-volatile storage elements are within corresponding threshold distributions of the group of non-volatile storage elements upon completion of a programming process. At least one of the particular set of target levels is below a corresponding target level of the group of target levels.

One embodiment includes programming a group of non-volatile storage elements using a group of target levels and programming a particular set of non-volatile storage elements using a particular set of target levels so that threshold voltage distributions of the particular set of non-volatile storage elements are shifted to at least protrude less (including not protruding at all) from corresponding threshold voltage distributions of the group of non-volatile storage elements upon completion of a programming process, at least one of the particular set of target levels is below a corresponding target level of the group of target levels.

One embodiment includes programming a set of one or more non-volatile storage elements using a group of target levels and programming a particular non-volatile storage element using a particular set of target levels. At least one of the particular set of target levels is below a corresponding target level of the group of target levels. The particular non-volatile storage element is adjacent to a source select gate.

One embodiment includes programming a first set of one or more non-volatile storage elements using a first set of target levels and programming a second set of one or more non-volatile storage elements using a second set of target levels after programming the first set of one or more non-volatile storage elements. The first set of one or more non-volatile storage elements are programmed first. The first set of one or more non-volatile storage elements are connected to a first word line and the second set of one or more non-volatile storage elements are connected to a set of word lines programmed after the first word line during a sequence of programming operations. The second set of target levels is different than the first set of target levels.

A system is proposed for programming and/or reading non-volatile storage that reduces the effect of program disturb. In one set of implementations, different read compare values are used for a particular word line (or other grouping of storage elements) during a read process. The word line that will receive the different read compare values is chosen based on position of the word line with respect to the position of a boosting region during the programming process.

One embodiment includes reading a first set of non-volatile storage elements using a first set of read compare values and reading a second set of one or more non-volatile storage elements using a second set of read compare values. The first set of non-volatile storage elements are connected to a first control line. The second set of non-volatile storage elements are connected to a second set of control lines different than the first control line. At least one of the first set of read compare values is different than a corresponding compare level of the second set of read compare values. In one example of an implementation (but not all implementations), the first control line is next to a source select control line.

One embodiment includes programming a first set of non-volatile storage elements using a first set of target levels and programming a second set of one or more non-volatile storage elements using the same first set of target levels. The first set of non-volatile storage elements is associated with a first control line. The first control line is adjacent to a second control line. The process also includes providing a programming signal on the first control line and providing a signal on the second control line requiring non-volatile storage elements connected to the second control line to turn off in response to the signal. The second set of one or more non-volatile storage elements are associated with a set of control lines. The first control line and the second control line are not in the set of control lines. The first set of one or more non-volatile storage elements are read using a first set of read compare values. The second set of one or more non-volatile storage elements are read using a second set read compare values. At least one of the first set of read compare values is different than a corresponding compare level of the second set of read compare values.

The various methods described herein can be performed by various devices. One example of a suitable apparatus includes non-volatile storage elements and a managing circuit in communication with the non-volatile storage elements. The non-volatile storage elements include a first set of non-volatile storage elements and a second set of non-volatile storage elements. The managing circuit performs the various methods described herein in relation to the first set of non-volatile storage elements and the second set of non-volatile storage elements. In one embodiment, the managing circuit includes any one or a combination of a controller, a state machine, command circuits, control circuits and decoders. In other embodiments, the managing circuit can also include other elements suitable for the particular implementations.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a top view of a NAND string.

FIG. 2 is an equivalent circuit diagram of the NAND string.

FIG. 3 is a schematic diagram depicting three NAND strings.

FIG. 4 shows a NAND string being programmed.

FIG. 5 shows a NAND string being inhibited, using a self boosting method.

FIG. 6 depicts a portion of a NAND string.

FIG. 7 is a block diagram of one example of a memory system.

FIG. 8 illustrates an example of an organization of a memory array.

FIG. 9 depicts a set of threshold voltage distributions.

FIGS. 10A, 10B and 10C depict threshold voltage distributions.

FIG. 11 is a flow chart describing one embodiment of a process for programming and reading non-volatile memory.

FIGS. 12A and 12B depict threshold voltage distributions.

FIG. 13 is a flow chart describing one embodiment of a process for programming and reading non-volatile memory.

FIG. 14 is a flow chart describing one embodiment of a process for programming and reading non-volatile memory.

FIG. 15 is a flow chart describing one embodiment of a process for programming and reading non-volatile memory.

FIG. 16 is a flow chart describing one embodiment of a programming operation.

FIG. 17 is a signal diagram depicting one embodiment of a read operation.

FIG. 18 is a flow chart describing one embodiment of a process for programming and reading non-volatile memory.

FIG. 19 depicts a set of threshold voltage distributions.

FIG. 20 is a flow chart describing one embodiment of a process for programming and reading non-volatile memory.

DETAILED DESCRIPTION

FIG. 7 is a block diagram of one embodiment of a flash memory system that can be used to implement one or more embodiments described herein. Other systems and implementations can also be used. Memory cell array 502 is controlled by column control circuit 504, row control circuit 506, p-well control circuit 508 and c-source control circuit 510. Column control circuit 504 is connected to the bit lines of memory cell array 502 for reading data stored in the memory cells, for determining a state of the memory cells during a program operation, and for controlling potential levels of the bit lines to promote or inhibit programming and erasing. Row control circuit 506 is connected to the word lines to select one of the word lines, to apply read voltages, to apply program voltages combined with the bit line potential levels controlled by column control circuit 504, and to apply an erase voltage. In one embodiment, row control 306 and column control 304 include decoders to select the appropriate word lines and bit lines. C-source control circuit 510 controls a common source line (labeled as "C-source" in FIG. 8) connected to the memory cells. P-well control circuit 508 controls the p-well voltage.

The data stored in the memory cells is read out by the column control circuit 504 and is output to external I/O lines via data input/output buffer 512. Program data to be stored in the memory cells is input to the data input/output buffer 512 via the external I/O lines, and transferred to the column control circuit 504. The external I/O lines are connected to controller 518.

Command data for controlling the flash memory device is input to controller 518. The command data informs the flash memory of what operation is requested. The input command is transferred to state machine 516 which is part of control circuitry 515. State machine 516 controls column control circuit 504, row control circuit 506, c-source control 510, p-well control circuit 508 and data input/output buffer 512. State machine 516 can also output status data of the flash memory such as READY/BUSY or PASS/FAIL.

Controller 518 is connected to or connectable with a host system such as a personal computer, a digital camera, or personal digital assistant, etc. It communicates with the host that initiates commands, such as to store or read data to or from the memory array 502, and provides or receives such data. Controller 518 converts such commands into command signals that can be interpreted and executed by command circuits 514 which are part of control circuitry 515. Command circuits 514 are in communication with state machine 516. Controller 518 typically contains buffer memory for the user data being written to or read from the memory array.

One exemplary memory system comprises one integrated circuit chip that includes controller 518, and one or more integrated circuit chips that each contain a memory array and associated control, input/output and state machine circuits. The memory arrays and controller circuits of a system can be integrated on one or more integrated circuit chips. The memory system may be embedded as part of the host system, or may be included in a memory card (or other package) that is removably inserted into the host systems. Such a card may include the entire memory system (e.g. including the controller) or just the memory array(s) with associated peripheral circuits (with the controller or control function being embedded in the host). Thus, the controller can be embedded in the host or included within the removable memory system.

In some implementations, some of the components of FIG. 7 can be combined. In various designs, one or more of the components of FIG. 7 (alone or in combination), other than memory cell array 502, can be thought of as a managing circuit. For example, a managing circuit may include any one of or a combination of control circuitry 515, command circuits 514, state machine 516, column control circuit 504, row control circuit 506, p-well control circuit 508, c-source control circuit 510 and data I/O 512.

With reference to FIG. 8, an exemplary structure of memory cell array 502 is described. As one example, a NAND flash EEPROM is described that is partitioned into 1,024 blocks. The data stored in each block can be simultaneously erased. In one embodiment, the block is the minimum unit of memory cells that are simultaneously erased. In each block, in this example, there are 8,512 columns. Each block is typically divided into a number of pages which can be a unit of programming. Other units of data for programming are also possible. In one embodiment, individual pages may be divided into segments and the segments may contain the fewest number of cells that are written at one time as a basic programming operation. One or more pages of data are typically stored in one row of memory cells.

In each block of the example in FIG. 8 there are 8,512 columns that are divided into even bit lines (BLe) and odd bit lines (BLo). In an odd/even bit line architecture, memory cells along a common word line and connected to the odd bit lines are programmed at one time, while memory cells along a common word line and connected to even bit lines are programmed at another time. FIG. 8 shows four memory cells connected in series to form a NAND string. Although four cells are shown to be included in each NAND string, more or less than four can be used (e.g., 16, 32, or another number). One terminal of the NAND string is connected to a corresponding bit line via a drain select gate (connected to select gate drain line SGD), and another terminal is connected to c-source via a source select gate (connected to select gate source line SGS).

In other embodiments, the bit lines are not divided into odd and even bit lines. Such architectures are commonly referred to as all bit line architectures. In an all bit line architecture, all the bit lines of a block can be simultaneously selected during read and program operations. Memory cells along a common word line and connected to any bit line can be programmed at the same time.

In another embodiment the bit lines are divided into planes. For example, there can be a left plane (left most 4256 bit lines) and a right plane (right most 4256 bit lines). Each plane can be programmed separately or both planes can be programmed at the same time. In some embodiments, there can be more than two planes. Other arrangements can also be used.

During read and programming operations of one embodiment using an odd/even bit line architecture, 4,256 memory cells are simultaneously selected. The memory cells selected have the same word line (e.g. WL2-i), and the same kind of bit line (e.g. even bit lines). Therefore, 532 bytes of data can be read or programmed simultaneously. These 532 bytes of data that are simultaneously read or programmed form a logical page. Therefore, in this example, one block can store at least eight pages. When each memory cell stores two bits of data (e.g. a multi-state cell), one block stores 16 pages. Other sized blocks and pages can also be used. Additionally, architectures other than that of FIGS. 7 and 8 can also be used to implement embodiments.

In the read and verify operations, the select gates of a selected block are raised to one or more select voltages and the unselected word lines (e.g., WL0, WL1 and WL3) of the selected block are raised to a read pass voltage (e.g. 4.5 volts) to make the transistors operate as pass gates. The selected word line of the selected block (e.g., WL2) is connected to a reference voltage, a level of which is specified for each read and verify operation in order to determine whether a threshold voltage of the concerned memory cell is above or below such level. For example, in a read operation of a binary memory cell, the selected word line WL2 is grounded, so that it is detected whether the threshold voltage is higher than 0V. In a verify operation of a binary memory cell, the selected word line WL2 is connected to 0.8V, for example, so that as programming progresses it is verified whether or not the threshold voltage has reached the target level of 0.8V. The source and p-well are at zero volts during read and verify. The selected bit lines (BLe) are pre-charged to a level of, for example, 0.7V. If the threshold voltage is higher than the read or verify level, the potential level of the concerned bit line (BLe) maintains the high level, because of the associated non-conductive memory cell. On the other hand, if the threshold voltage is lower than the read or verify level, the potential level of the concerned bit line (BLe) decreases to a low level, for example less than 0.5V, because of the conductive memory cell. The state of the memory cell is detected by a sense amplifier that is connected to t