Title: Clock control circuit and method
Abstract: A clock controlling circuit and method for eliminating the delay difference in the entire clock propagation line. Circuit scale is reduced as compared to a case of using a PLL or DLL circuit. A timing averaging circuit 10 is fed with clocks from a position on a forward route 111 of a direction-reversed clock propagation path, adapted for being fed with input clocks at its one end, and from a position on a return route 112 corresponding to the position on the forward route 111. The timing difference between these clocks is averaged to output an averaged timing difference.
Patent Number: 6,987,411 Issued on 01/17/2006 to Saeki
| Inventors:
|
Saeki; Takanori (Tokyo, JP)
|
| Assignee:
|
NEC Electronics Corporation (Kawasaki, JP)
|
| Appl. No.:
|
844553 |
| Filed:
|
May 13, 2004 |
Foreign Application Priority Data
| Apr 27, 2000[JP] | 2000-128424 |
| Apr 24, 2001[JP] | 2001-126661 |
| Current U.S. Class: |
327/292; 327/293; 327/295 |
| Current Intern'l Class: |
H03K 3/00 (20060101); G06F 1/04 (20060101) |
| Field of Search: |
327/291-293,295,297,141,144
713/401,503
|
References Cited [Referenced By]
U.S. Patent Documents
| 4998262 | Mar., 1991 | Wiggers.
| |
| 5361277 | Nov., 1994 | Grover.
| |
| 5528187 | Jun., 1996 | Sato et al.
| |
| 5663661 | Sep., 1997 | Dillon et al.
| |
| 5684424 | Nov., 1997 | Felix et al.
| |
| 5726596 | Mar., 1998 | Perez.
| |
| 5896055 | Apr., 1999 | Toyonaga et al.
| |
| 5990721 | Nov., 1999 | Mellitz.
| |
| 6111448 | Aug., 2000 | Shibayama.
| |
| 6157238 | Dec., 2000 | Na et al.
| |
| 6191632 | Feb., 2001 | Iwata et al.
| |
| 6229368 | May., 2001 | Lee.
| |
| Foreign Patent Documents |
| 04-229634 | Aug., 1992 | JP.
| |
| 06-314970 | Nov., 1994 | JP.
| |
| 09-134226 | May., 1997 | JP.
| |
| 09-213808 | Aug., 1997 | JP.
| |
| 09-258841 | Oct., 1997 | JP.
| |
| 9-258841 | Oct., 1997 | JP.
| |
| 09-325830 | Dec., 1997 | JP.
| |
| 10-283059 | Oct., 1998 | JP.
| |
| 11-4145 | Jan., 1999 | JP.
| |
| 11-4146 | Jan., 1999 | JP.
| |
| 11-004145 | Jan., 1999 | JP.
| |
| 11-007764 | Jan., 1999 | JP.
| |
| 11-353268 | Dec., 1999 | JP.
| |
| 2000/-099190 | Apr., 2000 | JP.
| |
Other References
Korean Office Action dated Jun. 27, 2003 with English translation.
Japanese Office Action dated Mar. 25, 2003 with partial translation.
"Full Swing or Partial Swing Complementary Metal-Oxide Semiconductor Driver",
IBM Technical Disclosure Bulletin, Jun. 1996.
|
Primary Examiner: Lam; Tuan T.
Attorney, Agent or Firm: McGinn & Gibb, PLLC
Parent Case Text
The present Application is a Divisional Application of U.S. patent application
Ser. No. 10/330,275, now U.S. Pat. No. 6,771,107, filed on Dec. 30, 2002, which
was a Divisional Application of U.S. patent application Ser. No. 09/842,200, now
U.S. Pat. No. 6,525,588, filed on Apr. 26, 2001.
Claims
What is claimed is:
1. A clock controlling circuit comprising:
a first timing averaging circuit for receiving two clocks from a certain position
on a forward route of a first clock propagation path, and from a position on a
return route corresponding to said position on said forward route, and for outputting
a first signal with a delay time corresponding to a time obtained on division of
a timing difference of said two clocks into two equal portions, respectively;
a second clock propagation path for receiving at one end said first signal output
from said first timing averaging circuit and direction-reversing the first signal;
and
a second timing averaging circuit for receiving two clocks, including a first
clock from a certain first position on a forward route of said second clock propagation
path, and a second clock from a second position on a return route corresponding
to the first position on said forward route, and for outputting a second signal
with a delay time corresponding to a time obtained on division of a timing difference
of said two clocks into two equal portions.
2. The clock controlling circuit as defined in claim 1, further comprising:
a first plurality of timing averaging circuits each being fed with clock pairs
each at two points on a forward route and return route of said first clock propagation
path for each outputting a signal of a delay time corresponding to a time obtained
on equally dividing the timing difference of each of the clock pairs; and
a second plurality of timing averaging circuits each being fed with clock pairs
each at two points on a forward route and return route of said second clock propagation
path for each outputting a signal of a delay time corresponding to a time obtained
on dividing the timing difference of each of the clock pairs into two equal portions;
wherein output signal nodes or lines of said timing averaging circuits are arranged
in a mesh-like fashion.
3. The clock controlling circuit of claim 1, wherein at least one of said first
and second timing averaging circuits is configured to issue an output signal with
a first delay time corresponding to a delay time until said output signal is issued
after one of said two clocks undergoing transition at an earlier time point is
input simultaneously to first and second inputs of said two clocks, added with
a second delay time corresponding to a time obtained on equally dividing the timing
difference T of said two clocks (T/2).
4. The clock controlling circuit of claim 1, wherein at least one of said first
and second timing averaging circuits is arranged for charging or discharging an
internal node based on one of said two input clocks undergoing transition at an
earlier time and for charging or discharging said internal node based on the other
clock undergoing transition with a delay time from said one clock, and on said
one clock;
said clock controlling circuit further comprising a buffer circuit connected
to an input end thereof to said internal node and whose output logical value is
changed when said internal node voltage exceeds or falls below a threshold voltage.
5. The clock controlling circuit of claim 1, wherein at least one of said first
and second timing averaging circuits comprises:
first and second switch elements connected in parallel across a first power source
and an internal node for being turned on and off when the first and second inputs
are at first and second values, respectively;
a third switch element connected across said internal node and a second power
source, said third switch element being fed with said first and second inputs and
being turned on when said third switch element is at said second value;
a capacitance connected across said internal node and said second power source;
and
a buffer circuit an output logical value of which is determined based on the
relative magnitudes of the potential of said internal node and a threshold value.
6. The clock controlling circuit of claim 1, wherein at least one of said first
and second timing averaging circuits comprises:
a plurality of first switch elements each connected in series across a first
power source and an internal node, said first switch elements having control terminals
fed with a first input and being turned off when said first input is at a first
value;
a plurality of second switch elements each connected in series across said internal
node and a second power source, each second switch element having its control terminal
connected to said first input and being turned on when said first input is at a
first value;
a third switch element and a fourth switch element connected in series across
said first power source and said internal node, said third switch element having
its control terminal connected to said first input, and being turned off when said
first input is at a first value, and said fourth switch element having its control
terminal connected to said second input and being turned off when said second input
is at a first value;
a fifth switch element and a sixth switch element connected in series across
said internal node and said second power source, said fifth switch element having
its control terminal connected to said second input, and being turned on when said
second input is at a first value, and said sixth switch element having its control
terminal connected to said first input and being turned on when said first input
is at said first value; and
an inverter circuit an output logical value of which is determined based on relative
magnitudes of said internal node and a threshold value.
7. The clock controlling circuit as defined in claim 6, wherein a switch element
having its control terminal connected to said first input is connected to said
first power source, a switch element having its control terminal connected to said
second input is connected to said second power source, and
wherein the numbers of the switch elements operating as loads for said first
and second inputs are equal to each other.
8. The clock controlling circuit of claim 1, wherein at least one of said first
and second timing averaging circuits comprises:
a first switch element, connected across said first power source and a first
internal node;
a first logical circuit fed with first and second input signals and having its
output end connected to a control terminal of said first switch element, said first
switch element being turned on when both said first and second input signals are
at a first value;
a second switch element and a third switch element connected in series across
said first internal node and the second power source, said second switch element
being turned off or on when said first input signal is at said first or second
value, respectively, said third switch element being turned on or off when the
output signal is at said first or second value, respectively;
a fourth switch element and a fifth switch element connected in series across
said first internal node and the second power source, said fourth switch element
being turned off or on when said second input signal is at said first or second
value, respectively, and said fifth switch element being turned on or off when
the output signal is at said first or second value, respectively;
a sixth switch element connected across said first power source and a third internal
node for inputting said first internal node to a control terminal;
a seventh switch element connected across said second power source and a second
internal node;
a second logical circuit fed with first and second input signals and having its
output end connected to a control terminal of said seventh switch element, said
seventh switch element being turned on when both said first and second input signals
are at a second value;
an eighth switch element and a ninth switch element connected in series across
said second internal node and the first power source, said eighth switch element
being turned on or off when said first input signal is at said first or second
value, respectively, said ninth switch element being turned off or on when the
output signal is at said first or second value, respectively;
a tenth switch element and an eleventh switch element connected in series across
said second internal node and the first power source, said tenth switch element
being turned on or off when said second input signal is at said first or second
value, respectively, and said eleventh switch element being turned off or on when
said output signal is at said first or second value, respectively;
a twelfth switch element connected across said second power source and said third
internal node for inputting said second internal node to a control terminal; and
an inverter circuit having its input terminal fed with said third internal node
and an output logical value of which is determined by the relative magnitudes of
said third internal node potential and a threshold value; and
wherein the clock control circuit further comprises:
a circuit means for on/off—controlling a first switch element pair made
up of said third switch element and the fifth switch element and a second switch
element pair made up of said ninth switch element and the eleventh switch element.
9. The clock controlling circuit of claim 1, wherein at least one of said first
and second timing averaging circuits comprises:
a first switch element connected across said first power source and a first internal
node;
a first logical circuit fed with first and second input signals and having its
output end connected to a control terminal of said first switch element, said first
switch element being turned on when both said first and second input signals are
at a first value;
a second switch element and a third switch element connected in series across
said first internal node and the second power source, said second switch element
being turned off or on when said first input signal is at said first or second
value, respectively, said third switch element being turned on or off when the
output signal is at said first or second value, respectively;
a fourth switch element and a fifth switch element connected in series across
said first internal node and the second power source, said fourth switch element
being turned off or on when said second input signal is at said first or second
value, respectively, said fifth switch element being turned on or off when the
output signal is at said first or second value, respectively;
a sixth switch element connected across said first power source and a third internal
node for inputting said first internal node to a control terminal;
a seventh switch element connected across said second power source and a second
internal node;
a second logical circuit fed with first and second input signals and having its
output end connected to a control terminal of said seventh switch element, said
seventh switch element being turned on when both said first and second input signals
are at a second value;
an eighth switch element and a ninth switch element connected in series across
said second internal node and the first power source, said eighth switch element
being turned on or off when said first input signal is at said first or second
value, respectively, said ninth switch element being turned off or on when an output
signal is at said first or second value, respectively;
a tenth switch element and an eleventh switch element connected in series across
said second internal node and the first power source, said tenth switch element
being turned on and off when said second input signal is at said first or second
value, respectively, said eleventh switch element being turned off or on when said
output signal is at said first or second value, respectively;
a twelfth switch element connected across said second power source and said third
internal node for inputting said second internal node to a control terminal; and
an inverter circuit having its input terminal fed with said third internal node
and an output logical value of which is determined by the relative magnitudes of
said third internal node potential and a threshold value,
wherein said output signal is issued from an output end of said inverter circuit,
and
wherein an output of a buffer circuit generating a normal output of said output
signal is connected in common to control terminals of said third switch element,
said fifth switch element, said ninth switch element and said eleventh switch element.
10. The clock controlling circuit of claim 1, wherein at least one of said first
and second timing averaging circuits comprises:
a first switch element connected across said first power source and a first internal
node;
a first logical circuit fed with first and second input signals and having its
output end connected to a control terminal of said first switch element, said first
switch element being turned on when both said first and second input signals are
at a first value;
second and third switch elements connected in series across said first internal
node and a second power source, said second switch element being turned off or
on when said first input signal is at said first or second value, respectively;
fourth and fifth switch elements connected in series across said first internal
node and second power source, said fourth switch element being turned off or on
when said second input signal is at said first or second value, respectively;
a sixth switch element connected across said first power source and a third internal
node for inputting said first internal node to a control terminal;
a seventh switch element connected across said second power source and a second
internal node;
a second logical circuit fed with first and second input signals and having its
output end connected to a control terminal of said seventh switch element, said
seventh switch element being turned on when both said first and second input signals
are at a second value;
eighth and ninth switch elements connected in series across said second internal
node and said first power source, said eighth switch element being turned on or
off when said first input signal is at said first or second value, respectively;
tenth and eleventh switch elements connected in series across said second internal
node and said first power source, said tenth switch element being turned on or
off when said second input signal is at said first or second value, respectively;
and
a twelfth switch element connected across said second power source and said third
internal node for inputting said second internal node to a control terminal; and
an inverter circuit having its input terminal fed with said third internal node,
and an output logical value of which is determined by the relative magnitudes of
said third internal node potential and a threshold value;
an output of said first logical circuit being connected to control terminals
of said ninth and eleventh switch elements;
an output of said second logical circuit being connected to control terminals
of said third and fifth switch elements.
11. A clock controlling circuit comprising:
means for receiving two clocks from a certain position on a forward route of
a first clock propagation path, and from a position on a return route corresponding
to said position on said forward route, and for outputting a first signal with
a delay time corresponding to a time obtained on division of a timing difference
of said two clocks into two equal portions, respectively;
means for receiving at one end said first signal output from means for receiving
two clocks and direction-reversing the first signal; and
means for receiving two clocks, including a first clock from a certain first
position on a forward route of said means for receiving, and a second clock from
a second position on a return route corresponding to the first position on said
forward route, and for outputting a second signal with a delay time corresponding
to a time obtained on division of a timing difference of said two clocks into two
equal portions.
12. A method for controlling a clock comprising:
receiving, at a first timing averaging circuit, two clocks from a certain position
on a forward route of a first clock propagation path, and from a position on a
return route corresponding to said position on said forward route;
outputting, from said a first timing averaging circuit, a first signal with a
delay time corresponding to a time obtained on division of a timing difference
of said two clocks into two equal portions, respectively;
receiving said first signal, at one end of a second clock propagation path, and
direction-reversing the first signal;
receiving, at a second timing averaging circuit, two clocks, including a first
clock from a certain first position on a forward route of said second clock propagation
path, and a second clock from a second position on a return route corresponding
to the first position on said forward route; and
outputting, from said a second timing averaging circuit, a second signal with
a delay time corresponding to a time obtained on division of a timing difference
of said two clocks into two equal portions.
Description
FIELD OF THE INVENTION
This invention relates to a clock controlling circuit and a clock controlling
method. More particularly, it relates to a clock controlling circuit and a clock
controlling method usable with advantage in a clock supplying circuit of a semiconductor
integrated circuit having a circuit synchronized with system clocks.
BACKGROUND OF THE INVENTION
In a semiconductor integrated circuit controlling the internal circuit in synchronism
with system clocks, preset circuit operations are executed each clock period to
control the internal circuit in its entirety. Recently, the chip size is increased
in keeping pace with the tendency towards the increasing degree of integration
and towards the higher function of the function of the semiconductor integrated
circuit. On the other hand, as the clock period becomes shorter with the increasing
operating frequency, the shortening of the delay time difference in the clock path
is presenting problems.
In order to cope with this task, there is disclosed in, for example, the JP Patent
Kokai JP-A-9-258841 a clock supplying method in which there are provided an oncoming
clock line and an outgoing clock line, these clock lines are divided into two lines
of forward and return paths, and in which the wiring delay is detected to adjust
clocks. There is disclosed a configuration comprising a receiver having first and
second input terminals at a first position on the forward path and a second position
near the first position on the forward path, respectively. The delay in the forward
path and return path is detected from these first and second input terminals to
output an average value of the delay caused in the forward and return paths.
That is, in the JP Patent Kokai JP-A-9-258841, a point A of a forward route
111, as an input, is coupled to an end of a phase detection circuit 181
through a variable delay line 171 and a variable delay line 172,
a point H of a return route 112, as an input, is coupled to the other end
of the phase detection circuit 181, the delay time of the variable delay
lines 171, 172 is variably controlled for phase adjustment, and an
output of a receiver is derived from a junction point of the variable delay lines
171, 172.
Since the delay time from the point A of the forward route 111 of the
clock propagation path up to a turning point 113 is a, the delay time from
the point A to the point H is 2a, an average value of the delay time between the
points A and H is a, the delay time from the point b of the forward route 111
of the clock transmitting line to the turning point 113 is b and the delay
time from the point B to the point G is 2b. So, the sum of the delay time (a-b)
from the input end to the point b and the delay time ((a-b)+(a-b)+2b) from the
input end to the point G is [(a-b)+((a-b)+(a-b)+2b)] is 2a, with an average value
being a. In this manner, clock signals with the corresponding phase can be obtained
without dependency on the positions of the clock propagation path.
In this manner, in the conventional method disclosed in the JP Patent Kokai JP-A-9-258841,
a clock path is direction-reversed and a delay timing of an intermediate point
between the forward and return routes is taken to adjust the delay amount of the
variable delay line in the clock path.
For adjusting the delay in this manner, a feedback circuit loop, exemplified
by a phase locked loop (PLL) or a delay lock loop (DLL), in which the phase difference
is detected by a phase detection circuit and the delay caused in the variable delay
line is varied based on the detected phase difference, is routinely used.
SUMMARY OF THE DISCLOSURE
However, the PLL or DLL, constituting a feedback circuit, presents a problem
that a period longer by about hundreds to thousands of cycles is needed until clock
stabilization is achieved.
There is also raised a problem that plural sets of the phase comparators and
delay circuit lines are needed thus increasing the circuit scale.
In view of the aforementioned problems, it is an object of the present invention
to provide a clock controlling circuit and a clock control method for a circuit
for eliminating the delay difference in the entire clock transmitting line, according
to which the delay difference may be eliminated in a shorter time than the case
where the PLL circuit or the DLL circuit is used.
It is another object of the present invention to provide a clock controlling
circuit
and a clock control method according to which a phase comparator may be eliminated
to prevent the circuit scale from increasing.
According to a first aspect of the present invention, there is provided
a clock controlling circuit comprising:
a timing difference dividing circuit for receiving a clock at a first position
on a forward route of a clock propagation path direction-reversing input clocks
fed at one end thereof, and a clock at a second position on a return route thereof
corresponding to the first position on the forward route,
the timing difference dividing circuit outputting a signal of a delay time corresponding
to a time obtained on dividing a timing difference of the two clocks by a preset
interior division ratio.
According to a second aspect of the present invention, there is provided
a clock controlling circuit comprising:
a timing difference averaging circuit for receiving a clock at a first position
on a forward route of a clock propagation path direction-reversing input clocks
fed at one end thereof, and a clock at a second position on a return route thereof
corresponding to the first position on the forward route,
the timing difference dividing circuit outputting a signal of a delay time corresponding
to a time obtained on evenly dividing a timing difference of the two clocks.
According to a third aspect of the present invention, the timing averaging
circuit is configured to issue an output signal with a delay time equal to the
sum of a first delay time until output signal is issued after one of the two input
clocks undergoing transition at an earlier time point is input simultaneously to
first and second inputs adapted for being fed with the two clocks and a second
delay time corresponding to a time (T/2) obtained on dividing the timing difference
T of said two clocks into two equal portions.
According to a fourth aspect of the present invention, there is provided
a timing averaging circuit fed with clocks from a first position on a forward route
of a clock propagation path, adapted for direction-reversing clocks frequency divided
by a frequency dividing circuit and input at an end of the clock propagation path
and from a second position on a return route thereof corresponding to the first
position on the forward route, and a multiplication circuit for multiplying an
output of the timing averaging circuit.
According to a fifth aspect of the present invention, there is provided
a clock controlling circuit comprising:
a timing averaging circuit provided with a frequency dividing function for frequency
dividing two, first and second, clocks, i.e., the first clock from a first position
on a forward route of a clock propagation path fed with input clocks at one end
and direction-reversing the input clocks and the second clock from a second position
corresponding to the first position to generate frequency divided multi-phase clocks
of plural different phases,
the timing averaging circuit outputting a signal of a delay time corresponding
to a time equally dividing a timing difference between frequency divided clocks
having a corresponding phase among clock signals obtained on frequency division
of the two clocks; and
a synthesis circuit for synthesizing plural outputs of the timing averaging circuits
into one signal and for outputting the one signal.
According to a sixth aspect of the present invention, there is provided
a clock controlling method, averages the timing difference of clocks taken from
a first position on a forward route of a clock propagation path fed with input
clocks at one end and direction-reversing the input clocks and from a second position
on a return route corresponding to the first position on the forward route to generate
a clock or clocks with matched clock timing irrespective of the clock taking positions
on the forward and return route.
Other aspects and features of the present invention are disclosed also in the
claims, the entire disclosure thereof being incorporated herein by reference thereto.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows the structure of an embodiment of the present invention.
FIG. 2 is a timing chart for illustrating the operation of the embodiment of
the present invention.
FIG. 3 shows the structure of a timing averaging circuit embodying the present invention.
FIG. 4 shows the operation of a timing averaging circuit embodying the present invention.
FIG. 5 shows the structure of a second embodiment of the present invention.
FIG. 6 shows the structure of another exemplary timing averaging circuit embodying
the present invention.
FIG. 7 shows the structure of another exemplary timing averaging circuit embodying
the present invention.
FIG. 8 shows the structure of another exemplary timing averaging circuit embodying
the present invention.
FIG. 9 shows the structure of a third embodiment of the present invention.
FIG. 10 is a timing chart for illustrating the operation of the third embodiment
of the present invention.
FIG. 11 shows an exemplary structure of a multiplication circuit of the third
embodiment of the present invention.
FIG. 12 shows an exemplary structure of a multi-phase clock multiplication circuit
shown in FIG. 11.
FIG. 13 shows an illustrative structure of the multi-phase clock multiplication circuit.
FIG. 14 is a timing chart for illustrating the operation of the multi-phase
clock multiplication circuit.
FIG. 15 shows an illustrative structure of timing difference dividing circuits
208, 209 of a four-phase clock multiplication circuit of FIG. 13.
FIG. 16 shows a structure of a fourth embodiment of the present invention.
FIG. 17 shows a structure of a timing averaging circuit provided with a frequency
dividing function.
FIG. 18 is a timing chart for illustrating the operation of the fourth embodiment
of the present invention.
FIG. 19 shows a structure of a fifth embodiment of the present invention.
FIG. 20 is a timing chart for illustrating the operation of the fifth embodiment
of the present invention.
FIG. 21 shows a structure of the fifth embodiment of the present invention.
FIG. 22 shows an exemplary structure of a conventional clock controlling circuit.
PREFERRED EMBODIMENTS OF THE INVENTION
A preferred embodiment of the present invention is explained. In its preferred
embodiment, shown in FIG. 1, the present invention includes a timing averaging
circuit which is fed with clocks from a first position on a forward route of a
clock propagation path adapted for being fed with input clocks at one end and direction-reversing
the input clocks and from a second position on a return route corresponding to
the first position on the forward route and which divides the timing difference
of these clocks into two equal portions to output the resulting clocks. The delay
time between the first position and the direction-reversing point
113
of the clock propagation path is equal to the delay time between the direction-reversing
point
113 of the clock propagation path and the second position.
The timing averaging circuit issues an output signal with a delay time equal
to the sum of a (first) delay time (Cons) until outputting of an output signal
after one of the two input clocks undergoing transition at an earlier time is input
simultaneously to the first and second input ends fed with the two clocks and a
(second) delay time corresponding to a time (T/2) obtained on dividing the timing
difference T of the two clocks into two equal portions. Namely, the present invention
does not use PLL nor DLL. The timing averaging circuit is configured so that the
internal node is charged or discharged, based on one of two input clocks that undergoes
an earlier transition and so that the internal load is charged or discharged based
on the other clock undergoing be later transition and the aforementioned one clock.
The internal node is connected to the input end. There is provided an inverting
or non-inverting buffer circuit an output logical value of which is changed when
the internal node voltage becomes higher or lower than a threshold voltage.
In its preferred embodiment of the present invention, shown in FIG. 5, input
clocks
are input from one end of a clock propagation path and branches to first and second
forward routes (
11A,
11B), with the first and second forward routes
being direction-reversed (preferably, in a crossing fashion) on an opposite end
to the said one end, with the return routes (
11C,
11D) of the first
and second routes thus direction-reversed being arranged along the forward routes
(
11A,
11B) of the second and first routes. The clock controlling
circuit includes timing averaging circuits
101,
102
for being fed with a clock from first positions (A, B) on the forward route
11A
of the first route and with a clock from the second position (C, D) on the return
route
11D of the second route for outputting a signal of delay time corresponding
to the time averaging a timing difference between the clocks in two equal portions,
and timing averaging circuits
104,
103 for
being fed with clocks from third positions E, F on a forward route
11b
of the second route and from fourth positions D, C on the return route
11C
of the second route to average out the timing difference of these clocks to output
the resulting clocks.
In a preferred embodiment of the present invention, shown in FIG. 9, there are
provided a frequency dividing circuit
14 for frequency dividing input clocks,
timing averaging circuits
101,
102,
103,
104 for being fed with clocks from first positions A, B, C and
D on a forward route of a clock propagation path adapted for being fed with clocks
frequency divided by the frequency dividing circuit, the path direction-reversing
the clocks, and second positions H, G, E and F on a return route corresponding
to the first position on the forward route, the timing averaging circuit outputting
a signal of a delay time corresponding to a time dividing a timing difference of
these clocks in two equal portions, and multiplication circuits
151,
152,
153,
154 for multiplying
an output signal from the timing averaging circuits
101,
102,
103,
104 and outputting a multiplied output signal.
In a preferred embodiment of the present invention, shown in FIG. 16, there are
provided timing averaging circuits provided with frequency dividing functions (function
units)
1001 to
1004 fed with two clocks from
first positions A, B, C and D on a forward route
111 of the clock
propagation path and from second positions H, G, F, E corresponding to the first
positions on the forward route, and synthesis circuits
161 to
164 for synthesizing plural outputs (L
1 to L
4,
K
1 to k
4, J
1 to J
4 and I
1 to I
4) of the
timing averaging circuits provided with the frequency dividing function
1001
to
1004 into one signal and for outputting the one signal.
The timing averaging circuit provided with the frequency dividing function has
first and second frequency dividing circuits
1011,
1012
for frequency dividing two clocks to output plural frequency divided clocks having
respective different phases, a plurality of timing averaging circuits
1021
to
1024 for being fed with two frequency divided clocks
of the first and the second frequency dividing circuits having corresponding phases
and a synthesis circuit
16 for synthesizing plural outputs L
1 to
L
4 of the timing averaging circuits
1021 to
1024
into one signal.
In a preferred embodiment of the present invention, shown in FIG. 19, there are
provided a frequency dividing circuit
14A for frequency dividing input clocks
for outputting frequency divided clocks of plural different phases, a plurality
of clock propagation paths
11-
1 to
11-
4 for being fed
at one end with a plurality of frequency divided clocks output from the frequency
dividing circuit, a plurality of timing averaging circuits (four TMs) for being
fed with two clocks from a first position on the forward route and from a second
position on a return route associated with the first position, for each of the
plural clock propagation paths, to output signals of delay time corresponding to
the time resulting from division of a timing difference of the two clocks into
two equal portions, and a synthesis circuit
16 for synthesizing plural outputs
of the plural timing averaging circuits (four TMs).
In a preferred embodiment of the present invention, shown in FIG. 21, there are
provided timing averaging circuits
1101 to
1104 for
being fed with two clocks from first positions A to D on a forward route of a clock
propagation path
111, and from second positions H, G, F and E on the return
route corresponding to the position on the forward route, and timing averaging
circuits
1201 to
1204 for being fed with two
clocks from a certain position on the forward route of the second clock propagation
path
1141, and from a position on the return route corresponding
to the position on the forward route.
There are also provided timing averaging circuits
1211 to
1214 for being fed with two clocks from a certain position on
a forward route of a second clock propagation path
1142, fed
with clocks output from the timing averaging circuits
1102 at
one end for direction-reversing the clocks and from a position on the return route
corresponding to the position on the forward route, timing averaging circuits
1221
to
1224 for being fed with two clocks from a certain position
on a forward route of a second clock propagation path
1143, fed
with clocks output from the timing averaging circuits
1103 at
one end for direction-reversing the clocks, and from a position on the return route
corresponding to the position on the forward route, and timing averaging circuits
1231 to
1234 for being fed with two clocks
from a certain position on a forward route of a second clock propagation path
1144,
and from a position on the return route corresponding to the position on the forward
route. The output signals of these timing averaging circuits are arranged e.g.,
in a mesh-like fashion on a two-dimensional plane of a semiconductor integrated
circuit or a printed wiring board.
A few circuit configurations of the timing averaging circuits are hereinafter
explained.
The timing averaging circuit in a preferred embodiment of the present invention
for being fed with clocks on forward and return routes of the direction-reversing
type clock propagation path, shown in FIG. 3, includes first and second switch
elements MP
1, MP
2 connected in parallel across the first power source
and an internal node and which are turned on and off when the first and second
inputs IN
1, IN
2 are at first and second values, respectively, a third
switch element MN
1 connected across the internal node N
1 and a second
power source GND, the third switch element being fed on a control terminal with
an output of a logic circuit NOR fed with the first and second inputs, and being
turned on when the first and second inputs are at the second value, a capacitance
C connected across the internal node N
1 and a second power source GND and
a buffer circuit BUT an output logical value of which is determined based on the
relative magnitudes of the potential of the internal node N
1 and the threshold value.
In a preferred embodiment of the present invention, shown in FIG. 6, the timing
averaging circuit includes a plurality of first switch elements MP
1, MP
2
connected in series across a first power source VCC and an internal node N
52,
the timing averaging circuit having its control terminal fed with a first input
IN
1 and being turned off when the first input IN
1 is at a first value,
a plurality of second switch elements MN
51, MN
52 connected in series
across the internal node N
52 and a second power source GND, each second
switch element having its control terminal connected to the first input IN
1
and being turned on when the first input IN
1 is at a first value, a third
switch element MP
53 connected in series across the first power source and
a second power source N
52, the fourth switch element having its control
terminal connected to the first input IN
1, and being turned off when the
first input IN
1 is at a first value, a fourth switch element MP
54
having its control terminal connected to the second input IN
2 and being
turned off when the second input IN
2 is at a first value, a fifth switch
element MN
54 connected in series across the internal node N
52 and
the second power source, the fifth switch element having its control terminal connected
to the first input, and being turned on when the first input is at a first value,
and a sixth switch element MN
53 having its control terminal connected to
the second input and being turned on when the second input is at the first value
and an inverter circuit INV
51 an output logical value of which is determined
based on the relative magnitudes of the internal node and a threshold value. The
switch elements MP
55, MP
56, control terminals which are connected
to the second input, are connected to the first power source, the switching elements
MN
55 MN
56, control terminals which are connected to the second input,
are connected to the second power source and the numbers of the switch elements
operating as loads for the first and second inputs are equal each other.
In a preferred embodiment of the present invention, shown in FIG. 7, the timing
averaging circuit includes a first switch element MP
61 connected across
the first power source VCC and a first internal node N
71, a first logical
circuit NAND
61 fed with first and second input signals IN
1, IN
2
from an input end and having its output end connected to a control terminal of
the first switch element MP
61, the first switch element being turned on
when both the first and second input signals are at a first value, a second switch
element MN
61 connected in series across the first internal node N
71
and the second power source GND and being turned off or on when the first input
signal is at the first or second value, respectively, a third switch element MN
62
turned on or off when an output signal OUT is at the first or second value, respectively,
a fourth switch element MN
63 connected in series across the first internal
node N
71 and the second power source and being turned off or on when the
first input signal is at the first or second value, respectively, a fifth switch
element MN
64 turned on or off when an output signal OUT is at the first
or second value, respectively, and a sixth switch element MP
66 connected
across the first power source and a third internal node N
73 for inputting
the first internal node N
71 to a control terminal.
The timing averaging circuit also includes a seventh switch element MN
65
connected across the second power source GND and the second internal node N
72,
a second logical circuit NOR
61 fed with first and second input signals
IN
1,
IN
2 and having its output end connected to a control terminal of the seventh
switch element MN
65, the seventh switch element MN
65 being turned
on when both the first and second input signals IN
1, IN
2 are at a
second value, an eighth switch element MP
64 connected in series across the
second internal node N
72 and the first power source VCC and being turned
on or off when the first input signal is at the first or second value, respectively,
a ninth switch element MP
62 turned off or on when an output signal is at
the first or second value, respectively, a tenth switch element MP
65 connected
in series across the second internal node N
72 and the first power source
VCC and being turned on and on when the second input signal is at the first or
second value, respectively, an eleventh switch element turned off or on when the
output signal is at the first or second value, respectively, a twelfth switch element
MP
63 connected across the second power source and the third internal node
for inputting the second internal node to a control terminal and an inverter circuit
INV
65 having its input terminal fed with the third internal node and an
output logical value of which is determined by the relative magnitudes of the third
internal node potential and a threshold value. The clock control circuit further
includes circuit means for on/off controlling a first switch element pair made
up of the third switch element MN
65 and the fifth switch element MN
64
and a second switch element pair made up of the ninth switch element MP
62
and the eleventh switch element MP
63.
The circuit means may, for example, be buffer circuits INV
67, INV
66
for generating normal signals of an output signal prescribed by the first and second
input signals IN
1, IN
2. An output of the buffer circuit is connected
in common to control terminals of the fifth switch element MN
65, fifth switch
element MN
64, ninth switch element MP
62 and the eleventh switch element MP
63.
In a preferred embodiment of the present invention, shown in FIG. 8, the timing
averaging circuit includes a first switch element MP
71 connected across
the first power source and a first internal node N
81, a first logical circuit
NAND
71 fed with first and second input signals and having its output end
connected to a control terminal of the first switch element MP
71, the first
switch element MP
71 being turned on when both the first and second input
signals are at a first value, second and third switch elements MN
71, MN
72
connected in series across the first internal node N
81 and the second power
source, with the second switch element MN
71 being turned off or on when
the first input signal is at the first or second value, respectively. The timing
averaging circuit also includes a sixth switch element MP
76 connected across
the first power source and a third internal node N
83 for inputting the first
internal node N
81 to a control terminal.
The timing averaging circuit also includes a seventh switch element MN
75
connected across the second power source GND and the second internal node N
82,
a second logical circuit NOR
71 fed with first and second input signals IN
1,
IN
2 and having its output end connected to a control terminal of the eleventh
switch element MP
72, MP
73, the seventh switch element being turned
on when both the first and second input signals are at a second value, eighth and
ninth switch elements MP
74, MP
72 connected in series across the second
internal node N
82 and the first power source and being turned on or off
when the first input signal is at the first or second value, respectively, a ninth
switch element turned off or on when an output signal is at the first or second
value, respectively, tenth and eleventh switch elements MP
75, MP
73
connected in series across the second internal node N
82 and the first power
source and being turned on or off when the first input signal is at the first or
second value, respectively, a twelfth switch element MN
76 connected across
the second power source and the third internal node N
83 for inputting the
second internal node to a control terminal and an inverter circuit INV
75
having its input terminal fed with the third internal node N
83 and an output
logical value of which is determined by the relative magnitudes of the third internal
node potential and a threshold value.
An output of the first logical circuit NAND
71 is connected in common to
control terminals of the ninth switch element MP
72 and the eleventh switch
element MP
73, whilst an output of the second logical circuit NOR
71
is connected in common to control terminals of the third switch element MN
72
and the fifth switch element MN
73.
In a preferred embodiment of the present invention, shown in FIG. 11, the structure
of multiplication circuits
151 to
154 includes
a frequency dividing circuit
2 for frequency dividing input clocks for generating
and outputting plural clocks of different phases (multi-phase clocks), a period
detection circuit
6 for detecting the period of the input clocks, and a
multi-phase clock multiplication circuit
5 fed with multi-phase clocks output
from the frequency dividing circuit for generating the multi-phase clocks as multiplied
clocks. The multi-phase clock multiplication circuit includes a plurality of timing
difference dividing circuits
4a outputting signals corresponding
to the divided timing difference between two inputs and a plurality of multiplication
circuits
4b for multiplying and outputting outputs of two the timing
difference dividing circuits. The plural timing difference dividing circuits includes
a timing difference dividing circuit fed with the same phase clocks and a timing
difference dividing circuit fed with outputs of two the timing difference dividing circuits.
In a preferred embodiment of the present invention, shown in FIG. 13, there are
provided 2n timing difference dividing circuits for outputting signals obtained
on dividing the timing difference of two input timings, the 2i-1st timing difference
dividing circuit
208,
210,
212,
214, where 1≦i≦n,
is fed with an ith same clock as the two inputs, the 2ith timing difference dividing
circuit (
209,
211,
213,
215), where 1≦i≦n,
is fed with the ith clock and (i+1 mod n)th clock, where mod denotes a remainder
operation such that i+1 mod n means a remainder obtained on dividing I+1 with n,
there being further provided 2n pulse width correction circuits
216 to
223
fed with an output of a Jth timing difference dividing circuit, where 1≦J≦2n,
and with an output of a timing difference dividing circuit, as input, where J+2
mod n means a remainder resulting from division of J+2 by n, and n multiplication
circuits
224 to
227 fed with an output of a Kth pulse width correction
circuit, where 1≦K≦n, and an output of the (K+n)th pulse width correction
circuit, as inputs.
In a preferred embodiment of the present invention, shown in FIG. 15, the timing
difference dividing circuit includes a logical circuit NOR
14 fed as input
with first and second input signals and which sets the internal node to the potential
of a first power source when the first and second input signals are at a first
value, and a buffer circuit or an inverter circuit INV
15 for changing the
output logical value depending on the relative magnitudes of the potential of the
internal node as an output of the logical circuit and a threshold value, a plurality
of series connected switch elements and capacitances are connected in parallel
across the internal node and the second power source (MN
51 and CAP
51,
MN
52 and CAP
52, and MN
53 and CAP
53). The capacitance
to be added to the internal node being determined by period control signal coupled
to a control terminal of the switch.
By providing a semiconductor integrated circuit with the clock control circuit
according to the present invention, for supplying clocks to a clock synchronization
circuit, phase-matched clocks can be supplied over the entire clock propagation path.
For explanation of the above-described embodiments of the present invention in
more detail, certain preferred embodiments of the present invention will be hereinafter
explained with reference to the drawings.
FIG. 1 shows a structure of a preferred embodiment of the present invention.
In the preferred embodiment of the present invention, shown in FIG. 1, a circuit
comprised of a clock propagation path, folded on itself to constitute a forward
route and a return route in which the timing at a mid point of the forward and
return routes is taken to adjust the delay induced in the clock path, includes
a timing averaging circuit for averaging the timing difference between respective
pulses of the clock signals.
On the forward route
111 of the clock propagation path, the
delay time from a point A to a reversing point
113 is a, the
delay time from a point B to the reversing point
113 is b, the
delay time from a point C to the reversing point
113 is c, and
the delay time from a point D to the reversing point
113 is d.
On the return route
112 of the clock propagation path, a point E is at the
delay time d from reversing point
113, a point F is at the delay
time c from reversing point
113, a point G is at the delay time
b from reversing point
113, and a point H is at the delay time
a from reversing point
113.
The clocks input from an input buffer
12 to the forward route
111
of the clock propagation path is turned back (direction-reversed) at the reversing
point
113 and propagate on the return route
112. Two clock
signals at points A and H are input to a timing averaging circuit
101,
from which a
