Compensation circuit and method for reducing intersymbol interference products caused by signal transmission via dispersive media Number:7,130,366 from the United States Patent and Trademark Office (PTO) owispatent

Title: Compensation circuit and method for reducing intersymbol interference products caused by signal transmission via dispersive media

Abstract: A compensation circuit and method for reducing ISI products within an electrical data signal corresponding to a detected data signal received via a signal transmission medium introduces distinct compensation effects for individual ISI products within the electrical data signal. Distinct data signal components within the detected data signal and corresponding to such ISI products can be selectively and individually compensated, thereby producing a compensated data signal in which each selected one of such individual data signal components is substantially removed. Individual data signal components or selected combinations of data signal components can be compensated as desired.

Patent Number: 7,130,366 Issued on 10/31/2006 to Phanse,   et al.

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Inventors:	Phanse; Abhijit (Santa Clara, CA), Shanbhag; Abhijit G. (San Jose, CA)
Assignee:	Scintera Networks, Inc. (San Jose, CA)
Appl. No.:	10/290,674
Filed:	November 8, 2002

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Current U.S. Class:	375/350 ; 375/229; 375/230; 375/231; 375/232; 375/233; 375/234
Current International Class:	H04B 1/00 (20060101)
Field of Search:	375/229-236,340,341,346,348,350 714/795

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References Cited [Referenced By]

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U.S. Patent Documents

	5127051		June 1992		Chan et al.
	5191462		March 1993		Gitlin et al.
	5561687		October 1996		Turner
	5692011		November 1997		Nobakht et al.
	5748674		May 1998		Lim
	6009120		December 1999		Nobakht
	6012161		January 2000		Ariyavisitakul et al.
	6088389		July 2000		Larsson
	6185250		February 2001		Wang et al.
	6226323		May 2001		Tan et al.
	6240133		May 2001		Sommer et al.
	6366613		April 2002		Sommer et al.
	6438164		August 2002		Tan et al.
	6563812		May 2003		De
	6668014		December 2003		Endres et al.

Other References

Merriam-Webster's Collegiate Dictionary (Tenth Edition, 2001) pp. 207 and 265. cited by examiner . John G. Proakis, Digital Communications Fourth Edition, Chapter 10, 2001, McGraw-Hill Higher Education, New York, NY. cited by other . John G. Proakis, Digital Communications Fourth Edition, Chapter 11, 2001, McGraw-Hill Higher Education, New York, NY. cited by other.

Primary Examiner: Tran; Khanh
Assistant Examiner: Odom; Curtis
Attorney, Agent or Firm: Vedder, Price, Kaufman & Kammholz P.C.

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Parent Case Text

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RELATED INVENTIONS

This application is a continuation-in-part of U.S. application Ser. No. 10/117,293, filed Apr. 5, 2002.

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Claims

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What is claimed is:

1. An apparatus including a compensation circuit for reducing intersymbol interference (ISI) products within data signal, comprising: an input terminal that conveys an input data signal including a first plurality of ISI products and corresponding to a detected data signal received via a signal transmission medium; an output terminal that conveys an output data signal including a second plurality of ISI products which is smaller than said first plurality of ISI products; first adaptive equalization circuitry, coupled to said input terminal, that adaptively equalizes said input data signal to provide a first equalized signal; equalization and processing circuitry, coupled to said input terminal, that selectively equalizes and processes said input data signal to provide a first processed signal; signal combining circuitry, coupled to said first adaptive equalization circuitry, that receives and selectively combines a second processed signal and said first equalized signal to provide a resultant signal; and output processing circuitry, coupled to said equalization and processing circuitry, said signal combining circuitry and said output terminal, that receives said first processed signal and in response thereto receives and processes said resultant signal to provide said output data signal and said second processed signal, and includes first signal slicing circuitry, coupled between said signal combining circuitry and said output terminal, that receives said first processed signal and in response thereto receives and slices said resultant signal to provide a first sliced signal as said output data signal, and nonlinear processing circuitry, coupled between said output terminal and said signal combining circuitry, that nonlinearly processes at least a portion of said first sliced signal to provide said second processed signal.

2. The apparatus of claim 1, wherein said first signal slicing circuitry comprises adaptive signal slicing circuitry.

3. The apparatus of claim 1, wherein said first adaptive equalization circuitry comprises linear equalization circuitry.

4. The apparatus of claim 1, wherein said first adaptive equalization circuitry comprises fractionally-spaced transversal equalization circuitry.

5. The apparatus of claim 1, wherein said equalization and processing circuitry comprises: second adaptive equalization circuitry, coupled to said input terminal, that adaptively equalizes said input data signal to provide a second equalized signal; and second signal slicing circuitry, coupled to said second adaptive equalization circuitry, that slices said second equalized signal to provide a second sliced signal as said first processed signal.

6. The apparatus of claim 5, wherein said second adaptive equalization circuitry comprises linear equalization circuitry.

7. The apparatus of claim 5, wherein said second adaptive equalization circuitry comprises fractionally-spaced transversal equalization circuitry.

8. The apparatus of claim 5, wherein said equalization and processing circuitry comprises decision feedback equalization circuitry, coupled to said input terminal, that adaptively equalizes said input data signal to provide said first processed signal.

9. An apparatus including a compensation circuit for reducing intersymbol interference (ISI) products within a data signal, comprising: an input terminal that conveys an input data signal including a first plurality of ISI products and corresponding to a detected data signal received via a signal transmission medium; an output terminal that conveys an output data signal including a second plurality of ISI products which is smaller than said first plurality of ISI products; first adaptive equalization circuitry, coupled to said input terminal, that adaptively equalizes said input data signal to provide a first equalized signal; equalization and processing circuitry, coupled between said input and output terminals, that selectively equalizes and processes said input data signal and at least a portion of said output data signal to provide first and second processed signals, and includes second adaptive equalization circuitry, coupled to said input terminal, that adaptively equalizes said input data signal to provide a second equalized signal, first signal slicing circuitry, coupled to said second adaptive equalization circuitry, that slices said second equalized signal to provide a first sliced signal as said first processed signal, and nonlinear processing circuitry, coupled between said first signal slicing circuitry and said output terminal, that nonlinearly processes said first sliced signal and said at least a portion of said output data signal to provide said second processed signal; signal combining circuitry, coupled to said first adaptive equalization circuitry and said equalization and processing circuitry, that receives and selectively combines said second processed signal and said first equalized signal to provide a resultant signal; and output processing circuitry, coupled to said equalization and processing circuitry, said signal combining circuitry and said output terminal, that receives said first processed signal and in response thereto receives and processes said resultant signal to provide said output data signal.

10. The apparatus of claim 9, wherein said second adaptive equalization circuitry comprises linear equalization circuitry.

11. The apparatus of claim 9, wherein said second adaptive equalization circuitry comprises fractionally-spaced transversal equalization circuitry.

12. The apparatus of claim 9, wherein said first adaptive equalization circuitry comprises linear equalization circuitry.

13. The apparatus of claim 9, wherein said first adaptive equalization circuitry comprises fractionally-spaced transversal equalization circuitry.

14. The apparatus of claim 9, wherein said output processing circuitry comprises second signal slicing circuitry, coupled to said equalization and processing circuitry, said signal combining circuitry and said output terminal, that in response to said first processed signal slices said resultant signal to provide a second sliced signal as said output data signal.

15. An apparatus including a compensation circuit for reducing intersymbol interference (ISI) products within a data signal, comprising: an input terminal that conveys an input data signal including a first plurality of ISI products and corresponding to a detected data signal received via a signal transmission medium; an output terminal that conveys an output data signal including a second plurality of ISI products which is smaller than said first plurality of ISI products; first adaptive equalization circuitry, coupled to said input terminal, that adaptaively equalizes said input data signal to provide a first equalized signal; equalization and processing circuitry, coupled between said input and output terminals, that selectively equalizes and processes said input data signal and at least a portion of said output data signal to provide first and second processed signals, and includes decision feedback equalization circuitry, coupled to said input terminal, that adaptively equalizes said input data signal to provide said first processed signal, and nonlinear processing circuitry, coupled between said decision feedback equalization circuitry and said output terminal, that nonlinearly processes said first processed signal and said at least a portion of said output data signal to provide said second processed signal; signal combining circuitry, coupled to said first adaptive equalization circuitry and said equalization and processing circuitry, that receives and selectively combines said second processed signal and said first equalized signal to provide a resultant signal; and output processing circuitry, coupled to said equalization and processing circuitry, said signal combining circuitry and said output terminal, that receives said first processed signal and in response thereto receives and processes said resultant signal to provide said output data signal.

16. The apparatus of claim 15, wherein said first adaptive equalization circuitry comprises linear equalization circuitry.

17. The apparatus of claim 15, wherein said first adaptive equalization circuitry comprises fractionally-spaced transversal equalization circuitry.

18. The apparatus of claim 15, wherein said output processing circuitry comprises signal slicing circuitry, coupled to said equalization and processing circuitry, said signal combining circuitry and said output terminal, that in response to said first processed signal slices said resultant signal to provide a sliced signal as said output data signal.

19. An apparatus including a compensation circuit for reducing intersymbol interference (ISI) products within a data signal, comprising: an input terminal that conveys an input data signal including a first plurality of ISI products and corresponding to a detected data signal received via a signal transmission medium; an output terminal that conveys an output data signal including a second plurality of ISI products which is smaller than said first plurality of ISI products; first adaptive equalization circuitry, coupled to said input terminal, that adaptively equalizes said input data signal to provide a first equalized signal; equalization and processing circuitry, coupled between said input and output terminals, that selectively equalizes and processes said input data signal and at least a portion of said output data signal to provide first and second processed signals; signal combining circuitry, coupled to said first adaptive equalization circuitry and said equalization and processing circuitry, that receives and selectively combines said second processed signal and said first equalized signal to provide a resultant signal; and output processing circuitry, coupled to said equalization and processing circuitry, said signal combining circuitry and said output terminal, that receives said first processed signal and in response thereto receives and processes said resultant signal to provide said output data signal, and includes signal slicing circuitry, coupled to said equalization and processing circuitry, said signal combining circuitry and said output terminal, that in response to said first processed signal slices said resultant signal to provide a sliced signal as said output data signal.

20. The apparatus of claim 19, wherein said signal slicing circuitry comprises adaptive signal slicing circuitry.

21. An apparatus including a compensation circuit for reducing intersymbol interference (ISI) products within a data signal, comprising: an input terminal that conveys an input data signal including a first plurality of ISI products and corresponding to a detected data signal received via a signal transmission medium; an output terminal that conveys an output data signal including a second plurality of ISI products which is smaller than said first plurality of ISI products; equalization and processing circuitry, coupled to said input terminal, that selectively equalizes and processes said input data signal to provide a first processed signal; signal combining circuitry, coupled to said input terminal, that receives and selectively combines a second processed signal and said input data signal to provide a resultant signal; and output processing circuitry, coupled to said equalization and processing circuitry, said signal combining circuitry and said output terminal, that receives said first processed signal and in response thereto receives and processes said resultant signal to provide said output data signal and said second processed signal, and includes first signal slicing circuitry, coupled to said equalization and processing circuitry, said signal combining circuitry and said output terminal, that receives said first processed signal and in response thereto receives and slices said resultant signal to provide a first sliced signal as said output data signal, and nonlinear processing circuitry, coupled between said output terminal and said signal combining circuitry, that nonlinearly processes at least a portion of said first sliced signal to provide said second processed signal.

22. The apparatus of claim 21, wherein said first signal slicing circuitry comprises adaptive signal slicing circuitry.

23. The apparatus of claim 21, wherein said equalization and processing circuitry comprises: adaptive equalization circuitry, coupled to said input terminal, that adaptively equalizes said input data signal to provide an equalized signal; and second signal slicing circuitry, coupled to said adaptive equalization circuitry, that slices said equalized signal to provide a second sliced signal as said first processed signal.

24. The apparatus of claim 23, wherein said adaptive equalization circuitry comprises linear equalization circuitry.

25. The apparatus of claim 23, wherein said adaptive equalization circuitry comprises fractionally-spaced transversal equalization circuitry.

26. The apparatus of claim 21, wherein said equalization and processing circuitry comprises decision feedback equalization circuitry, coupled to said input terminal, that adaptively equalizes said input data signal to provide said first processed signal.

27. An apparatus including a compensation circuit for reducing intersymbol interference (ISI) products within a data signal, comprising: an input terminal that conveys an input data signal including a first plurality of ISI products and corresponding to a detected data signal received via a signal transmission medium; an output terminal that conveys an output data signal including a second plurality of ISI products which is smaller than said first plurality of ISI products; equalization and processing circuitry, coupled between said input and output terminals, that selectively equalizes and processes said input data signal and at least a portion of said output data signal to provide first and second processed signals, and includes adaptive equalization circuitry, coupled to said input terminal, that adaptively equalizes said input data signal to provide an equalized signal, first signal slicing circuitry, coupled to said adaptive equalization circuitry, that slices said equalized signal to provide a first sliced signal as said first processed signal, and nonlinear processing circuitry, coupled between said first signal slicing circuitry and said output terminal, that nonlinearly processes said first sliced signal and said at least a portion of said output data signal to provide said second processed signal; signal combining circuitry, coupled to said input terminal and said equalization and processing circuitry, that receives and selectively combines said second processed signal and said input data signal to provide a resultant signal; and output processing circuitry, coupled to equalization and processing circuitry, said signal combining circuitry and said output terminal, that receives said first processed signal and in response thereto receives and processes said resultant signal to provide said output data signal.

28. The apparatus of claim 27, wherein said adaptive equalization circuitry comprises linear equalization circuitry.

29. The apparatus of claim 27, wherein said adaptive equalization circuitry comprises fractionally-spaced transversal equalization circuitry.

30. The apparatus of claim 27, wherein said output processing circuitry comprises second signal slicing circuitry, coupled between said signal combining circuitry and said output terminal, that slices said resultant signal to provide a second sliced signal as said output data signal.

31. An apparatus including a compensation circuit for reducing intersymbol interference (ISI) products within a data signal, comprising: an input terminal that conveys an input data signal including first plurality of ISI products and corresponding to a detected data signal received via a signal transmission medium; an output terminal that conveys an output data signal including a second plurality of ISI products which is smaller than said first plurality of ISI products; equalization and processing circuitry, coupled between said input and output terminals, that selectively equalizes and processes said input data signal and at least a portion of said output data signal to provide first and second processed signals, and includes decision feedback equalization circuitry, coupled to said input terminal, that adaptively equalizes said input data signal to provide said first processed signal, and nonlinear processing circuitry, coupled between said decision feedback equalization circuitry and said output terminal, that nonlinearly processes said first processed signal and said at least a portion of said output data signal to provide said second processed signal; signal combining circuitry, coupled to said input terminal and said equalization and processing circuitry, that receives and selectively combines said second processed signal and said input data signal to provide a resultant signal; and output processing circuitry, coupled to equalization and processing circuitry, said signal combining circuitry and said output terminal, that receives said first processed signal and in response thereto receives and processes said resultant signal to provide said output data signal.

32. The apparatus of claim 31, wherein said output processing circuitry comprises signal slicing circuitry, coupled between said signal combining circuitry and said output terminal, that slices said resultant signal to provide a sliced signal as said output data signal.

33. An apparatus including a compensation circuit for reducing intersymbol interference (ISI) products within a data signal, comprising: input means for conveying an input data signal including a first plurality of ISI products and corresponding to a detected data signal received via a signal transmission medium; output means for conveying an output including a second plurality of ISI products which is smaller than said first plurality of ISI products; first adaptive equalizer means for adaptively equalizing said input data signal to provide a first equalized signal; equalizer and processor means for selectively equalizing and processing said input data signal to provide a first processed signal; signal combiner means for receiving and selectively combining a second processed signal and said first equalized signal to provide a resultant signal; and output processor means for receiving said first processed signal and in response thereto receiving and processing said resultant signal to provide said output data signal and said second processed signal, and including signal slicer means for slicing said resultant signal in response to said first processed signal to provide a sliced signal as said output data signal, and nonlinear processor means for nonlinearly processing at least a portion of said sliced signal to provide said second processed signal.

34. The apparatus of claim 33, wherein said equalizer and processor means comprises: second adaptive equalizer means for adaptively equalizing said input data signal to provide a second equalized signal; and signal slicer means for slicing said second equalized signal to provide a sliced signal as said first processed signal.

35. The apparatus of claim 33, wherein said equalizer and processor means comprises decision feedback equalizer means for adaptively equalizing said input data signal to provide said first processed signal.

36. An apparatus including a compensation circuit for reducing intersymbol interference (ISI) products within a data signal, comprising: input means for conveying an input data signal including a first plurality of ISI products and corresponding to a detected data signal received via a signal transmission medium; output means for conveying an output data signal including a second plurality of ISI products which is smaller than said first plurality of ISI products; first adaptive equalizer means for adaptively equalizing said input data signal to provide a first equalized signal; equalizer and processor means for selectively equalizing and processing said input data signal and at least a portion of said output data signal to provide first and second processed signals, and including second adaptive equalizer means for adaptively equalizing said input data signal to provide a second equalized signal, signal slicer means for slicing said second equalized signal to provide a sliced signal as said first processed signal, and nonlinear processor means for nonlinearly processing said sliced signal and said at least a portion of said output data signal to provide said second processed signal; signal combiner means for receiving and selectively combining said second processed signal and said first equalized signal to provide a resultant signal; and output processor means for receiving said first processed signal and in response thereto receiving and processing said resultant signal to provide said output data signal.

37. An apparatus including a compensation circuit for reducing intersymbol interference ISI products within a data signal, comprising: input means for conveying an input data signal including a first plurality of ISI products and corresponding to a detected data signal received via a signal transmission medium; output means for conveying an output data signal including a second plurality of ISI products which is smaller than said first plurality of ISI products; first adaptive equalizer means for adaptively equalizing said input data signal to provide a first equalized signal; equalizer and processor means for selectively equalizing and processing said input data signal and at least a portion of said data signal to provide first and second processed signals, and including decision feedback equalizer means for adaptively equalizing said input data signal to provide said first processed signal, and nonlinear processor means for nonlinearly processing said first processed signal and said at least a portion of said output data signal to provide said second processed signal; signal combiner means for receiving and selectively combining said second processed signal and said first equalized signal to provide a resultant signal; and output processor means for receiving said first processed signal and in response thereto receiving and processing said resultant signal to provide said output data signal.

38. An apparatus including a compensation circuit for reducing intersymbol interference (ISI) products within a data signal, comprising: input means for conveying an input signal including a first plurality of ISI products and corresponding to a detected data signal received via a signal transmission medium; output means for conveying an output data signal including a second plurality of ISI products which is smaller than said first plurality of ISI products; first adaptive equalizer means for adaptively equalizing said input data signal to provide a first equalized signal; equalizer and processor means for selectively equalizing and processing said input data signal and at least a portion of said output data signal to provide first and second processed signals; signal combiner means for receiving and selectively combining said second processed signal and said first equalized signal to provide a resultant signal; and output processor means for receiving said first processed signal and in response thereto receiving and processing said resultant signal to provide said output data signal, and including signal slicer means for slicing said resultant signal in response to said first processed signal to provide a sliced signal as said output data signal.

39. An apparatus including a compensation circuit for reducing intersymbol interference (ISI) products within a data signal, comprising: input means for conveying an input data signal including a first plurality of ISI products and corresponding to a detected data signal received via a signal transmission medium; output means for conveying data signal including a second plurality of ISI products which is smaller than said first plurality of ISI products; equalizer and processor means for selectively equalizing and processing said input data signal to provide a first processed signal; signal combiner means for receiving and selectively combining a second processed signal and said input data signal to provide a resultant signal; and output processor means for receiving said first processed signal and in response thereto receiving and processing said resultant signal to provide said output data signal and said second processed signal, and including first signal slicer means for slicing said resultant signal in response to said first processed signal to provide a first sliced signal as said output data signal, and nonlinear processor means for nonlinearly processing at least a portion of said first sliced signal to provide said second processed signal.

40. The apparatus of claim 39, wherein said equalizer and processor means comprises: adaptive equalizer means for adaptively equalizing said input data signal to provide an equalized signal; and second signal slicer means for slicing said equalized signal to provide a second sliced signal as said first processed signal.

41. The apparatus of claim 39, wherein said equalizer and processor means comprises decision feedback equalizer means for adaptively equalizing said input data signal to provide said processed signal.

42. An apparatus including a compensation circuit for reducing intersymbol interference (ISI) products within a data signal, comprising: input means for conveying an input data signal including a first plurality of ISI products and corresponding to a detected data signal received via a signal transmission medium; output means for conveying an output data signal including a second plurality of ISI products which is smaller than said first plurality of ISI products; equalizer and processor means for selectively equalizing and processing said input data signal and at least a portion of said output data signal to provide first and second processed signals, and including adaptive equalizer means for adaptively equalizing said input data signal to provide an equalized signal, signal slicer means for slicing said equalized signal to provide a sliced signal as said first processed signal, and nonlinear processor means for nonlinearly processing said sliced signal and said at least a portion of said output data signal to provide said second processed signal; signal combiner means for receiving and selectively combining said second processed signal and said input data signal to provide a resultant signal; and output processor means for receiving said first processed signal and in response thereto receiving and processing said resultant signal to provide said output data signal.

43. An apparatus including a compensation circuit for reducing intersymbol interference (ISI) products within a data signal, comprising: input means for conveying an input data signal including a first plurality of ISI products corresponding to a detected data signal received via a signal transmission medium; output means for conveying an output data signal including a second plurality of ISI products which is smaller than said first plurality of ISI products; equalizer and processor means for selectively equalizing and processing said input data signal and at least a portion of said output data signal to provide first and second processed signals, and including decision feedback equalizer means for adaptively equalizing said input data signal to provide said first processed signal, and nonlinear processor means for nonlinearly processing said first processed signal and said at least a portion of said output data signal to provide said second processed signal; signal combiner means for receiving and selectively combining said second processed signal and said input data signal to provide a resultant signal; and output processor means for said first processed signal and in response thereto receiving and processing said resultant signal to provide said output data signal.

44. A compensation method for reducing intersymbol interference (ISI) products within a data signal, comprising: receiving an input data signal including a first plurality of ISI products and corresponding to a detected data signal received via a signal transmission medium; adaptively equalizing said input data signal to provide a first equalized signal; selectively equalizing and processing said input data signal to provide a first processed signal; selectively combining a second processed signal and said first equalized signal to provide a resultant signal; and processing said resultant signal in response to said first processed signal to provide said second processed signal and an output data signal including a second plurality of ISI products which is smaller than said first plurality of ISI products by slicing said resultant signal in response to said first processed signal to provide a first sliced signal as said output data signal, and nonlinearly processing at least a portion of said first sliced signal to provide said second processed signal.

45. The method of claim 44, wherein said selectively equalizing and processing said input data signal to provide said first processed signal comprises: adaptively equalizing said input data signal to provide a second equalized signal; and slicing said second equalized signal to provide a second sliced signal as said first processed signal.

46. A compensation method for reducing intersymbol interference (ISI) products within a data signal comprising: receiving an input data signal including a first plurality of ISI products and corresponding to a detected data signal received via a signal transmission medium; adaptively equalizing said input data signal to provide a first equalized signal; selectively equalizing and processing said input data signal and at least a portion of said output data signal to provide first and second processed signals by adaptively equalizing said input data signal to provide a second equalized signal, slicing said second equalized signal to provide a sliced signal as said first processed signal, and nonlinearly processing said sliced signal and said at least a portion of said output data signal to provide said second processed signal; selectively combining said second processed signal and said first equalized signal to provide a resultant signal; and processing said resultant signal in response to said first processed signal to provide an output data signal including a second plurality of ISI products which is smaller than said first plurality of ISI products.

47. A compensation method for reducing intersymbol interference (ISI) products within a data signal comprising: receiving an input data signal in including a first plurality of ISI products and corresponding to a detected data signal received via a signal transmission medium; adaptively equalizing said input data signal to provide a first equalized signal; selectively equalizing and processing said input data signal and at least a portion of said output data signal to provide first and second processed signals by adaptively equalizing said input data signal to provide said first processed signal, and nonlinearly processing said first processed signal and said at least a portion of said output data signal to provide said second processed signal; selectively combining said second processed signal and said first equalized signal to provide a resultant signal; and processing said resultant signal in response to said first processed signal to provide an output data signal including a second plurality of ISI products which is smaller than said first plurality of ISI products.

48. A compensation method for reducing intersymbol interferenee (ISI) products within a data signal; and receiving an input data signal including a first plurality of ISI products and corresponding to a detected data signal received via a signal transmission medium; adaptively equalizing said input data signal to provide a first equalized signal; selectively equalizing and processing said input data signal and at least a portion of said output data signal to provide first and second processed signals; selectively combining said second processed signal and said first equalized signal to provide a resultant signal; and processing said resultant signal in response to said first processed signal to provide an output data signal including a second plurality of ISI products which is smaller than said first plurality of ISI products by slicing said resultant signal in response to said first processed signal to provide a sliced signal as said output data signal.

49. A compensation method for reducing intersymbol interference (ISI) products within a data signal comprising: receiving an input data signal including a first plurality of ISI products and corresponding to a detected data signal received via a signal transmission medium; selectively equalizing and processing said input data signal to provide a first processed signal; selectively combining a second processed signal and said input data signal to provide a resultant signal; and processing said resultant signal in response to said first processed signal to provide said second processed signal and an output data signal including a second plurality of ISI products which is smaller than said first plurality of ISI products by slicing said resultant signal in response to said first processed signal to provide a first sliced signal as said output data signal, and nonlinearly processing at least a portion of said first sliced signal to provide said second processed signal.

50. The method of claim 49, wherein said selectively equalizing and processing said input data signal to provide said first processed signal comprises: adaptively equalizing said input data signal to provide an equalized signal; and slicing said equalized signal to provide a second sliced signal as said first processed signal.

51. A compensation method for reducing intersymbol interference (ISI) products within a data signal, comprising: receiving an input data signal including a first plurality of ISI products and corresponding to a detected data signal received via a signal transmission medium; selectively equalizing and processing said input data signal and at least a portion of said output data signal to provide first and second processed signals by adaptively equalizing said input data signal to provide an equalized signal, slicing said equalized signal to provide a sliced signal as said first processed signal, and nonlinearly processing said sliced signal and said at least a portion of said output data signal to provide said second processed signal; selectively combining said second processed signal and said input data signal to provide a resultant signal; and processing said resultant signal in response to said first processed signal to provide an output data signal including a second plurality of ISI products which is smaller than said first plurality of ISI products.

52. A compensation method for reducing intersymbol interference (ISI) products within a data signal, comprising: receiving an input data signal including a first plurality of ISI products and corresponding to a detected data signal received via a signal transmission medium; selectively equalizing and processing said input data signal and at least a portion of said output data signal to provide first and second processed signals by adaptively equalizing said input data signal to provide said first processed signal, and nonlinearly processing said first processed signal and said at least a portion of said output data signal to provide said second processed signal; selectively combining said second processed signal and said input data signal to provide a resultant signal; and processing said resultant signal in response to said first processed signal to provide an output data signal including a second plurality of ISI products which is smaller than said first plurality of ISI products.

53. A interference (ISI) products within a data signal, comprising: receiving an input data signal including a first plurality of ISI products and corresponding to a detected data signal received via a signal transmission medium; selectively equalizing and processing said input data signal and at least a portion of said output data signal to provide first and second processed signals; selectively combining said second processed signal and said input data signal to provide a resultant signal; and processing said resultant signal in response to said first processed signal to provide an output data signal including a second plurality of ISI products which is smaller than said first plurality of ISI products by slicing said resultant signal to provide a sliced signal as said output data signal.

54. An apparatus including a compensation circuit for reducing intersymbol interference (ISI) products within a data signal, comprising: an input terminal that conveys an input data signal including a first plurality of ISI products and corresponding to a detected data signal received via a signal transmission medium; an output terminal that conveys an output data signal including a second plurality of ISI products which is smaller than said first plurality of ISI products; adaptive equalization circuitry, coupled to said input terminal, that adaptively equalizes said input data signal to provide an equalized signal; first signal combining circuitry, coupled to said adaptive equalization circuitry, that receives and selectively combines a feedback signal and said equalized signal to provide an intermediate signal; first signal slicing circuitry, coupled to said first signal combining circuitry, that slices said intermediate signal to provide a first sliced signal; first intermediate processing circuitry, coupled to said first signal slicing circuitry and said first signal combining circuitry, that processes at least one of said first sliced signal and at least a portion of said output data signal to provide said feedback signal; second intermediate processing circuitry, coupled between said first signal slicing circuitry and said output terminal, that processes said first sliced signal and another portion of said output data signal to provide a first processed signal; second signal combining circuitry, coupled to said input terminal and said second intermediate processing circuitry, that receives and selectively combines said first processed signal, a second processed signal and said input data signal to provide a resultant signal; and output processing circuitry, coupled between said second signal combining circuitry and said output terminal, that processes said resultant signal to provide said output data signal and said second processed signal.

55. The apparatus of claim 54, wherein said adaptive equalization circuitry comprises linear equalization circuitry.

56. The apparatus of claim 54, wherein said first intermediate processing circuitry comprises decision feedback equalization circuitry.

57. The apparatus of claim 54, wherein said output processing circuitry comprises: second signal slicing circuitry, coupled between said second signal combining circuitry and said output terminal, that slices said resultant signal to provide a second sliced signal as said output data signal; and further processing circuitry, coupled between said output terminal and said second signal combining circuitry, that processes at least a portion of said second sliced signal to provide said second processed signal.

58. The apparatus of claim 57, wherein said second signal slicing circuitry comprises adaptive signal slicing circuitry.

59. The apparatus of claim 58, wherein said adaptive equalization circuitry comprises linear equalization circuitry.

60. The apparatus of claim 58, wherein said first intermediate processing circuitry comprises decision feedback equalization circuitry.

61. An apparatus including a compensation circuit for reducing intersymbol interference (ISI) products within a data signal, comprising: an input terminal that conveys an input data signal including a first plurality of ISI products and corresponding to a detected data signal received via a signal transmission medium; an output terminal that conveys an output data signal including a second plurality of ISI products which is smaller than said first plurality of ISI products; adaptive equalization circuitry, coupled to said input terminal, that adaptively equalizes said input data signal to provide an equalized signal; first signal combining circuitry, coupled to said adaptive equalization circuitry, that receives and selectively combines a feedback signal and said equalized signal to provide an intermediate signal; first signal slicing circuitry, coupled to said first signal combining circuitry, that slices said intermediate signal to provide a first sliced signal; first intermediate processing circuitry, coupled to said first signal slicing circuitry and said first signal combining circuitry, that processes at least one of said first sliced signal and at least a portion of said output data signal to provide said feedback signal; second intermediate processing circuitry, coupled between said first signal slicing circuitry and said output terminal, that processes said first sliced signal and another portion of said output data signal to provide a processed signal; second signal combining circuitry, coupled to said input terminal and said adaptive equalization circuitry, that receives and selectively combines said processed signal and said input data signal to provide a resultant signal; and output processing circuitry, coupled between said second signal combining circuitry and said output terminal, that processes said resultant signal to provide said output data signal.

62. The apparatus of claim 61, wherein said adaptive equalization circuitry comprises linear equalization circuitry.

63. The apparatus of claim 61, wherein said first intermediate processing circuitry comprises decision feedback equalization circuitry.

64. The apparatus of claim 61, wherein said output processing circuitry comprises second signal slicing circuitry, coupled between said second signal combining circuitry and said output terminal, that slices said resultant signal to provide a second sliced signal as said output data signal.

65. The apparatus of claim 64, wherein said second signal slicing circuitry comprises adaptive signal slicing circuitry.

66. The apparatus of claim 65, wherein said adaptive equalization circuitry comprises linear equalization circuitry.

67. The apparatus of claim 65, wherein said first intermediate processing circuitry comprises decision feedback equalization circuitry.

68. An apparatus including a compensation circuit for reducing intersymbol interference (ISI) products within a data signal, comprising: an input terminal that conveys an input data signal including a first plurality of ISI products and corresponding to a detected data signal received via a signal transmission medium; an output terminal that conveys an output data signal including a second plurality of ISI products which is smaller than said first plurality of ISI products; first adaptive equalization circuitry, coupled to said input terminal, that adaptively equalizes said input data signal to provide a first equalized signal; second adaptive equalization circuitry, coupled to said input terminal, that adaptively equalizes said input data signal to provide a second equalized signal; first signal combining circuitry, coupled to said second adaptive equalization circuitry, that receives and selectively combines a feedback signal and said second equalized signal to provide an intermediate signal; first signal slicing circuitry, coupled to said first signal combining circuitry, that slices said intermediate signal to provide a first sliced signal; first intermediate processing circuitry, coupled to said first signal slicing circuitry and said first signal combining circuitry, that processes at least one of said first sliced signal and at least a portion of said output data signal to provide said feedback signal; second intermediate processing circuitry, coupled between said first signal slicing circuitry and said output terminal, that processes said first sliced signal and another portion of said output data signal to provide a first processed signal; second signal combining circuitry, coupled to said first adaptive equalization circuitry and said second adaptive equalization circuitry, that receives and selectively combines said first processed signal, a second processed signal and said first equalized signal to provide a resultant signal; and output processing circuitry, coupled between said second signal combining circuitry and said output terminal, that processes said resultant signal to provide said output data signal and said second processed signal.

69. The apparatus of claim 68, wherein said first adaptive equalization circuitry comprises linear equalization circuitry.

70. The apparatus of claim 68, wherein said second adaptive equalization circuitry comprises linear equalization circuitry.

71. The apparatus of claim 68, wherein said first intermediate processing circuitry comprises decision feedback equalization circuitry.

72. The apparatus of claim 68, wherein said output processing circuitry comprises: second signal slicing circuitry, coupled between said second signal combining circuitry and said output terminal, that slices said resultant signal to provide a second sliced signal as said output data signal; and further processing circuitry, coupled between said output terminal and said second signal combining circuitry, that processes at least a portion of said second sliced signal to provide said second processed signal.

73. The apparatus of claim 72, wherein said second signal slicing circuitry comprises adaptive signal slicing circuitry.

74. The apparatus of claim 73, wherein said first adaptive equalization circuitry comprises linear equalization circuitry.

75. The apparatus of claim 73, wherein said second adaptive equalization circuitry comprises linear equalization circuitry.

76. The apparatus of claim 73, wherein said first intermediate processing circuitry comprises decision feedback equalization circuitry.

77. An apparatus including a compensation circuit for reducing intersymbol interference (ISI) products within a data signal, comprising: input means for conveying an input data signal including a first plurality of ISI products and corresponding to a detected data signal received via a signal transmission medium; output means for conveying an output data signal including a second plurality of ISI products which is smaller than said first plurality of ISI products; adaptive equalizer means for adaptively equalizing said input data signal to provide an equalized signal; first signal combiner means for receiving and selectively combining a feedback signal and said equalized signal to provide an intermediate signal; first signal slicer means for slicing said intermediate signal to provide a first sliced signal; first intermediate processor means for processing at least one of said first sliced signal and at least a portion of said output data signal to provide said feedback signal; second intermediate processor means for processing said sliced signal and another portion of said output data signal to provide a first processed signal; second signal combiner means for receiving and selectively combining said first processed signal, a second processed signal and said input data signal to provide a resultant signal; and output processor means for processing said resultant signal to provide said output data signal and said second processed signal.

78. The apparatus of claim 77, wherein said output processor means comprises: second signal slicer means for slicing said resultant signal to provide a second sliced signal as said output data signal; and further processor means for processing at least a portion of said second sliced signal to provide said second processed signal.

79. An apparatus including a compensation circuit for reducing intersymbol interference (ISI) products within a data signal, comprising: input means for conveying an input data signal including a first plurality of ISI products and corresponding to a detected data signal received via a signal transmission medium; output means for conveying an output data signal including a second plurality of ISI products which is smaller than said first plurality of ISI products; adaptive equalizer means for adaptively equalizing said input data signal to provide an equalized signal; first signal combiner means for receiving and selectively combining a feedback signal and said equalized signal to provide an intermediate signal; first signal slicer means for slicing said intermediate signal to provide a first sliced signal; first intermediate processor means for processing at least one of said first sliced signal and at least a portion of said output data signal to provide said feedback signal; second intermediate processor means for processing said sliced signal and another portion of said output data signal to provide a processed signal; second signal combiner means for receiving and selectively combining said processed signal and said input data signal to provide a resultant signal; and output processor means for processing said resultant signal to provide said output data signal.

80. The apparatus of claim 79, wherein said output processor means comprises second signal slicer means for slicing said resultant signal to provide a second sliced signal as said output data signal.

81. An apparatus including a compensation circuit for reducing intersymbol interference (ISI) products within a data signal, comprising: input means for conveying an input data signal including a first plurality of ISI products and corresponding to a detected data signal received via a signal transmission medium; output means for conveying an output data signal including a second plurality of ISI products which is smaller than said first plurality of ISI products; first adaptive equalizer means for adaptively equalizing said input data signal to provide a first equalized signal; second adaptive equalizer means for adaptively equalizing said input data signal to provide an equalized signal; first signal combiner means for receiving and selectively combining a feedback signal and said equalized signal to provide an intermediate signal; first signal slicer means for slicing said intermediate signal to provide a first sliced signal; first intermediate processor means for processing at least one of said first sliced signal and at least a portion of said output data signal to provide said feedback signal; second intermediate processor means for processing said sliced signal and another portion of said output data signal to provide a first processed signal; signal combiner means for receiving and selectively combining said first processed signal, a second processed signal and said first equalized signal to provide a resultant signal; and output processor means for processing said resultant signal to provide said output data signal and said second processed signal.

82. The apparatus of claim 81, wherein said output processor means comprises: second signal slicer means for slicing said resultant signal to provide a second sliced signal as said output data signal; and further processor means for processing at least a portion of said sliced signal to provide said second processed signal.

83. A method for reducing intersymbol interference (ISI) products within a data signal, comprising: receiving an input data signal that includes a first plurality of ISI products and corresponds to a detected data signal received via a signal transmission medium; adaptively equalizing said input data signal to provide an equalized signal; selectively combining a feedback signal and said equalized signal to provide an intermediate signal; slicing said intermediate signal to provide a first sliced signal; processing at least one of said first sliced signal and at least a portion of said output data signal to provide said feedback signal; processing said first sliced signal and another portion of said output data signal to provide a first processed signal; selectively combining said first processed signal, a second processed signal and said input data signal to provide a resultant signal; and processing said resultant signal to provide said second processed signal and an output data signal that includes a second plurality of ISI products which is smaller than said first plurality of ISI products.

84. The method of claim 83, wherein said adaptively equalizing said input data signal to provide an equalized signal comprises linearly equalizing said input data signal.

85. The method of claim 83, wherein said processing said resultant signal to provide said second processed signal and an output data signal that includes a second plurality of ISI products which is smaller than said first plurality of ISI products comprises: slicing said resultant signal to provide a second sliced signal as said output data signal; and processing at least a portion of said second sliced signal to provide said second processed signal.

86. The method of claim 85, wherein said slicing said resultant signal to provide a second sliced signal as said output data signal comprises adaptively slicing said resultant signal.

87. The method of claim 86, wherein said adaptively equalizing said input data signal to provide an equalized signal comprises linearly equalizing said input data signal.

88. A method for reducing intersymbol interference (ISI) products within a data signal, comprising: receiving an input data signal that includes a first plurality of ISI products and corresponds to a detected data signal received via a signal transmission medium; adaptively equalizing said input data signal to provide an equalized signal; selectively combining a feedback signal and said equalized signal to provide an intermediate signal; slicing said intermediate signal to provide a first sliced signal; processing at least one of said first sliced signal and at least a portion of said output data signal to provide said feedback signal; processing said first sliced signal and another portion of said output data signal to provide a processed signal; selectively combining said processed signal and said input data signal to provide a resultant signal; and processing said resultant signal to provide an output data signal that includes a second plurality of ISI products which is smaller than said first plurality of ISI products.

89. The method of claim 88, wherein said adaptively equalizing said input data signal to provide an equalized signal comprises linearly equalizing said input data signal.

90. The method of claim 88, wherein said processing said resultant signal to provide an output data signal that includes a second plurality of ISI products which is smaller than said first plurality of ISI products comprises slicing said resultant signal to provide a second sliced signal as said output data signal.

91. The method of claim 90, wherein said slicing said resultant signal to provide a second sliced signal as said output data signal comprises adaptively slicing said resultant signal.

92. The method of claim 91, wherein said adaptively equalizing said input data signal to provide an equalized signal comprises linearly equalizing said input data signal.

93. A method for reducing intersymbol interference (ISI) products within a data sign