Concept of compensating for piezo influences on integrated circuitry Number:7,437,260 from the United States Patent and Trademark Office (PTO) owispatent A semiconductor chip includes a first functional element having a first electronic functional-element parameter exhibiting a dependence relating to the mechanical stress present in the semiconductor circuit chip, and being configured to provide a first output signal, a second functional element having a second electronic functional-element parameter exhibiting a dependence in relation to the mechanical stress present in the semiconductor circuit chip, and being configured to provide a second output signal in dependence on the second electronic functional-element parameter and the mechanical stress, and a combination means for combining the first and second output signals to obtain a resulting output signal exhibiting a predefined dependence on the mechanical stress present in the semiconductor circuit chip, the first and second functional elements being integrated on the semiconductor circuit chip and arranged, geometrically, such that that the first and second functional-element stress influence functions are identical within a tolerance range.<H compensating, integrated, Concept, of, comp, 7437260.html, Patent, pto, 7437260

Title: Concept of compensating for piezo influences on integrated circuitry

Abstract: A semiconductor chip includes a first functional element having a first electronic functional-element parameter exhibiting a dependence relating to the mechanical stress present in the semiconductor circuit chip, and being configured to provide a first output signal, a second functional element having a second electronic functional-element parameter exhibiting a dependence in relation to the mechanical stress present in the semiconductor circuit chip, and being configured to provide a second output signal in dependence on the second electronic functional-element parameter and the mechanical stress, and a combination means for combining the first and second output signals to obtain a resulting output signal exhibiting a predefined dependence on the mechanical stress present in the semiconductor circuit chip, the first and second functional elements being integrated on the semiconductor circuit chip and arranged, geometrically, such that that the first and second functional-element stress influence functions are identical within a tolerance range.

Patent Number: 7,437,260 Issued on 10/14/2008 to Ausserlechner, et al.

Inventors: Ausserlechner; Udo (Villach, AT), Motz; Mario (Wernberg, AT)
Assignee: Infineon Technologies AG (Munich, DE)

Appl. No.: 11/037,536

Filed: January 17, 2005

Foreign Application Priority Data


Jan 26, 2004 [DE]			10 2004 003 853

Current U.S. Class: 702/107 ; 257/427; 323/293; 323/294; 324/251; 324/252; 327/511; 73/1.15; 73/1.48; 73/35.11; 73/514.34; 73/721; 73/727

Current International Class: G01R 35/00 (20060101)

Field of Search: 702/107 324/251-252 327/511 257/427 323/293-294 73/1.15,1.48,35.11,35.13,514.34,721,727

References Cited [Referenced By]

U.S. Patent Documents


4703302	October 1987	Hino et al.
4739381	April 1988	Miura et al.
6653688	November 2003	Takasu et al.
7302357	November 2007	Ausserlechner et al.

Foreign Patent Documents


10 2004 003 853.8	Jan., 2004	DE

Other References

JF. Creemer, P.J. French, "A New Model of the Effect of Mechanical Stress on The Saturation Current of Bipolar Transistors," Jul. 5, 2001. cited by examiner .
J.F. Creemer et al.; "Anisotropy of the Piezojunction Effect in Silicon Transistors"; Technical Digest; The Fifteenth IEEE International Conference on Micro Electro Mechanical Systems, Jan. 20-24, 2002. cited by other .
Fabiano Fruet et al.; "The Piezojunction effect in NPN and PNP Vertical transistors and its influence on silicon temperature sensors"; Sensors and Actuators 85; pp. 70-74, 2000. cited by other .
Buddhika Abesingha; et al.; "Voltage Shift in Plastic-Packaged Bandgap References"; IEEE Transactions on Circuits and Systems-11: Analog and Digital signal Processing, vol. 49, No. 10, Oct. 2002. cited by other .
Fabiano Fruett, et al.; "Minimization of the Mechanical-Stress-Induced Inaccuracy in Bandgap Voltage references"; IEEE Journal of Solid-State Circuits, Vo. 38, No. 7, Jul. 2003. cited by other .
F. Fruett, et al.; "Compensation of Piezoresistivity effect in p-type implanted resistors"; Electronic Letters 2nd, Vo.. 35, No. 18, Sep. 1999. cited by other .
R.C. Jaeger et al.,; "CMOS Stress Sensors on (100) Silicon"; IEEE JSSC; vol. 35, No. 1, Jan. 2000. cited by other .
J.F. Creemer et al.; "A New Model of the Effect of Mechanical Stress on the Saturation Current of Bipolar Transistors"; Sensors and Actuators A97-98, 2002. cited by other .
Abesingha, Buddhika et al., "Voltage Shift in Plastic-Packaged Bandgap References", IEEE Transactions on Circuits and Systems--II: Analog and Digital Signal Processing, vol. 49, No. 10, pp. 681-685, Oct. 2002. cited by other .
Creemer, J.F., et al., "A New Model of the Effect of Mechanical Stress on the Saturation Current of Bipolar Transistors", Delft University of Technology, Sensors and Actuators A 97-98 (2002), pp. 289-295, 2002. cited by other .
Creemer, J.F., et al., "Anisotropy of the Piezojunction Effect in Silicon Transistors", Technical Digest, The Fifteenth IEEE International Conference on Micro Electro Mechanical Systems, pp. 316-319, Jan. 20, 2002. cited by other .
Fruett, Fabiano, et al., "The Piezojunction Effect in NPN and PNP Vertical Transistors and its Influence on Silicon Temperature Sensors", Delft University of Technology, Sensors and Actuators 85 (2000), pp. 70-74, 2000. cited by other .
Fruett, Fabiano, et al., "Minimization of the Mechanical-Stress-Induced Inaccuracy in Bandgap Voltage References", Journal of Solid-State Circuits, vol. 38, No. 7, pp. 1288-1291, Jul. 2003. cited by other .
Fruett, Fabiano, et al., "Compensation of Piezoresistivity Effect in p-Type Implanted Resistors", Electronics Letters, vol. 35, No. 18, pp. 1587-1588, Sep. 2, 1999. cited by other .
Jaeger, Richard C., et al., "CMOS Stress Sensors on (100) Silicon", Jounal of Solid-State Circuits, vol. 35, No. 1, pp. 85-95, Jan. 2000. cited by other.

Primary Examiner: Lau; Tung S.
Assistant Examiner: Kundu; Sujoy K
Attorney, Agent or Firm: Eschweiler & Associates LLC

Claims

What is claimed is:

1. A circuitry on a semiconductor circuit chip, comprising: a first functional element comprising a first electronic functional-element parameter exhibiting a dependence in relation to the mechanical stress in the semiconductor circuit chip in accordance with a first functional-element stress influence function, the first functional element being configured to provide a first output signal in dependence on the first electronic functional-element parameter and the mechanical stress, a second functional element having a second electronic functional-element parameter exhibiting a dependence in relation to the mechanical stress in the semiconductor circuit chip in accordance with a second functional-element stress influence function, the second functional element being configured to provide a second output signal in dependence on the second electronic functional-element parameter and the mechanical stress, and a combination means for combining the first and second output signals to obtain a resulting output signal with a predefinable dependence on the mechanical stress in the semiconductor circuit chip, wherein the first and second functional elements being integrated on the semiconductor circuit chip and arranged, geometrically, such that the first and second functional element stress influence functions are identical within a tolerance range.

2. The circuitry as claimed in claim 1, wherein the first electronic functional-element parameter comprises a first piezo influence factor, and the second electronic functional-element parameter comprises a second piezo influence factor, and the first piezo influence factor and the second piezo influence factor being different from one another.

3. The circuitry as claimed in claim 1, wherein the resulting output signal is stress-independent within a tolerance range.

4. The circuitry as claimed in claim 1, wherein the combination means is configured to perform a linear combination of the first and second output signals.

5. The circuitry as claimed in claim 1, wherein the combination means is configured to perform an analog or digital combination algorithm in relation to the first and second output signals.

6. The circuitry as claimed in claim 1, wherein the combination means comprises an analog or digital arithmetical circuit.

7. The circuitry as claimed in claim 1, wherein the first functional-element stress influence function exhibits one or several components of the stress tensor describing the mechanical stress present in the semiconductor circuit chip.

8. The circuitry as claimed in claim 7, wherein the first functional-element stress influence function is a normal stress component and/or a shear stress component of the mechanical stress in the semiconductor circuit chip.

9. The circuitry as claimed in claim 1, wherein the second functional-element stress influence function comprises one or several components of the stress tensor describing the mechanical stress present in the semiconductor circuit chip.

10. The circuitry as claimed in claim 9, wherein the second functional-element stress influence function comprises a normal stress component and/or a shear stress component of the mechanical stress present in the semiconductor circuit chip.

11. The circuitry as claimed in claim 7, wherein the components of the stress tensor are the two normal stress components in the plane of the surface of the semiconductor circuit chip.

12. The circuitry as claimed in claim 1, wherein the first and/or second functional-element stress influence function comprises, in a first approximation, a linear combination of two stress direction components.

13. The circuitry as claimed in claim 1, wherein the first and/or second functional-element stress influence function comprises, in a first approximation, the sum of both normal stress components in the plane of the surface of the semiconductor circuit chip.

14. The circuitry as claimed in claim 1, wherein the first electronic functional-element parameter and/or the second electronic functional-element parameter comprise a temperature dependence.

15. The circuitry as claimed in claim 1, wherein the first and second functional elements are exposed, within a tolerance range, to the same mechanical stress present in the semiconductor material of the semiconductor circuit chip.

16. The circuitry as claimed in claim 1, wherein the first and second functional elements are exposed, within a tolerance range, to the same temperature in the semiconductor material of the semiconductor circuit chip.

17. The circuitry as claimed in claim 1, wherein the first and second functional elements are arranged on the semiconductor circuit chip so as to be immediately adjacent to one another.

18. The circuitry as claimed in claim 1, wherein the first and second functional elements are arranged to be interlaced.

19. The circuitry as claimed in claim 1, wherein the first and second functional elements are arranged centrally on the semiconductor circuit chip.

20. The circuitry as claimed in claim 1, wherein the first functional element comprises a device of a group of devices, the group comprising a Hall probe element, a vertical bipolar transistor, a lateral bipolar transistor, a diode, an n-type diffusion resistor, a p-type diffusion resistor, an n-type implantation resistor, a p-type implantation resistor, a field-effect transistor, a polysilicon resistor of a polysilicon semiconductor material, or metal, SiCr, NiCr resistors.

21. The circuitry as claimed in claim 1, wherein the second functional element comprises a device of a group of devices, the group comprising a Hall probe element, a vertical bipolar transistor, a lateral bipolar transistor, a diode, an n-type diffusion resistor, a p-type diffusion resistor, an n-type implantation resistor, a p-type implantation resistor, a field-effect transistor, a polysilicon resistor of a polysilicon semiconductor material, or metal, SiCr, NiCr resistors.

22. The circuitry as claimed in claim 20, wherein the first functional element is a Hall probe element, and the first electronic functional-element parameter is the current-related magnetic sensitivity and/or the bulk resistance of the Hall probe element.

23. The circuitry as claimed in claim 21, wherein the second functional element is a Hall probe element, and the second electronic functional-element parameter is the current-related magnetic sensitivity and/or the bulk resistance of the Hall probe element.

24. The circuitry as claimed in claim 20, wherein the first functional element is a vertical bipolar transistor, and the first electronic functional-element parameter is the saturation current which is influenced by the piezojunction effect and is flowing through the vertical bipolar transistor.

25. The circuitry as claimed in claim 21, wherein the second functional element is a vertical bipolar transistor, and the second electronic functional-element parameter is the saturation current which is influenced by the piezojunction effect and is flowing through the vertical bipolar transistor.

26. The circuitry as claimed in claim 20, wherein the first functional element is a diode, and the first electronic functional-element parameter is the saturation current which is influenced by the piezojunction effect and is flowing through the diode.

27. The circuitry as claimed in claim 21, wherein the second functional element is a diode, and the second electronic functional-element parameter is the saturation current which is influenced by the piezojunction effect and is flowing through the diode.

28. The circuitry as claimed in claim 20, wherein the first functional element is a diffusion resistor, and the first electronic functional-element parameter is the resistance of the diffusion resistor.

29. The circuitry as claimed in claim 21, wherein the second functional element is a diffusion resistor, and the second electronic functional-element parameter is the resistance of the diffusion resistor.

30. The circuitry as claimed in claim 20, wherein the first functional element is an implantation resistor, and the first electronic functional-element parameter is the resistance of the implantation resistor.

31. The circuitry as claimed in claim 21, wherein the second functional element is an implantation resistor, and the second electronic functional-element parameter is the resistance of the implantation resistor.

32. The circuitry as claimed in claim 1, wherein the semiconductor material of the semiconductor circuit chip comprises a {100} silicon semiconductor material.

33. The circuitry as claimed in claim 1, wherein the semiconductor material of the semiconductor circuit chip comprises a {111} silicon semiconductor material.

34. The circuitry as claimed in claim 1, wherein the semiconductor material of the semiconductor circuit chip comprises a {110} silicon semiconductor material.

35. The circuitry as claimed in claim 20, wherein the diffusion resistor is a 90.degree. arrangement of partial resistors.

36. The circuitry as claimed in claim 20, wherein the implantation resistor is a 90.degree. arrangement of partial resistors.

37. The circuitry as claimed in claim 20, wherein the polysilicon resistor is a 90.degree. arrangement of partial resistors.

38. The circuitry as claimed in claim 35, wherein the 90.degree. arrangement of partial resistors preferably comprises a .+-.45.degree. alignment to the primary flat in the case of p-doped resistors, and preferably a 0.degree. and/or 90.degree. alignment to the primary flat in the case of n-doped resistors.

39. The circuitry as claimed in claim 38, wherein the semiconductor material is <100> silicon.

40. The circuitry as claimed in claim 1, wherein the first and second functional elements comprise different, but isotropic stress dependencies in a {100} semiconductor material.

41. Circuitry on a semiconductor circuit chip, comprising: a first functional element having a first electronic functional-element parameter, the first electronic functional-element parameter being representable by the following relationship: F(T)=F.sub.0(T)(1+.pi..sub.F(T)f.sub.F(.sigma.)), wherein F.sub.0(T) is a basic value of the first electronic functional-element parameter, .pi..sub.F is a first scalar piezo influence factor for describing the influence of the mechanical stress in the semiconductor circuit chip on the first electronic functional-element parameter, and f.sub.F(.sigma.) is a first scalar functional-element stress influence function for providing a scalar description of the mechanical stress in the semiconductor circuit chip, the first functional element being configured to provide a first output signal in dependence on the first electronic functional-element parameter and the mechanical stress, a second functional element having a second electronic functional-element parameter, the second electronic functional-element parameter being representable by the following relationship: G(T)=G.sub.0(T)(1+.pi..sub.G(T)f.sub.G(.sigma.) wherein G.sub.0(T) is a basic value of the second electronic functional-element parameter, .pi..sub.G is a second scalar piezo influence factor for describing the influence of the mechanical stress in the semiconductor circuit chip on the second electronic functional-element parameter G.sub.0(T), and f.sub.G(.sigma.) is a second scalar functional-element stress influence function for providing a scalar description of the mechanical stress in the semiconductor circuit chip, the second functional element being configured to provide a second output signal dependence on the second electronic functional-element parameter and the mechanical stress, and a combination means for combining the first and second output signals to obtain a resulting output with a predefinable dependence on the mechanical stress in the semiconductor circuit chip, the first and second functional elements being integrated on the semiconductor circuit chip and arranged, geometrically, such that the first and second functional-element stress influence functions are identical within a tolerance range with a deviation of less than 10%.

42. The circuitry as claimed in claim 1, wherein the first piezo influence factor and the second piezo influence factor are different from one another.

Description

PRIORITY

This application claims priority from German Patent Application No. 102004003853.8, which was filed on Jan. 26, 2004.

TECHNICAL FIELD OF THE INVENTION

The present invention relates to integrated circuitries in a semiconductor substrate, and in particular to a concept of compensating the negative influence of a mechanical stress component in the semiconductor substrate on the parameter accuracy and parameter stability of the circuitry integrated on the semiconductor substrate.

DESCRIPTION OF PRIOR ART

Integrated circuitries, or integrated circuits (ICs), are typically mounted in packages to protect the sensitive integrated circuitries from environmental influences. However, one disadvantageous side effect that may be observed is that accommodating and mounting the integrated circuitry in a package exerts considerable mechanical stress on the semiconductor material, and thus on the semiconductor substrate of the integrated circuitry.

This applies, in particular, to low-cost package shapes configured as mass articles, such as to package forms wherein a sealing compound is injected around the integrated circuitry. The sealing compound hardens by cooling down to ambience temperature from a temperature of about 150.degree. C.-185.degree. C. Since the semiconductor material of the integrated circuitry and the plastic sealing material of the package surrounding the integrated circuitry exhibit thermal expansion coefficients which do not match, during the cooling to ambient temperature, i.e. room temperature, the plastic materials will shrink more and exert essentially non-reproducible mechanical stress on the semiconductor material of the integrated circuitry. The plastic material generally has a higher thermal expansion coefficient than the semiconductor material of the integrated circuitry, the semiconductor materials used mostly being silicon or even germanium, gallium arsenide (GaAs), InSb, InP, etc.

The mechanical stress, or the mechanical strain, present in the semiconductor material of the semiconductor substrate and acting on the integrated circuitry is generally hard to reproduce because the mechanical stress depends on the combination of the materials used for the semiconductor substrate and for the sealing compound, and, in addition, on the processing parameters, such as the hardening temperature and hardening period of the sealing compound of the package of the integrated circuitry.

Various piezo effects present in the semiconductor material, such as the piezoresistive effect, piezo MOS effect, piezojunction effect, piezo Hall effect and piezo-tunnel effect, also influence important electrical and/or electronic parameters of the integrated circuitry due to mechanical stress of the integrated circuitry which is operating. In connection with the description below, the generic term "piezo effects" is to generally refer to the changes of electrical and/or electronic parameters of the circuitry integrated in the semiconductor material under the influence of mechanical stress in the semiconductor material.

Mechanical stress in the semiconductor material results in a change in the properties of the charge carriers with regard to the charge-carrier transport, such as mobility, collision time, scattering factor, Hall constant, etc.

In more general words, the piezoresistive effect determines how the specific ohmic resistance of the respective semiconductor material will behave under the influence of mechanical stress. The piezojunction effect results, among other things, in changes in the characteristics of diodes and bipolar transistors. The piezo Hall effect describes the dependence of the Hall constant of the semiconductor material on the mechanical stress condition in the semiconductor material.

The piezo-tunnel effect occurs at reversely operated, highly doped, shallow lateral pn junctions. This current is dominated by band-to-band tunnel effects and is also dependent on stresses.

In connection with the present invention it is also to be noted that the piezoresistive effect and the term "piezo MOS effect", which may occasionally be found in literature, are comparable, since with the piezo MOS effect, essentially just like with the piezoresistive effect, the mobility of the charge carriers in the MOS channel of an MOS field-effect transistor changes under the influence of the mechanical stress present in the semiconductor material of the integrated circuit chip.

It therefore becomes clear that due to mechanical stresses in the semiconductor material of an integrated circuitry, the electrical and/or electronic characteristics of the integrated circuitry could be changed, or negatively affected, in a non-predictable manner, a reduction in the performance, or parameter, of the integrated circuitry being noticeable, e.g., in the form of an impairment of the dynamic range, the resolution, the bandwidth, the power consumption or the accuracy etc.

Specifically, the above-mentioned piezoresistive effect indicates how the specific ohmic resistance .rho. of the respective semiconductor material behaves under the influence of a mechanical stress tensor .sigma. and of the piezoresistive coefficients .pi.: .rho.=.rho..sub.0(1+.SIGMA..pi..sub.i,j.sigma..sub.i,j)

Here, factor .rho..sub.0 is the basic value of the specific resistance which remains unaffected by the mechanical stress.

In integrated circuitries (ICs), the respective current I, e.g. a control current, a reference current etc., is generated by circuit elements of the integrated circuitry on the semiconductor chip. Here, a defined voltage U is produced at an integrated resistor having the resistance R, and current I is decoupled. Current I may generally also be generated at any resistive element, e.g. also at a MOS field-effect transistor located in the linear operating range.

The voltage U may also be created, e.g., by known bandgap principles, in a manner which is relatively constant in relation to mechanical stresses in the semiconductor material (apart from the comparatively small piezojunction effect on the bandgap voltage produced). The resistance R, however, is subject to the piezoresistive effect in accordance with the following relationship: R=R.sub.0(1+.SIGMA..pi..sub.i,j.sigma..sub.i,j)

Here, factor R.sub.0 is the basic value of the resistance, which remains unaffected by the mechanical stress, and the value .pi..sub.ij is a piezoresistive coefficient. Thus, the current I produced at the resistive element may be expressed as follows: I=U /R=U/(R.sub.0(1+.SIGMA..pi..sub.ij.sigma..sub.ij))

If the mechanical pressure present on the semiconductor, and thus the mechanical stress present in the semiconductor may be subdivided into an essentially constant basic value .sigma..sub.0ij and a pressure fluctuation .delta..sigma..sub.ij which is mostly fairly small and is variable across operating conditions and service life, i.e. may be subdivided into .sigma..sub.ij=.sigma..sub.0ij.+-..delta..sigma..sub.ij, the current may be expressed as follows, in linear approximation: I=I.sub.0(1+.SIGMA..pi..sub.ij.delta..sigma..sub.ij), with I.sub.0U/(R.sub.0(1+.SIGMA..pi..sub.ij.sigma..sub.0ij))

It also becomes clear that the factor taken from the coefficient .pi..sub.ij and the pressure fluctuation .delta..sigma..sub.ij is problematic and could produce an interference with regard to current I generated, and should come as close to zero as possible.

Since mechanical stresses present in the semiconductor material have an impact on the semiconductor circuit chip, due to the package of the integrated circuitry, in a manner which is difficult to control, the resistance R used for generating current I, and therefore also current I which has been generated, are changed in an undesired and unpredictable manner.

The piezo Hall effect, in contrast, describes the dependence of the Hall constant R.sub.h on the condition of mechanical stress in the semiconductor material, with: R.sub.h=R.sub.h0(1+.SIGMA.P.sub.i,j.sigma..sub.i,j)

.sigma..sub.ij is the mechanical stress tensor, P.sub.ij are the piezo Hall coefficients, the summation extending across i=1 . . . 3 and j=1 . . . 3 with the piezo Hall effect (and the piezoresistive effect).

Both the piezoresistive effect and the piezo Hall effect are highly disruptive in the operation of integrated circuitry, in particular a sensor array, such as an integrated Hall probe, including control electronics and evaluation electronics.

Due to the piezo Hall effect, which occurs in the semiconductor material of the semiconductor chip of the integrated circuitry also as a result of mechanical stresses, the current-related sensitivity S.sub.i of the Hall probe changes as follows, e.g. in the case of a Hall probe array:

.times..times. ##EQU00001##

U.sub.h is the Hall voltage present at the output side of the Hall probe, I.sub.H is the current (control current) flowing through the Hall probe, B is the magnetic flux density to be detected, t is the effective thickness of the active layer of the Hall probe, and g is a geometry factor describing the influence of the contact electrodes on the Hall voltage.

As a result of the piezoresistive effect in the presence of mechanical stresses in the semiconductor material of the Hall-probe array, Hall current I.sub.H flowing through the Hall probe will change, since Hall current I.sub.H (control current) is defined, in addition, for example, only across a co-integrated resistance R where a voltage U is made to drop, possibly by means of a control loop. A change in the Hall current I.sub.H due to the change in the resistance as a result of the piezoresistive effect therefore leads to a change in the sensitivity S of the Hall probe, since the sensitivity S of the Hall probe is identical with the product of the current-related sensitivity S.sub.i times the Hall current I.sub.H: S=S.sub.iI.sub.h=U.sub.h/B.varies.S.sub.i/R

The magnetic sensitivity of the Hall probe S may be defined (as indicated above) as the ratio of the output voltage U.sub.H of the Hall probe to the operating magnetic-field component B.

A mechanical stress .sigma..sub.ij present in the semiconductor material of the Hall-probe array therefore influences the current-related magnetic sensitivity S.sub.i of a Hall probe in accordance with S.sub.i=S.sub.i0(1+.SIGMA.P.sub.ij.sigma..sub.ij)

Factor S.sub.i0 is the basic value of the current-related magnetic sensitivity, which remains unaffected by the mechanical stress, and factor P.sub.ij is a piezo Hall coefficient.

Generally, attempts have been made at keeping the magnetic sensitivity S of a Hall probe as constant as possible, with influences due to mechanical stress due to the piezoresistive effects and piezo Hall effects set forth above being disruptive, in particular.

With regard to integrated Hall sensor circuitries generating a switching signal dependent on the operating magnetic-field component B, one should take into account that the magnetic switching threshold B.sub.S may always be returned to the following form: B.sub.S.varies.R/S.sub.i

Thus, it can generally be said that the ratio of the current-related magnetic sensitivity S.sub.i to a resistance R is decisive for the magnetic parameters, such as the sensitivity or the switching thresholds of a Hall-probe array.

Eventually, mechanical stresses in the semiconductor material of an integrated circuitry thus have a negative influence on the magnetic sensitivity and/or the switching thresholds of a total system structured by a Hall-probe array.

In practice, magnetic switching sensors show, prior to the packaging process (i.e. on a wafer plane), switching thresholds which differ by about 10% from those switching thresholds after accommodation in a package. The reasons for this are the above-mentioned piezo effects. In particular, after being accommodated in a package, an undesired behavior of the "magnetic switching thresholds versus temperature" in the form of a hysteresis loop may be observed, which opens between 1% and 4%, this being observable, in particular, if the IC package had absorbed a lot of moisture prior to or during the packaging process and if the dwelling time of the semiconductor circuit chip with temperatures above 100.degree. C. is more than 10 minutes (this is typically the diffusion time constant of small packages for integrated circuits). The reasons for this are, again, the above-mentioned piezo effects.

With regard to the piezo effects represented above it should be noted that the coefficients .sigma..sub.ij, P.sub.ij and .pi..sub.ij defining the mechanical stresses occurring in the semiconductor material are so-called "tensors", i.e. that the current-related magnetic sensitivity S.sub.i of a Hall element and the resistance R of a resistive element do change not only because of the magnitude of the mechanical stress in the semiconductor material, but also because of the direction of the stress in the semiconductor material. The pronounced directional dependence of the influence of a mechanical stress present in the semiconductor material on electrical and electronic parameters of an integrated circuitry have been known in the art. Thus, the scientific publication [1] "Anisotropy of the Piezojunction Effect in Silicon Transistors" by Creemer, J. F.; French, P. J. in Technical Digest MEMS 2002, the 15. IEEE international conference on Micro Electro Mechanical Systems, Las Vegas, pp. 316 ff, relates to the anisotropy of the piezojunction effect in silicon transistors.

The piezojunction effect indicates how mechanical stresses present in a semiconductor material lead to a shift of the energy level of the band edges of the semiconductor material which result, among other things, in changes in the characteristics of diodes and bipolar transistors.

When mounting an integrated semiconductor circuit chip (IC) in a plastic package, mechanical stresses occur in the semiconductor material of the integrated semiconductor circuit chip, as described above. The mechanical stress present in the semiconductor material influences, by means of the piezojunction effect, the saturation current I.sub.S due to changes in the mobility of the minority carriers .DELTA..mu. and changes in the intrinsic charge-carrier concentration .DELTA.n.sub.i:

.DELTA..times..times..apprxeq..DELTA..times..times..mu..mu..DELTA..times..- times. ##EQU00002##

By means of the known exponential characteristics, the collector current or the base-emitter voltage of a transistor is influenced:

.times..function. ##EQU00003##

V.sub.BE is the base-emitter voltage of a bipolar transistor, q is the elementary charge, and T is the absolute temperature. These connections have been well known in literature. The scientific publication [2] "The piezojunction effect in NPN and PNP vertical transistors and its influence on silicon temperature sensors" by Fabiano Fruet, Guijie Wang, Gerard C. M. Meijer in Sensors and Actuators 85 (2000) 70-74 relates to the piezojunction effect in vertical npn- and pnp-type transistors and its influence on silicon temperature sensors.

If, for example, a bipolar transistor is used for a constant-voltage source, the bandgap voltage V.sub.BG of the constant-voltage source is influenced by the piezojunction effect and by the piezoresistive effect because of the mechanical stress in the semiconductor material. The base-emitter voltage V.sub.BE of the bipolar transistor contained in the constant-voltage source changes because of the piezojunction effect and also because of the piezoresistive effect, since the resistances of the resistors contained in the constant-voltage source are influenced by the piezoresistive effect.

The bandgap voltage V.sub.BG is formed, as is known, by the base-emitter voltage V.sub.BE and the temperature voltage V.sub.PTAT (PTAT=voltage proportional to the absolute temperature), the negative temperature dependence of the base-emitter voltage V.sub.BE being compensated for by a positive temperature dependence of the temperature voltage V.sub.PTAT (=.DELTA.V.sub.BE). The temperature voltage V.sub.PTAT is essentially independent of piezo effects since the temperature voltage V.sub.PTAT is formed only by current-density ratios in the bipolar transistors, it being possible to adjust the current-density ratios in a very precise and constant manner by means of layout and design measures. In contrast, the currents in bandgap circuits, however, are in turn defined by resistors, which are subject to piezoresistive effects due to mechanical stresses present in the semiconductor material, e.g. due to being accommodated in a package. Taking into account the piezoresistive effect on the resistance of the integrated resistor (resistive element), the temperature current (I.sub.PTAT) may be expressed as follows:

##EQU00004##

Accordingly, the following applies to current I.sub.VBE, which is formed by means of a base-emitter voltage V.sub.BE and a resistance R2 of a further resistor:

##EQU00005##

Here, too, mechanical stresses present in the semiconductor material have an effect on the semiconductor circuit chip which is difficult to control, since humidity, material constants and geometries of the packages may vary. Thereby, both the resistance of the reference resistor for generating the operating current flowing through the bandgap circuit, as well as the base-emitter voltage V.sub.BE used in the bandgap circuit, and thus the stability of the constant voltage (bandgap voltage), V.sub.BG, are changed in an undesired manner.

The bandgap principle is used, for example, with temperature sensors due to its technological robustness. Due to the above-mentioned piezo effects, however, both the reference resistance for generating the operating currents in such a temperature sensor, and the base-emitter voltage V.sub.BE used in the temperature sensor, and thus the stability of the temperature measurement, i.e., for example, long-term drift, influence of humidity etc., are changed in an undesired manner by means of scattering due to the fact that the integrated semiconductor circuit chip is accommodated in a plastic package.

Prior to the wafer-level packaging process, i.e. prior to being accommodated in a package, bandgap circuits exhibit voltage values differing by about 0.5 to 2% from the voltage values established once the bandgap circuits are accommodated in a package, the reason for this being the so-called piezo effects. Accordingly, prior to the wafer-level packaging process, temperature sensors exhibit temperature readings (or with temperature switches, temperature threshold values) differing by about 1-5.degree. C. from temperature sensors accommodated in the package due to the above-mentioned piezo effects.

Since the factors .sigma..sub.ij, P.sub.ij and .pi..sub.ij represented in the above formulae are so-called tensors, the base-emitter voltages V.sub.BE and the resistances R which are used in the bandgap circuit change not only due to the quantities of the respective mechanical stresses, but also due to the direction of the stresses in relation to the semiconductor material. With regard to examinations with regard to the directional dependence, reference shall be made to the scientific publications mentioned below. The directional dependence of the mechanical stress in the semiconductor material applies to the {100} silicon material for p- and n-doped resistors, which is used for the most part. In addition, it is to be noted that {100} wafers and {001} wafers correspond to one another, for reasons of symmetry, in cubic crystals. In the literature mentioned below, both notations are used. For the piezojunction effect of parasitic vertical pnp substrate transistors, which are used, for the most part, in modem CMOS technologies, there are also known figures for stress dependence. Stress dependence is non-directional essentially for in-plane normal, or direct, stress (main-axis stress components on the chip level) in a {100} material for vertical bipolar transistors. Because of the stress dependence of the saturation current of a bipolar transistor, the base-emitter voltage V.sub.BE becomes stress-dependent, in dependence on the collector current I.sub.C, essentially across the logarithmic characteristic, so that: U.sub.BE=f(I.sub.c)

Below, a brief explanation will be given of how attempts have been made, in accordance with the prior art, at reducing the above disruptive piezo influences. It has been known in the art that with {100} silicon material, the mechanical stress dependence of integrated resistors may be reduced by using p-doped resistors instead of n-doped resistors as much as possible, since p-doped integrated resistors generally have smaller piezo coefficients. In addition, n-type resistors are oriented, in general, such that the major part of the current flow flows in a <110> direction, whereas p-type resistors, in contrast, are rotated by an angle of 45.degree. thereto, since p-type resistors generally have smaller piezo coefficients in <100> directions.

In addition, the art has known arrangements, wherein two nominally equal resistors are arranged to be perpendicular to one another and to have a small distance from one another in the layout, and are electrically connected in series or in parallel. Thereby, the total resistance becomes as independent as possible of the direction of the mechanical stress present in the semiconductor material, and therefore becomes reproducible as much as possible. At the same time, the piezo sensitivity of such an arrangement for any direction of the mechanical stress will also become minimal.

In addition, efforts have been made in the art to configure the IC package such that the mechanical stresses acting upon the semiconductor circuit chip may become easier to reproduce. To this effect, the art has either used expensive ceramic packages, or the mechanical parameters of the package components, i.e. semiconductor circuit chip, lead frame, sealing compound, adhesive material or soldering material, are matched such that the influences of the different package components compensate for one another as much as possible or are at least as constant as possible with regard to assembly batch and stress load of the integrated circuitry on the fly. However, it should become clear that matching the mechanical parameters of the package components is extremely expensive, and that, in addition, the slightest changes in the progress of the process again will lead to a change in the influences of the various package components.

Up to now, efforts have been made, in the prior art, to reduce the above-mentioned piezo influences on bandgap circuits by means of suitable devices, e.g. vertical pnp transistors and polysilicon resistors or silicon-chrome resistors, and, additionally, by means of suitable package techniques, e.g. ceramic packages, low-stress plastic materials, grain size of the filler material in plastic, etc., all of which has also been supposed to reduce influences due to humidity and lifetime drift.

The scientific publication [3] "Voltage Shift in Plastic-Packaged Bandgap References" by Buddhika Abesingha, Gabriel A. Rincon-Mora and David Briggs in IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--II: ANALOG AND DIGITAL SIGNAL PROCESSING, Vol. 49, No. 10, October 2002, pp. 681 relates to voltage shifts of bandgap reference voltage sources accommodated in a plastic package. The scientific publication [4] "Minimization of the Mechanical-Stress-Induced Inaccuracy in Bandgap Voltage References" by Fabiano Fruett, Gerard C. M. Meijer, and Anton Bakker in IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 38, No. 7, July 2003, pp. 1288-1291, relates to minimizing the inaccuracies caused by mechanical stress in bandgap reference voltage sources by using vertical pnp transistors and chopper techniques.

The scientific publication [5] "Compensation for piezoresistivity effect in p-type implanted resistors" by F. Fruett, G. C. M. Meijer in Electronic letters 2 Sep. 1999, Vol. 35, No. 18, pp. 1587, relates to the compensation for the piezoresistive effect in implanted p-type resistors.

The above illustrations and the above-mentioned scientific publications clearly show that an influence, which is undesired and difficult to control, on the physical functional parameters of semiconductor devices of integrated circuitries on a semiconductor circuit chip may be caused by mechanical stresses in the semiconductor material by means of various piezo effects. A compensation for the influence of the piezo effects on the physical and electronic functional parameters of the semiconductor devices is problematic in that the stress components occurring in the semiconductor material are generally neither known in advance, nor do they remain constant during the life period, so that when the integrated circuitry is accommodated in a package, the mechanical parameters, i.e., for example, the material of the semiconductor chip, the lead frame, the sealing compound, the adhesive or the solder material, are difficult or impossible to match with one another so as to check the above-mentioned piezo influences on the semiconductor material, and, thus, on the electronic and physical functional parameters of the semiconductor devices in a suitable manner.

SUMMARY OF THE INVENTION

Starting from this prior art, it is the object of the present invention to provide an improved concept for compensating for piezo influences on integrated circuitry.

In accordance with a first aspect, the invention provides a circuitry on a semiconductor circuit chip, having: a first functional element having a first electronic functional-element parameter, the first electronic functional-element parameter exhibiting a dependence in relation to the mechanical stress in the semiconductor circuit chip in accordance with a first functional-element stress influence function, the first functional element being configured to provide a first output signal in dependence on the first electronic functional-element parameter and the mechanical stress, a second functional element having a second electronic functional-element parameter, the second electronic functional-element parameter exhibiting a dependence in relation to the mechanical stress in the semiconductor circuit chip in accordance with a second functional-element stress influence function, the second functional element being configured to provide a second output signal in dependence on the second electronic functional-element parameter and the mechanical stress, and a combination means for combining the first and second output signals to obtain a resulting output signal with a predefinable dependence on the mechanical stress in the semiconductor circuit chip, the first and second functional elements being integrated on the semiconductor circuit chip and arranged, geometrically, such that the first and second functional-element stress influence functions are identical within a tolerance range.

In accordance with a second aspect, the invention provides a method of generating an output signal of a circuitry on a semiconductor circuit chip, including: generating, by means of a first functional element, a first output signal in dependence on a first electronic functional-element parameter of the first functional element, and on the mechanical stress in the semiconductor circuit chip, the first electronic functional-element parameter exhibiting a dependence in relation to the mechanical stress in the semiconductor circuit chip in accordance with a first functional-element stress influence function, and generating, by means of a second functional element, a second output signal in dependence on a second electronic functional-element parameter of the second functional element, and on the mechanical stress in the semiconductor circuit chip, the second electronic functional-element parameter exhibiting a dependence in relation to the mechanical stress in the semiconductor circuit chip in accordance with a second functional-element stress influence function, and combining the first and second output signals to obtain the resulting output signal of the circuitry with a predefinable dependence on the mechanical stress in the semiconductor circuit chip, the first functional element and the second functional element being integrated on the semiconductor circuit chip and arranged, geometrically, such that the first and second functional-element stress influence functions are identical within a tolerance range.

The inventive circuitry on a semiconductor chip includes a first functional element having a first electronic functional-element parameter, the first electronic functional-element parameter exhibiting a dependence with regard to the mechanical stress in the semiconductor circuit chip according to a first functional-element stress influence function, the first functional element being configured to provide a first output signal in dependence on the first electronic functional-element parameter and the mechanical stress, a second functional element having a second electronic functional-element parameter, the second electronic functional-element parameter exhibiting a dependence in relation to the mechanical stress in the semiconductor circuit chip in accordance with a second functional-element stress influence function, the second functional element being configured to provide a second output signal in dependence on the second electronic functional-element parameter and the mechanical stress, and a combination means for combining the first and second output signals to obtain a resulting output signal with a predefined dependence on the mechanical stress in the semiconductor circuit chip, the first and second functional elements being integrated on the semiconductor circuit chip and arranged, geometrically, such that the first and second functional-element stress influence functions are identical within a tolerance range.

An inventive method of producing an output signal of a circuitry on a semiconductor circuit chip comprises generating, by means of a first functional element, a first output signal in dependence on a first electronic functional-element parameter of the first functional element, and on the mechanical stress in the semiconductor circuit chip, the first electronic functional-element parameter exhibiting a dependence with regard to the mechanical stress in the semiconductor circuit chip in accordance with a first functional-element stress influence function, and generating, by means of a second functional element, a second output signal in dependence on a second electronic functional-element parameter of the second functional element, and on the mechanical stress in the semiconductor circuit chip, the second electronic functional-element parameter exhibiting a dependence with regard to the mechanical stress in the semiconductor circuit chip in accordance with a second functional-element stress influence function, and combining the first and second output signals to obtain the resulting output signal of the circuitry with a predefined dependence on the mechanical stress in the semiconductor circuit chip, the first functional element and the second functional element being integrated on the semiconductor circuit chip and arranged, geometrically, such that the first and second functional-element stress influence functions are identical within a tolerance range.

The present invention is based on the findings that the impact of a piezo effect on an electronic functional parameter of a semiconductor device may be compensated for, or that a desired setting of a remaining piezo dependence may be performed, by combining and/or mixing the electronic functional parameter of the semiconductor device with a further electronic functional parameter of a further semiconductor device (or of the same semiconductor device) (and/or by combining signals obtained by means of the first and second functional parameters), the further electronic functional parameter being subject to a further piezo influence.

The inventive compensation for piezo influences on a semiconductor circuit device by combining various piezo effects is achieved, in accordance with the invention, in that preferably two semiconductor devices, which are both integrated on a semiconductor circuit chip so as to be as close to one another as possible, are arranged, geometrically, such that the piezo influences on the two electronic functional parameter which are influenced by piezo effects exhibit predefined directional dependencies within a tolerance range, and exhibit, preferably, identical directional dependencies and/or stress-influence functions or are both non-directional. This enables the achievement of a mutual compensation for the impact, caused by varying piezo effects, on the electronic functional parameters of the electronic semiconductor devices by means of a combination of the various piezo influences and, in particular, by a simple linear combination of same.

In accordance with the invention, the piezo dependence of the scalar electronic functional parameter F may be represented as a product of a scalar, temperature-dependent piezo coefficient .pi..sub.F(T) and any scalar function, which may also be non-linear, of the stress tensor f(.sigma.): F(T)=F.sub.0(T)(1+.pi..sub.F(T)f.sub.F(.sigma.)), with f.sub.F(.sigma.)=0 if .sigma.=0

The terms with double underlining indicate a matrix representation.

The function of the stress tensor f(.sigma.) will be referred to below as a so-called "functional-element stress influence function" of the functional-element parameter F. If a further, second electronic functional-element parameter G can be represented as follows: G(T)=G.sub.0(T)(1+.pi..sub.G(T)f.sub.G(.sigma.)), with f.sub.G(.sigma.)=0 if .sigma.=0 the inventive compensation for various piezo effects may be performed as follows:

Initially, a prerequisite is that the functional-element stress influence functions are made to be identical by configuring the functional elements in a suitable manner (in {100}-Si, with Hall probes, no specific configuration measures are needed; with bipolar transistors, one should use, e.g., vertical types; with resistors, one should use, e.g., an L layout), so that: f.sub.F(.sigma.)=f.sub.G(.sigma.) so that in the following, we will only need to speak of functional-element stress influence functions f(.sigma.).

The output signal of the integrated circuitry (generally IC) and, e.g., of a sensor array is generated by mixing the two electronic functional parameters G and F by means of a mathematical mixing function, or combination function m(G, F). So that the inventive compensation for various piezo effects may be performed, the following general condition needs to be met, in accordance with the invention, in addition to the above precondition of identical functional-element stress influence functions, for the output signal of the integrated circuitry to become independent of stress:

.differential..function..differential. ##EQU00006## which is equivalent to the following requirement:

.differential..differential..differential..differential..function..functio- n..times..pi..function..pi..function. ##EQU00007##

Independently of the above-mentioned requirement with regard to the independence of the output signal of stress, one may further obtain any thermal response of the output signal by multiplying the mixed function m(G, F) by a suitable scalar temperature-influence function t(T). From the above, latter equation it becomes clear that this temperature-influence function t(T) then drops out in the above ratio (dm/dG)/(dm/dF) because the temperature-influence function t(T) is present both in the numerator and in the denominator and thus is eliminated due to reduction.

If one does not want to make the output signal independent of stress, in a more general case, but wants to make it dependent on stress in accordance with a predefinable function s(f(.sigma.),T), the condition m(G,F)=s(f(.sigma.),T) is to be met, which is possible, in principle, since G and F are functions of T and f(.sigma.).

This is how the inventive compensation for different piezo effects differs, when setting a thermal response desired, also from the temperature compensations known in the prior art. In the latter, only voltages, currents or Hall sensitivities and/or switch points are indeed temperature-compensated by mixing voltages or currents which are temperature-dependent to various degrees, but they are not stress-compensated.

The inventive approach including the introduction of a stress-influence function f(.sigma.) results in the fact that the individual components of the stress tensor, which are actually to be considered for piezo compensation due to mechanical stress in the semiconductor material, need not all be considered individually, and that the output signal of the integrated circuitry and/or the above-mentioned mixed function thus need not be differentiated by the individual components of the stress tensor, but only by the stress-influence function introduced in accordance with the invention. In this connection it should be noted, in particular, that the inventive introduction of the stress-influence function in piezo compensation not only presents a mathematical transformation of the underlying problem, but also provides a completely new concept of piezo compensation which consists in that, starting from a scalar evaluation of the complex stress condition in the semiconductor material of the integrated circuitry, a suitable input quantity for the piezo compensation, i.e. a suitable input quantity for a piezo-compensation control loop, is obtained.

Minor deviations from the above equations are inevitable in practice, but it must be noted that the quality of the inventive piezo compensation is improved by as small deviations as possible.

This is why, in accordance with the invention, a so-called tolerance range is introduced for the stress dependence, or directional stress dependence of an electronic functional parameter of a semiconductor device. Thus, it is taken into account, in accordance with the invention, that the stress condition present on the surface of the integrated circuit is dependent on the base, i.e. it varies as the position on the semiconductor material varies. Therefore, the first and second functional elements are subject, strictly speaking, to different stress components. By taking suitable layout measures on the semiconductor circuit chip, as will be described below in detail within the framework of the specification of the present invention, attempts are now made at subjecting the first and second functional elements essentially to the same stress condition and also to the same temperature in the semiconductor material of the semiconductor circuit chips.

The inventive compensation concept accounts for this fact by enabling two different stresses, and thus two different directional stress dependencies, of the electronic functional parameters to occur at these two different locations, which, however, are identical within a certain tolerance range.

Concerning the tolerance range, it is also to be noted that in the art, there are deviations from the theoretical ideal case in all fields of physics, these deviations from the functionality of the inventive compensation concept needing to be sufficiently small only. If the deviations are, e.g., 10%, i.e. lie within a tolerance range of 10%, it will be possible to eliminate, with an otherwise ideal compensation, about 90% of the overall effect, i.e. of the influence of mechanical stresses present in the semiconductor material on the useful signal, or on the resulting output signal.

To be able to conduct effective stress compensation, the tolerance range should be smaller than 50%, preferably smaller than 10%, and, in the most preferred case, smaller than 1%.

In accordance with one aspect of the present invention, the different piezoresistive dependencies on resistors of varying technological architectures may be mixed in a suitable manner to thus obtain a piezo dependence of the combined total resistance and/or of a combined total current derived therefrom, it being possible, for example, to either set the resulting piezo dependence in a suitable manner, or to essentially eliminate it. To this end, the dependence of the resistance of the n- and p-doped reference resistors used on the mechanical stress is made, for example, non-directional by layout measures, so that the resistances of an n-doped reference resistor and a p-doped reference resistor (within a tolerance range) exhibit essentially the same directional dependence, and thus, therefore, the piezo dependencies of the two resistors may be combined, by simple combination, preferably a linear combination, so as to obtain the above-mentioned desired piezo dependence of the total resistance. For this purpose, reference currents are generated from the p- and n-doped resistors, respectively, both reference currents having a suitable ratio in accordance with the n-type piezoresistive dependence and the p-type piezoresistive dependence. By means of linear combination, e.g. summation or formation of difference, of both reference currents, which may be re-amplified and/or re-weighted, a total reference current is thus obtained which is independent, to a very large extent, on the mechanical stress exerted on the semiconductor chip, and/or which exhibits a desired, adjusted dependence on the mechanical stress exerted on the semiconductor chip.

To enable compensation for mechanical stress influences on the total current to be effected also across a wide temperature range, the thermal response of the ratio of n- to p-type reference currents may be selected in a suitable manner. In addition, it is also possible to set the thermal response of the total current (i.e. of the linear combination of n- and p-type reference currents) in any manner desired by making a suitable choice of the thermal response of a common pre-factor of the two n- and p-type reference currents.

In the present invention, use may also be made of so-called polysilicon resistors having a smaller stress dependence, and/or of metal, SiCr-, NiCr-resistors instead of the n-type resistors and/or p-type resistors, e.g. for the second conductivity type, it being essential only that their piezoresistive dependencies (piezo coefficients) differ with regard to the piezoresistive dependencies (piezo coefficients) of the resistive element of the first conductivity type, so that two different isotropic piezoresistive partial signals, e.g. partial voltages or partial currents, may be generated from the different resistor elements.

In addition, it should be noted that so-called magnetoresistive elements, such as AMR elements (AMR=anisotropic magnetoresistance) and/or GMR elements (GMR=giant magnetoresistance) may also be used. In this case, the electronic functional parameter of an AMR element is constituted by the anisotropic magnetoresistive effect which may be influenced by piezo effects and, in particular, the piezoresistive effect. The electronic functional parameter of a GMR element is formed by the giant magnetoresistive effect which is also influenced by piezo effects and, in particular, the piezoresistive effect.

In accordance with a further aspect of the present invention, it is possible, in accordance with the invention, with an integrated Hall-probe circuitry, to compensate, e.g., the piezo Hall effect, which has an impact on the magnetic current-related sensitivity of the Hall element, by means of the piezoresistive effect, which has an impact on the resist