Title: Copper transition layer for improving copper interconnection reliability
Abstract: The structure and the fabrication method of an integrated circuit in the horizontal surface of a semiconductor body comprising a dielectric layer over said semiconductor body and a substantially vertical hole through the dielectric layer, the hole having sidewalls and a bottom. A barrier layer is positioned over the dielectric layer including the sidewalls within the hole and the bottom of the hole; the barrier layer is operable to seal copper. A copper-doped transition layer is positioned over the barrier layer; the transition layer has a resistivity higher than pure copper and is operable to strongly bond to copper and to the barrier layer, whereby electomigration reliability is improved. The remainder of said hole is filled with copper. The hole can be either a trench or a trench and a via.
Patent Number: 6,951,812 Issued on 10/04/2005 to Jiang, et al.
| Inventors:
|
Jiang; Qing-Tang (Austin, TX);
Tsu; Robert (Plano, TX);
Brennan; Kenneth D. (Austin, TX)
|
| Assignee:
|
Texas Instruments Incorporated (Dallas, TX)
|
| Appl. No.:
|
739980 |
| Filed:
|
December 17, 2003 |
| Current U.S. Class: |
438/643; 438/613; 438/637; 438/638; 438/687; 438/692 |
| Intern'l Class: |
H01L 021/47.63 |
| Field of Search: |
438/643,637,638,692,687,613
|
References Cited [Referenced By]
U.S. Patent Documents
Primary Examiner: Smith; Matthew
Assistant Examiner: Anya; Igwe U.
Attorney, Agent or Firm: McLarty; Peter K., Brady, III; W. James, Telecky, Jr.; Frederick J.
Parent Case Text
This application is a divisional of application Ser. No. 10/107,630, filed Mar.
27, 2002 now U.S. Pat. No. 6,693,356.
Claims
1. A method for fabricating an integrated circuit in the horizontal surface of
a semiconductor body, comprising the steps of:
forming a dielectric layer over said semiconductor body;
etching a substantially vertical hole through said dielectric layer, said hole
having a bottom and sidewalls;
forming a barrier layer over said dielectric layer including said sidewalls within
said hole and the bottom of said hole, said barrier layer operable to seal copper;
forming a copper-doped transition layer over said barrier layer, thereby providing
strong bonding to copper and improving electromigration reliability;
selectively removing said barrier layer using an anisotropic plasma etching process,
which removes the generally horizontal barrier portion on the bottom of said hole;
and
filling the remainder of said hole with copper using copper plating without the
need for a copper seed layer deposition.
2. The method according to claim 1, further comprising the step of chemically-mechanically
polishing said copper, transition layer and barrier layer, thereby planarizing
said surface.
3. The method according to claim 1 wherein said step of forming said cooper-doped
transition layer includes physical vapor deposition, or chemical vapor deposition,
or atomic layer chemical mechanical deposition.
4. A method for completing an integrated circuit in the horizontal surface of
a semiconductor body having interconnecting metal lines, comprising the steps of:
forming an interlevel dielectric layer over said semiconductor body;
forming an intrametal dielectric layer over said interlevel dielectric layer;
etching a substantially vertical trench into said intrametal dielectric layer
and a substantially vertical via into said interlevel dielectric layer;
depositing a barrier layer over said intrametal dielectric layer including within
said trench and said via, said barrier layer operable to seal copper;
depositing a copper-doped transition layer over said barrier layer including
within said trench and said via;
selectively removing said barrier layer and said transition layer from the bottom
of said via, thereby exposing said metal line; and
filling the remainder of said trench and said via with copper.
Description
FIELD OF THE INVENTION
The present invention is related in general to the field of electronic systems
and semiconductor devices, and more specifically to processes in integrated circuit
fabrication aiming at reliable multi-level copper metallization.
DESCRIPTION OF THE RELATED ART
In the last few years, copper interconnection has been adapted to silicon integrated
circuits due to its low resistance and high electromigration reliability compared
to the traditional aluminum interconnection. Single-damascene and dual-damascene
methods have been employed for the fabrication of copper interconnection. For multi-level
copper interconnects using any of these two methods, improved electromigration
reliability, especially improved lifetime of early failures have been reported,
for example, in the recent article "A High Reliability Copper Dual-Damascene Interconnection
with Direct-Contact Via Structure" (K. Ueno et al, IEEE Internat. Electron Devices
Meeting 2000, Dec. 10-13, pp. 265-268). In the technique described, the improvement
in multi-level copper circuits has been achieved by making the copper contacts
on the bottom of interconnecting vias barrier-free except for an ultra-thin adhesion layer.
In spite of progress such as described in that paper, in known technology many
problems still remain related to the copper interconnection concept. For example,
the copper traces have to be sealed by barrier layers in order to prevent copper
migration into the silicon circuitry where copper atoms are known to offer energy
levels for electron recombination/generation, acting as electron life-time killers.
The same sealing barriers should protect the porous insulating layers of low dielectric
constant (so-called low-k materials) against intruding atoms, which may initiate
coalescence of micro-voids into larger voids.
As an additional example, in the preparation process of copper-filled vias, care
has to be taken to prepare the via linings so that copper resistivity is prevented
from increasing inordinately when the via diameter is shrinking. Some progress
in this direction has been described recently in U.S. patent application Ser. No.
90/975,571, filed on Oct. 11, 2001 (Qing-Tang Jiang, "Reducing Copper Line Resistivity
by Smoothing Trench and Via Sidewalls"). No attention has been given, however,
to practical methods such as whether the via fabrication steps are cost-effective
and simple enough for easy clean-up after via preparation.
It has been well documented that grain boundaries, dislocations, and point defects
aid the material transport of electromigration (see, for example, S. M. Sze, "VLSI
Technology", McGraw Hill, pp. 409-413, 1988). With the continuing trend of shrinking
integrated circuit feature sizes, these unwelcome effects become ever more important,
but no techniques have been disclosed for copper metallization to mitigate or avoid
these effects.
An urgent need has, therefore, arisen for a coherent, low-cost method of fabricating
copper metallizations and copper-filled via interconnections in single and especially
dual damascene technology and, simultaneously, improve the degree of component
reliability. The fabrication method should be simple, yet flexible enough for different
semiconductor product families and a wide spectrum of design and process variations.
Preferably, these innovations should be accomplished without extending production
cycle time, and using the installed equipment, so that no investment in new manufacturing
machines is needed.
SUMMARY OF THE INVENTION
The invention describes the structure and the fabrication method of an integrated
circuit in the horizontal surface of a semiconductor body comprising a dielectric
layer over said semiconductor body and a substantially vertical hole through the
dielectric layer, the hole having sidewalls and a bottom. A barrier layer is positioned
over the dielectric layer including the sidewalls within the hole and the bottom
of the hole; the barrier layer is operable to seal copper. A copper-doped transition
layer is positioned over the barrier layer; the transition layer has a resistivity
higher than pure copper and is operable to strongly bond to copper and to the barrier
layer, whereby electomigration reliability is improved. The remainder of said hole
is filled with copper. The hole can be either a trench or a trench and a via.
The barrier deposition and etching method described by the invention is applicable
to any dielectric layer, but especially to porous materials of low dielectric constants.
The barrier materials acceptable by the invention include many refractory metals,
compounds such as dielectric metal carbides and nitrides, organic dielectric materials,
and silicon dioxide. The barrier layers have a thickness in the range from 1 to
50 nm.
The copper-doped transition layer over the barrier layer include materials which
provide an electrical resistivity high enough and a current density low enough
to suppress electromigration. In some materials, the copper doping exhibits a gradient
from low to high, and therefore the resistivity from high to low, from the barrier
layer to the copper in the hole. The transition layers have a thickness in the
range from 50 to 120 nm.
If the transition layer resistivity can be maintained low enough while still
satisfying
the basic requirement that copper plating can directly take place on the transition
layer, then a copper seed layer deposition will not be necessary. Copper plating
can follow right after the copper transition layer deposition.
As a technical advantage of the invention, the transition and barrier layers
offer
easy chemical clean-up after completing the selective removal process in order
to selectively remove the transition and barrier layers from the bottom of the vias.
For the composite structure of a trench-level dielectric and a via-level dielectric,
coupled by a middle stop layer, the process step of selectively removing the transition
and barrier layers on the bottom of the via comprises a fine-tuned anisotropic
plasma etching process. According to the invention, the etch step is designed to
remove the (generally horizontal) transition and barrier portions on the bottom
of the hole together with the (generally horizontal) transition and barrier portions
on the middle stop layer and penetrate only partially into the middle stop layer.
Consequently, the remaining stop layer continues to seal the porous dielectric material.
It is an aspect of the invention that the method is fully compatible with dual
damascene process flow and deep sub-micron (0.18 μm and smaller) technologies.
The technical advances represented by the invention, as well as the aspects thereof,
will become apparent from the following description of the preferred embodiments
of the invention, when considered in conjunction with the accompanying drawings
and the novel features set forth in the appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates schematic cross sections through copper filled trenches and
vias in insulators to illustrate the effect of increasingly important interfaces
due to shrinking feature sizes.
FIG. 2A shows a schematic cross section through copper-filled trenches and via,
lined with barrier layers.
FIG. 2B shows a schematic cross section through copper-filled trenches and via,
lined with copper-doped transition layers and barrier layers according to the invention.
FIG. 3 shows the top view of a copper line, embedded in barrier layers and insulators,
illustrating the electrical current flow in the line and the barrier to emphasize
the origin of electromigration.
FIGS. 4A and 4B show Weibull plots with lifetime data for copper lines with
barrier layers having different resistivities and current-carrying capabilities.
FIG. 5 shows the top view of a copper line, embedded on copper-doped transition
layers and barrier layers, illustrating the electrical current flow in the line
and the transition layers to emphasize the suppression of electromigration.
FIG. 6 is a plot of resistivity and current density in the transition layer
due to copper doping.
FIG. 7 compares diffusivity in copper of materials for the transition layer,
illustrating layer stability.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
The present invention is related to U.S. patent application Ser. No. 09/863,687,
filed on May 23, 2001 (Brennan et al., "Method for Sealing Via Sidewalls in Porous
Low-k Dielectric Layers"); and Ser. No. 09/975,571, filed on Oct. 11, 2001 (Jiang,
"Reducing Copper Line Resistivity by Smoothing Trench and Via Sidewalls").
FIG. 1 is a schematic cross section through two-level integrated circuit (IC)
metallization structure, generally designated
100. Over a semiconductor
body
101 is formed a first intralevel dielectric layer
102, followed
by an interlevel dielectric layer
103, and topped by a second intralevel
dielectric layer
104. The dielectric material is a low-k material
140.
A trench
105 has been etched in the first intralevel dielectric layer
101,
another trench
106 has been etched in the second intralevel layer
104,
and a via
107 has been etched in the interlevel dielectric layer
103.
Both trenches
105 and
106 and the via
107 have been filled
with copper
150 (trench
105 forming the first metallization level,
and trench
106 forming the second metallization level). Because of the nature
of the copper, the sidewalls of the trenches and the via have to be lined with
a thin barrier layer
130 in order to prevent any out-diffusion out-drifting
of copper into the dielectric material
110 (or into the semiconductor body
101).
160 is a top dielectric barrier, preferably a layer of silicon
carbide or silicon carbo-nitride, or a stack of both layers.
In order to symbolize the trend for shrinking feature sizes, another trench
115
has been etched in the first intralevel dielectric layer
101; trench
115
has smaller cross section than trench
105. Likewise, trench
116,
etched in the second intralevel dielectric layer
104, has a smaller cross
section than trench
106. Also via
117, etched in the interlevel dielectric
layer
103, has smaller cross section than via
107. Again, both trenches
115 and
116 and the via
117 are filled with copper. Consequently,
the needed barrier layer
131 is substantially the same as barrier layer
130.
The ongoing trend for linewidth miniaturization is indicated by the third set
of trenches
125 and
126 and via
127 in FIG.
1. Again,
barrier
132 is substantially the same as barriers
130 and
131.
This miniaturization trend has two consequences for electromigration:
The current density in the metallization increases; and
The unchanged interface barrier/copper increases in importance relative
to the shrinking copper line and via. The percentage of copper in the sidewall
interface region increases as the linewidth decreases.
The drift velocity of migrating ions is proportional to the current density,
the electrical resistivity, and the diffusivity, and inverse proportional to an
exponential term containing the diffusion activation energy (see S. M. Sze, "VLSI
Technology", p. 410, McGraw Hill 1988). The diffusivity is greatly determined by
the presence of interfaces, grain boundaries, dislocation, etc. Consequently, the
sidewall electromigration reliability of metal interconnections as illustrated
in FIG. 1 becomes more important as the line and via dimensions decrease relative
to the sidewall interface region.
The schematic cross section of FIG. 2A repeats the status of the present technology
for copper metallization in order to compare it with FIG. 2B, which illustrates
the solution according to the teachings of the present invention. In FIG. 2A as
well as in FIG. 2B, a barrier layer
201 lines trench
202, trench
203 and via
204. Trenches
202 and
203, as well as via
204 are filled with copper. There are several options for the barrier layer:
The barrier layer is made of a refractory metal selected from a group consisting
of titanium, tantalum, tungsten, molybdenum, chromium, and compounds thereof;
the barrier layer is made of an insulating dielectric compound selected
from a group consisting of silicon carbon nitride, silicon carbide, titanium nitride,
tantalum nitride, tungsten nitride, tungsten carbide, silicon nitride, titanium
silicon nitride, and tantalum silicon nitride;
the barrier layer is made of an organic dielectric material.
Preferably, the barrier layer
201 has a thickness in the range
from 1 to 50 nm. The barrier layer seals porous dielectric layers
210,
211
and
212 (low dielectric constants) so that micro-voids within said porous
dielectric layers are prevented from coalescing into larger voids, and copper is
prevented from migrating from said hole into said dielectric layers. The structures
in FIGS. 2A and 2B further have dielectric layers
220, preferably made of
silicon carbo-nitride, silicon nitride, or silicon carbo-oxide.
According to the invention, a transition layer
240 of copper-containing
material lines the trenches
202 and
203 and the via
204. The
transition layer provides an electrical resistivity high enough and a current density
low enough to suppress electromigration originating at the copper-barrier interface.
The transition layer is selected from a group of materials consisting of:
copper tantalum, copper magnesium, copper aluminum, copper silicon, copper
chromium, copper beryllium, copper zirconium, copper nickel, copper zinc, copper
silver, copper titanium, and copper palladium.
- Preferred choices are copper zirconium and copper tin.
The transition layer has a thickness in the range 50 to 120 nm. Over this range,
copper may be incorporated in a gradient fashion or in constant concentration.
A comparison between the flow of electrical current through the copper metallization
line in the presence of a copper-containing transition layer to the case without
such transition layer, is schematically illustrated by a comparison between FIGS.
5 and 3. Both figures represent lengthwise cross sections through, or top views
of, the metallization lines. In FIG. 3, the copper line is designated
301,
with the arrows
301a schematically indicating the current strength
and density (the length and density of the arrows
301a in FIG. 3
are not necessarily to be interpreted in a quantitative sense). The copper line
301 is surrounded by and embedded in barrier layer
302. In FIG. 3,
the barrier layer consists of a refractory metal such as tantalum, which can carry
a small amount of current, indicated by the small arrow
302a. If
the barrier layer were an insulator such as tantalum nitride, no current would
flow in the barrier layer. The barrier layers
302, in turn, are imbedded
in isolation material
303.
For electromigration, the critical interface is the interface
310 between
the copper line
301 with its good current-conducting property and the barrier
layer
302 with its poor current-conducting capability. As discussed above,
it is at this interface
310 where electromigration failures are likely to originate.
FIGS. 4A and 4B show measured data of the copper metallization lifetime as
a function of the barrier material, or current-carrying capability of the barrier.
Both figures represent Weibull plots of dual damascene samples at 325° C.,
in FIG. 4A for 0.35 μm line width and 1.6 mA/cm
2 current density,
in FIG. 4B for 0.5 μm line width and 1.0 mA/cm
2 current density.
Plotted are the log-log survival rates as a function of the time-to-failure (measured
in hours). In both FIGS. 4A and 4B, the trend is clearly demonstrated that copper
line lifetimes become the better the lower the resistivity of the barrier is. Copper
samples with tantalum nitride barriers have clearly the poorest survival rate.
Longer lifetimes are obtained in copper samples where a tantalum layer has been
added to outermost tantalum nitride layer (bi-layer barrier samples). Clearly the
best lifetimes are obtained with tantalum-on-copper samples, where the barrier
layers exhibit the best electrical conductivity of the particular samples studied.
According to the invention, an additional layer is inserted between the
copper line and the barrier layer, and the electrical conductivity of this transition
layer is enhanced by "doping" (or alloying) the base metal with copper. FIG. 5,
analogous to FIG. 3, is a schematic cross section through, or top view of, the
copper line
501. The arrows
501a indicate schematically the
current strength and density (the length and density of the arrows
501a
are not necessarily to be interpreted in a quantitative sense). The copper
line
501 is surrounded by and embedded in the copper transition layer
520.
The intermediate length of arrows
520a represents a non-zero, preferably
intermediate strength of the electrical current, although much reduced in comparison
to the current in the copper line
501. Layer
520 consists of a material
from the list quoted above. The copper transition layer is embedded in and surrounded
by the barrier layer
502. It consists of a refractory metal, such as tantalum,
which can carry a small amount of current, indicated by the small arrow
502a.
If the barrier were an insulator such as tantalum nitride, no current would flow
in the barrier layer. The barrier layers
502, in turn, are imbedded in isolation
material
503.
For electromigration, the critical interface is the interface
510 between
the copper line
501 with its good current-conducting property and the copper-doped
transition layer
502 with its intermediate current-conducting capability.
Experience has shown that at this interface
510 hardly any electromigration
failures originate; consequently, the lifetime of devices having the copper-doped
transition layer is dramatically increased.
The main reason for this improvement is the gradual increase of the current density,
rather than the abrupt increase as in the sample illustrated in FIG.
3.
FIG. 6 depicts the correlation of the resistivity (in μΩcm) as created
by the copper doping and the resultant current density (in a/cm
2), as
a function of the depth (in nm) from the beginning
511 of the copper-doped
transition layer (or sidewall).
The metal selection of the transition layer is greatly determined by the desire
to retain the integrity of the transition layer and to prevent any gradual diminishing
or shrinkage by out-diffusion, out-solution, or any other intermixing. Two examples,
which basically fulfill this condition, are listed in FIG. 7 (the data are reproduced
from the paper of C. P. Wang et al., IITC Conference, June 2001, pp. 86). As can
be seen from this example, zirconium hardly diffuses in copper, even at 400°
C., while tin slightly diffuses in copper @400° C. The addition of 1% zirconium
in copper creates a significant resistivity (19.8 μΩcm); the resistivity
of 1% tin in copper creates just 5.4 μΩcm. The data suggest that in
principal both zirconium and tin are acceptable candidates for transition layer metals.
Another aspect in the selection of the transition layer metals is the need
for perfect adhesion between the transition layer and the copper line, and also
between the transition layer and the barrier layer. Besides the compatibility of
the metals, the deposition methods are important. See method description below.
The process of fabricating an integrated circuit in the horizontal surface of
a semiconductor body according to the invention comprises the steps of:
forming a dielectric layer over the semiconductor body;
etching a substantially vertical hole through the dielectric layer, the
hole having a bottom and sidewalls;
depositing a barrier layer over the dielectric layer including the sidewalls
within the hole and the bottom of the hole, the barrier layer operable to seal copper;
depositing a copper-doped transition layer over the barrier layer, thereby
providing strong bonding to copper and improving electromigration reliability.
Deposition techniques include physical vapor deposition, chemical vapor deposition,
or atomic layer chemical mechanical deposition; and
filling the remainder of the hole with copper. Techniques include copper
plating without the need for copper seed layer deposition.
Further, the step of chemically-mechanically polishing the copper, transition
layer and barrier layer may be added, thereby planarizing the surface.
Further, the step of selectively removing the barrier layer may be added,
comprising an anisotropic plasma etching process, which removes the generally horizontal
barrier portion on the bottom of the hole.
The process for completing an integrated circuit in the horizontal surface of
a semiconductor body having metal lines according to the invention comprises the
steps of:
forming an interlevel dielectric layer over the semiconductor body;
forming an intrametal dielectric layer over the interlevel dielectric layer;
etching a substantially vertical trench into the intrametal dielectric layer
and a substantially vertical via into said interlevel dielectric layer;
depositing a barrier layer over the intrametal dielectric layer including
within said trench and the via, the barrier layer operable to seal copper;
depositing a copper-doped transition layer over the barrier layer including
within the trench and the via;
selectively removing the barrier layer and the transition layer from the
bottom of the via, thereby exposing the metal line; and
filling the remainder of the trench and the via with copper.
While this invention has been described in reference to illustrative embodiments,
this description is not intended to be construed in a limiting sense. Various modifications
and combinations of the illustrative embodiments, as well as other embodiments
of the invention, will be apparent to persons skilled in the art upon reference
to the description. An example is the fine-tuning of the anisotropic plasma etch
to achieve specific side wall structures when the via diameter is scaled down with
the shrinking feature sizes of the integrated circuit designs. It is therefore
intended that the appended claims encompass any such modifications or embodiments.
*
