Current driver and display device Number:7,145,379 from the United States Patent and Trademark Office (PTO) owispatent

Title: Current driver and display device

Abstract: The first and second chips are provided side by side. The first chip includes: a current supply section for outputting a drive current, the current supply section including a current mirror; a current distribution MISFET; a current input MISFET for transmitting an electric current to the current supply section, the current input MISFET being connected to the current distribution MISFET; and a second current distribution MISFET. The current distribution MISFET and the second current distribution MISFET constitute a current mirror. The second chip includes a second current input MISFET which is connected to the second current distribution MISFET. The ratio between the W/L ratio of the current distribution MISFET and the W/L ratio of the current input MISFET connected thereto is the same in the first and second chips.

Patent Number: 7,145,379 Issued on 12/05/2006 to Date,   et al.

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Inventors:	Date; Yoshito (Shiga, JP), Omori; Tetsuro (Osaka, JP), Dosho; Shiro (Osaka, JP), Mizuki; Makoto (Kyoto, JP)
Assignee:	Matsushita Electric Industrial Co., Ltd. (Osaka, JP)
Appl. No.:	10/815,800
Filed:	April 2, 2004

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Foreign Application Priority Data

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Jul 29, 2003 [JP]			2003-281848

Current U.S. Class:	327/431 ; 345/90
Current International Class:	H03K 17/687 (20060101); G09G 3/36 (20060101)
Field of Search:	327/430-431,427,434,437,108,112 323/315 345/90,204

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References Cited [Referenced By]

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U.S. Patent Documents

	5596372		January 1997		Berman et al.
	5633653		May 1997		Atherton
	5696459		December 1997		Neugebauer et al.
	5748044		May 1998		Xue
	6204834		March 2001		Baker et al.
	6222357		April 2001		Sakuragi
	6456270		September 2002		Itakura
	6509854		January 2003		Morita et al.
	6586888		July 2003		Kitahara et al.
	6646481		November 2003		Blankenship et al.
	6765560		July 2004		Ozawa
	6777885		August 2004		Koyama
	6882186		April 2005		Nishitoba
	6897619		May 2005		Shimizu
	6858742		October 2005		Date et al.
	2003/0067345		April 2003		Blankenship et al.
	2003/0151687		August 2003		Hanada et al.
	2003/0184566		October 2003		Date et al.
	2005/0073513		April 2005		Date

Foreign Patent Documents

	62-262517		Nov., 1987		JP
	05-216439		Aug., 1993		JP
	09-319323		Dec., 1997		JP
	11-205147		Jul., 1999		JP
	11-340765		Dec., 1999		JP
	2000-310981		Nov., 2000		JP
	2002-202823		Jul., 2002		JP

Primary Examiner: Ton; My-Trang Nu
Attorney, Agent or Firm: McDermott Will & Emery LLP

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Claims

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What is claimed is:

1. A current driver integrated on a semiconductor chip, comprising: a first current distribution MISFET of a first conductivity type, a source of the first current distribution MISFET being supplied with a supply voltage; a first current input MISFET of a second conductivity type, a drain of the first current input MISFET being electrically connected to a drain of the first current distribution MISFET, the drain and a gate electrode of the first current input MISFET being electrically connected to each other; a second current input MISFET of the second conductivity type, a gate electrode of the second current input MISFET being electrically connected to the gate electrode of the first current input MISFET, a drain and the gate electrode of the second current input MISFET being electrically connected to each other; a plurality of current supply sections each including a current source MISFET of the second conductivity type, electrodes of a plurality of current source MISFETs of the plurality of current supply sections being electrically connected to the gate electrodes of the first and second current input MISFETs; a second current distribution MISFET of the first conductivity type, a gate electrode of the second current distribution MISFET being electrically connected to a gate electrode of the first current distribution MISFET, a drain of the second current distribution MISFET being electrically connected to the drain of the second current input MISFET; a third current distribution MISFET of the first conductivity type provided adjacent to the second current distribution MISFET, a gate electrode of the third current distribution MISFET being electrically connected to the gate electrodes of the first current distribution MISFET and the second current distribution MISFET; and a first current output terminal being electrically connected to a drain of the third current distribution MISFET.

2. The current driver of claim 1, wherein a distance between the second current distribution MISFET and the third current distribution MISFET is equal to or shorter than 200 um.

3. The current driver of claim 1, further comprising a bias power supplying terminal being electrically connected to the gate electrode of the second current distribution MISFET and the gate electrode of the third current distribution MISFET.

4. The current driver of claim 1, further comprising: an additional current distribution MISFET of the first conductivity type provided in a region of the semiconductor chip which is distant from the third current distribution MISFET by 200 um or less, a gate electrode of the additional current distribution MISFET being electrically connected to the gate electrodes of the second current distribution MISFET and the third current distribution MISFET; and an additional current output terminal being electrically connected to a drain of the additional current distribution MISFET.

5. The current driver of claim 1, further comprising: a first cascode MISFET of the first conductivity type which is provided between the first current distribution MISFET and the first current input MISFET; a second cascode MISFET of the first conductivity type which is provided between the second current distribution MISFET and the second current input MISFET; a third cascode MISFET of the first conductivity type which is provided between the third current distribution MISFET and the first current output terminal; and a first gate bias line being electrically connected to gate electrodes of the first cascode MISFET, the second cascode MISFET and the third cascode MISFET, one end of the first gate bias line being electrically connected to a node supplying a first constant-voltage power supply.

6. The current driver of claim 1, further comprising: a fourth cascode MISFET of the second conductivity type which is provided between the first current distribution MISFET and the first current input MISFET, a drain of the fourth cascode MISFET being electrically connected to the gate electrode of the first current input MISFET; a fifth cascode MISFET of the second conductivity type which is provided between the second current distribution MISFET and the second current input MISFET, a drain of the fifth cascode MISFET being electrically connected to the gate electrode of the second current input MISFET; a plurality of sixth cascode MISFETs of the second conductivity type, each of the plurality of sixth cascode MISFETs being electrically connected to each drain of each of the plurality of current source MISFETs of the plurality of current supply sections; and a second gate bias line being electrically connected to gate electrodes of the fourth cascode MISFET, the fifth cascode MISFET and the plurality of sixth cascode MISFETs, one end of the second gate bias line being electrically connected to a node supplying a second constant-voltage power supply.

7. A current driver integrated on a semiconductor chip, comprising: a first current input terminal; a first current input MISFET of a first conductivity type, a drain of the first current input MISFET being electrically connected to the first current input terminal, and the drain and a gate electrode of the first current input MISFET being electrically connected to each other; a plurality of current supply sections each including a current source MISFET of the first conductivity type, each gate electrode of a plurality of current source MISFETs of the plurality of current supply sections being electrically connected to the gate electrode of the first current input MISFET; a second current input MISFET of the first conductivity type, a drain and a gate electrode of the second current input MISFET being electrically connected to each other, the gate electrode of the second current input MISFET being electrically connected to the gate electrode of the first current input MISFET; a bias power input tenninal; a first current distribution MISFET of a second conductivity type, a gate electrode of the first current distribution MISFET being electrically connected to the bias power input terminal, a drain of the first current distribution MISFET being electrically connected to the drain of the second current input MISFET; a second current distribution MISFET of the second conductivity type provided in a region of the semiconductor chip which is distant from the first current distribution MISFET by 200 um or less, a gate electrode of the second current distribution MISFET being electrically connected to the gate electrode of the first current distribution MISFET; a first current output terminal being electrically connected to a drain of the second current distribution MISFET; and a first bias power output terminal being electrically connected to the gate electrode of the second current distribution MISFET.

8. A current driver integrated on a semiconductor chip, comprising: a first current input terminal; a first current input MISFET of a first conductivity type, a drain of the first current input MISFET being electrically connected to the first current input terminal, and the drain and a gate electrode of the first current input MISFET being electrically connected to each other; a plurality of current supply sections each including a current source MISFET of the first conductivity type, each gate electrode of a plurality of current source MISFETs of the plurality of current supply sections being electrically connected to the gate electrode of the first current input MISFET; a second current input MISFET of the first conductivity type, a drain and a gate electrode of the second current input MISFET being electrically connected to each other, the gate electrode of the second current input MISFET being electrically connected to the gate electrode of the first current input MISFET; and a second current input terminal being electrically connected to the drain of the second current input MISFET.

9. A current driver integrated on a semiconductor chip, comprising: a first current input terminal; a first current input MISFET of a first conductivity type, a drain of the first current input MISFET being electrically connected to the first current input terminal, and the drain and a gate electrode of the first current input MISFET being electrically connected to each other; a plurality of current supply sections each including a current source MISFET of the first conductivity type, each gate electrode of a plurality of current source MISFETs of the plurality of current supply sections being electrically connected to the gate electrode of the first current input MISFET; a current output MISFET of the first conductivity type, a gate electrode of the current output MISFET being electrically connected to the gate electrode of the first current input MISFET and the gate electrodes of the plurality of current source MISFETs; a first current distribution MISFET of a second conductivity type, a drain and a gate electrode of the first current distribution MISFET being electrically connected to each other, the drain of the first current distribution MISFET being electrically connected to a drain of the current output MISFET; a second current input MISFET of the first conductivity type, a drain and a gate electrode of the second current input MISFET being electrically connected to each other, the gate electrode of the second current input MISFET being electrically connected to the gate electrode of the first current input MISFET; a second current distribution MISFET of the second conductivity, a gate electrode of the second current distribution MISFET being electrically connected to the gate electrode of the first current distribution MISFET and a drain of the second current distribution MISFET being electrically connected to the drain of the second current input MISFET; a third current distribution MISFET of the second conductivity provided in a region of the semiconductor chip which is distant from the second current distribution MISFET by 200 um or less, a gate electrode of the third current distribution MISFET being electrically connected to the gate electrode of the second current distribution MISFET; and a first current output terminal being electrically connected to a drain of the third current distribution MISFET.

10. A current driver integrated on a semiconductor chip, comprising: a first current distribution MISFET of a first conductivity type; a first current input MISFET of a second conductivity type, a drain of the first current input MISFET being electrically connected to a drain of the first current distribution MISFET, the drain and a gate electrode of the first current input MISFET being electrically connected to each other; a second current input MISFET of the second conductivity type, a gate electrode of the second current input MISFET being electrically connected to the gate electrode of the first current input MISFET, a drain and the gate electrode of the second current input MISFET being electrically connected to each other; a plurality of current supply sections each including a current source MISFET of the second conductivity type, a plurality of current source MISFETs of the plurality of current supply sections being between the first current input MISFET and second current input MISFET and gate electrodes of the plurality of current source MISFETs being electrically connected to the gate electrodes of the first and second current input MISFETs; a second current distribution MISFET of the first conductivity type, a gate electrode of the second current distribution MISFET being electrically connected to a gate electrode of the first current distribution MISFET, a drain of the second current distribution MISFET being electrically connected to the drain of the second current input MISFET; a third current distribution MISFET of the first conductivity type, a gate electrode of the third current distribution MISFET being electrically connected to the gate electrodes of the first current distribution MISFET and the second current distribution MISFET; and a first current output terminal being electrically connected to a drain of the third current distribution MISFET.

11. The current driver of claim 10, wherein the plurality of current source MISFETs of the plurality of current supply sections are formed in a region between the first current input MISFET and second current input MISFET.

12. The current driver of claim 10, wherein the plurality of current source MISFETs of the plurality of current supply sections are formed in a region extending between the first current input MISFET and second current input MISFET.

13. The current driver of claim 10, wherein a distance between the second current distribution MISFET and the third current distribution MISFET is equal to or shorter than 200 um.

14. The current driver of claim 10, further comprising: a bias power supplying terminal being electrically connected to the gate electrode of the second current distribution MISFET and the gate electrode of the third current distribution MISFET.

15. The current driver of claim 10, further comprising: an additional current distribution MISFET of the first conductivity type, a gate electrode of the additional current distribution MISFET being electrically connected to the gate electrodes of the second current distribution MISFET and the third current distribution MISFET; and an additional current output terminal being electrically connected to a drain of the additional current distribution MISFET.

16. The current driver of claim 10, further comprising: a first cascode MISFET of the first conductivity type being provided between the first current distribution MISFET and the first current input MISFET; a second cascode MISFET of the first conductivity type being provided between the second current distribution MISFET and the second current input MISFET; a third cascode MISFET of the first conductivity type being provided between the third current distribution MISFET and the first current output terminal, wherein gate electrodes of the first cascode MISFET, the second cascode MISFET and the third cascode MISFET are electrically connected to a node supplying a first constant-voltage power supply.

17. The current driver of claim 10, further comprising: a fourth cascode MISFET of the second conductivity type being provided between the first current distribution MISFET and the first current input MISFET, a drain of the fourth cascode MISFET being electrically connected to the gate electrode of the first current input MISFET; a fifth cascode MISFET of the second conductivity type being provided between the second current distribution MISFET and the second current input MISFET, a drain of the fifth cascode MISFET being electrically connected to the gate electrode of the second current input MISFET; a plurality of sixth cascode MISFETs of the second conductivity type, each of the plurality of sixth cascode MISFETs being electrically connected to each drain of the plurality of current source MISFETs, wherein gate electrodes of the fourth cascode MISFET, the fifth cascode MISFET and the plurality of sixth cascode MISFETs are electrically connected a node supplying to a second constant-voltage power supply.

18. A current driver integrated on a semiconductor chip, comprising: a first current input terminal; a first current input MISFET of a first conductivity type, a drain of the first current input MISFET being electrically connected to the first current input terminal, and the drain and a gate electrode of the first current input MISFET being electrically connected to each other; a second current input MISFET of the first conductivity type, a drain and a gate electrode of the second current input MISFET being electrically connected to each other, the gate electrode of the second current input MISFET being electrically connected to the gate electrode of the first current input MISFET; a plurality of current supply sections each including a current source MISFET of the first conductivity type, a plurality of current source MISFETs of the plurality of current supply sections being between the first current input MISFET and the second current input MISFET and each gate electrode of the plurality of current source MISFETs being electrically connected to the gate electrodes of the first and second current input MISFETs; a bias power input terminal; a first current distribution MISFET of a second conductivity type, a gate electrode of the first current distribution MISFET being electrically connected to the bias power input terminal, a drain of the first current distribution MISFET being electrically connected to the drain of the second current input MISFET; a second current distribution MISFET of the second conductivity type, a gate electrode of the second current distribution MISFET being electrically connected to the gate electrode of the first current distribution MISFET; a first current output terminal being electrically connected to a drain of the second current distribution MISFET; and a first bias power output terminal being electrically connected to the gate electrode of the second current distribution MISFET.

19. The current driver of claim 18, wherein the plurality of current source MISFETs of the plurality of current supply sections are formed in a region between the first current input MISFET and second current input MISFET.

20. The current driver of claim 18, wherein the plurality of current source MISFETs of the plurality of current supply sections are formed in a region extending between the first current input MISFET and second current input MISFET.

21. A current driver integrated on a semiconductor chip, comprising: a first current input terminal; a first current input MISFET of a first conductivity type, a drain of the first current input MISFET being electrically connected to the first current input terminal, and the drain and a gate electrode of the first current input MISFET being electrically connected to each other; a second current input MISFET of the first conductivity type, a drain and a gate electrode of the second current input MISFET being electrically connected to each other, the gate electrode of the second current input MISFET being electrically connected to the gate electrode of the first current input MISFET; a plurality of current supply sections each including a current source MISFET of the first conductivity type, a plurality of current source MISFETs of the plurality of current supply sections being between the first current input MISFET and the second current input MISFET and each gate electrode of the plurality of current source MISFETs being electrically connected to the gate electrodes of the first and second current input MISFETs; and a second current input terminal being electrically connected to the drain of the second current input MISFET.

22. The current driver of claim 21, wherein the plurality of current source MISFETs of the plurality of current supply sections are formed in a region between the first current input MISFET and second current input MISFET.

23. The current driver of claim 21, wherein the plurality of current source MISFETs of the plurality of current supply sections are formed in a region extending between the first current input MISFET and second current input MISFET.

24. A current driver integrated on a semiconductor chip, comprising: a first current input terminal; a first current input MISFET of a first conductivity type, a drain of the first current input MISFET being electrically connected to the first current input terminal, and the drain and a gate electrode of the first current input MISFET being electrically connected to each other; a second current input MISFET of the first conductivity type, a drain and a gate electrode of the second current input MISFET being electrically connected to each other, the gate electrode of the second current input MISFET being electrically connected to the gate electrode of the first current input MISFET; a plurality of current supply sections each including a current source MISFET of the first conductivity type, a plurality of current source MISFETs of the plurality of current supply sections being between the first current input MISFET and the second current input MISFET and each gate electrode of the plurality of current source MISFETs being electrically connected to the gate electrodes of the first and second current input MISFETs; a current output MISFET of the first conductivity type, a gate electrode of the current output MISFET being electrically connected to the gate electrodes of the first and second current input MISFETs and the gate electrodes of the plurality of current source MISFETs; a first current distribution MISFET of a second conductivity type, a drain and a gate electrode of the first current distribution MISFET being electrically connected to each other, the drain of the first current distribution MISFET being electrically connected to a drain of the current output MISFET; a second current distribution MISFET of the second conductivity type, a gate electrode of the second current distribution MISFET being electrically connected to the gate electrode of the first current distribution MISFET and a drain of the second current distribution MISFET being electrically connected to the drain of the second current input MISFET; a third current distribution MISFET of the second conductivity type, a gate electrode of the third current distribution MISFET being electrically connected to the gate electrodes of the first and second current distribution MISFETs; and a first current output terminal being electrically connected to a drain of the third current distribution MISFET.

25. The current driver of claim 24, wherein the plurality of current source MISFETs of the plurality of current supply sections are formed in a region between the first current input MISFET and second current input MISFET.

26. The current driver of claim 24, wherein the plurality of current source MISFETs of the plurality of current supply sections are formed in a region extending between the first current input MISFET and second current input MISFET.

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Description

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CROSS-REFERENCE TO RELATED APPLICATION

This nonprovisional application claims priority under 35 U.S.C. .sctn.119(a) on Japanese Patent Application No. 2003-281848, the entire contents of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a current driver and particularly to a technology of current drivers suitable as a display driver for a display device, such as an organic EL (electroluminescent) panel, and the like.

2. Description of the Prior Art

In recent years, in the fields of flat panel displays, such as organic EL panels, and the like, the screen size and definition have been increasing while the thickness, weight and production cost have been decreasing. In general, the active matrix method has been favorably employed as a method for driving a large, high-definition display panel. Hereinafter, a display driver for a conventional active matrix display panel is described.

FIG. 14 is a circuit diagram showing the structure of a display panel and a conventional current driver connected to the display panel. In the example of FIG. 14, the current driver is a display driver. The display panel is an organic EL panel.

Referring to FIG. 14, the conventional current driver includes current supply sections 1001a1, 1001a2, . . . and 1001an (hereinafter, referred to as "current supply section(s) 1001a" when generically mentioned) for supplying driving currents respectively to a plurality of pixel circuits 1005a1, 1005a2, . . . and 1005am (hereinafter, referred to as "pixel circuit(s) 1005a", when generically mentioned) which are arranged in a matrix over the display panel, and a reference current supply section (bias circuit) 1101 for supplying the reference current to the current supply sections 1001a. In the present specification, the "reference current" means an electric current having a predetermined value, which is supplied from a reference current source. The "reference current" also means an electric current derived from the reference current source and transmitted by a current mirror circuit.

In the case of a device having a large size display panel, such as a television display device, a plurality of semiconductor chips (driver LSI chips) 1105 in which current supply sections 1001a having m output terminals are integrated are used for driving the display panel. In many cases, these semiconductor chips 1105 are aligned in a line at a peripheral portion of the display panel.

Each of the pixel circuits 1005a1, 1005a2, . . . and 1005am includes a first TFT (Thin Film Transistor) 1104 of p-channel type, which is connected to the current supply section 1001a through a signal line, a second TFT 1102, and an organic EL element 1103 which emits light according to an electric current supplied from the second TFT 1102. The first TFT 1104 and second TFT 1102 constitute a current mirror circuit.

The reference current supply section 1101 includes: a first MISFET 1108 of p-channel type, one end of which being supplied with a supply voltage; a resistor 1107 for generating a reference current, which is connected to the first MISFET 1108; a second MISFET 1109 of p-channel type; and a current input MISFET 1110 of n-channel type for transmitting the reference current to the current supply sections 1001a, which is connected to the second MISFET 1109. The first MISFET 1108 and second MISFET 1109 constitute a current mirror circuit. In the example of FIG. 14, the reference current supply section 1101 is provided outside the semiconductor chips 1105. However, the reference current supply section 1101 may be provided on the semiconductor chip 1105. In this specification, in an example where a plurality of semiconductor chips 1105 are provided in a display device, a semiconductor chip for supplying the reference current to the other semiconductor chips is referred to as "master chip" while the semiconductor chips which receive the reference current from the "master chip" are referred to as "slave chips".

In a system where n-bit scale is controlled, each of the current supply sections 1001a includes current sources 1112-1, 1112-2, . . . and 1112-n (n is a positive integer) arranged in parallel to each other with respect to an output section that is connected to the pixel circuit 1005a, and switches 1115-1, 1115-2, . . . and 1115-n for controlling the on/off states of the electric current flowing through the current sources 1112-1, 1112-2, . . . and 1112-n. Herein, each of the current sources 1112-1, 1112-2, . . . and 1112-n is formed by an n-channel type MISFET. This n-channel type MISFET and the current input MISFET 1110 constitute a current mirror circuit. Each of the switches 1115-1, 1115-2, . . . and 1115-n independently carries out the switching operation according to display data.

With the above-described structure, the operation of a display device driven by an electric current is controlled.

SUMMARY OF THE INVENTION

However, in the display device having the above-described structure, a defect of image display, such as display unevenness, or the like, is sometimes seen during the display of images. In these years, the screen size of the display panel has been increasing, and accordingly, it is necessary to provide a larger number of driver LSI chips having a longitudinal length of 10 mm to 20 mm as compared with a conventional display panel. In such a case, in a semiconductor chip including a conventional current driver, there is a possibility that a variation occurs among the output currents from output terminals which are distant from each other, and as a result, deterioration in the image quality, such as uneven brightness in a displayed image, or the like, is caused. Especially, a larger variation in the output currents occurs between output terminals of different semiconductor chips 1105 rather than between output terminals of the same semiconductor chip 1105.

The present inventors examined the reasons for the variation among the output voltages at the output terminals of one driver LSI chip (semiconductor chip) for a display device and found that a variation occurs among the electric currents distributed to MISFETs which constitute the current sources 1112 on the semiconductor chip 1105 (see FIG. 14).

A current mirror circuit is originally designed under prerequisites that the dispersion condition of transistors constituting the current mirror circuit are the same, and no significant difference occurs in threshold value Vt or in the carrier mobility between the transistors. In the presence of such prerequisites, the electric current is distributed according to the size ratio of the transistors. However, in the case where the length of the driver LSI chips for a display device is as long as 10 mm to 20 mm, it is considered to be difficult to uniformly disperse impurities in the transistors. Furthermore, if the positions of the transistors are different, a variation in the production process, such as an etching variation, occurs and accordingly a variation in display can also be caused. As a result, a variation occurs among the threshold values of transistors which constitute a current mirror. In the case where a variation occurs among the threshold values of the transistors, an error occurs in the output current when the same gate voltage is applied to the transistors. In general cases, a variation in the dispersion is gradient over a wafer surface. Thus, even when uniform display is carried out based on certain display data, a gradation from darker portions to brighter portions occurs over the display panel.

Furthermore, a variation occurs in the current value among electric currents output from current drivers on different semiconductor chips. In many display devices, the production conditions, such as the dispersion condition, and the like, are different among a plurality of semiconductor chips arranged side by side. Therefore, a variation in the characteristics among the MISFETs which constitute the current sources of the current supply section 1001a1 is greater than that caused in the same chip, and accordingly, uneven display corresponding to respective semiconductor chips 1105 is likely to be seen. We thus concluded that suppressing a variation in output currents from an output terminal among the semiconductor chips 1105 is the most effective solution to suppress uneven display over a display panel.

An objective of the present invention is to provide a current driver capable of suppressing a variation in the output currents among a plurality of driver LSI chips that drive a display device, and a display device including such a current driver.

The first current driver of the present invention is a current driver integrated on a semiconductor chip, comprising: a first current distribution MISFET of a first conductivity type, a source of the first current distribution MISFET being supplied with a supply voltage; a first current input MISFET of a second conductivity type, a drain of the first current input MISFET being connected to a drain of the first current distribution MISFET, the drain and a gate electrode of the first current input MISFET being connected to each other; a second current input MISFET of a second conductivity type, the second current input MISFET and the first current input MISFET constituting a current mirror circuit, a drain and a gate electrode of the second current input MISFET being connected to each other; a first bias line for connecting the gate electrode of the first current input MISFET and the gate electrode of the second current input MISFET; a plurality of current supply sections each including a current source MISFET, the current source MISFET, the first current input MISFET and the second current input MISFET constituting a current mirror circuit, a gate electrode of the current source MISFET being connected to the first bias line; a second current distribution MISFET of the first conductivity type, the second current distribution MISFET and the first current distribution MISFET constituting a current mirror circuit, a drain of the second current distribution MISFET being connected to the drain of the second current input MISFET; a third current distribution MISFET provided adjacent to the second current distribution MISFET, the third current distribution MISFET, the first current distribution MISFET and the second current distribution MISFET constituting a current mirror circuit; and a first current output terminal which is connected to a drain of the third current distribution MISFET.

With the above structure, in a display device, for example, the third current distribution MISFET is connected to a current input MISFET on a neighboring semiconductor chip, whereby an error in the output current at a connecting portion between the adjoining semiconductor chips is reduced as compared with a case where the third current distribution MISFET and the current input MISFET are on the same chip.

The second current driver of the present invention is a current driver integrated on a semiconductor chip, comprising: a first current input terminal; a first current input MISFET of a first conductivity type, a drain of the first current input MISFET being connected to the first current input terminal, and the drain and gate electrode of the first current input MISFET being connected to each other; a plurality of current supply sections including current source MISFETs of the first conductivity type, the current source MISFETs and the first current input MISFET constituting a current mirror circuit; and a bias line which is commonly connected to the gate electrode of the first current input MISFET and the gate electrodes of the current source MISFETs.

For example, the second current driver having the above structure is connected to the first current driver of the present invention, whereby the output current from the current supply section is uniform between the semiconductor chips.

The third current driver of the present invention is a current driver integrated on a semiconductor chip, comprising: a first current distribution MISFET of a first conductivity type, a source of the first current distribution MISFET being supplied with a supply voltage; a current input MISFET of a second conductivity type, a drain of the current input MISFET being connected to a drain of the first current distribution MISFET, the drain and gate electrode of the current input MISFET being connected to each other; a current input/output MISFET of the second conductivity type, a drain and gate electrode of the current input/output MISFET being connected to each other, the current input/output MISFET and the current input MISFET constituting a current mirror circuit; a first bias line for connecting the gate electrode of the current input MISFET and the gate electrode of the current input/output MISFET; a plurality of current supply sections including current source MISFETs, gate electrodes of the current source MISFETs being connected to the first bias line, the current source MISFETs, the current input MISFET and the current input/output MISFET constituting a current mirror circuit; a second current distribution MISFET of the first conductivity type, a drain of the second current distribution MISFET being connected to the drain of the current input/output MISFET; a current-voltage converter connected to at least the gate electrode and source of the second current distribution MISFET and provided in a region of the semiconductor chip which is distant from the second current distribution MISFET by 200 .mu.m or less; and a current input/output terminal which is connected to the current-voltage converter.

In a display device including the third current driver, for example, a current-voltage converter provided on a neighboring chip is connected in series to the current-voltage converter of the present invention so that substantially-equal electric currents flow through adjoining current input MISFETs.

The first display device of the present invention is a display device comprising a first semiconductor chip which includes a first current driver and a second semiconductor chip which include a second current driver and is provided adjacent to the first semiconductor chip, wherein: the first current driver includes a first current distribution MISFET of a first conductivity type, a source of the first current distribution MISFET being supplied with a supply voltage, a first current input MISFET of a second conductivity type, a drain of the first current input MISFET being connected to a drain of the first current distribution MISFET, the drain and a gate electrode of the first current input MISFET being connected to each other, a second current input MISFET of the second conductivity type, the second current input MISFET and the first current input MISFET constituting a current mirror circuit, a drain and a gate electrode of the second current input MISFET being connected to each other, a first bias line for connecting the gate electrode of the first current input MISFET and the gate electrode of the second current input MISFET, a plurality of first current supply sections each including a first current source MISFET, the first current source MISFET, the first current input MISFET and the second current input MISFET constituting a current mirror circuit, a gate electrode of the first current source MISFET being connected to the first bias line, a second current distribution MISFET of the first conductivity type, the second current distribution MISFET and the first current distribution MISFET constituting a current mirror circuit, a drain of the second current distribution MISFET being connected to the drain of the second current input MISFET, a third current distribution MISFET provided in a region which is distant from the second current distribution MISFET by 200 .mu.m or less, the third current distribution MISFET, the first current distribution MISFET and the second current distribution MISFET constituting a current mirror circuit, and a first current output terminal which is connected to a drain of the third current distribution MISFET; and the second current driver includes a first current input terminal which is connected to the first current output terminal, a third current input MISFET of the second conductivity type, a drain of the third current input MISFET being connected to the first current input terminal, and the drain and gate electrode of the third current input MISFET being connected to each other, a plurality of second current supply sections including second current source MISFETs, the second current source MISFETs and the third current input MISFET constituting a current mirror circuit, and a second bias line which is commonly connected to the gate electrode of the third current input MISFET and the gate electrodes of the second current source MISFETs.

With the above structure, an electric current is supplied from the third current distribution MISFET on the first semiconductor chip to the third current input MISFET at the next stage. Thus, a variation among the output currents in each chip is suppressed as compared with a conventional structure.

The second display device of the present invention is a display device comprising a first semiconductor chip which includes a first current driver and a second semiconductor chip which include a second current driver and is provided adjacent to the first semiconductor chip, wherein: the first current driver includes a first current distribution MISFET of a first conductivity type, a source of the first current distribution MISFET being supplied with a supply voltage, a first current input MISFET of a second conductivity type, a drain of the first current input MISFET being connected to a drain of the first current distribution MISFET, the drain and gate electrode of the first current input MISFET being connected to each other, a current input/output MISFET of the second conductivity type, a drain and gate electrode of the current input/output MISFET being connected to each other, the current input/output MISFET and the first current input MISFET constituting a current mirror circuit, a first bias line for connecting the gate electrode of the first current input MISFET and the gate electrode of the current input/output MISFET, a plurality of first current supply sections including current source MISFETs, gate electrodes of the current source MISFETs being connected to the first bias line, the current source MISFETs, the first current input MISFET and the current input/output MISFET constituting a current mirror circuit, a second current distribution MISFET of the first conductivity type, a drain of the second current distribution MISFET being connected to the drain of the current input/output MISFET, a first current-voltage converter connected to the gate electrode and source of the second current distribution MISFET and a reference power supply and provided in a region of the semiconductor chips which is distant from the second current distribution MISFET by 200 .mu.m or less, and a current input/output terminal which is connected to the first current-voltage converter, the second current driver includes a current input terminal which is connected to the current input/output terminal, a second current-voltage converter which is connected in series to the first current-voltage converter through the current input terminal, a third current distribution MISFET of the first conductivity type, a source and gate electrode of the third current distribution MISFET being connected to the second current-voltage converter, a second current input MISFET of the second conductivity type which is connected to the drain of the third current distribution MISFET, and a plurality of second current supply sections including second current source MISFETs, the second current source MISFETs and the second current input MISFET constituting a current mirror circuit.

With the above structure, substantially-equal electric currents flow through the first current-voltage converter and the second current-voltage converter. Thus, an error in the output current is suppressed at least in the vicinity of a connecting portion between adjoining semiconductor chips.

The third display device of the present invention is a display device comprising a first semiconductor chip which includes a first current driver and a second semiconductor chip which include a second current driver and is provided adjacent to the first semiconductor chip, wherein: the first current driver includes a first current distribution MISFET of a first conductivity type, a source of the first current distribution MISFET being supplied with a supply voltage, a first current input MISFET of a second conductivity type, a drain of the first current input MISFET being connected to a drain of the first current distribution MISFET, the drain and gate electrode of the first current input MISFET being connected to each other, a current input/output MISFET of the second conductivity type, a drain and gate electrode of the current input/output MISFET being connected to each other, the current input/output MISFET and the current input MISFET constituting a current mirror circuit, a first bias line for connecting the gate electrode of the first current input MISFET and the gate electrode of the current input/output MISFET, a plurality of first current supply sections including first current source MISFETs, gate electrodes of the first current source MISFETs being connected to the first bias line, the first current source MISFETs, the first current input MISFET and the current input/output MISFET constituting a current mirror circuit, a second current distribution MISFET of the first conductivity type, a drain of the second current distribution MISFET being connected to the drain of the current input/output MISFET, a first current-voltage converter connected to the gate electrode and source of the second current distribution MISFET and a reference power supply and provided in a region of the first semiconductor chip which is distant from the second current distribution MISFET by 200 .mu.m or less, a first current input terminal which is connected to the first current-voltage converter, a first load circuit provided in a region of the first semiconductor chip which is distant from the first current-voltage converter by 200 .mu.m or less, and a first current output terminal which is connected to the load circuit; and the second current driver includes a second current output terminal which is connected to the first current input terminal, a second load circuit which is connected in series to the first current-voltage converter through the first current input terminal, a second current input terminal which is connected to the first current output terminal, a second current-voltage converter which is connected in series to the first load circuit through the first current output terminal, a third current distribution MISFET of the first conductivity type, a source and gate electrode of the third current distribution MISFET being connected to the second current-voltage converter, a second current input MISFET of the second conductivity type which is connected to a drain of the third current distribution MISFET, and a plurality of second current supply sections including second current source MISFETs, the second current source MISFETs and the second current input MISFET constituting a current mirror circuit.

With the above structure, the values of the electric currents flowing through the first current-voltage converter and the second current-voltage converter are precisely adjusted to be equal. Thus, the output currents (electric currents for driving a panel) are uniform at least in the vicinity of a connecting portion of the semiconductor chips.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram schematically showing an organic EL display device including current drivers according to the present invention.

FIG. 2 is a circuit diagram showing semiconductor chips which include current drivers according to embodiment 1 of the present invention.

FIG. 3 is a circuit diagram showing semiconductor chips which include current drivers according to embodiment 2 of the present invention.

FIG. 4 is a circuit diagram showing semiconductor chips which include current drivers according to embodiment 3 of the present invention.

FIG. 5 is a circuit diagram showing semiconductor chips which include current drivers according to embodiment 4 of the present invention.

FIG. 6 is a circuit diagram showing semiconductor chips which include current drivers according to embodiment 5 of the present invention.

FIG. 7 is a circuit diagram showing semiconductor chips which include current drivers according to embodiment 6 of the present invention.

FIG. 8 is a circuit diagram showing a specific example of a first current-voltage converter in the semiconductor chip of embodiment 6 shown n FIG. 7.

FIG. 9 is a circuit diagram showing semiconductor chips which include current drivers according to embodiment 7 of the present invention.

FIG. 10 is a circuit diagram showing semiconductor chips which include current drivers according to embodiment 8 of the present invention.

FIG. 11 is a circuit diagram showing a specific example of a current-voltage converter and a load circuit in the current driver of embodiment 8 shown n FIG. 10.

FIG. 12 is a circuit diagram showing another specific example of a current-voltage converter and a load circuit in the current driver of embodiment 8 shown n FIG. 10.

FIG. 13 is a circuit diagram showing semiconductor chips which include current drivers according to embodiment 9 of the present invention.

FIG. 14 is a circuit diagram schematically showing a structure of a general organic EL display device.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 is a circuit diagram schematically showing an organic EL display device 210 including current drivers according to the present invention.

Referring to FIG. 1, the organic EL display device 210 includes a display panel, pixel circuits 216-1, 216-2, . . . and 216-m arranged in a matrix over the display panel, a first semiconductor chip 20, and a second semiconductor chip 22 provided adjacent to the first semiconductor chip 20. The first semiconductor chip 20 has a first current driver including first current supply sections 8-1, 8-2, . . . and 8-m (hereinafter, referred to as "first current supply section(s) 8" when generically mentioned) for respectively supplying driving currents through signal lines to the pixel circuits 216-1, 216-2, . . . and 216-m (hereinafter, referred to as "pixel circuit(s) 216" when generically mentioned). The second semiconductor chip 22 has a second current driver including a second current supply section 17 for supplying a driving current to the pixel circuit 216. In the example illustrated in FIG. 1, the first semiconductor chip 20 is a master chip for transmitting a reference current to the second semiconductor chip 22 which is a slave chip. In the display device of the present invention, the first semiconductor chip 20 and the second semiconductor chip 22 may have different circuit structures so long as an electric current transmitted from the first current driver on the first semiconductor chip 20 to the second current driver on the second semiconductor chip 22 is substantially equal to the reference current.

Each semiconductor chip, which includes a current driver of the present invention, has an elongated shape whose longitudinal length is equal to or longer than 10 mm and equal to or shorter than 20 mrn. The number of output terminals of each current driver, m, is 528, for example. Although only the first semiconductor chip 20 and the second semiconductor chip 22 are shown in FIG. 1, a large number of semiconductor chips which are supplied with an electric current substantially equal to the reference current flowing through the current drivers of the first semiconductor chip 20 and the second semiconductor chip 22 may further be provided in some cases.

Hereinafter, embodiments of the current driver of the present invention are described with reference to the drawings.

Embodiment 1

FIG. 2 is a circuit diagram showing semiconductor chips which include current drivers according to embodiment 1 of the present invention. The current drivers shown in FIG. 2 are used as source drivers of a current-driven display device, such as an organic EL display device, an LED display device, or the like, as are the current drivers of FIG. 14. In the example of FIG. 2, the first semiconductor chip 20 is a master chip, and the second semiconductor chip 22 provided adjacent to the first semiconductor chip 20 is a slave chip. These two chips are provided in the display device.

A first current driver is provided on the first semiconductor chip 20 of embodiment 1. The first current driver includes a plurality of first current supply sections 8, a reference current supply section for supplying the drive current (reference current) to the first current supply sections 8, a first bias circuit 5, a second bias circuit 10, a first current distribution MISFET 12, and a first current output terminal 9 connected to the first current distribution MISFET 12. The first current supply sections 8 include first current source MISFETs 200 of n-channel type. Gate electrodes of the first current source MISFETs 200 are commonly connected to a first bias line 205. The first bias circuit 5 transmits an electric current generated in the reference current supply section to the first current supply sections 8 at the side of the first current supply section 8-1. The second bias circuit 10 transmits the electric current generated in the reference current supply section to the first current supply sections 8 at the side of the first current supply section 8-m. The first current distribution MISFET 12 transmits the reference current to the second semiconductor chip 22.

The reference current supply section includes a first current source 4 and a first MISFET 1 of p-channel type. One end of the first current source 4 is grounded. The source and gate electrode of the first MISFET 1 are connected to the first current source 4. The drain of the first MISFET 1 is supplied with the supply voltage. In embodiment 1, the supply voltage is, for example, about 5 V.

The first bias circuit 5 includes a second current distribution MISFET 2 of p-channel type and a first current input MISFET 3 of n-channel type. The source of the second current distribution MISFET 2 is supplied with the supply voltage. The second current distribution MISFET 2 and the first MISFET 1 constitute a current mirror circuit. The drain and gate electrode of the first current input MISFET 3 are connected to each other. The drain of the first current input MISFET 3 is connected to the second current distribution MISFET 2. The gate electrode of the first current input MISFET 3 is connected to the first bias line 205. The source of the first current input MISFET 3 is grounded.

The second bias circuit 10 has the same structure as that of the first bias circuit 5. The second bias circuit 10 includes a third current distribution MISFET 6 of p-channel type and a second current input MISFET 7 of n-channel type. The third current distribution MISFET 6, the first MISFET 1 and the second current distribution MISFET 2 constitute a current mirror circuit. The drain and gate electrode of the second current input MISFET 7 are connected to each other. The drain of the second current input MISFET 7 is connected to the third current distribution MISFET 6. The gate electrode of the second current input MISFET 7 is connected to the first bias line 205. The sourc