Title: Current folding cell and circuit comprising at least one folding cell
Abstract: A current folding cell has current inputs and current outputs. Input currents are transferred from one current path to another and finally leading to the current outputs to establish a continuous folding characteristic. The signal current through one of the current paths often does not need to be substantially zero around the folding point in the folding characteristic. Comparator outputs in the cell provide digital outputs corresponding to the currents at the current inputs. An A/D converter can be constructed utilizing such current folding circuit cells in cascade and/or in parallel. The well-determined relationship between folder outputs can be used in a feedback loop to reduce or eliminate mismatch contributions. A mixer can be constructed using such current folding cells.
Patent Number: 6,972,706 Issued on 12/06/2005 to Snoeijs
| Inventors:
|
Snoeijs; Walter Jan Maria (Sous-Verzin, Cernex, FR)
|
| Appl. No.:
|
669590 |
| Filed:
|
September 23, 2003 |
| Current U.S. Class: |
341/158; 341/155 |
| Intern'l Class: |
H03M 001/34 |
| Field of Search: |
341/122,123,124,125,155-161,118,120,168,129
307/352,491,494,570,572,443
327/91-96,336,337
330/9
|
References Cited [Referenced By]
U.S. Patent Documents
| 3984832 | Oct., 1976 | Henry.
| |
| 4970703 | Nov., 1990 | Hariharan et al.
| |
| 5291074 | Mar., 1994 | Nayebi.
| |
| 5874912 | Feb., 1999 | Hasegawa.
| |
| 6535156 | Mar., 2003 | Wang et al.
| |
| 6806745 | Oct., 2004 | Fujimoto.
| |
| Foreign Patent Documents |
| 1 266 962 | Mar., 1972 | GB.
| |
Primary Examiner: Young; Brian
Attorney, Agent or Firm: Pearne & Gordon LLP
Parent Case Text
This application is a Continuation of PCT/EP20/03410 filed on Mar. 22, 2002,
claiming priority of European Application No. EP01107305.3 filed on Mar. 21, 2001
and U.S. Provisional Application No. 60/311,622 filed Aug. 10, 2001.
Claims
1. A current folding cell comprising a plurality of current inputs for receiving
at least two distinct input currents to be folded, further comprising:
at least one current output, and
a plurality of current paths between said current inputs and said at least one
current output, each path comprising at least one element,
wherein the current path taken by each input current depends on one or both of
the sign or the magnitude of said input current,
wherein for at least one input current, when it changes from a first current
path to a second current path, and therefore from at least one element to at least
one other element, these two or more elements continue to conduct a non-zero current
during the complete change of current path.
2. The current folding cell of claim 1, wherein for at least two input currents,
when they change from a first current path to a second current path, and therefore
from at least one element to at least one other element, these two or more elements
continue to conduct a non-zero current during the complete change of current path.
3. The current folding cell of claim 2, comprising two current inputs, two current
outputs and one current path between each current input and each current output,
wherein one current input receives an input current while the second current input
receives the same input current with the opposite sign.
4. The current folding cell of claim 3, wherein one current output delivers an
output current while the second current output delivers the same output current
with the opposite sign.
5. The current folding cell of claim 3, further comprising at least one current
summing circuit where more than one current arrives, the output of said current
summing circuit being connected to one of said current inputs.
6. The current folding cell of claim 3, further comprising first comparison means
yielding one digital output indicating the path taken by said current, said comparison
means comprising a multi-level comparator yielding a plurality of bits representative
of the sign and/or amplitude of at least one of said input currents.
7. The current folding cell of claim 2, wherein said element is a non-linear element.
8. The current folding cell of claim 7, wherein at least one of said non-linear
elements is constituted by a diode or by a diode-connected transistor.
9. The current folding cell of claim 7, wherein at least one of said non-linear
elements is constituted by a transistor.
10. The current folding cell of claim 2, further comprising comparison means
yielding at least one digital output representative of the sign and/or magnitude
of said input current or input currents.
11. The current folding cell of claim 1, comprising at least two current outputs.
12. The current folding cell claim 1, comprising a first current input and a
second current input, a first circuit providing two alternate current paths for
the first input current, a second circuit providing two alternate current paths
for the second input current, each of said current paths comprising at least one
of said elements, a first current summing circuit for adding the current from one
of the current paths of said first circuit with the current from one of the current
paths of said second circuit and for providing the result of the addition to said
first current output, and a second current summing circuit for adding the current
from the other current path of said first circuit with the current from the other
current path of said second circuit, the output of said second current summing
circuit being connected to said second current output and for providing the result
of the addition to said second current output.
13. The current folding cell of claim 12, wherein the input current in said first
circuit is equal in magnitude and opposite in sign to the input current in said
second circuit.
14. The current folding cell of claim 13, further comprising first comparison
means yielding one digital output indicating the path taken by said current in
said first circuit, and second comparison means yielding a second digital output
indicating the path taken by said current in said second circuit.
15. The current folding cell of claim 14, the output of one of said comparison
means being used for testing said current folding cell.
16. The current folding cell of claim 1, further comprising a biasing circuit
for biasing said elements in each path with a bias current sufficiently high compared
to the input currents to have two elements conduct when a small non-zero input
current is presented to said current input.
17. The current folding cell of claim 16, wherein different biases are applied
to said elements in two circuits in the cell.
18. The current folding cell of claim 1, further comprising at least one clipping
circuit for limiting the range of said at least one of input current, thus allowing
the folding cell to have a larger input current range than without clipping.
19. The current folding cell of claim 18, comprising a plurality of current outputs
and further comprising a means to add the output currents of the current folding
cell to the output currents of the clipping circuit in such a way that the sign
and/or magnitude of the input currents determines to which output terminal each
of the input currents are transferred.
20. The current folding cell of claim 1, wherein at least one of said outputs
is used in a feedback loop to control at least one of said inputs in order to obtain
negative dynamic resistance in some part of the range of input currents.
21. A circuit comprising at least one folding cell of one of the 20.
22. A circuit comprising a plurality of current folding cells connected in cascade, wherein
at least two of said cascade connected current folding cells each comprise a
plurality of current inputs for receiving at least two distinct input currents
to be folded: at least one current output, a plurality of current paths between
said current inputs and said at least one current output, each path comprising
at least one element, and wherein
the current path taken by each input current depends on one or both of the sign
or the magnitude of said input current, and further wherein
for at least one input current, when it changes from a first current path to
a second current path, and therefore from at least one element to at least one
other element, these two or more elements continue to conduct a non-zero current
during the complete change of current path.
23. The circuit of claim 22, wherein the bias current applied to the most significant
cells in the cascade is such that the DC-current in the elements in each path is
higher than what would be needed to reach the precision of current detection of
the least significant stage or stages.
24. The circuit of claim 23, wherein said circuit comprises a plurality of current
folding cells operating in parallel on signals of same significance.
25. The circuit of claim 22, wherein said circuit comprises a plurality of cascades
of current folding cells operating in parallel on signals of same significance.
26. The circuit of claim 25, further comprising mismatch compensating means for
reducing the undesired mismatch between folding cells in different cascades or
between the input signals of said cascades.
27. The circuit of claim 26, wherein said mismatch compensating means comprise
means for comparing the output currents of each of said cascades and feed-back
means for adjusting the mismatch in said cascades depending on the result of the comparison.
28. The circuit of claim 27, wherein said mismatch compensating means comprise
a load after a stage in said cascade, said comparison means comparing the voltage
loss over said load with a reference, the current after said load being fed back
in order to adjust said mismatch.
29. The circuit of claim 22, further comprising at least one re-injection circuit
for reducing the influence of a parasitic capacitance linked to a node by re-injecting
in a node a current equal to the capacitive current, but with an opposite sign.
30. The circuit of claim 29, wherein said re-injection circuit re-injects said
current into a different node along the current path.
31. The circuit of claim 22, being an analog-to-digital converter.
32. The circuit of claim 31, comprising a plurality of cascades of current folding
cells, wherein at least one bit of the digital output of the converter is derived
from a plurality of outputs provided by folding cells of the same order or significance
in different cascades.
33. The circuit of claim 32, wherein a different offset current is added to the
input currents of the different cascades, and wherein the least significant bit(s)
is/are determined by establishing the cascade of which the output currents of the
last stage were nearest to the zero crossing.
34. The circuit of claim 32, wherein said outputs are current outputs, and wherein
output currents provided by folding cells of the same order in different cascades
are summed, the result of said sum being used for determining said one bit.
35. The circuit of claim 32, wherein a majority voting scheme is used for deriving
said one bit from a plurality of output currents provided by folding cells of the
same order in different cascades.
36. The circuit of claim 32, wherein said one bit is derived from a plurality
of output currents provided by one or several selected folding cells of the same
order in different cascades, wherein only the folding cells corresponding to the
cascade or cascades of which the current outputs are nearer to the zero crossing
are selected.
37. The circuit of claim 22, further comprising a track and hold circuit or sample
and hold circuit between at least some stages in the cascade of folding cells to
construct a pipelined analog-to-digital converter.
38. The circuit of claim 22, further comprising means for measuring the output
current of the last folding cell in said folding cell.
39. The circuit of claim 22, being a mixer for mixing several currents, said
mixer comprising a at least one current summing circuit where more than one current
arrives, the output of said current summing circuit being connected to one of said
current inputs.
40. The circuit of claim 22, being a multilevel memory in which an output current
of at least one of said folding cell is used in a feedback loop which controls
one or more input of the circuit.
41. The circuit of claim 22, being an array of cells in which said current folding
cell are used for providing multi-level detection of the currents in the cells.
42. The circuit of claim 22, being a self-latching analog-to-digital converter
in which the current of at least one of said folding cell is used in a feedback
loop which controls one or more input of the circuit.
43. The circuit of claim 22, being an oscillator using the change in slopes of
the output currents as a function of the input currents, provided by the folding cell.
44. The circuit of claim 22, being used to implement a frequency multiplier.
45. The circuit of claim 22, being used to provide switching means.
46. The circuit of claim 22, further comprising:
level detection means for detecting the level of each of said output,
verification means for verifying the relationship between said levels, and
feed-back means for correcting this relationship by acting on one or both of
said circuit or the input signal of said circuit.
47. The circuit of claim 46, wherein said outputs are current outputs.
48. The circuit of claim 47, wherein said level detection means comprise:
a load after said output, and
comparing means for comparing the voltage loss over said load to a reference.
49. The circuit of claim 48, wherein said level detection means comprise a load
after said output, wherein said verification and feed-back means make use of the
current after said load which is fed back into said circuit in order to adjust
said relationship.
50. The circuit of claim 22, further comprising at least one current sample-and-hold
or track-and-hold circuit.
51. The circuit of claim 50, wherein an input current of said current sample-and-hold
or track-and-hold circuit is injected into a terminal of a component or circuit
to convert the input current to a voltage so that this voltage can be stored on
a storage capacitor, and where the input current is transferred to another terminal
of this component or circuit from where it is provided to one folding cell.
52. The circuit of claim 22, wherein for at least two input currents of one of
said current folding cell, when they change from a first current path to a second
current path, and therefore from at least one element to at least one other element,
these two or more elements continue to conduct a non-zero current during the complete
change of current path.
53. The circuit of claim 22, wherein at least one current folding cell comprises
at least two current outputs.
54. The circuit of claim 22, wherein at least one current folding cell comprises:
two current inputs,
two current outputs, and
one current path between each current input and each current output, wherein
one current input receives an input current while the second current input receives
the same input current with the opposite sign.
55. The circuit of claim 54, further comprising at least one amplification stage
between two cascaded folding cells.
56. The circuit of claim 54, wherein said amplification stage includes a current
mirror to amplify the current flowing from one stage to the next one.
57. The circuit of claim 54, wherein one current output delivers an output current
while the second current output delivers the same output current with the opposite sign.
58. The circuit of claim 57, wherein at least one of said outputs of at least
one folding cell in the cascade is used in a feedback loop to control at least
one of said inputs of at least one folding cell the cascade.
59. A current sample-and-hold or track-and-hold circuit, wherein an input current
is injected into a terminal of a transistor to convert the input current to a voltage
so that this voltage can be stored on a storage capacitor, and where the input
current is transferred to another terminal of the transistor from where it is made
available for further use.
60. The current sample-and-hold or track-and-hold circuit of claim 59, said output
being cascade-connected to the input of another current sample-and-hold or track-and-hold circuit.
61. The current sample-and-hold or track-and-hold circuit of claim 60, the storage
nodes of said current sample-and-hold or track-and-hold circuits being mutually
capacitively coupled.
62. The current sample-and-hold or track-and-hold circuit of claim 59, wherein
an isolation of the storage capacitor during hold mode is provided by means of
a circuit acting solely on the source or emitter of one or more transistors.
63. A current sample-and-hold or track-and-hold circuit, wherein an input current
is injected into a terminal of a transconductor to convert the input current to
a voltage so that this voltage can be stored on a storage capacitor, and where
the input current is transferred to another terminal of the transconductor from
where it is made available for further use.
Description
FIELD OF THE INVENTION
The invention relates to current folding circuit cells. It also relates to an
analog-to-digital conversion circuit (A/D conversion circuit) and mixers employing
such folding circuit cells. It also relates to signal processors incorporating
such A/D conversion circuits, mixers or folding cells.
DESCRIPTION OF THE PRIOR ART
Folding circuit cells have been extensively used to reduce the number of
components and hence the cost and power consumption in analog-to-digital converters.
As an example, FIG. 1 shows a schematic diagram of a conventional serial type analog-to-digital
converter comprising folding circuits F0 . . . F4 in cascade. Each
folding circuit produces a V-shaped output signal, which is presented to the input
of the next folding circuit. FIG. 2
a to 2
e show the outputs
of the folding circuits as a function of the input signal. FIG. 2
a shows
the output of F0, FIG. 2
b the output of F1, etc . . . . Each
folding block F0 . . . F4 also contains a comparator which provides
a digital output D0 . . . D4 (D0 corresponds to F0,
D1 to F1, etc . . . ) indicating the sign of the signal at the input
of the folding block. Such a converter needs one folding circuit cell per bit,
and therefore only needs a small number of components.
To produce such a continuous V-shaped signal exhibiting two opposite slopes from
a single signal, a sign reversal operation for part of the input range or a difference
producing circuit is required. Continuous means in this context that the folded
current signal does not exhibit abrupt steps, it only changes slope abruptly.
U.S. Pat. No. 4,599,602 describes such a conventional serial type A/D converter
using folding circuit cells in cascade, where each cell converts a differential
potential input into a current difference using a differential amplifier. A comparator
included in the cell switches over the current paths for the differential current
to implement the sign reversal and to obtain a folding characteristic. The current
difference is further converted into a differential voltage, which serves as output
of the folding circuit cell and is applied to the next cell in the cascade.
Continuous folded output currents exhibiting changing slopes as a function
of the input currents can be obtained without sign reversal operations or conversions
to voltage and back in the folding cell if more than one time-varying current is
applied to the current folding cell. An example of applying input currents to more
than one current input to obtain two different slopes is described in GB1266962.
One current input receives the input current while the second one receives the
input current with the opposite sign. The signals are fully rectified and then
transferred to the next stage. The disadvantage of such full rectifier circuit
is that when current paths for the signal currents are switched from one current
path to another, the current in both paths is zero. This requires operating the
non-linear elements at effectively zero current around the switching point. This
yields a large input impedance around the switching points requiring large voltage
swings around the zero transition. Any capacitance associated with the input nodes
has to be charged and discharged by the input current over this large voltage range
rendering this circuit slow.
A current folding cell addressing this problem in part is described in U.S. Pat.
No. 4,179,687. The circuit provides two current paths, only one of which is conducting
significant current at a given time. The current in one of the two paths is fed
to a current sink. The current in the other path is used for further comparisons.
A cascade of N such cells leads to a folded signal with N+1 line segments.
Another way to obtain a continuous V-shaped signal is the use of switches.
In one case (FIG. 5 of U.S. Pat. No. 4,179,687) reference currents are switched
in or out the current path of an input current. In another case (FIG. 6 of U.S.
Pat. No. 4,179,687) switches are used to open or close current paths to recover
the correct residue current for subsequent comparisons.
Also in other cases switches have been used to switch from one current path
to another. These switches are controlled by some controlling input, i.e. the differential
voltage on the gates of a differential transistor pair. These switches often are
the cause of large switching transients in the signal current, or they require
complicated circuitry to minimize this effect. In addition, when a current path
is changed by means of switches, the switches are driven from on to fully of or
vice versa. Therefore a large voltage swing is often required to control the switches.
If this large swing is to be applied at high frequency, a power penalty is incurred.
In addition, in several embodiments in U.S. Pat. No. 4,179,687 use is made of
current dividers which are subject to mismatch.
Another current folding cell is described in U.S. Pat. No. 4,325,054. It
provides two alternate paths for the input current. The value of the input current
determines along which of the two current paths the input current will flow. The
currents flowing through these two alternate paths are fed to a difference producing
circuit, which in the embodiment described is implemented using a current-to-voltage
conversion for the current in each of the two current paths, and a difference producing
circuit using the two voltages generated in these current to voltage converters
as input.
An alternate implementation for the difference producing circuit is based on
taking
the difference of the two currents directly, which requires a sign reversal of
one of the two currents. Such a sign inversion can be implemented using a current
mirror or a circuit using an operational amplifier. An example of this is described
in U.S. Pat. No. 4,574,270. Without a sign reversal the folding circuit of U.S.
Pat. No. 4,325,054 still works, but N-1 folding cells are needed to obtain a folding
characteristic with N segments, which yields a slow signal and a costly solution
in terms of area and power for large values of N.
Voltage-to-current conversion circuits, current-to-voltage conversion
circuits, current mirrors, and circuits implementing a current sign reversal are
sensitive to device parameters and device parameter mismatch. Device parameter
mismatch can be improved by increasing device size but this leads to higher cost
and larger capacitive load. If this larger capacitive load is seen by the varying
signal a slower circuit is obtained.
Folding circuit cells which include voltage-to-current or current-to-voltage
conversion circuits acting on the time-varying signal, or which include current
mirrors or current sign reversal circuits in the path of the time-varying signal,
therefore limit the speed and/or the accuracy of the serial analog-to-digital converter
in which they are used.
In the prior art, all folding circuits with current inputs and current outputs
which can be cascaded without any intermediate circuitry to produce a continuous
folded signal at the output with 2N segments where N is the number of stages satisfy
at least one of the following conditions:
- The folding cell contains a current sign reversal operation on the time-varying
signal (like a current mirror for instance);
- The folding cell contains a current difference operation which requires
a current sign reversal operation on the time-varying signal;
- The folding cell requires a current-to-voltage conversion operation
on the time-varying signal and later on a voltage-to-current conversion;
- The folding cell requires comparatively large voltage transitions around
at least some of the switching points, because the currents through some of the
various current paths provided for each input signal are substantially zero when
current paths are switched from one to another for that input signal.
It is an aim of the invention to provide a folding circuit which can be cascaded
to construct an analog-to-digital converter without the need for a sign reversal,
or voltage-to-current or current-to-voltage conversion, and which provides the
possibility of obtaining a folding characteristic with 2 to the power N segments
with only N folding circuit cells.
Advantageously, as will be seen, the folding cell of the invention
does not require that currents through the various current paths provided for the
different input signals are substantially zero when current paths are switched
from one to another. As the currents are transferred from one current path to another
without requiring substantially zero current in at least one of the current paths
near the switching point, a higher speed can be reached.
Advantageously, as will be seen, the folding cell of the invention
requires only a small number of components even for a large number of segments
in the folding characteristic, thus presenting a low cost and low power solution.
Advantageously, the folding cell of the invention should have a limited
sensitivity to mismatch of the components in the path of the time-varying signal,
so that those components can be made small, thus yielding lower parasitic capacitances
and higher speed.
Advantageously, as will be seen, the limited number of components
in the folding cell allows to actively compensate some fraction of the parasitic
capacitances, the small number of components allowing this without a large power penalty.
Due to its economic importance significant effort has been invested in decreasing
the density of memory. One approach has been the use of multi-level memory cells.
The use of such cells requires a multilevel readout. Traditionally power and spatial
constraints of the cell readout (multilevel sense amplifier) have limited the number
of levels per cell to only a small number.
It is another aim of the invention to propose a new current folding cell and a
new analog-to-digital converter which provide a way to detect a large number of
levels and this with a low power consumption. In addition, the folding cells allow
to construct multi-level memory cells.
Several techniques have been proposed to reduce or eliminate cell mismatch
in analog-to-digital conversion to improve the linearity of the conversion. One
example is the use of chopper amplifiers and filtering in the digital domain. Such
a technique usually introduces considerable additional power and circuit complexity.
U.S. Pat. No. 5,835,048 and U.S. Pat. No. 6,014,098 describe a way to reduce
cell mismatch in a plurality of cells containing a differential amplifier having
first and second branches. The technique uses averaging impedances, preferably
resistors, connected between the output terminals in the first branches of the
differential amplifier, and the output terminals in the second branches of the
differential amplifier, in successive pairs of cells. The impedances have relatively
low values, particularly compared to the impedances of current sources connected
to the branch output terminals.
It is another aim of the invention to propose a new circuit for reducing cell
mismatch which provides for significant improvement compared to the prior art in
terms of linearity improvement of the converter. As will be explained, those improvements
are due to the fact that there exists a well defined relationship between the output
currents of a folder constructed from a cascade of current folding cells according
to the invention. Instead of only reducing the influence of offsets due to averaging,
the circuit of the invention provides the possibility of fully eliminating some
offset contributions, and this with only a small number of components. Since the
circuit of the invention allows to fully eliminate offset contributions from some
components, these components can be designed with smaller dimensions. This results
in a smaller circuit and hence a reduced cost, and also yields a speed advantage
as the parasitic capacitances associated with these components is reduced.
Testing of analog-to-digital converters is often time consuming and often
requires special equipment, both of which cause the testing to be important in
the overall cost of such converters. As will be explained, the folding cells of
the invention can provide two digital outputs per cell or 2N digital signals for
an N bit converter. This redundancy can be used advantageously to simplify the
testing and significantly reduce the testing cost for a converter based on these
folding cells.
Mixers are often used in systems for telecommunication and networks to superimpose
and extract a signal from the carrier. Very often an analog-to-digital converter
is required after the mixer. It is another aim of the invention to propose an improved
mixer, based on the inventive folding cell, in which no signal conversion (e.g.
current-to-voltage) is required eliminating conversion errors, and where several
biases could be shared yielding a smaller circuit area, lower power, and hence
a reduced circuit cost.
Several current comparators have been proposed in the past. All are subject
to a trade-off between speed, maximum current range, and minimum current resolution.
The minimum current resolution requires a certain minimum signal, for instance
a voltage, to be generated in order for it to be detected. This signal can be reduced
on the condition that larger devices are used to decrease the influence of random
device fluctuations (mismatch). Larger parasitics are associated with larger devices,
yielding slower circuits for the same minimum current resolution. The maximum current
range is determined by the maximum current which can be absorbed by the current comparator.
It is another aim of the invention to provide a circuit which allows to decouple
the maximum current range from the minimum current resolution allowing smaller
devices for the current comparison and hence a faster circuit.
Prior art current sample-and-hold or track-and-hold circuits are traditionally
classified into first generation (FIG. 2
x) and second generation circuits
(FIG. 2
y). In the first generation circuits (FIG. 2
x) the input current
Iin is transformed into a voltage by means of a first transistor T1. This
voltage is sampled on a storage capacitor CA by means of the switch SWX. Neglecting
circuit non-idealities, opening the switch SWX will cause the voltage on the capacitor
to remain at its value at the moment the switch was opened. A second transistor
T2 receives the voltage on the capacitor CA and transforms it back to current.
The biasing for the circuit is provided through the current sources IT1
and IT2. The disadvantage of this class of circuits is that mismatch between
the two transistors will introduce an error causing the output current to be not
exactly equal to the input current.
In circuits of the second generation (FIG. 2
y) the same transistor T3
is used for both the current to voltage conversion and the subsequent conversion
back into current. In the figure the bias is provided through the current source
IT3, and the switches SX1 . . . SX3 allow to couple the storage
capacitor CB to the input during track mode and to isolate the gate of T1
linked to the storage capacitor during the hold mode. The use of only one transistor
avoids an error between input and output current due to mismatch but no output
current is available when the input current is being sampled or tracked. This is
a disadvantage as not the full clock period can be used to treat input and output
current. The clock period has to be divided into a part allocated to sample or
track the input current and another non-overlapping part during which the current
output is provided. If a meaningful output current has to be provided for the full
clock period, at least two transistors need to be used in parallel, where they
alternate as sampling and output transistor. So, when one transistor is sampling
or tracking the input, the other one is providing the output current.
It is therefore another aim of the invention to provide a current sample-and-hold
or current track-and-hold circuit which is not subject to errors introduced between
input and output current due to mismatch, and which allows to sample or track the
input current and provide an output current simultaneously during the full clock
cycle. This sample and hold circuit principle should also allow to present well-matched
input currents to several folding circuits in parallel.
Charge injection in the switches of a sample-and-hold or track-and-hold circuit
has always been an issue. In some cases injected charge has been balanced using
dummy switches driven with control signals of the opposite sign. In other cases
the switches were placed inside a feedback loop to obtain an injected charge less
dependent on the input signal.
Therefore a further object of the invention is a way to implement a switch
which inherently minimizes the amount of injected charge.
Folding circuit cells which include voltage-to-current or current-to-voltage
conversion circuits acting on the time-varying signal, or which include current
mirrors or current sign reversal circuits in the path of the time-varying signal,
limit the speed and/or the accuracy of the circuit in which they are used.
Because the currents through some of the various current paths provided for
the different input signals are substantially zero when current paths are switched
from one to another, folding cells which require comparatively large voltage transitions
around at least some of the switching points are limited in speed.
Continuous folded output currents exhibiting at least two different slopes
different from zero as a function of the input currents can be obtained without
sign reversal or scaling operations in the folding cell if more than one time-varying
current is applied to the current folding cell. Continuous means in this context
that the folded current signal does not exhibit abrupt steps, it only changes slope
abruptly. Abrupt steps can be created by switches, but such switches can introduce
significant switching noise in a circuit and can cause significant speed limitations.
SUMMARY OF THE INVENTION
According to the invention, those problems are solved among other by a
current folding circuit cell where:
- currents at a plurality of current inputs are transferred to current
outputs via different current paths,
- the magnitude or sign of the current signals only determines which current
path is taken by each current,
- signal currents change from one current path to another without requiring
substantially zero current in at least one of the current paths,
- at least two input currents differ from each other and are time-varying,
In a preffered embodiment, this cell comprises:
- at least two current input terminals;
- a current summing circuit at every current input terminal where more
than one input current arrives yielding a single input current at every current
input terminal,
- a circuit providing at least two alternate current paths for the input
current associated with at least one of the input terminals, where the sign or
magnitude of the input currents associated with these one or more input terminals
determines the current path taken to conduct each of the input currents;
- a current summing circuit at every current output where more than one
current arrives yielding a single output current at every current output;
The current summing circuit can be made by using wires to connect together the
output terminals providing these currents and further providing a wire to the input
terminal for the current sum. In an embodiment, currents are added using a way
to avoid a large capacitive load at the input of the folding cell. For instance,
some currents can be added on one node, different from the node sensitive to the
parasitics, and the result can be transferred to the sensitive node using a cascode
transistor which does not represent a large capacitive load on this sensitive node.
In a preferred embodiment, the folding cell comprises:
- two current input terminals and two current output terminals;
- a current summing circuit at every current input terminal where more
than one input current arrives yielding a single input current at every current
input terminal, a first input current for the first current input terminal and
a second input current for the second current input terminal, both input currents
being time-varying and proportional to a signal to be folded;
- a circuit providing two alternate current paths for the first input
current, the sign of which determines the current path taken to conduct this first
input current, and further providing two alternate current paths for the second
input current, the sign of which determines the current path taken to conduct this
second input current;
- a current summing circuit to add the current from one of the current
paths associated with the first current input to one of the current paths associated
with the second current input, and including a means to provide the result of the
addition to the first current output of the folding circuit cell;
- a current sunning circuit to add the current from one of the current
paths associated with the second current input to one of the current paths associated
with the second current input, and including a means to provide the result of the
addition to the second current output of the folding circuit cell;
In an embodiment, the first current input terminal a first input current is added
to a first reference current provided by a first reference source, and at the second
input a second input current is added to a second reference current provided by
a second reference source. The reference currents can be generated as a sum of
several reference currents.
In an embodiment, the folding cell includes at least one comparison means yielding
a digital output. This digital output can for instance represent the sign of a
current in the folding cell or whether a current in the folding cell is above or
below a certain threshold, or whether one current is smaller or larger than another
one in the current folding cell.
In an embodiment, for such folding cells with two current input terminals, the
input current at the first input terminal can be made equal in magnitude and opposite
in sign to the input current at the second input terminal. This provides an easy
way to cascade these current folding circuit cells without any intermediate circuit
to construct an analog-to-digital converter to produce a folded signal at the output
with 2 to the power N segments where N is the number of stages in the cascade.
Using this approach, if comparison means are included in the folding cells, a digital
code with Gray-code properties is obtained with only one folding cell per bit in
the cascade. The need for only one cell per bit yields a very small number of components
resulting in a low power and low cost solution.
In an embodiment, these current folding circuit cells are used in an analog-to-digital
converter. Preferably, these current folding circuit cells can be cascaded, wherein
the output terminals of a preceding stage cell are connected to the inputs of a
succeeding stage cell. Furthermore, the outputs of these folding cells can be combined
by for instance adding them, before inputting them to a succeeding stage cell.
This can be advantageous for instance to increase the operating speed of the analog-to-digital
converter or to increase the size of the input signal of the succeeding cell.
In an embodiment, gain stages are inserted in-between consecutive stages of folding
cells. This will provide an increase in conversion speed for the following stages
for the same number of stages.
In an embodiment, these folding cells are used in combination with interpolating
means, for instance in analog to digital converters to obtain a larger number of
bits with the same number of folding cells.
In an embodiment, an analog-to-digital converter is constructed from a plurality
of cascades of such current folding cells, where the inputs of the first cells
of the different cascades have some relation with respect to one another. This
relation can comprise a constant offset between the inputs of the different cascades,
or an offset which is well defined between the zero transitions, but which varies
with the input signals.
Due to the well-defined relationship between the output signals of these folders,
they can be combined or mutually compared to provide signals which can be fed back
to the circuitry providing the current inputs to these folders. Such feedback loops
can be used to reduce or eliminate mismatch between components, to reduce or eliminate
common mode components in input signals and/or to obtain negative dynamic resistance
in some part of the range of input currents. This principle could be used also
for voltage folding cells and for cascades of current or voltage folding cells,
where one output or one intermediary output could be fed back to one input or to
one intermediary input.
A sample-and-hold or track-and-hold circuit can be placed in front of such folding
cells or cascade of folding cells, or in-between consecutive stages of folding
cells to improve the conversion rate of the circuit.
Testing integrated circuits often forms an important factor in the overall
cost of these circuits. The folding cell can be provided with one comparison means
per current input terminal. In case there is a relationship between the currents
at the different current input terminals, some degree of redundancy is created
which can be beneficially used for testing. For example, the digital outputs of
the comparison means in the folding cell can be mutually compared to detect anomalies
in the operation of the current folding circuit cell.
Traditionally power and spatial constraints of the cell readout (multilevel
sense amplifier) have limited the number of levels per cell in a memory to only
a small number. The new current folding cell proposed here and the new analog-to-digital
converter that can be constructed with it can provide a readout for a relatively
large number of levels in a small circuit area, and this with a low power consumption.
This makes this new cell and this new converter ideally suited for the readout
of memories containing multilevel cells. The folding cells introduced here can
also be used to construct multilevel memory cells themselves. The principle can
also be used to construct a self-latching analog-to-digital converter.
The current folding cell introduced here can also be used in a mixer. By superimposing
a time varying (like a square wave) signal onto the input signal and providing
the result as an input to the current folding cell, a mixing function can be realized.
This new mixer operates in current mode. Therefore the new current folding cells
proposed here allow to implement a mixer-converter combination where no signal
conversion (e.g. current-to-voltage) is required eliminating conversion errors,
and where several biases could be shared yielding a smaller circuit area, lower
power, and hence a reduced circuit cost.
In an embodiment, the capacitive loading at a node of a circuit which transfers
the current or part thereof from one or more current inputs to one or more current
outputs is minimized by means of a shield driven by a circuit following the ac
component of this one node. Doing so can yield an increase in circuit speed.
In an embodiment, the capacitive loading at a node of a circuit which transfers
the current or part thereof from one or more current inputs to one or more current
outputs is compensated for by re-injecting a fraction or the totality of the capacitive
current, or an approximation thereof, with the opposite sign into said node or
another node of same current path. Doing so can yield an increase in circuit speed.
All current comparators are subject to a trade-off between speed, maximum current
range, and minimum current resolution. It is another aspect of the invention that
the maximum current range can be decoupled from the minimum current resolution;
this provides a speed advantage as well. This decoupling can be achieved by first
clipping the input current to limit its maximum range by means of a coarse comparison,
and presenting the resulting signal of reduced range to a current comparator for
fine comparison. The clipping should be carried out such that not only the signal
of reduced range is made available by the clipping circuit, but also the remainder,
i.e. the signal of a range too large to be accepted by the fine comparator. This
signal of too large a range can then be added to the output current of the comparator
carrying out the fine comparison. This way the same output current can be obtained
as would be provided by a current comparator circuit with the same minimum current
resolution but a larger input current range. The clipping and addition of the currents
can be carried out without a current to voltage conversion and subsequent voltage
to current conversion, and is therefore not subject to errors introduced by mismatch.
If clipping and fine comparison are carried out as described above, the components
in the fine comparator can be kept small with lower parasitics resulting in a faster
circuit compared to a comparator with the same minimum current resolution and a
larger input current range. The same principle can be used to construct folding
cells with a larger input current range.
Prior art current sample-and-hold circuits or current track-and-hold circuits
are constructed by injecting the current to be sampled or tracked into a component,
for instance a transistor, which converts the current to a voltage which can be
stored on a capacitor, and which transfers this current to a fixed potential, for
instance ground, where it is lost for further use.
Therefore, an other aim of the invention is to provide a current sample-and-hold
or track-and-hold circuit which can be constructed by injecting the current to
be sampled or tracked into a component or circuit, for instance a transistor, which
carries out the current to voltage conversion for storage but which transfers this
input current to a terminal from which it can be recuperated for further use. This
terminal can then serve to provide the output current of the sample-and-hold or
track-and-hold circuit. Neglecting the transients required to charge or discharge
the storage and parasitic capacitances, this output current is equal to the input
current during the sample or track mode. During hold mode, this output current
is equal to the value of the input current at the start of the hold mode. This
provides the significant advantage that no errors are introduced due to mismatch,
while a meaningful output current remains available during the sampling or tracking
phase. Therefore both input and output current can be treated simultaneously over
the full clock period, thus allowing more time and hence lower power for the same
function, or a faster circuit for the same power. In addition, in case meaningful
output currents are not required during the sampling or tracking phase of the clock
cycle, the presence of an output terminal which reproduces the input current without
being sensitive to mismatch and which is separate from the input terminal of the
sample-and-hold or track-and-hold circuit allows to have more than one current
output (i.e. two outputs) insensitive to mismatch for one current input, and also
allows to cascade several current sample-and-hold and/or track-and-hold circuits
during the sampling or tracking phase.
Parasitic charge injection by the switches in sample-and-hold and/or track-and-hold
circuits is often an important source of performance degradation for these circuits,
and significant effort has been made in the past to minimize this. Here we introduce
a new switch which in one embodiment can be implemented by the current folding
cells introduced in this invention and which minizes the charge injection.
In a preferred embodiment, the new current folding cell and the new analog-to-digital
converter are used as level-detecting devices in large arrays of cells. They can
provide multi-level detection at low power in a small area, and can act directly
on a current signal. Current readout is ideally suited for large arrays of cells
in general since the long readout busses which represent a large capacitive load
do not need to be subject to a large voltage swing. This usually results in a speed
and/or a power advantage. Examples of such large arrays of cells are imaging detectors
like CMOS imagers, and semiconductor memories which can contain multilevel memory cells.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention and its additional features, which may optionally be used to implement
the invention to best advantage, will be apparent from and elucidated with reference
to the embodiments described hereafter with reference to the accompanying drawings, wherein:
FIG. 1 shows, in block diagram form, how a prior art serial analog-to-digital
converter is constructed from a cascade of folding circuit cells. In the figure
the cascade comprises 5 folding circuit cells F0 . . . F4;
FIG. 2
a to 2
e refer to FIG. 1 and show the signal shape
of the output of folding circuit cell F0 to F4, respectively, as
a function of the input signal of the prior art converter shown in FIG. 1;
FIG. 2
x shows a prior-art first generation current sample-and-hold or
track-and-hold circuit; one transistor T1 is used to sample or track the
input signal, and to convert it to a voltage which can be stored on a capacitor
CA, the other transistor T2 provides the current output;
FIG. 2
y shows a prior-art second generation current sample-and-hold or
track-and-hold circuit; here the same transistor T3 is used to receive the
input signal and to provide the output signal, but both actions cannot be performed
simultaneously in time;
FIG. 3 shows an embodiment C1 of one half of the current folding cell
and a possible schematic B1 to bias the circuit C1;
FIG. 4 shows an embodiment C2 of one half of a current folding cell including
a comparison means to determine the sign of the sum of the currents at the input,
and a possible schematic B1 to bias the circuit C2;
FIG. 5 shows a block diagram representation of the circuit C2 of FIG. 4;
FIGS. 6
a and 6
b show the output currents I
outu
and I
outd of the circuit C1 of FIG. 3, and of the circuit C2
of FIG. 4 as a function of the input current. The sign of the current is positive
if it flows in the direction of the arrow;
FIG. 7 shows an implementation example of the novel folding circuit cell comprising
two circuits C2 from FIG. 5;
FIG. 8 shows an implementation example of the novel folding circuit cell comprising
two circuits C2 from FIG. 4, where at each current input a signal current
and a reference current are summed;
FIG. 9 shows the circuit of FIG. 8 in more detail;
FIG. 10 shows a block diagram view of the novel folding circuit cell of FIG. 8;
FIG. 11 shows, for the folding circuit cell of FIG. 8, the sum of the current
outputs I
outu1 and I
outu2 as a function of
the input current I1 in the folding circuit cell, and this for the case
where I1 is equal to I2, but opposite in sign. The resulting current
is the current output I
out2 of the folding circuit cell;
FIG. 12 shows, for the folding circuit cell of FIG. 8, the sum of the current
outputs I
outd1 and I
outd2 as a function of
the input current I1 in the folding circuit cell, and this for the case
where I1 is equal to I2, but opposite in sign. The resulting current
is the current output I
out1 of the folding circuit cell;
FIG. 13 shows, in block diagram form, how a novel serial analog-to-digital converter
is constructed from a cascade of novel current folding circuit cells. In the figure,
the cascade comprises n cells;
FIG. 14 shows the current I1 of the second folding circuit cell in the
cascade of FIG. 12 as a function of the input current I1 in the first cell,
for the case where I1 in the first cell is equal to I2 in the first
cell, but opposite in sign;
FIG. 15 shows the current I2 of the second folding circuit cell in the
cascade of FIG. 12 as a function of the input current I1 in the first cell,
for the case where I1 in the first cell is equal to I2 in the first
cell, but opposite in sign;
FIG. 16 shows the current I1 of the third folding circuit cell in the
cascade of FIG. 12 as a function of the input current I1 in the first cell,
for the case where I1 is equal to I2, but opposite in sign for the
first two cells;
FIG. 17 shows the current I2 of the third folding circuit cell in the
cascade of FIG. 12 as a function of the input current I1 in the first cell,
for the case where I1 is equal to I2, but opposite in sign for the
first two cells;
FIG. 18 shows in more detail how a cascade of current folding cells FO1
. . . FO4 of FIG. 8 can be constructed for use in an analog-to-digital converter;
FIG. 19 shows the core of another embodiment of the current folding cell;
FIG. 20 shows the core of another embodiment of the current folding cell;
FIG. 21 shows the core of another embodiment of the current folding cell;
FIG. 22 shows the core of another embodiment of the current folding cell;
FIG. 23 shows a possible way of how the proper bias can be provided for the
core of the current folding cell shown in FIG. 19;
FIG. 24 shows a possible way of how the proper bias can be provided for the
core of the current folding cell shown in FIG. 20;
FIG. 25 shows an alternative way to apply the proper bias to the core of the
current folding cell shown in FIG. 20;
FIG. 26 shows an embodiment of the current folding cell based on the core shown
in FIG. 19, where at each of the two inputs of the current folding cell the input
current is added to a reference current, and where the means for proper biasing
of the core is provided;
FIG. 27 illustrates how the means for proper biasing of the core of a previous
current folding cell can be provided by the succeeding current folding cell in
a cascade of current folding cells;
FIG. 28 shows in more detail how a cascade of current folding cells containing
the core of FIG. 19 can be constructed for use in an analog-to-digital converter;
FIG. 29 gives a block diagram representation of the circuit in FIG. 28;
FIG. 30 gives a block diagram representation of another cascade of folding circuit cells;
FIG. 31 gives a block diagram representation of the cascade of folding circuit
cells of FIG. 30;
FIG. 32 illustrates how several cascades of folding circuit cells can be put
in parallel for the construction of an analog-to-digital converter;
FIG. 33 shows the magnitude of the output currents after the first stage in
the cascades of FIG. 32;
FIG. 34 shows the magnitude of the output currents after the second stage in
the cascades of FIG. 32;
FIG. 35 shows the magnitude of the output currents after the third stage in
the cascades of FIG. 32;
FIG. 36 shows the magnitude of the output currents after the fourth stage in
the cascades of FIG. 32;
FIG. 37 shows the current outputs after addition of the currents delivered by
the current sources after the fourth stage in FIG. 32;
FIG. 38 illustrates how averaging for the most significant bits can be implemented
in case a plurality of parallel folding cells or cascades of folding cells are
used in the analog-to-digital converter;
FIG. 39 illustrates one example of how current outputs of an embodiment of the
novel current folding cell can be combined;
FIG. 40 shows an example with two folding circuits fed by two differential pairs
to explain how offset between the two differential pairs can be detected;
FIG. 41 shows the output currents f1, f1-, f2 and f2-
of the two folding circuits of FIG. 40 as a function of the input current, in case
no offset is present apart from the one deliberately introduced. The figure also
shows a corrective signal "Corr" derived from these output currents which is proportional
to the random offset between the two differential pairs shown in FIG. 40;
FIG. 42 shows the output currents f1, f1-, f2 and f2-
of the two folding circuits of FIG. 40 and the corrective signal "Corr" derived
from these output currents, as a function of the input current, in case some random
offset is present apart from the one deliberately introduced between the differential
pairs shown in FIG. 40;
FIG. 43 shows how the corrective signal Corr can be derived from the folder
output currents of the circuit show
