Data inversion circuits having a bypass mode of operation and methods of operating the same Number:7,142,021 from the United States Patent and Trademark Office (PTO) owispatent

Title: Data inversion circuits having a bypass mode of operation and methods of operating the same

Abstract: An integrated circuit device includes a data inversion circuit configured to support an inversion mode of operation. The inversion mode of operation inverts selected ones of a plurality of N-bit words received in consecutive sequence at inputs thereof. The data inversion circuit is further configured to support a bypass mode of operation. The bypass mode of operation disables inversion of a second one of the plurality of N-bit words when a delay between receipt of the second one of the plurality of N-bit words and receipt of an immediately preceding first one of the plurality of N-bit words is greater than a predetermined time interval. Related methods are also discussed.

Patent Number: 7,142,021 Issued on 11/28/2006 to Park

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Inventors:	Park; Min-sang (Gyeonggi-do, KR)
Assignee:	Samsung Electronics Co., Ltd. (Suwon-si, KR)
Appl. No.:	10/991,076
Filed:	November 17, 2004

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Foreign Application Priority Data

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Dec 13, 2003 [KR]			10-2003-0090940

Current U.S. Class:	326/104 ; 326/56; 365/206; 365/233
Current International Class:	H03K 19/20 (20060101)
Field of Search:	326/46,52,56,104,113 365/194,233,189.05,206

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References Cited [Referenced By]

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U.S. Patent Documents

	4462102		July 1984		Povlick
	5477551		December 1995		Parks et al.
	5881076		March 1999		Murray
	5915082		June 1999		Marshall et al.
	5931927		August 1999		Takashima
	6456551		September 2002		Sohn et al.
	6633951		October 2003		Cohen
	6731567		May 2004		Acharya et al.
	6735733		May 2004		La Rosa
	6788106		September 2004		Kwak et al.
	6992506		January 2006		Park et al.
	2004/0066213		April 2004		Kwak et al.

Foreign Patent Documents

	1 336 972		Aug., 2003		EP
	000046659		Jul., 2000		KR
	000050971		Aug., 2000		KR

Primary Examiner: Chang; Daniel
Attorney, Agent or Firm: Myers Bigel Sibley & Sajovec, PA

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Claims

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The invention claimed is:

1. An integrated circuit device, comprising: a data inversion circuit configured to support an inversion mode of operation that inverts selected ones of a plurality of N-bit words received in consecutive sequence at inputs thereof, and further configured to support a bypass mode of operation that disables inversion of a second one of the plurality of N-bit words in response to detecting that a delay between receipt of the second one of the plurality of N-bit words and receipt of an immediately preceding first one of the plurality of N-bit words is greater than a predetermined time interval.

2. The device of claim 1, wherein the data inversion circuit comprises an inversion unit configured to support the inversion mode of operation and a bypass unit configured to support the bypass mode of operation, wherein the bypass mode of operation is selectively enabled in response to a control signal indicating that the delay is greater than the time interval.

3. The device of claim 2, wherein the control signal indicates when a delay window between receiving two consecutive read instructions is greater than a predetermined number of clock cycles.

4. The device of claim 2, wherein the bypass unit is selectively enabled when the control signal has a first logic value, and wherein the bypass unit is disabled when the control signal has a second logic value opposite the first logic value.

5. The device of claim 4, wherein the inversion unit is disabled when the control signal has the first logic value, and wherein the inversion unit is enabled when the control signal has the second logic value.

6. The device of claim 2, further comprising a controller that evaluates the delay and generates the control signal when the delay is greater than a predetermined number of clock cycles.

7. The device of claim 6, wherein the delay is a read interval between receiving a first read instruction for the first word and a second read instruction for the second word, and wherein the controller further comprises a control signal generator that generates the control signal at a logic 1 value when the read interval is greater than the predetermined number of clock cycles.

8. The device of claim 7, wherein the control signal generator comprises: a latch unit configured to generate the control signal at a logic 1 value responsive to a clock signal indicating passage of a predetermined number of clock cycles from receipt of the first read instruction; and a reset unit configured to reset the control signal to a logic 0 value responsive to receipt of the second read instruction.

9. The device of claim 1, wherein the plurality of N-bit words comprises groups of N-bit words received in consecutive sequence in response to corresponding consecutive read instructions, and wherein the bypass mode of operation disables inversion of a first one of a second group of N-bit words when a delay between receipt of the first one of the second group of N-bit words and receipt of a last one of an immediately preceding first group of N-bit words is greater than a predetermined number of clock cycles.

10. The device of claim 9, wherein the device is a dual data rate (DDR) memory device, and further comprising a memory cell array that is configured to support a 4-bit prefetch operation in response to the consecutive read instructions, wherein each group comprises four N-bit words.

11. An integrated circuit device, comprising: a data inversion circuit in a read path of the integrated circuit device, the data inversion circuit comprising an inversion unit configured to inhibit simultaneous switching noise by inverting selected ones of a plurality of N-bit words received in consecutive sequence at inputs thereof, and further comprising a bypass unit configured to remove the inversion unit from the read path of the integrated circuit device in response to a control signal indicating that a delay between receipt of two consecutive N-bit words in the read path exceeds a predetermined time interval.

12. The device of claim 11, further comprising a controller that evaluates the delay and generates the control signal when the delay is greater than a predetermined number of clock cycles.

13. The device of claim 12, wherein the delay is a read interval between receiving a first read instruction for a first word and a second read instruction for a second word, and wherein the controller further comprises a control signal generator that generates the control signal at a logic 1 value when the read interval is greater than the predetermined number of clock cycles.

14. The device of claim 13, wherein the control signal generator comprises: a latch unit configured to generate the control signal at a logic 1 value responsive to a clock signal indicating passage of a predetermined number of clock cycles from receipt of the first read instruction; and a reset unit configured to reset the control signal to a logic 0 value responsive to receipt of the second read instruction.

15. The device of claim 11, wherein the plurality of N-bit words comprises groups of N-bit words received in consecutive sequence in response to corresponding consecutive read instructions, and wherein the bypass mode of operation disables inversion of a first one of a second group of N-bit words when a delay between receipt of the first one of the second group of N-bit words and receipt of a last one of an immediately preceding first group of N-bit words is greater than a predetermined number of clock cycles.

16. A method of operating a memory device read path having a data inversion circuit therein that is configured to reduce simultaneous switching noise when enabled, comprising: reading data through an inversion unit of the data inversion circuit to thereby reduce simultaneous switching noise at outputs of the memory device during first read operations; and bypassing the inversion unit to thereby reduce a read latency of the read path during second read operations that are less susceptible to simultaneous switching noise relative to the first read operations.

17. A data inversion circuit of a semiconductor device comprising: a controller which receives read commands enabled sequentially per a predetermined read interval and a clock signal, wherein the controller outputs a control signal according to the read interval and generates initial input data and an initial flag signal in response to the control signal and the read commands; a bypass unit which is enabled or disabled in response to the control signal, wherein the bypass unit outputs input data read from a memory cell array as output data in response to the read commands when the bypass unit is enabled; and an inversion unit which is enabled or disabled in response to the control signal, wherein the inversion unit performs inversion/non-inversion of the input data in response to the input data, the initial input data and the initial flag signal when the inversion unit is enabled, and wherein the inversion unit generates the inverted/non-inverted data as the output data, wherein the inversion unit is disabled when the bypass unit is enabled and the read interval is changed by a frequency in which the read command is generated.

18. The data inversion circuit of claim 17, wherein the read commands include a first read command enabled during a first predetermined time and a second read command enabled after the first predetermined time, wherein the first read command is prior to the second read command, and wherein the input data includes first input data read from the memory cell array in response to the first read command, and second input data read from the memory cell array in response to the second read command.

19. The data inversion circuit of claim 18, wherein the controller comprises: a control signal generator, which receives the first and second read commands and the clock signal, determines whether the read interval exceeds a second predetermined time, and generates the control signal according to the determined result; an initial input data generator, which stores the first input data in response to the control signal and the first read command, and outputs the stored first input data as the initial input data in response to the second read command; and an initial flag signal generator, which stores a first flag signal indicating inversion/non-inversion of the first input data in response to the control signal and the first read command, and outputs the stored first flag signal as the initial flag signal in response to the control signal and the second read command.

20. The data inversion circuit of claim 19, wherein the controller further comprises: a first inverter, which inverts the control signal and outputs an inverted control signal; and a second inverter, which inverts the initial flag signal and outputs an inverted initial flag signal.

21. The data inversion circuit of claim 19, wherein the control signal generator comprises: a latch unit, which receives a first internal control signal in response to the clock signal, delays the first internal control signal during a third predetermined time, and outputs the delayed first internal control signal as the control signal; and a reset unit, which resets the latch unit in response to each of the read commands.

22. The data inversion circuit of claim 21, wherein the latch unit comprises: a first inverter, which inverts the clock signal and outputs an inverted clock signal; first switches, which are turned on or off in response to the clock signal and the inverted clock signal; second switches, whose input terminals are connected respectively to output terminals of the first switches, which are turned on or off in response to the clock signal and the inverted clock signal, and are turned off when the first switches are turned on; first latch circuits, which are connected respectively between output terminals of the first switches and input terminals of the second switches and latch and output first output signals of the first switches to the second switches; and second latch circuits, whose input terminals are connected respectively to output terminals of the second switches and which latch and output second output signals of the second switches, wherein at least a switch of the first switches receives the first internal control signal and outputs the first internal control signal as the first output signal when the switch is turned on, and at least a latch circuit of the second latch circuits outputs a second output signal received from the second switch as the control signal, an input terminal of the latch circuit being connected to an output terminal of the second switch.

23. The data inversion circuit of claim 22, wherein the reset unit comprises: a second inverter, which inverts the read commands respectively and outputs inverted read commands; first pre-discharge circuits, which are enabled or disabled in response to the read commands and pre-discharge input terminals of the first latch circuits to a ground voltage level when the first pre-discharge circuits are enabled; and second pre-discharge circuits, which are enabled or disabled in response to the inverted read commands, and pre-charge input terminals of the second latch circuits to an internal voltage level when the second pre-discharge circuits are enabled.

24. The data inversion circuit of claim 19, wherein the initial input data generator comprises: a data storage unit, which is enabled or disabled in response to the control signal and the first read command and latches and stores the first input data when the data storage unit is enabled; and a data output unit, which is enabled or disabled in response to the second read command and outputs first input data received from the data storage unit as the initial input data when the data output unit is enabled.

25. The date inversion circuit of claim 19, wherein the initial flag signal generator comprises: a flag storage unit, which is enabled or disabled in response to the control signal and the first read command and latches and stores the first flag signal when the flag storage unit is enabled; and a flag output unit, which is enabled or disabled in response to the second read command, and outputs the initial flag signal in response to the control signal and a first flag signal received from the flag storage unit when the flag output unit is enabled.

26. The data inversion circuit of claim 25, wherein the flag output unit maintains the initial flag signal in a low level when the control signal is in a high level, and outputs the first flag signal as the initial flag signal when the control signal is in a low level.

27. A data inversion method used in a semiconductor device, the method comprising: (a) receiving read commands enabled sequentially per a predetermined read interval and a clock signal; (b) determining whether the read interval exceeds a predetermined time interval and generating a control signal according to the determined result; (c) generating initial input data and an initial flag signal in response to the control signal and the read commands; (d) bypassing input data read from a memory cell array in response to the read commands when the control signal is enabled and outputting the input data as output data; and (e) performing inversion/non-inversion of the input data in response to the input data, the initial input data, and the initial flag signal, and generating the inverted/non-inverted data as output data when the control signal is disabled, wherein the read interval is changed by a frequency in which the read commands are generated.

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Description

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REFERENCE TO PRIORITY APPLICATION

This application claims priority to Korean Patent Application No. 2003-90940, filed on Dec. 13, 2003, the disclosure of which is hereby incorporated by reference herein in its entirety.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is related to commonly assigned U.S. patent application Ser. No. 10/815,505, filed Apr. 1, 2004, the disclosure of which is hereby incorporated herein by reference. This application is also related to commonly assigned U.S. Pat. No. 6,788,106, filed Mar. 26, 2003, the disclosure of which is hereby incorporated by reference herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to integrated circuit devices, and more particularly, to integrated circuit devices having high data bandwidth..

2. Description of the Related Art

Generally, semiconductor memory devices have a high bandwidth input/output (I/O) structure, and may include 32 data output pins, or DQ pins. In such a high bandwidth memory device, the 32 DQ pins may operate at the same time when data is output, resulting in a great amount of noise, known as simultaneous switching noise (SSN). Due to SSN, waveforms of data output signals may be distorted, which may deteriorate signal integrity of the memory device. As such, it may be difficult for the memory device to satisfy the input/output performance required in a high-frequency system. For this reason, conventional techniques to reduce SSN have included the use of data inversion circuits.

Data inversion methods may aim to reduce the amount of SSN generated in memory devices by limiting the number of parallel data signals that switch value during consecutive data output cycles. A memory device using the data inversion method may either invert and output current data or output the current data without inversion based on how many bits of data (generally, 8 bits) to be currently output are switched or "toggled" as compared to corresponding bits of previously output data. More particularly, if the number of toggled bits is greater than or equal to one-half of the number of bits to be currently output, the memory device may invert and output the data, and additionally may output a flag signal of 1-bit indicating that the data was inverted. On the other hand, if the number of toggled bits is less than one-half of the number of bits to be currently output, the memory device may output the data without inversion, and may additionally output a flag signal of 1-bit indicating that the data was not inverted. As such, the number of bits of the output data to be toggled can be reduced to less than half of the total number of bits to be output, and accordingly, switching noise in the memory device can be reduced. As a result, the signal intensity of output signals may be improved, such that input/output performance of the memory device may also be improved.

FIG. 1 illustrates a conventional data inversion circuit. FIG. 1 shows a data inversion circuit that performs inversion/non-inversion on 8-bit data to be output to 8 data output pads (DQ pads).

Referring to FIG. 1, the data inversion circuit 10 includes logic circuits 11 and 12 and a comparator 13. Each of the logic circuits 11 and 12 includes 8 XOR gates. The logic circuit 11 determines whether or not bits of data FDO1 through FDO8 to be currently output (which are read from a memory cell), are to be toggled based on corresponding bits of data DO1 through DO8 which were previously output from the data inversion circuit 10. The comparator 13 outputs a flag signal FLG with a predetermined level according to the determined result of the logic circuit 11. The logic circuit 12 inverts and outputs the data FDO1 through FDO8 to be currently output, or alternatively, outputs the data FDO1 through FDO8 without inversion, in response to the flag signal FLG.

As described above, a conventional data inversion circuit may determine whether or not each bit of the previous data (which may have been output in an inverted state or in a non-inverted state) is toggled compared to a corresponding bit of data to be currently output, in order to decide whether the data to be currently output should be inverted or should not be inverted. The previously output data and the data to be currently output may be continuous or non-continuous. In other words, an interval in which no data is read (i.e., an interval where no read instructions are received) may exist between a time when the previous data has been read and a time when the data to be currently output is read. For example, a time interval (i.e., a reading interval) between receipt of a first read command for reading first data and receipt of a second read command for reading second data may exceed a predetermined time interval. In such a case, the data output circuit of the memory device may achieve a stable state during this time interval. Once the data output circuit reaches a stable state, SSN may not be generated in the data output voltage.

However, a conventional data inversion circuit may be inefficient in that an inversion operation may be performed on the data to be currently output regardless of the presence of a reading interval between the previous data and the data to be currently output. In other words, the current output may be inverted to inhibit SSN even though SSN may not be present because of an extended reading interval where no switching is performed. Also, such an inversion operation may reduce the operating speed of the semiconductor device.

Also, a conventional data inversion circuit may compare data to be currently output with previously output data in order to decide whether or not the data to be currently output should be inverted. The previously output data may have been subjected to inversion/non-inversion, while the data to be currently output is data before being subjected to inversion/non-inversion. Accordingly, a timing margin may exist between the previous data and the data to be currently output. Such a timing margin may further reduce the operating speed of the data inversion circuit, and may limit the operational frequency of the semiconductor device.

SUMMARY OF THE INVENTION

According to some embodiments of the present invention, an integrated circuit device may include a data inversion circuit configured to support an inversion mode of operation. The inversion mode of operation inverts selected ones of a plurality of N-bit words received in consecutive sequence at inputs thereof. The data inversion circuit is further configured to support a bypass mode of operation. The bypass mode of operation disables inversion of a second one of the plurality of N-bit words when a delay between receipt of the second one of the plurality of N-bit words and receipt of an immediately preceding first one of the plurality of N-bit words is greater than a predetermined time interval.

In other embodiments, the data inversion circuit may include an inversion unit configured to support the inversion mode of operation and a bypass unit configured to support the bypass mode of operation. The bypass mode of operation may be selectively enabled in response to a control signal indicating that the delay is greater than the time interval. In further embodiments, the control signal may indicate that a delay window between receiving a first read instruction for the first word and a second read instruction for the second word in a consecutive sequence is greater than a predetermined number of clock cycles.

n some embodiments, the bypass unit may be selectively enabled when the control signal has a first logic value, and wherein the bypass unit is disabled when the control signal has a second logic value opposite the first logic value. In further embodiments, the inversion unit may be disabled when the control signal has the first logic value, and wherein the inversion unit is enabled when the control signal has the second logic value.

In other embodiments, the data inversion circuit may further include a controller that evaluates the delay and generates the control signal when the delay is greater than a predetermined number of clock cycles. In some embodiments, the delay may be a read interval between receiving a first read instruction for the first word and a second read instruction for the second word, and the controller may further include a control signal generator that generates the control signal at a logic 1 value when the read interval is greater than the predetermined number of clock cycles.

In further embodiments, the control signal generator may include a latch unit configured to generate the control signal at a logic 1 value responsive to a clock signal indicating passage of a predetermined number of clock cycles from receipt of the first read instruction. The control signal generator may further include a reset unit configured to reset the control signal to a logic 0 value responsive to receipt of the second read instruction.

In some embodiments, the plurality of N-bit words may include groups of N-bit words received in consecutive sequence in response to corresponding consecutive read instructions. The bypass mode of operation may disable inversion of a first one of a second group of N-bit words when a delay between receipt of the first one of the second group of N-bit words and receipt of a last one of an immediately preceding first group of N-bit words is greater than a predetermined number of clock cycles. In further embodiments, the device may be a dual data rate (DDR) memory device, and may include a memory cell array that is configured to support a 4-bit prefetch operation in response to the consecutive read instructions, wherein each group comprises four N-bit words.

According to other embodiments of the present invention, an integrated circuit device may include a data inversion circuit in a read path of the integrated circuit device. The data inversion circuit may include an inversion unit configured to inhibit simultaneous switching noise by inverting selected ones of a plurality of N-bit words received in consecutive sequence at inputs thereof. The data inversion circuit may further include a bypass unit configured to remove the inversion unit from the read path of the integrated circuit device in response to a control signal that indicates a delay between receipt of the second one of the plurality of N-bit words and receipt of an immediately preceding first one of the plurality of N-bit words is greater than a predetermined time interval.

In some embodiments, the data inversion circuit may further include a controller that evaluates the delay and generates the control signal when the delay is greater than a predetermined number of clock cycles. In further embodiments, the delay may be a read interval between receiving a first read instruction for the first word and a second read instruction for the second word, and wherein the controller further comprises a control signal generator that generates the control signal at a logic 1 value when the read interval is greater than the predetermined number of clock cycles.

In other embodiments, the control signal generator may include a latch unit configured to generate the control signal at a logic 1 value responsive to a clock signal indicating passage of a predetermined number of clock cycles from receipt of the first read instruction, and a reset unit configured to reset the control signal to a logic 0 value responsive to receipt of the second read instruction.

In some embodiments, the plurality of N-bit words may include groups of N-bit words received in consecutive sequence in response to corresponding consecutive read instructions. The bypass mode of operation may disable inversion of a first one of a second group of N-bit words when a delay between receipt of the first one of the second group of N-bit words and receipt of a last one of an immediately preceding first group of N-bit words is greater than a predetermined number of clock cycles.

According to further embodiments of the present invention, a method of operating a memory device read path having a data inversion circuit therein that is configured to reduce simultaneous switching noise when enabled may include reading data through an inversion unit of the data inversion circuit in order to reduce simultaneous switching noise at outputs of the memory device during first read operations. The method may further include bypassing the inversion unit to thereby reduce a read latency of the read path during second read operations that are less susceptible to simultaneous switching noise relative to the first read operations.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a conventional data inversion circuit.

FIG. 2 is a block diagram illustrating an exemplary semiconductor memory device including a data inversion circuit according to some embodiments of the present invention.

FIG. 3 is a block diagram illustrating a data inversion circuit according to some embodiments of the present invention as shown in FIG. 2.

FIG. 4 is a block diagram illustrating a controller according to some embodiments of the present invention as shown in FIG. 3.

FIG. 5 is a schematic diagram illustrating a control signal generator according to some embodiments of the present invention as shown in FIG. 4.

FIG. 6 is a schematic diagram illustrating an initial input data generator according to some embodiments of the present invention as shown in FIG. 4.

FIG. 7 is a schematic diagram illustrating an initial flag signal generator according to some embodiments of the present invention as shown in FIG. 4.

FIG. 8 is a block diagram illustrating an inversion unit and a bypass unit according to some embodiments of the present invention as shown in FIG. 3.

FIG. 9 is a schematic diagram illustrating first and second logic circuits, a comparison circuit and a selector according to some embodiments of the present invention as shown in FIG. 8.

FIG. 10 is a schematic diagram illustrating a comparison circuit according to some embodiments of the present invention as shown in FIG. 9.

FIG. 11 is a schematic diagram illustrating XOR gates of a second logic circuit according to some embodiments of the present invention as shown in FIG. 9.

FIG. 12 is a schematic diagram illustrating a third NAND gate according to some embodiments of the present invention as shown in FIG. 11.

FIG. 13 is a timing diagram illustrating input and output signals of a data inversion circuit according to some embodiments of the present invention as shown in FIG. 3.

FIG. 14 is a block diagram illustrating a semiconductor memory device including a data inversion circuit according to further embodiments of the present invention.

FIG. 15 is a block diagram illustrating a data inversion circuit according to further embodiments of the present invention as shown in FIG. 14.

FIG. 16 is a block diagram illustrating an inversion unit and a bypass unit according to further embodiments of the present invention as shown in FIG. 15.

FIG. 17 is a schematic diagram illustrating comparison circuits according to further embodiments of the present invention as shown in FIG. 16.

FIG. 18 is a timing diagram illustrating main input and output signals of a data inversion circuit according to further embodiments of the present invention as shown in FIG. 15.

FIG. 19 is a block diagram illustrating a conventional data inversion circuit.

FIG. 20 is a timing diagram illustrating main input and output signals of a conventional data inversion circuit as shown in FIG. 19.

DETAILED DESCRIPTION OF THE INVENTION

The present invention now will be described more fully herein with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout and signal lines and signals thereon may be referred to by the same reference characters. Signals may also be synchronized and/or undergo minor boolean operations (e.g., inversion) without being considered different signals. Moreover, when a device or element is stated as being responsive to a signal(s), it may be directly responsive to the signal(s) or indirectly responsive to the signal(s) (e.g., responsive to another signal(s) that is derived from the signal(s)).

The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the description of the invention and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. All publications, patent applications, patents, and other references mentioned herein are incorporated by reference in their entirety.

FIG. 2 is a block diagram of a semiconductor memory device including a data inversion circuit according to some embodiments of the present invention. FIG. 2 illustrates a semiconductor device 100 including 8 DQ pads DQ1 through DQ8. Referring now to FIG. 2, the semiconductor memory device 100 includes a memory cell array 110, a data inversion circuit 200, a data output buffer 120 and a flag signal buffer 130. The memory cell array 110 outputs input data FDOi (i=1 8) to the data inversion circuit 200 in response to a read instruction READ. In FIG. 2, the designator "i" is used to identify data to be output to similarly designated DQ pads. Since the semiconductor memory device 100 of FIG. 2 has 8 DQ pads, "i" may be an integer from 1 to 8. For example, FDO1 represents data to be output to a DQ pad DQ1, and FDO2 represents data to be output to a DQ pad DQ2.

The data inversion circuit 200 receives a clock signal CLK and the read command READ, and receives the input data FDOi from the memory cell array 110. Although not shown in FIG. 2, the read command READ includes read commands READ(k-1) and READ(k) (where k can be a natural number equal to or greater than two) which are sequentially generated per a predetermined time interval. The data inversion circuit 200 determines whether or not a time interval or delay between receipt of a read command READ(k-1) and receipt of the following read command READ(k) exceeds a predetermined time interval, such as a predetermined number of clock cycles. The data inversion circuit 200 either performs inversion/non-inversion of the input data FDOi or bypasses the inversion operation according to the determined result, and outputs output data DOi (i=1 8). In other words, the data inversion circuit 200 may support a bypass operation that can disable an inversion operation of the data inversion circuit when a delay between receipt of initial input data FDOi(k-1) and receipt of input data FDOi(k) is greater than a predetermined time interval. The data inversion circuit 200 also outputs a flag signal S, indicating whether or not the input data FDOi is inverted.

The data output buffer 120 receives the output data DOi from the data inversion circuit 200 and outputs the output data DOi from the semiconductor memory device 100 through the first through eighth DQ pads DQ1 through DQ8.

Meanwhile, the flag signal S output from the data inversion circuit 200 is output to an external source through the flag signal buffer 130. The flag signal S may preferably be output to the external source through a data masking pin (DM pin). The DM pin may be a separate pin from the data output pins/pads and may generally be included in SDRAM. The DM pin may be used to mask input data in a write mode, i.e. used to prevent input data from being written in a semiconductor memory device. The DM pin is generally not used in a read mode. Accordingly, since an existing DM pin may be used to output the flag signal, additional pins to output the flag signal may be unnecessary in the semiconductor memory device.

FIG. 3 is a detailed block diagram of a data inversion circuit according to some embodiments of the present invention as shown in FIG. 2. In FIG. 3, input data FDOi(k-1) is read from the memory cell array 110 of FIG. 2 in response to a read command READ(k-1), and input data FDOi(k) is read from the memory cell array 110 in response to a read command READ(k). In the embodiments illustrated in FIG. 3, the read command READ(k-1) is received prior to the read command READ(k), i.e. the read command READ(k-1) is an initial read command.

Referring now to FIG. 3, the data inversion circuit 200 includes a controller 210, an inversion unit 220, and a bypass unit 230. When the controller 210 receives the read command READ(k-1), the controller 210 stores the input data FDOi(k-1) and a flag signal S(k-1) (where k can be a natural integer greater than or equal to two). The flag signal S(k-1) indicates whether or not the input data FDOi(k-1) is inverted. The controller 210 also receives a clock signal CLK and the read commands READ(k-1) and READ(k), and determines whether a read interval between read commands exceeds a predetermined number of clock cycles. The controller 210 outputs a control signal CTL and an inverted control signal CTLB according to the determined result. If the controller 210 receives the read command READ(k) when the read interval is equal to or smaller than the predetermined number of clock cycles, the controller 210 outputs initial input data PFDOi, an initial flag signal PS and an inverted initial flag signal PSB. The initial input data PFDOi and the initial flag signal PS are the input data FDOi(k-1) and the flag signal S(k-1) stored in the controller 210. The initial input data PFDOi is then compared (bit-to-bit) with the data FDOi(k) to be currently output, in order to determine whether or not to invert the data to be currently output. In other words, when the read interval is less than or equal to the predetermined period, the controller 210 enables the inversion unit 220. Also, the initial flag signal PS indicates whether or not the initial input data PFDOi is inverted.

Meanwhile, when the read interval exceeds the predetermined number of clock cycles, the controller 210 does not output the initial input data PFDOi, the initial flag signal PS and the inverted initial flag signal PSB to the inversion unit 220. The controller 210 is described in greater detail below with reference to FIGS. 4 through 7.

Still referring to FIG. 3, the inversion unit 220 is enabled or disabled in response to the control signal CTL and the inverted control signal CTLB. When the inversion unit 220 is enabled, the inversion unit 220 determines whether each of the bits of the input data FDOi(k) are toggled with respect to the corresponding bits of the initial input data PFDOi. Then, the inversion unit 220 inverts and outputs the input data FDOi(k) or outputs the input data FDOi(k) without inversion, in response to the determined result. Also, the inversion unit 220 outputs a flag signal S(k) indicating whether or not the input data FDOi(k) is inverted.

The bypass unit 230 is enabled or disabled in response to the control signal CTL and the inverted control signal CTLB. When the bypass unit 230 is enabled, the bypass unit 230 receives and outputs the input data FDOi(k) as the output data DOi(k). The controller 210 enables the bypass unit 230 when the read interval is greater than the predetermined period. In other words, when the bypass unit 230 is enabled, the inversion unit 220 is disabled. The inversion unit 220 and the bypass unit 230 are described below in further detail with reference to FIG. 8.

FIG. 4 is a detailed block diagram of a controller according to some embodiments of the present invention as shown in FIG. 3. Referring to FIG. 4, the controller 210 includes a control signal generator 240, an initial input data generator 250, an initial flag signal generator 260, and inverters 270 and 280. The control signal generator 240 receives the clock signal CLK and the read commands READ(k-1) and READ(k), and determines whether or not the read interval exceeds the predetermined number of clock cycles.

The control signal generator 240 outputs the control signal CTL with a high (logic 1) level when the read interval exceeds the predetermined number of clock cycles. Alternatively, the control signal generator 240 outputs the control signal CTL with a low (logic 0) level when the read interval is less than or equal to the predetermined number of clock cycles. For example, if the predetermined number of clock cycles is two, the control signal generator 240 outputs the control signal CTL with a high level if the read command READ(k) is not received within two clock cycles after the read command READ(k-1) is received. On the other hand, the control signal generator 240 outputs the control signal CTL with a low level if the read command READ(k) is received within two clock cycles after the read command READ(k-1) is received. The inverter 270 inverts the control signal CTL and outputs an inverted control signal CTLB.

The initial input data generator 250 stores the input data FDOi(k-1) in response to the read command READ(k-1) and the control signal CTL, and outputs the input data FDOi(k-1) as initial input data PFDOi in response to the read command READ(k).

The initial flag signal generator 260 stores the flag signal S(k-1) in response to the read command READ(k-1) and the control signal CTL, and outputs the flag signal S(k-1) as an initial flag signal PS in response to the read command READ(k). The inverter 280 inverts the initial flag signal PS and outputs an inverted initial flag signal PSB.

FIG. 5 is a schematic diagram of a control signal generator according to some embodiments of the present invention as shown in FIG. 4. Referring to FIG. 5, the control signal generator 240 includes a latch unit 241 and a reset unit 242. The latch unit 241 latches and stores a first internal control signal ICTL in response to a clock signal CLK, delays the first internal control signal ICTL by a predetermined time, and outputs the delayed signal as the control signal CTL. The first internal control signal ICTL has an internal voltage level VDD.

The latch unit 241 includes an inverter 21, transmission gates 31 through 36, and latch circuits 41 through 46. The number of the transmission gates and latch circuits included in the latch unit 241 may be changed according to the predetermined time period. In FIG. 5, for example, the predetermined time period is 3 clock cycles.

Still referring to FIG. 5, the inverter 21 inverts the clock signal CLK and outputs an inverted clock signal CLKB. The transmission gates 31 through 36 are connected in series, and the latch circuits 41 through 46 are each connected to respective output terminals of the transmission gates 31 through 36. The transmission gates 31 through 36 are turned on or off in response to the clock signal CLK and the inverted clock signal CLKB. When the transmission gates 31, 33 and 35 are turned on, the transmission gates 32, 34 and 36 are turned off. In other words, the transmission gates 31, 33 and 35 and the transmission gates 32, 34 and 36 are alternately turned on in response to the clock signal CLK and the inverted clock signal CLKB. As a result, the first internal control signal ICTL is passed sequentially through the transmission gates 31 through 35 and latched sequentially by the latch circuits 41 through 45. Transmission gate 36 and latch circuit 46 output the first internal control signal ICTL as the control signal CTL.

The first internal control signal ICTL passes through two transmission gates in one clock cycle. Accordingly, the first internal control signal ICTL passes through the six transmission gates 31 through 36 in three clock cycles, i.e. in the predetermined period.

Again referring to FIG. 5, the reset unit 242 resets the latch unit 241 in response to the read commands READ(k-1) and READ(k). The reset unit 242 includes an inverter 51, NMOS transistors N1 through N3, and PMOS transistors P1 through P3. The inverter 51 inverts the read commands READ(k-1) and READ(k) received sequentially and sequentially outputs inverted read commands READ(k-1)B and READ(k)B.

The respective drains of the NMOS transistors N1 through N3 are connected to respective input terminals of the latch circuits 41, 43 and 45, respective sources of the NMOS transistors N1 through N3 are connected to a ground voltage, and the read commands READ(k-1) and READ(k) are applied sequentially to respective gates of NMOS transistors N1 through N3. The NMOS transistors N1 through N3 are turned on or off in response to the sequentially received read commands READ(k-1) and READ(k). When the NMOS transistors N1 through N3 are turned on, the NMOS transistors N1 through N3 pre-discharge the input terminals of the latch circuits 41, 43 and 45 to a ground voltage level.

The sources of the PMOS transistors P1 through P3 are connected to an internal voltage VDD, respective drains of the PMOS transistors P1 through P3 are connected to respective input terminals of the latch circuits 42, 44 and 46, and the inverted read commands READ(k-1)B and READ(k)B are applied sequentially to respective gates to PMOS transistors P1 through P3. The PMOS transistors P1 through P3 are turned on or off in response to the inverted read commands READ(k-1)B and READ(k)B. When the PMOS transistors P1 through P3 are turned on, the PMOS transistors P1 through P3 pre-charge the input terminals of the latch circuits 42, 44 and 46 to the internal voltage level VDD.

Operations of the control signal generator 240 will now be described in greater detail with reference to FIG. 5. When the clock signal CLK is at a high (logic 1) level, the read command READ(k-1) is enabled for a predetermined time and then disabled. If the read command READ(k-1) is enabled, the reset unit 242 resets the latch unit 241 in response to the read command READ(k-1). Thereafter, when the clock signal CLK is changed to a low (logic 0) level, the transmission gates 31, 33 and 35 of the latch unit 241 are turned-on and the transmission gates 32, 34 and 36 are turned-off. The transmission gate 31 receives and outputs the first internal control signal ICTL with a high level. The latch circuit 41 latches the first internal control signal ICTL with the high level received from the transmission gate 31 and outputs the first internal control signal ICTL with a low level. If the clock signal CLK is changed to a high level, the transmission gates 31, 33 and 35 are turned off, and the transmission gates 32, 34 and 36 are turned on. The transmission gate 32 receives and outputs the first internal control signal ICTL with a low level received from the latch circuit 41. The latch circuit 42 latches the first internal control signal ICTL with the low level received from the transmission gate 32 and outputs the first internal control signal ICTL with a high level. The transmission gates 33 through 36 and the latch circuits 43 through 46 operate similarly to the transmission gates 31 and 32 and the latch circuits 41 and 42.

If the following read command READ(k) is received within three clock cycles after the read command READ(k-1) is received, the latch unit 241 is reset to maintain the control signal CTL in a low level, thereby enabling the inversion unit 220. Alternatively, if the following read command READ(k) is received later than three clock cycles from receipt of the read command READ(k-1), the latch unit 241 outputs the control signal CTL with a high level, thereby enabling the bypass unit 230.

FIG. 6 is a schematic diagram of an initial input data generator according to some embodiments of the present invention as shown in FIG. 4. Although a single initial input data generator is shown in FIG. 6, additional initial input data generators corresponding to the number of bits of input data may be necessary. For example, if 8-bit input data FDO1 through FDO8 is used, eight input data generators may be necessary. With reference to FIG. 6, operation of a single initial input data generator will be described for convenience.

Referring now to FIG. 6, the initial input data generator 250 includes a data latch unit 251 and a data output unit 252. The data latch unit 251 is enabled or disabled in response to the read command READ(k-1). If the data latch unit 251 is enabled, the data latch unit 251 latches and stores input data FDOi(k-1). The data latch unit 251 includes inverters 61 and 62, transmission gates 63 and 64, and latch circuits 65 and 66.

The inverter 61 inverts the read command READ(k-1) and outputs an inverted read command READ(k-1)B. The inverter 62 again inverts the inverted read command READ(k-1)B and outputs the read command READ(k-1).

The transmission gates 63 and 64 are connected in series, and have output terminals connected to respective latch circuits 65 and 66. The transmission gates 63 and 64 are turned on or off in response to the read command READ(k-1) and the inverted read command READ(k-1)B. If the transmission gate 63 is turned on, the transmission gate 64 is turned off. As a result, the input data FDOi(k-1) passes sequentially through the transmission gates 63 and 64 and is latched sequentially by the latch circuits 65 and 66.

The data output unit 252 is enabled or disabled in response to the read command READ(k). If the data output unit 252 is enabled, the data output unit 252 receives the input data FDOi(k-1) from the latch circuit 67 and outputs the input data FDOi(k-1) as initial input data PFDOi.

The data output unit 252 includes inverters 71 and 72, a transmission gate 73, and a latch circuit 74. The inverter 71 inverts the read command READ(k) and outputs an inverted read command READ(k)B. The input terminal of the transmission gate 73 is connected to the output terminal of the latch circuit 66, and the output terminal of the transmission gate 73 is connected to the input terminal of the latch circuit 74. The output terminal of the latch circuit 74 is connected to the input terminal of the inverter 72. The transmission gate 73 is turned on or off in response to the read command READ(k) and the inverted read command READ(k)B. When the transmission gate 73 is turned on, the transmission gate 73 receives the input data FDOi(k-1) from the latch circuit 66 and outputs the input data FDOi(k-1). The latch circuit 74 latches and outputs the input data FDOi(k-1) output from the transmission gate 73. The inverter 72 outputs the input data FDOi(k-1) received from the latch circuit 74 as initial input data PFDOi.

Operations of the initial input data generator 250 will now be described in greater detail with reference to FIG. 6. If the read command READ(k-1) is enabled at a high (logic 1) level during a predetermined time period, the inverter 61 inverts the read command READ(k-1) and outputs an inverted read command READ(k-1)B at a low (logic 0) level. Also, the inverter 62 again inverts the inverted read command READ(k-1)B and outputs the read command READ(k-1) at a high level. The transmission gate 63 is turned on and the transmission gate 64 is turned off in response to the read command READ(k-1) at a high level and the inverted read command READ(k-1)B at a low level. The transmission gate 63 receives and outputs the input data FDOi(k-1), and the latch circuit 65 latches and outputs the input data FDOi(k-1).

When the read command READ(k-1) is disabled to a low (logic 0) level, the inverter 61 outputs an inverted read command READ(k-1)B at a high (logic 1) level and the inverter 62 outputs a read command READ(k-1) at a low level. The transmission gate 64 is turned off and the transmission gate 64 is turned on in response to the read command READ(k-1) at a low level and the inverted read command READ(k-1)B at a high level. The transmission gate 64 receives the input data FDOi(k-1) from the latch circuit 65, and the latch circuit 66 latches and outputs the input data FDOi(k-1) output from the transmission gate 64.

Thereafter, if the read command READ(k) is enabled to a high (logic 1) level, the inverter 71 outputs an inverted read command READ(k)B with a low (logic 0) level. The transmission gate 73 is turned on and receives the input data FDOi(k-1) from the latch circuit 66 and outputs the input data FDOi(k-1), in response to the read command READ(k) at a high level and the inverted read command READ(k)B at a low level. The latch circuit 74 latches and outputs the input data FDOi(k-1) output from the transmission gate 73. The inverter 72 receives the input data FDOi(k-1) from the latch circuit 74 and outputs the input data FDOi(k-1) as the initial input data PFDOi.

FIG. 7 is a schematic diagram of an initial flag signal generator according to some embodiments of the present invention as shown in FIG. 4. The initial flag signal generator 260 of FIG. 7 includes a flag latch unit 261 and a flag output unit 262. The flag latch unit 261 includes inverters 81 and 82, transmission gates 83 and 84, and latch circuits 85 and 86. The configuration and operation of the flag latch unit 261 are similar to that of the data latch unit 251 shown in FIG. 6, with the exception that the data latch unit 251 latches and stores the input data FDOi(k-1), while the flag latch unit 261 latches and stores the flag signal S(k-1). The flag output unit 262 includes inverters 91 and 92, a transmission gate 93 and a latch circuit 94. The configuration and operation of the flag output unit 262 are also similar to that of the data output unit 252 shown in FIG. 6, with the exception that the data output unit 252 receives and outputs the input data FDOi(k-1) as the initial input data PFDOi, while the flag output unit 262 receives and outputs the flag signal S(k-1) as the initial flag signal PS.

Operations of the initial flag signal generator 260 will now be described in greater detail with reference to FIG. 7. When the read command READ(k-1) is enabled to a high (logic 1) level during a predetermined time period, the inverter 81 inverts the read command READ(k-1) and outputs an inverted read command READ(k-1)B at a low (logic 0) level. Also, the inverter 82 again inverts the inverted read command READ(k-1)B and outputs the read command READ(k-1) at a high level. The transmission gate 83 is turned on and the transmission gate 84 is turned off in response to the read command READ(k-1) at a high level and the inverted read command READ(k-1)B at a low level. The transmission gate 83 receives and outputs the flag signal S(k-1), and the latch circuit 85 latches and outputs the flag signal S(k-1).

Then, when the read command READ(k-1) is disabled to a low (logic 0) level, the inverter 81 inverts the read command READ(k-1) and outputs an inverted read command READ(k-1)B at a high (logic 1) level. Also, the inverter 82 again inverts the inverted read command READ(k-1)B and outputs the read command READ(k-1) at a low level. The transmission gate 83 is turned off and the transmission gate 84 is turned on in response to the read command READ(k-1) at a low level and the inverted read command READ(k-1)B at a high level. The transmission gate 84 receives the flag signal S(k-1) from the latch circuit 85 and outputs the flag signal S(k-1). The latch circuit 86 latches and outputs the flag signal S(k-1) output from the transmission gate 84.

Thereafter, when the read command READ(k) is enabled to a high (logic 1) level, the inverter 91 of the flag output unit 262 outputs an inverted read command READ(k)B at a low (logic 0) level. The transmission gate 93 is turned on in response to the read command READ(k) and the inverted read command READ(k)B, receives the flag signal S(k-1) from the latch circuit 86, and outputs the flag signal S(k-1). The latch circuit 94 latches and outputs the flag signal S(k-1) that was output from the transmission gate 93. The inverter 92 receives the flag signal S(k-1) from the latch circuit 94 and outputs the flag signal S(k-1) as the initial flag signal PS.

FIG. 8 is a detailed block diagram illustrating an inversion unit and a bypass unit according to some embodiments of the present invention as shown in FIG. 3. Referring to FIG. 8, the inversion unit 220 includes switches 221 and 228, first and second logic circuits 222 and 225, a comparison circuit 223, a selector 224, and NMOS transistors 226 and 227. The switches 221 and 228 are turned on or off in response to a control signal CTL and an inverted control signal CTLB. The switches 221 and 228 may preferably be implemented by transmission gates. The switch 221 receives and outputs input data FDOi(k) when turned on. Also, the first logic circuit 222 outputs an internal logic signal XOi (i=1 through 8) in response to initial input data PFDOi received from the controller 210 of FIG. 3 and the input data FDOi(k) received through the transmission gate 221. More particularly, the first logic circuit 222 determines whether each of the bits of the initial input data FDOi are toggled with respect to corresponding bits of the input data FDOi(k), and outputs the internal logic signal XOi according to the determined result. The comparison circuit 223 is enabled or disabled in response to the control signal CTL. The comparison circuit 223 outputs internal flag signals P and PB in response to the internal logic signal XOi when enabled. The selector 224 outputs any one of the internal flag signals P and PB as a flag signal S(k) in response to the initial flag signal PS and the inverted initial flag signal PSB.

The second logic circuit 225 is enabled or disabled in response to the control signal CTL. The second logic circuit 225 receives the input data FDOi(k) from the switch 221 when enabled, and inverts and outputs the input data FDOi(k) as an output data DOi(k) or outputs the input data FDOi(k) without inversion as the output data DOi(k) in response to the flag signal S(k). The switch 228 receives the output data DOi(k) from the second logic circuit 225 and outputs the output data DOi(k) when turned on.

The drain of the NMOS transistor 226 is connected to th