Data processor Number:6,738,894 from the United States Patent and Trademark Office (PTO) owispatent To obtain a correct vector address even if an interrupt occurs during erasing or programming of the data in a built-in ROM 18 by moving a part of a built-in RAM13 to a vector address area by a bus controller 27. Thereby, a microcomputer is prevented from running away and the safety of a system is improved at the time of on-board programming of the built-in ROM 18.<H processor, Data, Data, processor, 6738894.html, Patent, pto, 6738894

Title: Data processor

Abstract: To obtain a correct vector address even if an interrupt occurs during erasing or programming of the data in a built-in ROM 18 by moving a part of a built-in RAM13 to a vector address area by a bus controller 27. Thereby, a microcomputer is prevented from running away and the safety of a system is improved at the time of on-board programming of the built-in ROM 18.

Patent Number: 6,738,894 Issued on 05/18/2004 to Iwata

Inventors: Iwata; Katsumi (Kokubunzi, JP)
Assignee: Hitachi, Ltd. (Tokyo, JP)

Appl. No.: 09/655,465

Filed: September 5, 2000

Related U.S. Patent Documents


Application Number	Filing Date	Patent Number	Issue Date
594022	Jan., 1996	5881295

Foreign Application Priority Data


Feb 07, 1995 [JP]			7-42301
Dec 27, 1995 [JP]			7-353256

Current U.S. Class: 712/200 ; 711/103

Current International Class: G06F 13/00 (20060101); G06F 9/22 (20060101)

Field of Search: 712/200 714/15 711/103

References Cited [Referenced By]

U.S. Patent Documents


4872106	October 1989	Slater
5163148	November 1992	Walls
5410711	April 1995	Stewart
5539890	July 1996	Rahman
5581457	December 1996	Tsukahara
5603038	February 1997	Crump
5844843	December 1998	Matsubara
5854937	December 1998	Woodward
5881295	March 1999	Iwata

Foreign Patent Documents


63266698	Nov., 1988	JP
03-043836	Feb., 1991	JP
04014699	Jan., 1992	JP
4257030	Sep., 1992	JP
06180664	Jun., 1994	JP
07-261997	Oct., 1995	JP
08179993	Jul., 1996	JP

Primary Examiner: Coleman; Eric
Attorney, Agent or Firm: Loudermilk & Associates

Parent Case Text

This application is a continuation of App. Ser. No. 08/594,022 filed Jan. 29, 1996, now U.S. Pat. No. 5,881,295.

Claims

What is claimed is:

1. A single-chip data processor comprising: a central processing unit; an electrically erasable and programmable memory including: a first area storing a first vector address, and a second area storing an operation program which the central processing unit executes in a normal operation mode; a memory having an area storing a second vector address; and an interrupt controller providing an interrupt request to the central processing unit in response to an interrupt event, wherein the operation program in the second area is capable of erasing or programming in an erase or programming mode, and wherein, if the interrupt controller provides an interrupt request to the central processing unit during the normal operation mode, the first vector address stored in the first area is used to respond to the interrupt request, and wherein, if the electrically erasable and programmable memory is in an erase or programming mode, and if the interrupt controller provides the interrupt request to the central processing unit, then the second vector address in the area of the memory is used to respond to the interrupt request.

2. The data processor according to claim 1, wherein the central processing unit performs interrupt handling corresponding to the interrupt request based on the second vector address during the erase or programming mode of the electrically erasable and programmable memory.

3. The data processor according to claim 2, further comprising: a bus controller inactivating a selection signal of the electrically erasable and programmable memory and activating a selection signal of the memory when the electrically erasable and programmable memory is in the erase or programming mode, so that the second vector address is fetched by the central processing unit if the interrupt request occurs from the interrupt controller.

4. The data processor according to claim 3, wherein the bus controller includes an address conversion circuit converting a first address to a second address, wherein the first address is generated from the central processing unit responding to the interrupt request during the erase or programming mode of the electrically erasable and programmable memory and corresponds to the first vector address, wherein the second address corresponds to the second vector address.

5. The data processor according to claim 1, wherein the electrically erasable and programmable memory comprises a flash memory including memory cells each having a floating gate and a control gate.

6. The data processor according to claim 1, wherein the memory comprises a random access memory.

7. The data processor according to claim 1, further comprising: a control register having a first control bit having a first state and a second state, which is determined by the central processing unit, wherein the first state enables the electrically erasable and programmable memory to be erased and wherein the second state disables the electrically erasable and programmable memory to be erased.

8. The data processor according to claim 7, wherein the control register further has a second control bit having a first state and a second state, which is determined by the central processing unit, wherein the first state enables the electrically erasable and programmable memory to be programmed and wherein the second state disables the electrically erasable and programmable memory to be programmed.

9. A single chip data processor comprising: a central processing unit; a first electrically erasable and programmable memory operable in a normal mode and an erasing or programming mode, wherein the first electrically erasable and programmable memory is assigned to an address space which can be accessed by the central processing unit and has a first address area storing one or more vector addresses and a second address area storing one or more operation programs, wherein the central processing unit executes the one or more operation programs stored in the second address area in the normal mode; a second memory assigned to the address space which can be accessed by the central processing unit, the second memory having an address area storing one or more vector addresses; and an interrupt control circuit supplying an interrupt request to the central processing unit in response to an interrupt event; wherein, if the interrupt control circuit supplies an interrupt request to the central processing unit when the electrically erasable and programmable memory is operating in the normal mode, the one or more vector addresses stored in the first address area is used to respond to the interrupt request, and wherein, if the first electrically erasable and programmable memory is in the erasing or programming mode, and if the interrupt request is supplied from the interrupt control circuit, then the one or more vector addresses stored in the second memory is used to respond to the interrupt request.

10. The data processor according to claim 9, wherein the central processing unit performs interrupt handling corresponding to the interrupt request during the erase or programming mode of the first electrically erasable and programmable memory, based on the one or more vector addresses stored in the second memory.

11. The data processor according to claim 10, further comprising a bus controller inactivating a selection signal of the first electrically erasable and programmable memory and activating a selection signal of the second memory, when the first electrically erasable and programmable memory is in the erasing or programming mode, wherein the second memory is accessed if the interrupt request is supplied from the interrupt control circuit.

12. The data processor according to claim 11, wherein the bus controller includes an address conversion circuit converting a first address signal into a second address signal, wherein the first address signal is generated from the central processing unit responding to the interrupt request during the erasing or programming mode of the first electrically erasable and programmable memory, wherein the first address signal designates an address of the first address area in the first electrically erasable and programmable memory, and wherein the second address signal designates an address of the address area in the second memory.

13. The data processor according to claim 9, wherein the first electrically erasable and programmable memory comprises a flash memory having a plurality of memory cells each of which comprises a floating gate and a control gate.

14. The data processor according to claim 9, wherein the second memory comprises a random access memory.

15. A single chip data processor comprising: a central processing unit; a mode control circuit coupled to receive mode selection signals and setting an operation mode of the data processor in accordance with the mode selection signals; a first electrically erasable and programmable memory, assigned to an address space which can be accessed by the central processing unit, and having a first address area storing one or more vector addresses and a second address area storing one or more operation programs, wherein the central processing unit executes the one or more operation programs stored in the second address area in a normal mode set in accordance with the mode selection signals, wherein the first electrically erasable and programmable memory is erased or programmed when the first electrically erasable and programmable memory is in an erasing or a programming mode set in accordance with the mode selection signals; a second memory, assigned to the address space which can be accessed by the central processing unit, and having an address area storing one or more vector addresses; and an interrupt control circuit supplying an interrupt request to the central processing unit in response to an interrupt event; wherein, if the interrupt control circuit supplies an interrupt request to the central processing unit when the electrically erasable and programmable memory is in the normal mode set in accordance with the mode selection signals, the first address area storing one or more vector addresses is accessed to respond to the interrupt request, and wherein, if the first electrically erasable and programmable memory is in an erasing or a programing mode set in accordance with the mode selection signals, and if the interrupt request is supplied from the interrupt control circuit, then the address area storing the one or more vector addresses in the second memory is accessed.

16. The data processor according to claim 15, wherein the central processing unit performs interrupt handling corresponding to the interrupt request during the erase or programming mode of the first electrically erasable and programmable memory, based on the one or more vector address stored in the second memory.

17. The data processor according to claim 16, further comprising a bus controller inactivating a selection signal of the first electrically erasable and programmable memory and activating a selection signal of the second memory, when the first electrically erasable and programmable memory is in an erasing or a programming mode, wherein the second memory is accessed if the interrupt request is supplied from the interrupt control circuit.

18. The data processor according to claim 17, wherein the bus controller includes an address conversion circuit for converting a first address signal into a second address signal, wherein the first address signal is generated from the central processing unit responding to the interrupt request during the erasing or programming mode of the first electrically erasable and programmable memory, wherein the first address signal designates an address of the first address area in the first electrically erasable and programmable memory, and wherein the second address signal designates an address of the address area in the second memory.

19. The data processor according to claim 15, further comprising a register controlling an operation mode of the first electrically erasable and programmable memory, wherein the register comprises: a first control bit having a set state and a reset state, wherein the set state of the first control bit enables the central processing unit to erase one or more programs in the second area, and wherein the reset state of the first control bit disables the central processing unit from erasing one or more programs in the second area; and a second control bit having a set state and a reset state, wherein the set state of the second control bit enables the central processing unit to program one or more programs in the second area, and wherein the reset state of the second control bit disables the central processing unit from programming one or more programs in the second area.

20. The data processor according to claim 15, wherein the first electrically erasable and programmable memory comprises a flash memory having a plurality of memory cells each of which comprises a floating gate and a control gate.

21. The data processor according to claim 15, wherein the second memory comprises a random access memory.

Description

BACKGROUND OF THE INVENTION

The present invention relates to an on-board write art of a program memory built in a single-chip microcomputer serving as a data processor, particularly to an art to be effectively applied to a single-chip microcomputer provided with a flash-type electrically erasable and programmable read only memory (hereafter referred to as a flash-type EEPROM or a flash memory).

A single-chip microcomputer (also known as a microcomputer) serving as a data processor has a built-in program memory for storing an operation program. The single-chip microcomputer executes predetermined data processing specified in the operation program stored in the built-in program memory.

The program memory has been formed with a mask-type nonvolatile memory (hereafter referred to as a mask-type read-only memory or mask ROM) or an electrically programmable nonvolatile memory (hereafter referred to as an electrically programmable read-only memory or EPROM). In recent years, however, a flash-type electrically erasable and programmable read-only memory (hereafter referred to as a flash-type EEPROM or flash memory) has been applied to a program memory.

The flash memory allows written data to be electrically erased or electrically rewritten. Therefore, a microcomputer having a built-in flash memory as a program memory has the following advantages.

Cutover of a software program (application software) developed by a user generally tends to be delayed. Therefore, it is possible to assemble the hardware for a microcomputer-applied system before the cutover of a software program and then write a developed software program in a flash memory of a microcomputer. Thereby, it is possible to quickly ship the microcomputer-applied system.

Moreover, when specification-modified software or function-added software (upgraded software or version-up software) is developed for already shipped application system software, it is possible for a user to rewrite the shipped application system software to the above newly-developed software.

That is, in the case of a microcomputer having a built-in flash memory as a program memory, the microcomputer is assembled on a printed circuit board, mounting board, or system board and then, the processing for writing an operation program in the above flash memory can be performed. In this specification, the processing for programming data in a built-in flash memory after assembling a microcomputer having the built-in flash memory on a printed circuit board, mounting board, or system board is referred to as "on-board programming" and this programming mode is referred to as "on-board programming mode".

Several methods are available to the flash memory programming. These methods are roughly divided into the following two types.

(1) The first method is referred to as a user program mode or boot mode. This mode uses a method for branching the flow of program execution by a central processing unit (CPU) built in a microcomputer to the on-board programming and changing the data in a flash memory by the CPU.

(2) The second method is referred to as a programming mode using a ROM writer. This mode uses a method for changing the data in a flash memory by external means (ROM writer) by stopping a microcomputer.

Japanese Patent Laid-Open No. 180664/1994 discloses a system for handling trouble at the time of rewriting by moving a trouble handling program to another area when rewriting a flash memory.

SUMMARY OF THE INVENTION

In the case of the above first method, because the information stored in a built-in flash memory are subject to rewriting, programming control programs present in memories other than a flash memory such as a built-in RAM (random access memory) are executed by a central processing unit (CPU) to erase or program the data in the flash memory.

In the case of the above first method, original functions of a microcomputer are not lost under the erasing or programming state of the flash memory. Therefore, an interrupt to the central processing unit (CPU) erroneously occurs due to a signal input supplied from a unit outside of the microcomputer or an address error occurs while the programming control program is executed. Moreover, because an NMI (Non-Maskable Interrupt) cannot inhibit an interrupt, an unexpected NMI may occur while the data in the flash memory is programmed or erased according to the above first method. A similar state may occur if an interrupt other than the NMI is enabled.

In general, when an interrupt or address error occurs, the processing by a central processing unit is branched to an interrupt handling routine or exception handling routine. A vector address showing the head address of an interrupt handling routine or exception handling routine is used to branch the processing by the central processing unit to the interrupt handling routine or exception handling routine. When an interrupt occurs or exception handling occurs, the vector address of a relative interrupt or exception handling routine is obtained by the central processing unit. The obtained vector address is programmed in a program counter of the central processing unit and the program flow of the central processing unit jumps to an address indicated by the vector address to execute relative interrupt or exception handling.

It is clarified as the result of study by the present inventor that the following is a matter to be cautioned.

That is, a plurality of vector addresses are generally stored in the vector address storage area of a program memory. Even when a flash memory is used as a program memory, the same is applied to the above mentioned and thus, a plurality of vector addresses are stored in the vector address storage area of the flash memory.

However, if an interrupt occurs or exception handling occurs when a flash memory is used as a program memory and erasing or programming is executed for the flash memory in the user program mode or boot mode, a central processing unit cannot obtain a desired vector address stored in the vector address storage area of the flash memory.

That is, vector addresses are present in the program memory, though a rewrite control program for erasing or programming the data in the flash memory in the user program mode or boot mode is present in a memory (e.g. RAM) other than the flash memory. Therefore, no correct vector address can be obtained during erasing or programming for the flash memory serving as the program memory. As a result, it has been clarified that a microcomputer may run away or an application system may be damaged if an interrupt occurs or exception handling occurs in the user program mode or boot mode of a program memory. Moreover, if the microcomputer runs away and data is over-erased from or over-programmed in the flash memory, it may be impossible to reproduce the microcomputer-application system. It is general means to detect trouble such as a power-supply voltage drop by an interrupt such as an NMI.

It is regarded that erasing or programming for the flash memory includes erasing verify operation and programming verify operation.

In the case of a microcomputer having a built-in flash memory as a program memory, a user can program software in the built-in flash memory after assembling the hardware of an application system or rewrite the software stored in the built-in flash memory of a shipped applied system. Therefore, there are a lot of advantages in setting a flash memory in a microcomputer. However, it is found that occurrence of an interrupt or occurrence of exception handling during on-board programming in the user program mode or boot mode of a built-in flash memory may cause a microcomputer to run away or an application system to be damaged.

It is an object of the present invention to improve the safety of a system during on-board programming of a program memory.

It is another object of the present invention to provide a data processor including an electrically erasable and programmable non-volatile memory as a program memory and capable of preventing a microcomputer from running away and from being damaged even when an interrupt handling or exception handling is requested during on-board programming of the above program memory.

It is still another object of the present invention to provide a microcomputer which includes a flash memory as a program memory and can respond to a request for an interrupt handling or exception handling made during on-board programming or erasing of the program memory.

It is still another object of the present invention to provide a single-chip microcomputer which includes a flash memory as a program memory and is constituted so as to be able to obtain a vector address related to the interrupt handling or exception handling to which a central processing unit responds. When an request for an interrupt handling or exception handling is made during on-board programming or erasing of the program memory.

The above and other objects and novel features of the present invention will become more apparent from the description and accompanying drawings of this specification.

The outline of a typical invention among those disclosed in this application is briefly described below.

A data processor comprises an electrically erasable or programmable program memory (18), a central processing unit (12) accessible to the program memory (18), and malfunction exclusion means for excluding a malfunction due to occurrence of an interrupt or occurrence of exception handling while the data in the program memory is erased or programmed.

The malfunction exclusion means can include the following structures.

(1) As shown in FIG. 6, a first control logic circuit (G5) for excluding or invalidating an interrupt request or an exception handling request to the central processing unit (12) while the data in the program memory (18) is erased or programmed is provided in the data processor.

Therefore, because the first control logic circuit (G5) excludes or invalidates the interrupt request or exception handling request to the central processing unit (12) while the data in the program memory (18) is erased or programmed in the user program mode or boot mode, the central processing unit (12) does not execute the operation for obtaining a vector address corresponding to the interrupt request or exception handling request while the data in the program memory (18) is erased or programmed. This improves the safety of a system during on-board programming of the program memory (18). Thereby, it is possible to inhibit an unintended interrupt request from occurring.

(2) As shown in FIG. 7, a second control logic circuit (G6) for stopping erasing or programming of the data in the program memory (18) in response to an interrupt request or exception handling request to the central processing unit (12) while the data in the program memory (18) is erased or programmed in the user program mode or boot mode is provided in the data processor.

That is, while the data in the program memory (18) is erased or programmed, the second control logic circuit (G5) responds to an interrupt request or exception handling request to the central processing unit (12) and stops erasing or programming of the data in the program memory (18). Specifically, the second control logic circuit (G5) changes the data in the control bits such as an erasing control bit (32), a programming control bit (33), and a verifying control bit (34) of an operation control register set to the program memory (18) from active state to inactive state.

Therefore, when an interrupt request or exception handling request to the central processing unit (12) occurs while the data in the program memory (18) is erased or programmed, the second control logic circuit (G5) stops erasing or programming of the data in the program memory (18). Occurrence of the above interrupt may be caused by a programming error of a programming and erasing control program or an emergency such as an outage. Therefore, by stopping erasing or programming of the data in the program memory (18), over-erasing or over-programming of data in a flash memory can be prevented. Moreover, thereafter, the central processing unit (12) can obtain a vector address corresponding to the interrupt request or exception handling request from the program memory (18). Thus, improvement of the safety of the system during on-board programming of the program memory (18) is achieved.

(3) As shown in FIGS. 3 and 5, selected memory change means (G1, G2, and G4) for changing a memory selecting operation from the program memory (18) to another memory are provided in the data processor so that a predetermined area of a memory other than the program memory (18) such as a random access memory (13) can be accessed by inhibiting access to the vector address storage area of the program memory (18) when an interrupt request or exception handling request to the central processing unit (12) occurs while the data in the program memory (18) is erased or programmed. Moreover, the selected memory change means (G1, G2, and G4) can be set to a bus controller (27).

In this case, vector address data for interrupt handling or exception handling to be processed when an interrupt request or exception handling request to the central processing unit (12) occurs while the data in the program memory (18) is erased or programmed is previously stored in a predetermined area of a memory other than the program memory (18). Moreover, the vector address data stored in the predetermined storage area is set so as to indicate the head address of a predetermined interrupt handling routine or exception handling routine stored in another storage area of the memory other than the program memory (18).

(3.1) In the above Item (3), when an interrupt request or exception handling request to the central processing unit (12) occurs while the data in the program memory (18) is erased or programmed, the selected memory change means (G1 and G2) respond to detection of the access to the vector address storage area of the program memory (18) and in activates a selection signal of the program memory (18) Instead, the selected memory change means (G1 and G2) activate a selection signal of the memory (13) other than the program memory (18).

(3.2) In the above Item (3), when an interrupt request or exception handling request to the central processing unit (12) occurs while the data in the program memory (18) is erased or programmed, the selected memory change means (G4) responds to detection of the access to the vector address storage area of the program memory (18) and converts an address signal for accessing the vector address storage area of the program memory (18) into an address signal for accessing a predetermined storage area of a memory such as the random access memory (13) other than the program memory (18).

According to the structure shown in the above Item (3.1) or (3.2), the central processing unit (12) can obtain a vector address related to a relative interrupt handling routine or exception handling routine by accessing another area of the memory other than the program memory (18) even if an interrupt request or exception handling request to the central processing unit (12) occurs while the data in the program memory (18) is erased or programmed in the user program mode or boot mode. Therefore, over-erasing or over-programming of data in a flash memory can be prevented by using an NMI and thereby, notifying a microcomputer of an emergency such as drop of power supply voltage Vcc due to an outage and stopping erasing or programming of the data in the program memory (18). In this case, it is possible to protect a flash memory from an abnormal state such as over-erasing, over-programming, or intermediate state by executing the processing for recording a stop state of erasing or programming in an interrupt handling routine to an NMI. This achieves the improvement of the safety of a system during on-board programming of the program memory (18).

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the whole structure of the single-chip microcomputer of an embodiment of the present invention;

FIG. 2 is an illustration for explaining an address map when moving part of a built-in RAM included in the above microcomputer to a vector address area;

FIG. 3 is an illustration showing the structure of the main portion of the bus controller 27 in terms of the relation between the built-in ROM 18 and the built-in RAM 13 when address-converting a vector address storage area B-V of the built-in RAM 13 into a vector address storage area A-V of the flash memory 18;

FIG. 4 is an illustration for explaining an address map of another embodiment of the present invention;

FIG. 5 shows an address conversion circuit ACC serving as malfunction exclusion means set to the bus control circuit 27 in FIG. 1;

FIG. 6 shows the bus controller 27 including a gate G5 for ignoring all interrupts including an NMI (Non-Maskable Interrupt) during erasing or programming of data in a flash memory serving as the built-in ROM 18;

FIG. 7 shows the control logic circuit G6 serving as malfunction exclusion means for resetting the erasing control bit register, programming control bit register, and verifying control bit register of the built-in ROM 18 when a programming request occurs during erasing, programming, or verifying of the data in the built-in ROM 18;

FIG. 8 shows a circuit for generating a control signal CONT explained in FIG. 3 and a control signal CONT' explained in FIG. 5;

FIG. 9 shows the programming method of the flash memory 18 of the microcomputer 30 in FIG. 1 in terms of the relation between the PROM mode and the on-board programming mode described above;

FIG. 10 shows a further detailed address map of the present invention, in which areas for storing a vector address of an NMI (Non-Maskable Interrupt) and an NMI handling routine for the vector address in the normal mode (single-chip mode or external memory expansion mode) and the on-board loading mode of a flash memory are shown;

FIG. 11 shows an illustration for explaining the usage of an NMI (Non-Maskable Interrupt) in the on-board programming mode and a circuit for generating the NMI;

FIG. 12 shows a reloading flow to be executed between the start and the end of the on-board programming mode (example of the user program mode) of the flash memory 18;

FIG. 13 shows a cross section of a memory cell of the flash memory 18;

FIG. 14 shows thresholds of the erasing state and the programming state of a memory cell of the flash memory 18;

FIG. 15 shows the structure of a memory array of the flash memory 18;

FIG. 16 shows a voltage condition for erasing and programming data in a memory cell of the flash memory 18;

FIG. 17 shows a block diagram of the flash memory 18;

FIG. 18 shows the whole block diagram of the flash memory 18; and

FIG. 19 shows a control register of the flash memory 18.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 shows the single-chip microcomputer 30 serving as the data processor of the present invention. Though not restricted, the single-chip microcomputer 30 is formed on a semiconductor substrate (semiconductor chip) such as a single-crystal silicon substrate.

As shown in FIG. 1, the single-chip microcomputer 30, though not restricted, comprises an interrupt control circuit 10, a clock generation circuit 11, the central processing unit (CPU) 12, the built-in random access memory (RAM),internal RAM or on-chip RAM 13, a host interface circuit 14, a serial communication interface circuit 15 serving as a serial communication circuit, a 10-bit analog-to-digital conversion circuit (A-D converter) 16, an 8-bit digital-to-analog conversion circuit (D-A converter) 17, the built-in read-only memory (ROM), internal'ROM or on-chip ROM 18 serving as a program memory, a watchdog timer circuit 19, a 16-bit free-running timer circuit 20, an 8-bit timer circuit 21, a PWM timer circuit 22 used for pulse width modulation, and ports P1 to P9 used for inputting and outputting a plurality of signals or inputting/outputting a plurality of signals.

These circuit modules (10, 12 to 22, and P1 to P9) are connected by an address bus 24 and a data bus 26 so that the central processing unit 12 can access the circuit modules (12 to 22 and P1 to P9) by using the address bus 24 and data buses 25 and 26.

When the central processing unit 12 accesses any one of the circuit modules (12 to 22 and P1 to P9), it outputs an address signal for selecting the address assigned to a circuit module to be accessed to the address bus 24. In this case, when the data read mode is set, the circuit module to be accessed outputs data to the data buses 25 and 26 and the central processing unit 12 captures the data through the data bus 26. However, when the data write mode is set, the central processing unit 12 outputs desired data to the data buses 25 and 26 and the circuit module to be accessed captures the data through the data buses 25 and 26.

Then, functions of the circuit blocks (10 to 22) are described below.

The clock generator 11, though not restricted, comprises an oscillator for oscillating by using a crystal oscillator, a duty correction circuit for correcting the duty of pulses output from the oscillator, a clock divider for generating built-in peripheral-module clock signals for the built-in peripheral modules (12 to 22) by dividing a system clock signal output from the duty correction circuit, and a prescaler for generating an internal clock signal by dividing the built-in peripheral-module clock signal output from the clock divider. The circuit modules (10 and 12 to 22) are operated synchronously with a system clock with a predetermined frequency generated by the clock generator 11.

The CPU 12, though not restricted, comprises an instruction register (IR) for storing a defined instruction in a program to be processed, an instruction decoder (IDEC) for decoding an instruction stored in the instruction register, and an instruction executing section (IEXE) whose operation is controlled in accordance with a control signal output from the instruction decoder. The instruction executing section (IEXE) comprises an arithmetic and logic unit (ALU) for executing arithmetic operations and logic operations, 8-bits.sub.-- 16 general-purpose registers (R0 to R15), and a program counter (PC) for storing data related to the instruction address of an instruction to be next executed in a program. The data in the program counter (PC) is incremented whenever an instruction is executed by the instruction executing section (IEXE). The instruction executing section (IEXE) performs predetermined types of processing and controls operations of the built-in peripheral modules (12 to 22) by using a system clock output from the clock generator 11 as a time base. The instruction register (IR), instruction decoder (IDEC), instruction executing section (IEXE), arithmetic and logic unit (ALU), general-purpose registers (R0 to R15), and program counter (PC) are not illustrated in FIG. 1 in order to simplify the drawing.

One of the general-purpose registers is used as a stack pointer when an interrupt or exception occurs. That is, when the interrupt or exception occurs, the data stored in the general-purpose register at the point of that time is saved in, for example, a predetermined external memory. In this case, the stack point stores address data showing the address of the saved data. At the time of returning from interrupt handling or exception handling, the data in the general-purpose register which is saved in the external memory is recovered into the general-purpose register by using the address data stored in the stack pointer when the interrupt handling or exception handling is accepted. Moreover, when one unit from one leading edge to the next leading edge of the system clock is assumed as one state, a memory cycle or bus cycle of the CPU 12 comprises, for example, two or three states. In other words, the CPU 12 is designed so as to be able to access the built-in peripheral modules (12 to 22) at two or three periods of the system clock.

The built-in RAM 13, though not restricted, uses a static RAM having a storage capacity of 1K bytes. The built-in RAM 13 is connected to the CPU 12 by the address bus 24 and the data buses 25 and 26 respectively having an 8-bit width. As a result, the built-in RAM 13 makes it possible to input and output byte data (8-bit data) and word data (16-bit data) at one two-state memory access cycle.

The host interface circuit 14 has a parallel interface function of two channels of the CPU 12 and a host system and, though not restricted, comprises a 4-byte data register, a high-speed gate logic, and an interrupt request circuit. The circuit 14 can communicate with the host system through five control signals from the host system, four output signals to the host system, and the data bus 25 with an 8-bit width serving as a command or data input/output bus.

The serial communication interface circuit 15 is a module for performing serial data communication with other LSI and makes it possible to select between the communication in a start-stop synchronous mode and the communication in a clock synchronous mode. The circuit 15 allows designation of an operation mode, designation of a data format, and setting of a bit rate, and includes a plurality of control registers for transmission/reception control, a transmission/reception control circuit, and a bus interface.

The A-D converter 16, though not restricted, is used to convert an input analog signal into a digital signal according to the sequential conversion system and, though not restricted, makes it possible to select analog inputs of up to 8 channels.

The D-A converter 17 has a function for converting a digital signal input through the data bus 25 into an analog signal and includes various registers, an 8-bit D-A converting section, and a control circuit.

The watchdog timer 19 monitors a system when values of a timer counter in the watchdog timer 19 overflow without being rewritten due to runaway of a system, the timer 19 outputs a reset signal or an NMI (Non-Maskable Interrupt) request to the CPU 12. When this function is not used, the timer counter in the watchdog time 19 can also be used as an interval timer.

The 16-bit free-running timer 20, though not restricted, can generate two types of independent waveform outputs by basing on the 16-bit free-running counter and moreover, makes it possible to measure the width of an input pulse and the period of an external clock.

The 8-bit timer 21 is provided with two channels and moreover, provided with an 8-bit time constant register in addition to a timer counter for each channel. Thereby, the timer 21 can output a pulse signal with any duty ratio.

The PWM timer 22 is provided with two channels and with an 8-bit timer counter and an 8-bit duty register for each channel, and makes it possible to obtain a duty pulse of 0 to 100% according to a value set to the 8-bit duty register.

The interrupt control circuit 10 has a function for receiving an NMI (Non-Maskable Interrupt) and IRQ0 and IRQ2 which serve as external interrupt request signals and not-illustrated internal interrupt requests supplied from the peripheral modules 15 to 22 and performing types of processing in accordance with a predetermined priority sequence so that an interrupt and exception handling request signal IRQS is transmitted to the CPU 12 in accordance with the interrupt request handling result. The interrupt control circuit 10, though not illustrated in FIG. 1, is connected to the address bus 24 and the data bus 25 so that an internal register can be accessed by the CPU 12. Moreover, the NMI (Non-Maskable Interrupt) is regarded as an interrupt which cannot be masked. Therefore, when the interrupt control circuit 10 receives the NMI (Non-Maskable Interrupt), it executes the interrupt handling according to the NMI.

The built-in ROM 18 is referred to as a program memory for storing a program to be executed by the CPU 12. The built-in ROM 18, though not restricted, is connected to the CPU 12 by the address bus 24 and the data buses 25 and 26 respectively having an 8-bit width. As a result, the built-in ROM 18 can output byte data (8-bit data) and word data (16-bit data) at one two-state memory access cycle. As described above, the built-in ROM 18 comprises a flash-type electrically erasable and programmable read-only memory (hereafter referred to as a flash-type EEPROM or flash memory). A program stored in the flash memory as data can be programmed by setting a single-chip microcomputer to the on-board programming mode.

When the operation mode of the microcomputer 30 of this embodiment is set to the on-board programming mode, it is possible to program, erase, and verify a program (data) in the built-in ROM 18. The on-board programming mode includes two types of operation modes (boot mode and user program mode) . The boot mode is referred to as a first on-board programming mode and the user program mode is referred to as a second on-board programming mode.

The operation mode of the microcomputer 30 is discriminated by a mode setting circuit MC and the mode setting circuit MC sets one of mode setting signals MS0 to MS4 to high level. The high-level mode setting signal showing a designated operation mode is supplied to, for example, circuits of the central processing unit CPU 12 and the bus controller 27. The mode setting circuit MC judges whether signal voltages of mode signals MDS0 to MDS2 supplied to mode setting terminals MD0 to MD2 and a high voltage Vp supplied to a high-voltage supply terminal Vpp are combined as predetermined and sets the operation mode of the microcomputer 30 to a desired operation mode. Thereby, the operation mode of the microcomputer 30 includes not only the boot mode and the user program mode but also the PROM mode, single chip mode, and external memory extension mode to be mentioned later. The single chip mode is a mode for constituting a microcomputer system by using address spaces of a built-in RAM and a built-in ROM. The external memory extension mode is a mode for constituting a microcomputer system by using not only the address spaces of the built-in RAM and ROM but also those of other memories. For example, when a voltage of 12 V is supplied to the mode setting terminal MD2 and the high-voltage supply terminal Vpp, the operation of the microcomputer 30 is set to the boot mode. That is, the mode setting signal MS0 is set to high level. In this case, a voltage of 0 or 5 V is supplied to the mode setting terminals MD1 and MD0 respectively in accordance with the address-space setting mode of the microcomputer 30. When a voltage of 12 V is supplied to the high-voltage supply terminal Vpp, the operation mode of the microcomputer 30 is set to the user program mode. That is, the mode setting signal MS1 is set to high level. In this case, a voltage of 0 or 5 V is supplied to the mode setting terminals MD0 to MD2 respectively in accordance with the address-space setting mode of the microcomputer 30. Though not restricted, the high level of the mode setting signal MS2 shows the above PROM mode, the high level of the mode setting signal MS3 shows the above single chip mode, and the high level of the mode setting signal MS4 shows the above external memory extension mode.

To use the boot mode, the programming and erasing user program (rewrite control program) of the flash memory 18 and programming data are previously prepared in a not-illustrated host system. When the boot mode is set, the boot program previously programmed in a boot ROM is started after resetting is canceled. Then, the low-level period of data transmitted from the host system is measured by the serial communication interface circuit 15, thereby the bit rate of the data transmitted from the host system is calculated, and the value of the bit rate register of the serial communication interface circuit 15 is determined. Then, the host system transfers the data constituting the rewrite control program. The data for the rewrite control program received by the serial communication interface circuit 15 is stored in the built-in RAM 13. After programming of the rewrite control program is completed, the processing of the boot program is branched to the head address of the rewrite control program of the built-in RAM 13. Thereby, the rewrite control program programmed in the built-in RAM 13 is executed by the CPU 12 and programming or erasing of the data in the flash memory is executed. The above boot ROM comprises a nonvolatile memory circuit such as a mask ROM and the data stored in the ROM is not erased even if the power supply potential lowers.

In the user program mode, programming or erasing of the data in the flash memory 18 can be made by the programming and erasing user program (rewrite control program) of the flash memory 18. In this case, high-voltage supply means for supplying a high voltage and data supply means for supplying rewrite data are provided on a mounting board. Then, the rewrite control program is stored in the flash memory 18 or a part of the program area of other memory (external memory). The CPU 12 stores the rewrite control program in the built-in RAM 13 in response to setting of the user program mode and on-board rewriting of the flash memory is performed by the CPU 12 for executing the rewrite control program.

It is possible to prepare not only the on-board programming mode but also the PROM mode as the erasing or programming mode of the flash memory 18 serving as a built-in ROM. The RPOM mode is a mode for making it possible to program the program data in the flash memory 18 by using a general-purpose PROM writer. The PROM mode is set by, for example, supplying the mode setting signals MDS0 to MDS2 at the low level "0" to all of the mode setting terminals MD0 to MD2.

If an interrupt request or exception handling request occurs during erasing or programming of the data in the flash memory 18 in the user program mode or boot mode when a vector address is present in the flash memory 18 serving as a built-in ROM, the CPU 12 cannot obtain a correct vector address. This is because the data in the built-in ROM 18 is being erased or programmed and thereby, the CPU 12 cannot access the vector address storage area of the flash memory 18. Thus, a microcomputer may run away as described above.

Therefore, this embodiment is constituted so that a part of the storage area (address area) of the built-in RAM 13 is moved to the vector address storage area of the flash memory 18 while the data in the flash memory 18 is erased or programmed in the user program mode or boot mode. That is, the address of the vector address storage area of the flash memory 18 is moved to the address of a part of the storage area of the built-in RAM 13 while the data in the flash memory 18 is erased or programmed. Thereby, an address signal for fetching a vector address generated during erasing or programming of the data in the flash memory 18 accesses a part of the storage area of the built-in RAM 13. Therefore, it is possible to prevent a microcomputer from running away by previously storing necessary addresses in a part of the storage area of the built-in RAM 13 so that a correct vector can be obtained. In other words, the built-in RAM 13 of this embodiment is used to substitute for the vector address storage area stored in the flash memory 18 while the data in the built-in. ROM 18 is erased or programmed in the user program mode or boot mode. In this case, available addresses are previously programmed in a part of the storage area of the built-in RAM 13 and thereafter, execution of a program for erasing or programming data in the built-in ROM 18 is started.

FIG. 2 shows the first embodiment of the address map according to the present invention including the vector address storage area B-V of the built-in RAM 13 used to erase or program the data in a flash memory serving as the built-in ROM 18.

An address space controlled by the CPU 12, in other words, an address space which can be accessed by the CPU 12, though not restricted, has 64K bytes (H'0000 to H'FFFF). That is, the address bus 24 has 16 bits.

The address area A of an address space assigned to the built-in ROM 18 has 32K bytes (H'0000 to H'7FFF). In the address area A, the vector address storage area A-V for storing address data related to a vector address has 256 bytes (H'0000 to H'00FF).

An address area B of the address space assigned to the built-in RAM 13 has 1K bytes (H'FC00 to H'FFFF). The address area B includes the address area B-V as shown in FIG. 2. The address area B-V serves as an area for substituting for the vector address storage area A-V in order to safely perform on-board programming of the built-in ROM 18 and, for example, 256 bytes (H'FC00 to H'FCFF) are assigned to the area B-V. Therefore, the vector address storage area B-V stores one or more vector addresses used when an interrupt request or exception handling request occurs in the on-board programming mode (user program mode) of the built-in ROM 18.

Even if the CPU 12 reads the vector address area A-V when the CPU 12 handles an interrupt request generated during erasing or programming of the data in the flash memory 18 in the user program mode or boot mode, the vector address storage area B-V is accessed because the addresses (H'FC00 to H'FCFF) assigned to the vector address storage area B-V are apparently moved to the vector address storage area A-V as described above. Thereby, a correct vector address is obtained from the vector address storage area B-V during erasing or programming of data in a flash memory serving as the built-in ROM 18. Therefore, the CPU 12 can correctly perform desired interrupt handling and exception handling correspondingly to an interrupt request and exception handling request even during erasing or programming of the data in the flash memory 18.

To realize the substitution for the above vector address area, it is necessary that the vector address storage area B-V of the built-in RAM 13 is accessed by the bus controller 27 so that the contents of the area B-V (predetermined vector address data) are read when a vector address signal is output from the CPU 12.

That is, when the CPU 12 generates an address signal for reading the vector address storage area A-V of the flash memory 18 at the time of interrupt handling during erasing or programming of data in a flash memory serving as the built-in ROM 18 in the user program mode or boot mode, it is necessary for the bus controller 27 to control a module selection signal as shown below. That is, the bus controller 27 inactivates a module selection signal of the built-in ROM 18, which should originally be activated and instead, activates a module selection signal of the built-in RAM 13 and performs control so that the vector address storage area B-V of the built-in RAM 13 is read. Specifically, it is necessary to set the control circuits (G1, G2, and G3) shown in FIG. 3 to the bus controller 27 shown in FIG. 1.

FIG. 3 shows a structure of main portion of the bus controller 27 when address-converting the vector address storage area B-V of the built-in RAM 13 into the vector address storage area A-V of the flash memory 18 in terms of the relation between the built-in ROM 18 and the built-in RAM 13.

The bus controller 27 includes a built-in ROM selection circuit 29 for selecting the built-in ROM 18, a built-in RAM selection circuit 28, and gates G1 to G3 serving as control logic circuits (malfunction exclusion means). The built-in ROM selection circuit 29 outputs an output signal A at the high level "1" when an address signal showing the address of the built-in ROM 18 is present on the address bus 24. The built-in RAM selection circuit 28 outputs an output signal B at the high level "1" when an address signal showing the vector address storage area A-V of the built-in ROM 18 is present on the address bus 24 and an output signal C at the high level "1" when an address signal showing the address of the built-in RAM 13 is present on the address bus 24. The gate G1 ANDs the inversion signal of the control signal CONT to be set to high level during erasing or programming of the data in the built-in ROM 18 in the user program mode or boot mode and under vector fetch with the output signal A and asserts a selection signal SEL1 serving as a module selection signal of the built-in ROM 18 from the low level "0" to the high level "1" when the built-in ROM 18 should be selected. The gate G2 ANDs the control signal CONT with the output signal B and outputs an output signal D at the high level "1" when these signals are set to the high level "1". The gate G3 receives the output signals C and D and asserts a selection signal SEL2 serving as a module selection signal of the built-in RAM 18 from the low level "0" to the high level "1" when the output signal C or D is set to the high level "1".

Addresses A14 to A0 (15 bits) are input to the built-in ROM 18 so that the built-in ROM (32K bytes) 18 can be accessed and addresses A9 to A0 (10 bits) are input to the built-in RAM 13 from the CPU so that the built-in RAM (1K bytes) can be accessed.

The built-in ROM selection circuit 29 receives an address A15 (only one bit) from the CPU 12 through the address bus 24. The output signal A is set to high level when the address A15 is low-level, that is, when addresses A15 to A0 output from the CPU 12 are set to "0xxx xxxx xxxx xxxx" (0 represents low level and x represents logic indetermination) and "0" or "1" is acceptable. That is, when an address signal for accessing the built-in ROM 18 is output onto the address bus 24, the output signal A becomes high-level.

The built-in RAM selection circuit 28 receives the addresses A15 to A8 from the CPU 12 through the address bus 24. When the addresses A15 to A0 output from the CPU 12 are set to "0000 0000 xxxx xxxx", the output signal B becomes high-level. That is, the output signal B is set to high level when an address signal for accessing the vector address storage area A-V of the built-in ROM 18 is output onto the address bus 24.

However, when the address signal is output onto the address bus 24 and the addresses A15 to A1 output from the CPU 12 are set to "1111 1100 xxxx xxxx", the output signal C becomes high-level. That is, the output signal C is set to high level when an address signal for accessing the built-in RAM 13 is output onto the address bus 24.

A high voltage is supplied to the built-in ROM 18 through a predetermined external terminal Vpp for erasing or programming. When the supplied high voltage is detected and a signal showing the vector fetch state is asserted by the CPU 12, the control signal CONT becomes high-level. That is, while the data in the built-in ROM 18 is erased or programmed and under vector fetch, the control signal CONT becomes high-level. The control signal CONT can be generated by a logic circuit constituted so as to be able to judge whether a high voltage is supplied through the predetermined external terminal Vpp and whether the CPU 12 is under the vector fetch state.

The gate G1 for obtaining the AND logic between the output signal A of the built-in ROM selection circuit 29 and the control signal CONT is arranged at the rear stage of the built-in ROM selection circuit 29 so that the built-in ROM 18 is selected when the selection signal SEL1 output from the gate G1 is set to high level. Moreover, the gate G2 for obtaining the AND logic between the output signal B of the built-in RAM selection circuit 28 and the control signal CONT and the gate G3 for obtaining the OR logic between the output logic of the gate G2 and the output signal C of the built-in RAM selection circuit 28 are used so that the built-in RAM 13 is selected when the selection signal SEL2 output from the gate G3 is set to high level. Therefore, when the addresses H'FC00 to H'FCFF are accessed, the selection signal SEL1 is set to low level and thereby, selection of the built-in ROM 18 is inhibited but instead, the selection signal SEL2 is set to high level and thereby the built-in RAM 13 is selected. That is, a vector address on the built-in ROM 18 is read while the data in the built-in ROM 18 is erased or programmed.

Moreover, in this case, it is assumed that the addresses A9 to A0 for designating the vector address storage area A-V of the built-in ROM 18 coincide with the addresses A9 to A0 of the vector address storage area B-V of the built-in RAM 13. Therefore, if the addresses A9 to A0 for designating the vector address storage area A-V of the built-in ROM 18 do not coincide with the addresses A9 to A0 of the vector address storage area B-V of the built-in RAM 13, it is necessary to design an address conversion circuit so that the address conversion function of the address conversion circuit operates when the output si