Title: Data storage system having dummy printed circuit boards
Abstract: A method and system for producing a data storage system for transferring data between a host computer/server and a bank of disk drives through a system interface. The system interface has a plurality of first directors, a plurality of second directors, and a global memory. The method includes: providing a backplane having slots adapted to have plugged therein a plurality of printed circuit board. The printed circuit boards include: a plurality of first director boards having the first directors; a plurality of second printed circuit boards having the second directors; a plurality of memory printed circuit boards providing the global memory; a plurality of dummy first director boards having first jumpers; a plurality of dummy second director boards having second jumpers; a plurality of dummy memory boards having third jumpers. The method includes wiring the backplane to effect a connection among the first, second and third jumpers to interconnect the first plurality of director to the host computer/server, the plurality of second plurality of directors to the bank of disk drives and the global memory to the first plurality of directors and to the second plurality of director. The method and system allows the same wired backplane to be used with systems having a different number of memory and director boards and still enable dual-write and redundancy to the global memory.
Patent Number: 6,877,061 Issued on 04/05/2005 to Thibault, et al.
| Inventors:
|
Thibault; Robert A. (Westboro, MA);
Castel; Daniel (Boston, MA);
Gallagher; Brian (Southboro, MA);
Wilson; Paul C. (Mendon, MA);
Walton; John K. (Mendon, MA);
MacLellan; Christopher S. (Walpole, MA)
|
| Assignee:
|
EMC Corporation (Hopkinton, MA)
|
| Appl. No.:
|
112598 |
| Filed:
|
March 28, 2002 |
| Current U.S. Class: |
710/312; 710/305; 710/313; 710/316; 710/104; 710/300 |
| Intern'l Class: |
G06F 013//00; G06F 013//14; H05K 007//10 |
| Field of Search: |
710/305-306,308-317,7-11,31-39,111-119,4-5
|
References Cited [Referenced By]
U.S. Patent Documents
| 950579 | Mar., 1910 | Seitz.
| |
| 4575780 | Mar., 1986 | Brombal et al.
| |
| 5212768 | May., 1993 | Itsuki et al. | 706/50.
|
| 5214768 | May., 1993 | Martin et al. | 711/114.
|
| 5261115 | Nov., 1993 | Saunders et al. | 710/104.
|
| 5819054 | Oct., 1998 | Ninomiya et al. | 712/3.
|
| 5903911 | May., 1999 | Gaskins | 711/141.
|
| 5943287 | Aug., 1999 | Walton | 365/230.
|
| 6058451 | May., 2000 | Bermingham et al. | 711/106.
|
| 6289398 | Sep., 2001 | Stallmo et al. | 710/5.
|
| 6295571 | Sep., 2001 | Scardamalia et al. | 710/308.
|
| Foreign Patent Documents |
| 950 579 | Feb., 1964 | GB.
| |
| 2258770 | Feb., 1993 | GB.
| |
| 2366425 | Mar., 2002 | GB.
| |
Other References
International Search Report from PCT/US03/09112 dated Apr. 7, 2004.
U.S. Appl. No. 10/109,583, filed Mar. 28, 2002.
|
Primary Examiner: Myers; Paul R.
Assistant Examiner: Phan; Raymond N
Parent Case Text
RELATED APPLICATIONS
This application is a continuation-in-part of co-pending patent application
Ser. No. 09/540,828, filed Mar. 31, 2000, entitled "Data Storage System
Having Separate Data Transfer Section And Message Network" inventors Yuval
Ofek et al. and a continuation-in-part of co-pending patent application
Ser. No. 09/606,730 filed Jun. 29, 2000 which is a continuation of
co-pending patent application Ser. No. 09/540,828, filed Mar. 31, 2000,
entitled "Data Storage System Having Separate Data Transfer Section And
Message Network" inventors Yuval Ofek et al. This application claims the
benefit of the filing dates of such co-pending applications under 35
U.S.C. 120.
Claims
What is claimed is:
1. A method for providing a data storage system for transferring data
between a host computer/server and a bank of disk drives through a system
interface, such system interface having a plurality of first directors, a
plurality of second directors, and a global memory, comprising:
providing a backplane having slots adapted to have plugged therein a
plurality of printed circuit board, such printed circuit boards
comprising:
a plurality of first director boards having the first directors;
a plurality of second printed circuit boards having the second directors;
a plurality of memory printed circuit boards providing the global memory;
a plurality of dummy first director boards having first jumpers;
a plurality of dummy second director boards having second jumpers;
a plurality of dummy memory boards having third jumpers;
wiring the backplane to effect a connection among the first, second and
third jumpers to interconnect the first plurality of director to the host
computer/server, the plurality of second plurality of directors to the
bank of disk drives and the global memory to the first plurality of
directors and to the second plurality of director; and
wherein each one of the memory boards has: a common memory array having a
pair of redundant data/control ports; and, a pair of logic networks each
one coupled to a corresponding one of the pair of data/control ports; and
wherein the printed circuit board is wired to effect a connection with the
jumpers to enable a pair of the first directors to be coupled to the pair
of logic networks and a pair of the second directors to be coupled to the
pair of logic networks.
2. The method recited in claim 1 wherein the printed circuit board is wired
to effect a connection with the jumpers to connect one of the first
directors the memory arrays of a pair of the memory boards.
3. The method recited in claim 2 including providing each one of the
directors on a different printed circuit board and wherein the backplane
is wired and connected to the jumpers to connect each one of the pair of
logic networks to one of the first directors and one of the second
directors.
4. A data storage system for transferring data between a host
computer/server and a bank of disk drives through a system interface, such
system interface having a plurality of first directors, a plurality of
second directors, and a global memory, comprising:
a backplane having slots adapted to have plugged therein a plurality of
printed circuit board, such printed circuit boards comprising:
a plurality of first director boards having the first directors;
a plurality of second printed circuit boards having the second directors;
a plurality of memory printed circuit boards providing the global memory;
a plurality of dummy first director boards having first jumpers;
a plurality of dummy second director boards having second jumpers;
a plurality of dummy memory boards having third jumpers; wherein the
backplane is wired to effect a connection among the first, second and
third jumpers to interconnect the first plurality of director to the host
computer/server, the plurality of second plurality of directors to the
bank of disk drives and the global memory to the first plurality of
directors and to the second plurality of director; and
wherein each one of the memory boards has: a common memory array having a
pair of redundant data/control ports; and, a pair of logic networks each
one coupled to a corresponding one of the pair of data/control ports; and
wherein the printed circuit board is wired to effect a connection with the
jumpers to enable a pair of the first directors to be coupled to the pair
of logic networks and a pair of the second directors to be coupled to the
pair of logic networks.
5. The system recited in claim 4 wherein the printed circuit board is wired
to effect a connection with the jumpers to connect one of the first
directors the memory arrays of a pair of the memory boards.
6. The system recited in claim 5 wherein each one of the directors is on a
different printed circuit board and wherein the backplane is wired and
connected to the jumpers to connect each one of the pair of logic networks
to one of the first directors and one of the second directors.
7. The system recited in claim 6 wherein the wired backplane and
interconnected jumpers provide separate point-to-point data paths between
each one of the directors arid the global memory.
Description
INCORPORATION BY REFERENCE
This application incorporates by reference, in their entirety, the
following co-pending patent applications all assigned to the same assignee
as the present invention:
FILING SERIAL
INVENTORS DATE NO. TITLE
Yuval Ofek et al. Mar. 31, 2000 09/540,828 Data Storage System
Having Separate Data
Transfer Section And
Message Network
Paul C. Wilson Jun. 29, 2000 09/606,730 Data Storage System
et al. Having Point-To-Point
Configuration
John K. Walton Jan. 22, 2002 10/054,241 Data Storage System
et al. (Divisional of
09/223,519 filed
Dec. 30, 1998)
Christopher S. Dec. 21, 2000 09/745,859 Data Storage System
MacLellan et al. Having Plural Fault
Domains
John K. Walton May 17, 2001 09/859,659 Data Storage System
Having No-Operation
Command
TECHNICAL FIELD
This invention relates generally to data storage systems, and more
particularly to data storage systems having redundancy arrangements to
protect against total system failure in the event of a failure in a
component or subassembly of the storage system.
BACKGROUND
As is known in the art, large host computers and servers (collectively
referred to herein as "host computer/servers") require large capacity data
storage systems. These large computer/servers generally includes data
processors, which perform many operations on data introduced to the host
computer/server through peripherals including the data storage system. The
results of these operations are output to peripherals, including the
storage system.
One type of data storage system is a magnetic disk storage system. Here a
bank of disk drives and the host computer/server are coupled together
through an interface. The interface includes "front end" or host
computer/server controllers (or directors) and "back-end" or disk
controllers (or directors). The interface operates the controllers (or
directors) in such a way that they are transparent to the host
computer/server. That is, data is stored in, and retrieved from, the bank
of disk drives in such a way that the host computer/server merely thinks
it is operating with its own local disk drive. One such system is
described in U.S. Pat. No. 5,206,939, entitled "System and Method for Disk
Mapping and Data Retrieval", inventors Moshe Yanai, Natan Vishlitzky,
Bruno Alterescu and Daniel Castel, issued Apr. 27, 1993, and assigned to
the same assignee as the present invention.
As described in such U.S. Patent, the interface may also include, in
addition to the host computer/server controllers (or directors) and disk
controllers (or directors), addressable cache memories. The cache memory
is a semiconductor memory and is provided to rapidly store data from the
host computer/server before storage in the disk drives, and, on the other
hand, store data from the disk drives prior to being sent to the host
computer/server. The cache memory being a semiconductor memory, as
distinguished from a magnetic memory as in the case of the disk drives, is
much faster than the disk drives in reading and writing data.
The host computer/server controllers, disk controllers and cache memory are
interconnected through a backplane printed circuit board. More
particularly, disk controllers are mounted on disk controller printed
circuit boards. The host computer/server controllers are mounted on host
computer/server controller printed circuit boards. And, cache memories are
mounted on cache memory printed circuit boards. The disk directors, host
computer/server directors, and cache memory printed circuit boards plug
into the backplane printed circuit board. In order to provide data
integrity in case of a failure in a director, the backplane printed
circuit board has a pair of buses. One set the disk directors is connected
to one bus and another set of the disk directors is connected to the other
bus. Likewise, one set the host computer/server directors is connected to
one bus and another set of the host computer/server directors is directors
connected to the other bus. The cache memories are connected to both
buses. Each one of the buses provides data, address and control
information.
The arrangement is shown schematically in FIG. 1. Thus, the use of two
buses B1, B2 provides a degree of redundancy to protect against a total
system failure in the event that the controllers or disk drives connected
to one bus, fail. Further, the use of two buses increases the data
transfer bandwidth of the system compared to a system having a single bus.
Thus, in operation, when the host computer/server 12 wishes to store data,
the host computer 12 issues a write request to one of the front-end
directors 14 (i.e., host computer/server directors) to perform a write
command. One of the front-end directors 14 replies to the request and asks
the host computer 12 for the data. After the request has passed to the
requesting one of the front-end directors 14, the director 14 determines
the size of the data and reserves space in the cache memory 18 to store
the request. The front-end director 14 then produces control signals on
one of the address memory busses B1, B2 connected to such front-end
director 14 to enable the transfer to the cache memory 18. The host
computer/server 12 then transfers the data to the front-end director 14.
The front-end director 14 then advises the host computer/server 12 that
the transfer is complete. The front-end director 14 looks up in a Table,
not shown, stored in the cache memory 18 to determine which one of the
back-end directors 20 (i.e., disk directors) is to handle this request.
The Table maps the host computer/server 12 addresses into an address in
the bank 14 of disk drives. The front-end director 14 then puts a
notification in a "mail box" (not shown and stored in the cache memory 18)
for the back-end director 20, which is to handle the request, the amount
of the data and the disk address for the data. Other back-end directors 20
poll the cache memory 18 when they are idle to check their "mail boxes".
If the polled "mail box" indicates a transfer is to be made, the back-end
director 20 processes the request, addresses the disk drive in the bank
22, reads the data from the cache memory 18 and writes it into the
addresses of a disk drive in the bank 22.
When data is to be read from a disk drive in bank 22 to the host
computer/server 12 the system operates in a reciprocal manner. More
particularly, during a read operation, a read request is instituted by the
host computer/server 12 for data at specified memory locations (i.e., a
requested data block). One of the front-end directors 14 receives the read
request and examines the cache memory 18 to determine whether the
requested data block is stored in the cache memory 18. If the requested
data block is in the cache memory 18, the requested data block is read
from the cache memory 18 and is sent to the host computer/server 12. If
the front-end director 14 determines that the requested data block is not
in the cache memory 18 (i.e., a so-called "cache miss") and the director
14 writes a note in the cache memory 18 (i.e., the "mail box") that it
needs to receive the requested data block. The back-end directors 20 poll
the cache memory 18 to determine whether there is an action to be taken
(i.e., a read operation of the requested block of data). The one of the
back-end directors 20 which poll the cache memory 18 mail box and detects
a read operation reads the requested data block and initiates storage of
such requested data block stored in the cache memory 18. When the storage
is completely written into the cache memory 18, a read complete indication
is placed in the "mail box" in the cache memory 18. It is to be noted that
the front-end directors 14 are polling the cache memory 18 for read
complete indications. When one of the polling front-end directors 14
detects a read complete indication, such front-end director 14 completes
the transfer of the requested data which is now stored in the cache memory
18 to the host computer/server 12.
The use of mailboxes and polling requires time to transfer data between the
host computer/server 12 and the bank 22 of disk drives thus reducing the
operating bandwidth of the interface.
SUMMARY OF THE INVENTION
In accordance with one feature of the invention, a data storage system is
provided for transferring data between a host computer/server and a bank
of disk drives through a system interface. The system interface includes:
a plurality of first directors coupled to the host computer/server; a
plurality of second directors coupled to the bank of disk drives; and, a
cache memory. The cache memory includes: a common memory array having a
pair of redundant data/control ports; and, a pair of logic networks each
one coupled to a corresponding one of the pair of data/control ports.
There are separate point-to-point data paths between each one of the
directors and the cache memory. A pair of the first directors are adapted
for coupling to the pair of logic networks of the cache memory.
In one embodiment, each one of the first directors is on a different
printed circuit board.
In accordance with another feature of the invention, a data storage system
is provided for transferring data between a host computer/server and a
bank of disk drives through a system interface. The system interface
includes: a plurality of first directors coupled to the host
computer/server; a plurality of second directors coupled to the bank of
disk drives; and a cache memory. The cache memory has: a common memory
array having a pair of redundant data/control ports; and a pair of logic
networks each one coupled to a corresponding one of the pair of
data/control ports. There are separate point-to-point data paths between
each one of the directors and the global cache memory. A pair of the
second directors are adapted for coupling to the pair of logic networks.
In one embodiment, each one of the pair of second directors is on a
different printed circuit board.
In accordance with still another feature of the invention, a data storage
system is provided for transferring data between a host computer/server
and a bank of disk drives through a system interface. The interface
includes: a plurality of first directors coupled to the host
computer/server; a plurality of second directors coupled to the bank of
disk drives; and a cache memory. The cache memory has a pair of memory
boards, each memory board having a memory array. There are separate
point-to-point data paths between each one of the directors and the global
cache memory. One of the first directors is adapted for coupling to the
memory arrays of the pair of memory boards.
In one embodiment, one of the second directors is adapted for coupling to
the memory arrays of the pair of memory boards.
In one embodiment, each one of the memory boards has: a common memory array
having a pair of redundant data/control ports; and, a pair of logic
networks each one coupled to a corresponding one of the pair of
data/control ports. The printed circuit board is wired to effect a
connection with jumpers to enable a pair of the first directors to be
coupled to the pair of logic networks and a pair of the second directors
to be coupled to the pair of logic networks.
In one embodiment, the printed circuit board is wired to effect a
connection with the jumpers to connect one of the first directors the
memory arrays of a pair of the memory boards.
In one embodiment, the method includes providing each one of the directors
on a different printed circuit board. The backplane is wired and connected
to the jumpers to connect each one of the pair of logic networks to one of
the first directors and one of the second directors.
The details of one or more embodiments of the invention are set forth in
the accompanying drawings and the description below. Other features,
objects, and advantages of the invention will be apparent from the
description and drawings, and from the claims.
DESCRIPTION OF DRAWINGS
These and other features of the invention will become more readily apparent
from the following detailed description when read together with the
accompanying drawings, in which:
FIG. 1 is a block diagram of a data storage system according to the PRIOR
ART;
FIG. 2 is a block diagram of a data storage system according to the
invention;
FIG. 3 is a sketch of an electrical cabinet storing a system interface used
in the data storage system of FIG. 2;
FIG. 4 is a diagramatical, isometric sketch showing printed circuit boards
providing the system interface of the data storage system of FIG. 2;
FIG. 5 is a block diagram of the system interface used in the data storage
system of FIG. 2;
FIG. 6 is a diagram of an exemplary global cache memory board used in the
system interface of FIG. 2;
FIG. 6A is a diagram showing an exemplary one of the memory printed circuit
boards used in the system of FIG. 2;
FIG. 7 is a diagram showing a pair of front-end director boards coupled
between a pair of host processors and global cache memory boards and a
pair of front-end director boards coupled between a pair of disk drives
and global cache memory boards used in the system interface of the system
of FIG. 2;
FIG. 8 is an elevation view of a backplane used in the system of FIG. 2,
such backplane having slots adapted to receive front-end director printed
circuit boards, back-end director printed circuit boards and memory
boards;
FIG. 9 is an elevation view of a backplane used in the system of FIG. 2,
such backplane having slots adapted to receive front-end director printed
circuit boards, back-end director printed circuit boards, memory boards
and dummy front-end director printed circuit boards, dummy back-end
director printed circuit boards, dummy memory boards, such dummy printed
circuit boards having jumpers to enable the same backplane to be used with
a fully populated system having all of the memory boards and directors in
FIG. 2 and a de-populated system having only a portion of the all of the
memory boards and directors in FIG. 2;
FIG. 10 shows the dummy memory boards used in the de-populated system;
FIG. 11 shows the dummy director boards used in the de-populated system;
FIG. 12 is a diagram showing an exemplary one of the memory printed circuit
boards used in the de-populated system;
FIG. 13 is a diagram showing a pair of front-end director boards coupled
between a pair of host processors and global cache memory boards and a
pair of front-end director boards coupled between a pair of disk drives
and global cache memory boards used in the system interface of the
de-populated system; and
FIG. 14 is a universal director board adapted for use in the system
interface of the de-populated system of FIG. 13.
DETAILED DESCRIPTION
Referring now to FIG. 2, a data storage system 100 is shown for
transferring data between a host computer/server 120 and a bank of disk
drives 140 through a system interface 160. The system interface 160
includes: a plurality of, here 32 front-end directors 180.sub.1
-180.sub.32 coupled to the host computer/server 120 via ports 123.sub.1
-123.sub.32 ; a plurality of back-end directors 200.sub.1 -200.sub.32
coupled to the bank of disk drives 140 via ports 123.sub.33 -123.sub.64 ;
a data transfer section 240, having a global cache memory 220, coupled to
the plurality of front-end directors 180.sub.1 -180.sub.16 and the
back-end directors 200.sub.1 -200.sub.16 ; and a messaging network 260,
operative independently of the data transfer section 240, coupled to the
plurality of front-end directors 180.sub.1 -180.sub.32 and the plurality
of back-end directors 200.sub.1 -200.sub.32, as shown. The front-end and
back-end directors 180.sub.1 -180.sub.32, 200.sub.1 -200.sub.32 are
functionally similar and include a microprocessor (.mu.P) 299 (i.e., a
central processing unit (CPU) and RAM), a message engine/CPU controller
314 and a data pipe 316, described in detail in the co-pending patent
applications referred to above. Suffice it to say here, however, that the
front-end and back-end directors 180.sub.1 -180.sub.32, 200.sub.1
-200.sub.32 control data transfer between the host computer/server 120 and
the bank of disk drives 140 in response to messages passing between the
directors 180.sub.1 -180.sub.32, 200.sub.1 -200.sub.32 through the
messaging network 260. The messages facilitate the data transfer between
host computer/server 120 and the bank of disk drives 140 with such data
passing through the global cache memory 220 via the data transfer section
240. More particularly, in the case of the front-end directors 180.sub.1
-180.sub.32, the data passes between the host computer to the global cache
memory 220 through the data pipe 316 in the front-end directors 180.sub.1
-180.sub.32 and the messages pass through the message engine/CPU
controller 314 in such front-end directors 180.sub.1 -180.sub.32. In the
case of the back-end directors 200.sub.1 -200.sub.32 the data passes
between the back-end directors 200.sub.1 -200.sub.32 and the bank of disk
drives 140 and the global cache memory 220 through the data pipe 316 in
the back-end directors 200.sub.1 -200.sub.32 and again the messages pass
through the message engine/CPU controller 314 in such back-end director
200.sub.1 -200.sub.32.
With such an arrangement, the cache memory 220 in the data transfer section
240 is not burdened with the task of transferring the director messaging.
Rather the messaging network 260 operates independent of the data transfer
section 240 thereby increasing the operating bandwidth of the system
interface 160.
In operation, and considering first a read request by the host
computer/server 120 (i.e., the host computer/server 120 requests data from
the bank of disk drives 140), the request is passed from one of a
plurality of, here 32, host computer processors 121.sub.1 -121.sub.32 in
the host computer 120 to one or more of the pair of the front-end
directors 180.sub.1 -180.sub.32 connected to such host computer processor
121.sub.1 -121.sub.32. (It is noted that in the host computer 120, each
one of the host computer processors 121.sub.1 -121.sub.32 is coupled to
here a pair (but not limited to a pair) of the front-end directors
180.sub.1 -180.sub.32, to provide redundancy in the event of a failure in
one of the front end-directors 181.sub.1 -181.sub.32 coupled thereto.
Likewise, the bank of disk drives 140 has a plurality of, here 32, disk
drives 141.sub.1 -141.sub.32, each disk drive 141.sub.1 -141.sub.32 being
coupled to here a pair (but not limited to a pair) of the back-end
directors 200.sub.1 -200.sub.32, to provide redundancy in the event of a
failure in one of the back-end directors 200.sub.1 -200.sub.32 coupled
thereto). Thus, front-end director pairs 180.sub.1, 180.sub.2 ; . . .
180.sub.31, 180.sub.32 are coupled to processor pairs 121.sub.1, 121.sub.2
; . . . 121.sub.31, 121.sub.32, respectively, as shown. Likewise, back-end
director pairs 200.sub.1, 200.sub.2 ; . . . 200.sub.31, 200.sub.32 are
coupled to disk drive pairs 141.sub.1, 141.sub.2 ; . . . 141.sub.31,
141.sub.32, respectively, as shown.
Each front-end director 180.sub.1 -180.sub.32 includes a microprocessor
(.mu.P) 299 (i.e., a central processing unit (CPU) and RAM) described in
detail in the referenced patent application. Suffice it to say here,
however, that the microprocessor 299 makes a request for the data from the
global cache memory 220. The global cache memory 220 has a resident cache
management table, not shown. Every director 180.sub.1 -180.sub.32,
200.sub.1 -200.sub.32 has access to the resident cache management table
and every time a front-end director 180.sub.1 -180.sub.32 requests a data
transfer, the front-end director 180.sub.1 -180.sub.32 must query the
global cache memory 220 to determine whether the requested data is in the
global cache memory 220. If the requested data is in the global cache
memory 220 (i.e., a read "hit"), the front-end director 180.sub.1
-180.sub.32, more particularly the microprocessor 299 therein, mediates a
DMA (Direct Memory Access) operation for the global cache memory 220 and
the requested data is transferred to the requesting host computer
processor 121.sub.1 -121.sub.32.
If, on the other hand, the front-end director 180.sub.1 -180.sub.32
receiving the data request determines that the requested data is not in
the global cache memory 220 (i.e., a "miss") as a result of a query of the
cache management table in the global cache memory 220, such front-end
director 180.sub.1 -180.sub.32 concludes that the requested data is in the
bank of disk drives 140. Thus the front-end director 180.sub.1 -180.sub.32
that received the request for the data must make a request for the data
from one of the back-end directors 200.sub.1 -200.sub.32 in order for such
back-end director 200.sub.1 -200.sub.32 to request the data from the bank
of disk drives 140. The mapping of which back-end directors 200.sub.1
-200.sub.32 control which disk drives 141.sub.1 -141.sub.32 in the bank of
disk drives 140 is determined during a power-up initialization phase. The
map is stored in the global cache memory 220. Thus, when the front-end
director 180.sub.1 -180.sub.32 makes a request for data from the global
cache memory 220 and determines that the requested data is not in the
global cache memory 220 (i.e., a "miss"), the front-end director 180.sub.1
-180.sub.32 is also advised by the map in the global cache memory 220 of
the back-end director 200.sub.1 -200.sub.32 responsible for the requested
data in the bank of disk drives 140. The requesting front-end director
180.sub.1 -180.sub.32 then must make a request for the data in the bank of
disk drives 140 from the map designated back-end director 200.sub.1
-200.sub.32. This request between the front-end director 180.sub.1
-180.sub.32 and the appropriate one of the back-end directors 200.sub.1
-200.sub.32 (as determined by the map stored in the global cache memory
200) is by a message which passes from the front-end director 180.sub.1
-180.sub.32 through the message network 260 to the appropriate back-end
director 200.sub.1 -200.sub.32. It is noted then that the message does not
pass through the global cache memory 220 (i.e., does not pass through the
data transfer section 240) but rather passes through the separate,
independent message network 260. Thus, communication between the directors
180.sub.1 -180.sub.32, 200.sub.1 -200.sub.32 is through the message
network 260 and not through the global cache memory 220. Consequently,
valuable bandwidth for the global cache memory 220 is not used for
messaging among the directors 180.sub.1 -180.sub.32, 200.sub.1
-200.sub.32.
Thus, on a global cache memory 220 "read miss", the front-end director
180.sub.1 -180.sub.32 sends a message to the appropriate one of the
back-end directors 200.sub.1 -200.sub.32 through the message network 260
to instruct such back-end director 200.sub.1 -200.sub.32 to transfer the
requested data from the bank of disk drives 140 to the global cache memory
220. When accomplished, the back-end director 200.sub.1 -200.sub.32
advises the requesting front-end director 180.sub.1 -180.sub.32 that the
transfer is accomplished by a message, which passes from the back-end
director 200.sub.1 -200.sub.32 to the front-end director 180.sub.1
-180.sub.32 through the message network 260. In response to the
acknowledgement signal, the front-end director 180.sub.1 -180.sub.32 is
thereby advised that such front-end director 180.sub.1 -180.sub.32 can
transfer the data from the global cache memory 220 to the requesting host
computer processor 121.sub.1 -121.sub.32 as described above when there is
a cache "read hit".
It should be noted that there might be one or more back-end directors
200.sub.1 -200.sub.32 responsible for the requested data. Thus, if only
one back-end director 200.sub.1 -200.sub.32 is responsible for the
requested data, the requesting front-end director 180.sub.1 -180.sub.32
sends a uni-cast message via the message network 260 to only that specific
one of the back-end directors 200.sub.1 -200.sub.32. On the other hand, if
more than one of the back-end directors 200.sub.1 -200.sub.32 is
responsible for the requested data, a multi-cast message (here implemented
as a series of uni-cast messages) is sent by the requesting one of the
front-end directors 180.sub.1 -180.sub.32 to all of the back-end directors
200.sub.1 -200.sub.32 having responsibility for the requested data. In any
event, with both a uni-cast or multi-cast message, such message is passed
through the message network 260 and not through the data transfer section
240 (i.e., not through the global cache memory 220).
Likewise, it should be noted that while one of the host computer processors
121.sub.1 -121.sub.32 might request data, the acknowledgement signal may
be sent to the requesting host computer processor 121.sub.1 or one or more
other host computer processors 121.sub.1 -121.sub.32 via a multi-cast
(i.e., sequence of uni-cast) messages through the message network 260 to
complete the data read operation.
Considering a write operation, the host computer 120 wishes to write data
into storage (i.e., into the bank of disk drives 140). One of the
front-end directors 180.sub.1 -180.sub.32 receives the data from the host
computer 120 and writes it into the global cache memory 220. The front-end
director 180.sub.1 -180.sub.32 then requests the transfer of such data
after some period of time when the back-end director 200.sub.1 -200.sub.32
determines that the data can be removed from such cache memory 220 and
stored in the bank of disk drives 140. Before the transfer to the bank of
disk drives 140, the data in the cache memory 220 is tagged with a bit as
"fresh data" (i.e., data which has not been transferred to the bank of
disk drives 140, that is data which is "write pending"). Thus, if there
are multiple write requests for the same memory location in the global
cache memory 220 (e.g., a particular bank account) before being
transferred to the bank of disk drives 140, the data is overwritten in the
cache memory 220 with the most recent data. Each time data is transferred
to the global cache memory 220, the front-end director 180.sub.1
-180.sub.32 controlling the transfer also informs the host computer 120
that the transfer is complete to thereby free-up the host computer 120 for
other data transfers. When it is time to transfer the data in the global
cache memory 220 to the bank of disk drives 140, as determined by the
back-end director 200.sub.1 -200.sub.32, the back-end director 200.sub.1
-200.sub.32 transfers the data from the global cache memory 220 to the
bank of disk drives 140 and resets the tag associated with data in the
global cache memory 220 (i.e., un-tags the data) to indicate that the data
in the global cache memory 220 has been transferred to the bank of disk
drives 140. It is noted that the un-tagged data in the global cache memory
220 remains there until overwritten with new data.
Referring now to FIGS. 3, 4, and 5, the system interface 160 is shown to
include an electrical cabinet 300 having stored therein: a plurality of,
here eight front-end director boards 190.sub.1 -190.sub.8, each one having
here four of the front-end directors 180.sub.1 -180.sub.32 ; a plurality
of, here eight back-end director boards 210.sub.1 -210.sub.8, each one
having here four of the back-end directors 200.sub.1 -200.sub.32 ; and a
plurality of, here eight, memory boards M0-M7 which together make up the
global cache memory 220. These boards plug into the front side of a
backplane 302. (It is noted that the backplane 302 is a mid-plane printed
circuit board). Plugged into the backside of the backplane 302 are message
network boards which together make up the message network 260 as described
in the co-pending patent applications referred to above. The backside of
the backplane 302 has plugged into it adapter boards, not shown in FIGS.
2-4, which couple the boards plugged into the back-side of the backplane
302 with the computer 120 and the bank of disk drives 140 as shown in FIG.
2.
That is, referring again briefly to FIG. 2, an I/O adapter, not shown, is
coupled between each one of the front-end (FE) directors 180.sub.1
-180.sub.32 and the host computer 120 and an I/O adapter, not shown, is
coupled between each one of the back-end (BE) directors 200.sub.1
-200.sub.32 and the bank of disk drives 140.
Referring now to FIG. 5, and as described in more in the co-pending patent
applications referred to above, each one of the director boards 190.sub.1
-210.sub.8 includes, as noted above four of the directors 180.sub.1
-180.sub.32, 200.sub.1 -200.sub.32 (FIG. 2). It is noted that the director
boards 190.sub.1 -190.sub.8 having four front-end directors per board,
180.sub.1 -180.sub.32 are referred to as front-end directors and the
director boards 210.sub.1 -210.sub.8 having four back-end directors per
board, 200.sub.1 -200.sub.32 are referred to as back-end directors. Each
one of the directors 180.sub.1 -180.sub.32, 200.sub.1 -200.sub.32 includes
the microprocessor 299 referred to above), the message engine/CPU
controller 314, and the data pipe 316 shown in FIG. 2.
The front-end director boards have ports 123.sub.1 -123.sub.32, as shown in
FIG. 2, coupled to the processors 121.sub.1 -121.sub.32, as shown. The
back-end director boards have ports 123.sub.33 -123.sub.64, as shown in
FIG. 2, coupled to the disk drives 141.sub.1 -141.sub.32, as shown.
Each one of the director boards 190.sub.1 -210.sub.8 includes a crossbar
switch 318 as shown in FIG. 5. The crossbar switch 318 has four
input/output ports C.sub.1 -C.sub.4, each one being coupled to the data
pipe 316 (FIG. 2) of a corresponding one of the four directors 180.sub.1
-180.sub.32, 200.sub.1 -200.sub.32 on the director board 190.sub.1
-210.sub.8. The crossbar switch 318 has eight output/input ports
collectively identified in FIG. 5 by numerical designation 321 (which plug
into the backplane 302). The crossbar switch 318 on the front-end director
boards 191.sub.1 -191.sub.8 is used for coupling the data pipe 316 of a
selected one of the four front-end directors 180.sub.1 -180.sub.32 on the
front-end director board 190.sub.1 -190.sub.8 to the global cache memory
220 via the backplane 302 and I/O adapter, not shown. The crossbar switch
318 on the back-end director boards 210.sub.1 -210.sub.8 is used for
coupling the data pipe 316 of a selected one of the four back-end
directors 200.sub.1 -200.sub.32 on the back-end director board 210.sub.1
-210.sub.8 to the global cache memory 220 via the backplane 302 and I/O
adapter, not shown. Thus, referring to FIG. 2, the data pipe 316 in the
front-end directors 180.sub.1 -180.sub.32 couples data between the host
computer 120 and the global cache memory 220 while the data pipe 316 in
the back-end directors 200.sub.1 -200.sub.32 couples data between the bank
of disk drives 140 and the global cache memory 220. It is noted that there
are separate point-to-point data paths PTH.sub.1 -PTH.sub.64 (FIG. 2)
between each one of the directors 180.sub.1 -180.sub.32, 200.sub.1
-200.sub.32 and the global cache memory 220. It is also noted that the
backplane 302 is a passive backplane because it is made up of only etched
conductors on one or more layers of a printed circuit board. That is, the
backplane 302 does not have any active components.
Further, as described in the co-pending patent applications referred to
above, crossbar switch 320 (FIG. 5) plugs into the backplane 302 and is
used for coupling to the directors to the message network 260 (FIG. 2)
through the backplane.
Referring again to FIG. 5, the crossbar switch 318 includes a pair of
crossbar switches 406X, 406Y. Each one of the switches 406X, 406Y includes
four input/output director-side ports C.sub.1 -C.sub.4 and the four
input/output memory-side ports collectively designated in FIG. 5 by
numerical designation 321. The director-side ports C.sub.1 -C.sub.4 of
switch 406X are connected to the four directors on the director board, as
indicated, and as described in more detail in the co-pending patent
applications referred to above. Likewise, director-side ports C.sub.1
-C.sub.4 of switch 406Y are also connected to the dual-ported directors on
such board, as indicated. Thus, as described in the co-pending patent
applications referred to above, each director is a dual-ported directors.
Each one of the ports C.sub.1 -C.sub.4 may be coupled to a selected one of
the four ports collectively designated by 321 in accordance with control
words provided to the switch 406X by the directors on such board,
respectively, as described in the above-referenced patent application.
Suffice it to say here, that port 402A of any one of the directors
180.sub.1, 180.sub.3, 180.sub.5, 180.sub.7 may be coupled to any one of
the ports 321 of switch 406X, selectively in accordance with the control
words. The coupling between the director boards 190.sub.1 -190.sub.8,
210.sub.1 -210.sub.8 and the global cache memory 220 is shown in FIG. 8.
Likewise for switch 406Y.
More particularly, and referring also to FIG. 2, as noted above, each one
of the host computer processors 121.sub.1 -121.sub.32 in the host computer
120 is coupled to a pair of the front-end directors 180.sub.1 -180.sub.32,
to provide redundancy in the event of a failure in one of the front
end-directors 181.sub.1 -181.sub.32 coupled thereto. Likewise, the bank of
disk drives 140 has a plurality of, here 32, disk drives 141.sub.1
-141.sub.32, each disk drive 141.sub.1 -141.sub.32 being coupled to a pair
of the back-end directors 200.sub.1 -200.sub.32, to provide redundancy in
the event of a failure in one of the back-end directors 200.sub.1
-200.sub.32 coupled thereto). Thus, considering exemplary host computer
processor 121.sub.1, such processor 121.sub.1 is coupled to a pair of
front-end directors 180.sub.1, 180.sub.2. Thus, if director 180.sub.1
fails, the host computer processor 121.sub.1 can still access the system
interface 160, albeit by the other front-end director 180.sub.2. Thus,
directors 180.sub.1 and 180.sub.2 are considered redundancy pairs of
directors. Likewise, other redundancy pairs of front-end directors are:
front-end directors 180.sub.3, 180.sub.4 ; 180.sub.5, 180.sub.6 ;
180.sub.7, 180.sub.8 ; 180.sub.9, 180.sub.10 ; 180.sub.11, 180.sub.12 ;
180.sub.13, 180.sub.14 ; 180.sub.15, 180.sub.16 ; 180.sub.17, 180.sub.18,
180.sub.19, 180.sub.20 ; 180.sub.21, 180.sub.22 ; 180.sub.23, 180.sub.24,
180.sub.25, 180.sub.26 ; 180.sub.27, 180.sub.28 ; 180.sub.29, 180.sub.30 ;
and 180.sub.31, 180.sub.32 (only directors 180.sub.31 and 180.sub.32 being
shown in FIG. 2).
Likewise, disk drive 141.sub.1 is coupled to a pair of back-end directors
200.sub.1, 200.sub.2. Thus, if director 200.sub.1 fails, the disk drive
141.sub.1 can still access the system interface 160, albeit by the other
back-end director 180.sub.2. Thus, directors 200.sub.1 and 200.sub.2 are
considered redundancy pairs of directors. Likewise, other redundancy pairs
of back-end directors are: back-end directors 200.sub.3, 200.sub.4 ;
200.sub.5, 200.sub.6, 200.sub.7, 200.sub.8, 200.sub.9, 200.sub.10 ;
200.sub.11, 200.sub.12 ; 200.sub.13, 200.sub.14, 200.sub.15, 200.sub.16,
200.sub.17, 200.sub.18, 200.sub.19, 200.sub.20 ; 200.sub.21, 200.sub.22 ;
200.sub.23, 200.sub.24 ; 200.sub.25, 200.sub.26 ; 200.sub.27, 200.sub.28 ;
200.sub.29, 200.sub.30 ; and 200.sub.31, 200.sub.32 (only directors
200.sub.31 and 200.sub.32 being shown in FIG. 2).
As noted above, there are four directors on each one of the director
boards. The physical position of the director boards along with a
positional designation, are shown in FIG. 8 (e.g., director board
190.sub.1 also has the designation D2). Further, Thus, referring to FIGS.
2 and 5:
FRONT-END FRONT-END DIRECTORS ON THE
DIRECTOR BOARD FRONT-END DIRECTOR BOARD
190.sub.1 (D2) 180.sub.1, 180.sub.3, 180.sub.5, 180.sub.7
190.sub.1 (DD) 180.sub.2, 180.sub.4, 180.sub.6, 180.sub.8
190.sub.2 (D3) 180.sub.9, 180.sub.11, 180.sub.13, 180.sub.15
190.sub.3 (DC) 180.sub.10, 180.sub.12, 180.sub.14, 180.sub.16
190.sub.4 (D9) 180.sub.17, 180.sub.19, 180.sub.21, 180.sub.23
190.sub.5 (D6) 180.sub.18, 180.sub.20, 180.sub.22, 180.sub.24
190.sub.6 (D8) 180.sub.25, 180.sub.27, 180.sub.29, 180.sub.31
190.sub.7 (D7) 180.sub.26, 180.sub.28, 180.sub.30, 180.sub.32
210.sub.1 (D0) 200.sub.1, 200.sub.3, 200.sub.5, 200.sub.7
210.sub.1 (DF) 200.sub.2, 200.sub.4, 200.sub.6, 200.sub.8
210.sub.2 (D2) 200.sub.9, 200.sub.11 200.sub.13, 200.sub.15
210.sub.3 (DE) 200.sub.10, 200.sub.12, 200.sub.14, 200.sub.16
210.sub.4 (DB) 200.sub.17, 200.sub.19, 200.sub.21, 200.sub.23
210.sub.5 (D4) 200.sub.18, 200.sub.20, 200.sub.22, 200.sub.24
210.sub.6 (DA) 200.sub.25, 200.sub.27, 200.sub.29, 200.sub.31
210.sub.7 (D5) 200.sub.26, 200.sub.28, 200.sub.30, 200.sub.32
Thus, to provide the redundant pairs of directors described above, the
following director boards are paired to enable achievement of the
above-described redundancy:
Front-end boards:
D2 and DD
D3 and DC
D9 and D6
D8 and D7
Back-end boards
D0 and DF
D2 and DE
DB and D4
DA and D5
Further, referring also to FIG. 5, the global cache memory 220 includes a
plurality of, here eight, cache memory boards M0-M7, as shown. Still
further, referring to FIG. 6, an exemplary one of the cache memory boards
is shown. Here, each cache memory board includes four memory array regions
1-4, an exemplary one thereof being shown and described in connection with
FIG. 6 of U.S. Pat. No. 5,943,287 entitled "Fault Tolerant Memory System",
John K. Walton, inventor, issued Aug. 24, 1999 and assigned to the same
assignee as the present invention, the entire subject matter therein being
incorporated herein by reference. Further detail of the exemplary one of
the cache memory boards is described in the co-pending patent applications
referred to above.
As shown in FIG. 6, the exemplary memory board includes a plurality of,
here four RAM memory array regions 1-4, each one of the array regions has
a pair of redundant data/control ports, i.e., an A port and a B port, for
receiving data to, or from, the memory array region as well as for
receiving memory control signals. The memory board itself has sixteen
ports; a set of eight domain A ports P.sub.0 -P.sub.7 and a set of eight
domain B ports P.sub.8 -P.sub.15. As described in more detail in the
co-pending patent applications referred to above and in the
above-reference U.S. Patent, each memory board has four logic networks
(here crossbar switches). These four logic networks 221.sub.1A,
221.sub.2A, 221.sub.1B, 221.sub.2B, are here cross bar switches. Logic
networks 221.sub.1A, 221.sub.2A, and logic networks 221.sub.1B,
221.sub.2B, are in two independent domains, i.e., domain A and domain B.
Thus, logic networks 221.sub.1A, 221.sub.2A, are in domain A and logic
networks 221.sub.1B, 221.sub.2B are in domain B, respectively. Further,
logic networks 221.sub.1A, 221.sub.2A, in domain A are designated as A1
and A2 respectively, and logic networks 221.sub.1B, 221.sub.2B in domain B
are designated as B1 and B2, respectively.
These connections between memory boards M0 through M7 and directors D0
through DF are in the following Tables I and II, respectively:
TABLE I
PORT LOGIC
MEMORY 0
DIRECTOR (END), PORT,
SWITCH
P.sub.0 A1 D8 (FE), Port 0, Switch 406X
P.sub.1 A1 D0 (BE), Port 0, Switch 406X
P.sub.2 A1 D9 (FE), Port 1, Switch 406X
P.sub.3 A1 D1 (BE), Port 1, Switch 406X
P.sub.4 A2 DA (BE), Port 2, Switch 406X
P.sub.5 A2 D2 (FE), Port 2, Switch 406X
P.sub.6 A2 DB (BE), Port 3, Switch 406X
P.sub.7 A2 D3 (FE), Port 3, Switch 406X
P.sub.8 B1 DC (FE), Port 4, Switch 406Y
P.sub.9 B1 D4 (BE), Port 4, Switch 406Y
P.sub.10 B1 DD (FE), Port 5, Switch 406Y
P.sub.11 B1 D5 (BE), Port 5, Switch 406Y
P.sub.12 B2 DE (BE), Port 6, Switch 406Y
P.sub.13 B2 D6 (FE), Port 6, Switch 406Y
P.sub.14 B2 DF (BE), Port 7, Switch 406Y
P.sub.15 B2 D7 (FE), Port 7, Switch 406Y
MEMORY 1
DIRECTOR, PORT, SWITCH
P.sub.0 A1 DC (FE), Port 0, Switch 406X
P.sub.1 A1 D4 (BE), Port 0, Switch 406X
P.sub.2 A1 DD (FE), Port 1, Switch 406X
P.sub.3 A1 D5 (BE), Port 1, Switch 406X
P.sub.4 A2 DE (BE), Port 2, Switch 406X
P.sub.5 A2 D6 (FE), Port 2, Switch 406X
P.sub.6 A2 DF (BE), Port 3, Switch 406X
P.sub.7 A2 D7 (FE), Port 3, Switch 406X
P.sub.8 B1 D8 (FE), Port 4, Switch 406Y
P.sub.9 B1 D0 (BE), Port 4, Switch 406Y
P.sub.10 B1 D9 (FE), Port 5, Switch 406Y
P.sub.11 B1 D1 (BE), Port 5, Switch 406Y
P.sub.12 B2 DA (BE), Port 6, Switch 406Y
P.sub.13 B2 D2 (FE), Port 6, Switch 406Y
P.sub.14 B2 DB (BE), Port 7, Switch 406Y
P.sub.15 B2 D3 (FE), Port 7, Switch 406Y
MEMORY 2
DIRECTOR, PORT, SWITCH
P.sub.0 A1 DF (BE), Port 0, Switch 406X
P.sub.1 A1 D1 (BE), Port 0, Switch 406X
P.sub.2 A1 D8 (FE), Port 1, Switch 406X
P.sub.3 A1 D2 (FE), Port 1, Switch 406X
P.sub.4 A2 D9 (FE), Port 2, Switch 406X
P.sub.5 A2 D3 (FE), Port 2, Switch 406X
P.sub.6 A2 DA (BE), Port 3, Switch 406X
P.sub.7 A2 D4 (BE), Port 3, Switch 406X
P.sub.8 B1 DB (BE), Port 4, Switch 406Y
P.sub.9 B1 D5 (BE), Port 4, Switch 406Y
P.sub.10 B1 DC (FE), Port 5, Switch 406Y
P.sub.11 B1 D6 (FE), Port 5, Switch 406Y
P.sub.12 B2 DD (FE), Port 6, Switch 406Y
P.sub.13 B2 D7 (FE), Port 6, Switch 406Y
P.sub.14 B2 DE (BE), Port 7, Switch 406Y
P.sub.15 B2 D0 (BE), Port 7, Switch 406Y
MEMORY 3
DIRECTOR, PORT, SWITCH
P.sub.0 A1 DB (BE), Port 0, Switch 406X
P.sub.1 A1 D5 (BE), Port 0, Switch 406X
P.sub.2 A1 DC (FE), Port 1, Switch 406X
P.sub.3 A1 D6 (FE), Port 1, Switch 406X
P.sub.4 A2 DD (FE), Port 2, Switch 406X
P.sub.5 A2 D7 (FE), Port 2, Switch 406X
P.sub.6 A2 DE (BE), Port 3, Switch 406X
P.sub.7 A2 D0 (BE), Port 3, Switch 406X
P.sub.8 B1 DF (BE), Port 4, Switch 406Y
P.sub.9 B1 D1 (BE), Port 4, Switch 406Y
P.sub.10 B1 D8 (FE), Port 5, Switch 406Y
P.sub.11 B1 D2 (FE), Port 5, Switch 406Y
P.sub.12 B2 D9 (FE), Port 6, Switch 406Y
P.sub.13 B2 D3 (FE), Port 6, Switch 406Y
P.sub.14 B2 DA (BE), Port 7, Switch 406Y
P.sub.15 B2 D4 (BE), Port 7, Switch 406Y
MEMORY 4
DIRECTOR, PORT, SWITCH
P.sub.0 A1 DE (BE), Port 0, Switch 406X
P.sub.1 A1 D2 (FE), Port 0, Switch 406X
P.sub.2 A1 DF (BE), Port 1, Switch 406X
P.sub.3 A1 D3 (FE), Port 1, Switch 406X
P.sub.4 A2 D8 (FE), Port 2, Switch 406X
P.sub.5 A2 D4 (BE), Port 2, Switch 406X
P.sub.6 A2 D9 (FE), Port 3, Switch 406X
P.sub.7 A2 D5 (BE), Port 3, Switch 406X
P.sub.8 B1 DA (BE), Port 4, Switch 406Y
P.sub.9 B1 D6 (FE), Port 4, Switch 406Y
P.sub.10 B1 DB (BE), Port 5, Switch 406Y
P.sub.11 B1 D7 (FE), Port 5, Switch 406Y
P.sub.12 B2 DC (FE), Port 6, Switch 406Y
P.sub.13 B2 D0 (BE), Port 6, Switch 406Y
P.sub.14 B2 DD (FE), Port 7, Switch 406Y
P.sub.15 B2 D1 (BE), Port 7, Switch 406Y
MEMORY 5
DIRECTOR, PORT, SWITCH
P.sub.0 A1 DA (BE), Port 0, Switch 406X
P.sub.1 A1 D6 (FE), Port 0, Switch 406X
P.sub.2 A1 DB (BE), Port 1, Switch 406X
P.sub.3 A1 D7 (FE), Port 1, Switch 406X
P.sub.4 A2 DC (FE), Port 2, Switch 406X
P.sub.5 A2 D0 (BE), Port 2, Switch 406X
P.sub.6 A2 DD (FE), Port 3, Switch 406X
P.sub.7 A2 D1 (BE), Port 3, Switch 406X
P.sub.8 B1 DE (BE), Port 4, Switch 406X
P.sub.9 B1 D2 (FE), Port 4, Switch 406Y
P.sub.10 B1 DF (BE), Port 5, Switch 406Y
P.sub.11 B1 D3 (FE), Port 5, Switch 406Y
P.sub.12 B2 D8 (FE), Port 6, Switch 406Y
P.sub.13 B2 D4 (BE), Port 6, Switch 406Y
P.sub.14 B2 D9 (FE), Port 7, Switch 406Y
P.sub.15 B2 D5 (BE), Port 7, Switch 406Y
MEMORY 6
DIRECTOR, PORT, SWITCH
P.sub.0 A1 DD (FE), Port 0, Switch 406X
P.sub.1 A1 D3 (FE), Port 0, Switch 406X
P.sub.2 A1 DE (BE), Port 1, Switch 406X
P.sub.3 A1 D4 (BE), Port 1, Switch 406X
P.sub.4 A2 DF (BE), Port 2, Switch 406X
P.sub.5 A2 D5 (BE), Port 2, Switch 406X
P.sub.6 A2 D8 (FE), Port 3, Switch 406X
P.sub.7 A2 D6 (FE), Port 3, Switch 406X
P.sub.8 B1 D9 (FE), Port 4, Switch 406Y
P.sub.9 B1 D7 (FE), Port 4, Switch 406Y
P.sub.10 B1 DA (BE), Port 5, Switch 406Y
P.sub.11 B1 D0 (BE), Port 5, Switch 406Y
P.sub.12 B2 DB (BE), Port 6, Switch 406Y
P.sub.13 B2 D1 (BE), Port 6, Switch 406Y
P.sub.14 B2 DC (FE), Port 7, Switch 406Y
P.sub.15 B2 D2 (FE), Port 7, Switch 406Y
MEMORY 7
DIRECTOR, PORT, SWITCH
P.sub.0 A1 D9 (FE), Port 0, Switch 406X
P.sub.1 A1 D7 (FE), Port 0, Switch 406X
P.sub.2 A1 DA (BE), Port 1, Switch 406X
P.sub.3 A1 D0 (BE), Port 1, Switch 406X
P.sub.4 A2 DB (BE), Port 2, Switch 406X
P.sub.5 A2 D1 (BE), Port 2, Switch 406X
P.sub.6 A2 DC (FE), Port 3, Switch 406X
P.sub.7 A2 D2 (FE), Port 3, Switch 406X
P.sub.8 B1 DD (FE), Port 4, Switch 406Y
P.sub.9 B1 D3 (FE), Port 4, Switch 406Y
P.sub.10 B1 DE (BE), Port 5, Switch 406Y
P.sub.11 B1 D4 (BE), Port 5, Switch 406Y
P.sub.12 B2 DF (BE), Port 6, Switch 406Y
P.sub.13 B2 D5 (BE), Port 6, Switch 406Y
P.sub.14 B2 D8 (FE), Port 7, Switch 406Y
P.sub.15 B2 D6 (FE), Port 7, Switch 406Y
TABLE II
DIREC- CROSS- MEMORY MEMORY
DIREC- TOR BAR MEMORY BOARD LOGIC
TOR PORT SWITCH BOARD PORT NETWORK
