Title: Design system of semiconductor integrated circuit element, program, program product, design method of semiconductor integrated circuit element, and semiconductor integrated circuit element
Abstract: A design system, a program, a program product and a design method which can easily design a semiconductor integrated circuit element having a decoupling capacitor are provided. In an element region which serves as an IC chip 100, an input/output block 110 is arranged, and analog-signal-circuit blocks 120 etc. are arranged. In the capacity insertion regions 160 etc. of an open region 115 which does not belong to the blocks, unit capacity cells 10a are arranged in a latticed pattern. Analog wiring lines 170 are arranged between the input/output block 110 and the analog-signal-circuit blocks 120 etc., and the unit capacity cells 10a of the capacity insertion region 160 are respectively connected wiring lines 171 and 172 of power source and GND potentials by via-conductors 173 and 174. Thereafter, unit cells 180 are arranged, and wiring lines 190 for the connections between the unit cells and between the input/output block 110 and memory blocks 140 etc. are arranged. Further, the unit capacity cells 10a of the capacity insertion regions 161 etc. are respectively connected to power source and GND wiring lines 191 and 192 by via-conductors.
Patent Number: 6,941,535 Issued on 09/06/2005 to Sekido
| Inventors:
|
Sekido; Yuji (Kasugai, JP)
|
| Assignee:
|
Fujitsu Limited (Kawasaki, JP)
|
| Appl. No.:
|
342297 |
| Filed:
|
January 15, 2003 |
Foreign Application Priority Data
| Mar 04, 2002[JP] | 2002-057530 |
| Current U.S. Class: |
716/8; 716/12 |
| Intern'l Class: |
G06F 017/50; G06F 009/45 |
| Field of Search: |
716/1- 21
|
References Cited [Referenced By]
U.S. Patent Documents
| 5512766 | Apr., 1996 | Kusunoki et al.
| |
| 5869852 | Feb., 1999 | Kinoshita.
| |
| 6170079 | Jan., 2001 | Kato et al.
| |
| 6434730 | Aug., 2002 | Ito et al.
| |
| 6480992 | Nov., 2002 | Runyon.
| |
| 6487702 | Nov., 2002 | Lin et al.
| |
| 6496964 | Dec., 2002 | Inui et al.
| |
| 6523159 | Feb., 2003 | Bernstein et al.
| |
| 6618844 | Sep., 2003 | Dansky et al.
| |
| 2002/0040467 | Apr., 2002 | Dansky et al.
| |
| 2003/0006481 | Jan., 2003 | Miyada et al.
| |
| 2003/0033578 | Feb., 2003 | Chan et al.
| |
| 2003/0148578 | Aug., 2003 | Ku et al.
| |
| 2004/0073881 | Apr., 2004 | Nassif et al.
| |
Primary Examiner: Whitmore; Stacy A.
Assistant Examiner: Dimyan; Magid Y.
Attorney, Agent or Firm: Staas & Halsey LLP
Claims
1. A design system of a semiconductor integrated circuit element, comprising:
an input/output-block arrangement unit for determining arrangement of an input/output
block;
a function-block arrangement unit for determining arrangement of all function
blocks which include an analog-signal-circuit block;
a unit-capacity-cell arrangement unit for arranging a plurality of unit capacity
cell blocks in adjacency to each other in a latticed pattern, at least, an interstice
between the input/output block and the analog-signal-circuit block within that
open region of an element region which does not belong to either the input/output
block or the function blocks; the unit capacity cell blocks symbolizing unit capacity
cells each of which includes a unit capacitor composed of a first electrode to
be set at a first power source potential, a dielectric layer, and a second electrode
opposing to the first electrode through the dielectric layer and to be set at a
second power source potential, and which have such a connection wiring pattern
that, when the unit capacity cells are arranged in adjacency to each other, the
first electrodes of the adjacent unit capacity cells can be electrically connected
to each other, while the second electrodes thereof can be electrically connected
to each other, wherein the unit capacity cell is a rectangular-shaped unit capacity
cell which is shaped rectangular when viewed in plan, and in which the first electrode
and the second electrode are electrically lead out to every side, and lead-out
positions of the first electrode and the second electrode are held in a relationship
of a mirror image between opposing sides, and the unit-capacity-cell arrangement
unit arranges rectangular-shaped unit capacity cell blocks symbolizing a plurality
of such rectangular-shaped unit capacity cells, in adjacency to each other in the
latticed pattern;
an analog-wiring arrangement unit for determining arrangement of wiring lines
between the input/output block and the analog-signal-circuit block; and
a via-conductor arrangement unit for determining arrangement of at least one
first via-conductor which is electrically connected with the first electrode while
extending from at least one first power source wiring line to be set at the first
power source potential, among the wiring lines, and at least one second via-conductor
which is electrically connected with the second electrode while extending from
at least one second power source wiring line to be set at the second power source
potential, among the wiring lines.
2. A design system of a semiconductor integrated circuit element according to
claim 1, wherein:
the function-block arrangement unit includes:
a tentative arrangement unit for tentatively arranging the function blocks;
an extraction unit for extracting a capacity insertion region in which the plurality
of unit capacity cell blocks are arranged;
a combined capacitance calculation unit for calculating a combined capacitance
value which is obtained in case of arranging the unit capacity cell blocks in the
capacity insertion region; and
a comparison unit for comparing the combined capacitance value with a predetermined
demanded capacitance value, for returning to the tentative arrangement unit when
the combined capacitance value is smaller than the demanded capacitance value,
and for determining a position of the tentative arrangement as a position of the
function block when the combined capacitance value is, same as or larger than the
demanded capacitance value; and
the unit-capacity-cell arrangement unit arranges the unit capacity cell blocks
in the capacity insertion region.
3. A design system of a semiconductor integrated circuit element according to
claim 1, wherein the unit capacity cell has a MOSFET structure, in which a drain,
a source and a back gate are short-circuited, and the unit capacitor is constructed
between them and a gate.
4. A computer program for designing a semiconductor integrated circuit element,
the computer program comprising instructions for causing a computer to perform
a method comprising:
determining arrangement of an input/output block;
determining arrangement of all function blocks which include an analog-signal-circuit
block;
arranging a plurality of unit capacity cell blocks in adjacency to each other
in a latticed pattern, at least, an interstice between the input/output block and
the analog-signal-circuit block within that open region of an element region which
does not belong to either the input/output block or the function blocks; the unit
capacity cell blocks symbolizing unit capacity cells each of which includes a unit
capacitor composed of a first electrode to be set at a first power source potential,
a dielectric layer, and a second electrode opposing to the first electrode through
the dielectric layer and to be set at a second power source potential, and which
have such a connection wiring pattern that, when the unit capacity cells are arranged
in adjacency to each other, the first electrodes of the adjacent unit capacity
cells can be electrically connected to each other, while the second electrodes
thereof can be electrically connected to each other, wherein the unit capacity
cell is a rectangular-shaped unit capacity cell which is shaped rectangular when
viewed in plan, and in which the first electrode and the second electrode are electrically
lead out to every side, and lead-out positions of the first electrode and the second
electrode are held in a relationship of a mirror image between opposing sides,
and the unit-capacity-cell arrangement unit arranges rectangular-shaped unit capacity
cell blocks symbolizing a plurality of such rectangular-shaped unit capacity cells,
in adjacency to each other in the latticed pattern;
determining arrangement of wiring lines between the input/output block and the
analog-signal-circuit block; and
determining arrangement of at least one first via-conductor which is electrically
connected with the first electrode while extending from at least one first power
source wiring line to be set at the first power source potential, among the wiring
lines, and at least one second via-conductor which is electrically connected with
the second electrode while extending from at least one second power source wiring
line to be set at the second power source potential, among the wiring lines.
5. A computer program product for designing a semiconductor integrate circuit
element, the computer program product comprising:
a computer readable medium; and
a computer program stored on the computer readable medium, the computer program
comprising instructions for causing a computer to perform a method comprising:
determining arrangement of an input/output block;
determining arrangement of all function blocks which include an analog-signal-circuit
block;
arranging a plurality of unit capacity cell blocks in adjacency to each other
in a latticed pattern, at least, an interstice between the input/output block and
the analog-signal-circuit block within that open region of an element region which
does not belong to either the input/output block or the function blocks; the unit
capacity cell blocks symbolizing unit capacity cells each of which includes a unit
capacitor composed of a first electrode to be set at a first power source potential,
a dielectric layer, and a second electrode opposing to the first electrode through
the dielectric layer and to be set at a second power source potential, and which
have such a connection wiring pattern that, when the unit capacity cells are arranged
in adjacency to each other, the first electrodes of the adjacent unit capacity
cells can be electrically connected to each other, while the second electrodes
thereof can be electrically connected to each other, wherein the unit capacity
cell is a rectangular-shaped unit capacity cell which is shaped rectangular when
viewed in plan, and in which the first electrode and the second electrode are electrically
lead out to every side, and lead-out positions of the first electrode and the second
electrode are held in a relationship of a mirror image between opposing sides,
and the unit-capacity-cell arrangement unit arranges rectangular-shaped unit capacity
cell blocks symbolizing a plurality of such rectangular-shaped unit capacity cells,
in adjacency to each other in the latticed pattern;
determining arrangement of wiring lines between the input/output block and the
analog-signal-circuit block; and
determining arrangement of at least one first via-conductor which is electrically
connected with the first electrode while extending from at least one first power
source wiring line to be set at the first power source potential, among the wiring
lines, and at least one second via-conductor which is electrically connected with
the second electrode while extending from at least one second power source wiring
line to be set at the second power source potential, among the wiring lines.
6. A design system of a semiconductor integrated circuit element comprising:
an input/output-block arrangement unit for determining arrangement of an input/output
block;
a function-block arrangement unit for determining arrangement of all function
blocks;
a unit-capacity-cell arrangement unit for arranging a plurality of unit capacity
cell blocks in adjacency to each other, in an interstice between the input/output
block and the function block or in an interstice between the function blocks within
that open region of the element region which does not belong to either the input/output
block or the function blocks; the unit capacity cell blocks symbolizing unit capacity
cells each of which includes a unit capacitor composed of a first electrode to
be set at a first power source potential, a dielectric layer, and a second electrode
opposing to the first electrode through the dielectric layer and to be set at a
second power source potential, and which have such a connection wiring pattern
that, when the unit capacity cells are arranged in adjacency to each other, the
first electrodes of the adjacent unit capacity cells can be electrically connected
to each other, while the second electrodes thereof can be electrically connected
to each other, wherein the unit capacity cell is a rectangular-shaped unit capacity
cell which is shaped rectangular when viewed in plan, and in which the first electrode
and the second electrode are electrically lead out to every side, and lead-out
positions of the first electrode and the second electrode are held in a relationship
of a mirror image between opposing sides, and the unit-capacity-cell arrangement
unit arranges rectangular-shaped unit capacity cell blocks symbolizing a plurality
of such rectangular-shaped unit capacity cells, in adjacency to each other in the
latticed pattern;
a wiring arrangement unit for determining arrangement of wiring lines between
the input/output block and the function blocks and wiring lines between the function
blocks; and
a via-conductor arrangement unit for determining arrangement of at least one
first via-conductor which is electrically connected with the first electrode while
extending from at least one first power source wiring line to be set at the first
power source potential, among the wiring lines, and at least one second via-conductor
which is electrically connected with the second electrode while extending from
at least one second power source wiring line to be set at the second power source
potential, among the wiring lines.
7. A design system of a semiconductor integrated circuit element according to
claim 6, wherein:
the function-block arrangement unit includes:
a tentative arrangement unit for tentatively arranging the function blocks;
an extraction unit for extracting a capacity insertion region in which the plurality
of unit capacity cell blocks are arranged;
combined capacitance calculation unit for calculating a combined capacitance
value which is obtained in case of arranging the unit capacity cell blocks in the
capacity insertion region; and
a comparison unit for comparing the combined capacitance value with a predetermined
demanded capacitance value, for returning to the tentative arrangement unit when
the combined capacitance value is smaller than the demanded capacitance value,
and for determining a position of the tentative arrangement as a position of the
function block when the combined capacitance value is, same as or larger than the
demanded capacitance value; and
the unit-capacity-cell arrangement unit arranges the unit capacity cell blocks
in the capacity insertion region.
8. A design system of a semiconductor integrated circuit element according to
claims
6, wherein the unit capacity cell has a MOSFET structure, in which
a drain, a source and a back gate are short-circuited, and the unit capacitor is
constructed between them and a gate.
9. A computer program for designing a semiconductor integrated circuit element,
the computer program comprising instructions for causing a computer to perform
a method comprising:
determining arrangement of an input/output block;
determining arrangement of all function blocks;
arranging a plurality of unit capacity cell blocks in adjacency to each other
in a latticed pattern, an interstice between the input/output block and the function
block or in an interstice between the function blocks within that open region of
the element region which does not belong to either the input/output block or the
function blocks; the unit capacity cell blocks symbolizing unit capacity cells
each of which includes a unit capacitor composed of a first electrode to be set
at a first power source potential, a dielectric layer, and a second electrode opposing
to the first electrode through the dielectric layer and to be set at a second power
source potential, and which have such a connection wiring pattern that, when the
unit capacity cells are arranged in adjacency to each other, the first electrodes
of the adjacent unit capacity cells can be electrically connected to each other,
while the second electrodes thereof can be electrically connected to each other,
wherein the unit capacity cell is a rectangular-shaped unit capacity cell which
is shaped rectangular when viewed in plan, and in which the first electrode and
the second electrode are electrically lead out to every side, and lead-out positions
of the first electrode and the second electrode are held in a relationship of a
mirror image between opposing sides, and the unit-capacity-cell arrangement unit
arranges rectangular-shaped unit capacity cell blocks symbolizing a plurality of
such rectangular-shaped unit capacity cells, in adjacency to each other in the
latticed pattern;
determining arrangement of wiring lines between the input/output block and the
function blocks and wiring lines between the function blocks; and
determining arrangement of at least one first via-conductor which is electrically
connected with the first electrode while extending from at least one first power
source wiring line to be set at the first power source potential, among the wiring
lines, and at least one second via-conductor which is electrically connected with
the second electrode while extending from at least one second power source wiring
line to be set at the second power source potential, among the wiring lines.
10. A computer program product for designing a semiconductor integrated circuit
element, the computer program product comprising:
a computer readable medium; and
a computer program stored on the computer readable medium, the computer program
comprising instructions for causing a computer to perform a method comprising:
determining arrangement of an input/output block;
determining arrangement of all function blocks;
arranging a plurality of unit capacity cell blocks in adjacency to each other
in a latticed pattern, in an interstice between the input/output block and the
function block or in an interstice between the function blocks within that open
region of the element region which does not belong to either the input/output block
and the function blocks; the unit capacity cell blocks symbolizing unit capacity
cells each of which includes a unit capacitor composed of a first electrode to
be set at a first power source potential, a dielectric layer, and a second electrode
opposing to the first electrode through the dielectric layer and to be set at a
second power source potential, and which have such a connection wiring pattern
that, when the unit capacity cells are arranged in adjacency to each other, the
first electrodes of the adjacent unit capacity cells can be electrically connected
to each other, while the second electrodes thereof can be electrically connected
to each other, wherein the unit capacity cell is a rectangular-shaped unit capacity
cell which is shaped rectangular when viewed in plan, and in which the first electrode
and the second electrode are electrically lead out to every side, and lead-out
positions of the first electrode and the second electrode are held in a relationship
of a mirror image between opposing sides, and the unit-capacity-cell arrangement
unit arranges rectangular-shaped unit capacity cell blocks symbolizing p plurality
of such rectangular-shaped unit capacity cells, in adjacency to each other in the
latticed pattern;
determining arrangement of wiring lines between the input/output block and the
function blocks and wiring lines between the function blocks; and
determining arrangement of at least one first via-conductor which is electrically
connected with the first electrode while extending from at least one first power
source wiring line to be set at the first power source potential, among the wiring
lines, and at least one second via-conductor which is electrically connected with
the second electrode while extending from at least one second power source wiring
line to be set at the second power source potential, among the wiring lines.
11. A design method of a semiconductor integrated circuit element, in a method
of designing a semiconductor integrated circuit element in an element region, comprising:
determining arrangement of an input/output block;
determining arrangement of all function blocks which include an analog-signal-circuit
block;
arranging a plurality of unit capacity cell blocks in adjacency to each other
in a latticed, pattern in at least, an interstice between the input/output block
and the analog-signal-circuit block within that open region of the element region
which does not belong to either the input/output block or the function blocks;
the unit capacity cell blocks symbolizing unit capacity cells each of which includes
a unit capacitor composed of a first electrode to be set at a first power source
potential, a dielectric layer, and a second electrode opposing to the first electrode
through the dielectric layer and to be set at a second power source potential,
and which have such a connection wiring pattern that, when the unit capacity cells
are arranged in adjacency to each other, the first electrodes of the adjacent unit
capacity cells can be electrically connected to each other, while the second electrodes
thereof can be electrically connected to each other, wherein the unit capacity
cell is a rectangular-shaped unit capacity cell which is shaped rectangular when
viewed in plan, and in which the first electrode and the second electrode are electrically
lead out to every side, and lead-out positions of the first electrode and the second
electrode are held in a relationship of a mirror image between opposing sides,
and arranging the rectangular-shaped unit capacity cell blocks symbolizing a plurality
of such rectangular-shaped unit capacity cells, in adjacency to each other in the
latticed pattern;
determining arrangement of wiring lines between the input/output block and the
analog-signal-circuit block; and
determining arrangement of at least one first via-conductor which is electrically
connected with the first electrode while extending from at least one first power
source wiring line to be set at the first power source potential, among the wiring
lines, and at least one second via-conductor which is electrically connected with
the second electrode while extending from at least one second power source wiring
line to be set at the second power source potential, among the wiring lines.
12. A design method of a semiconductor integrated circuit element according to
claim 11, wherein:
the determining the arrangement of all function blocks includes:
tentatively arranging the function blocks;
extracting a capacity insertion region in which the plurality of unit capacity
cell blocks are arranged;
calculating a combined capacitance value which is obtained in case of arranging
the unit capacity cell blocks in the capacity insertion region;
comparing the combined capacitance value with a predetermined demanded capacitance
value, for returning to tentatively arranging of the function blocks when the combined
capacitance value is smaller than the demanded capacitance value, and for determining
a position of the tentative arrangement as a position of the function block when
the combined capacitance value is, same as or larger than the demanded capacitance
value; and
arranging the unit capacity cell blocks in the capacity insertion region.
13. A design method of a semiconductor integrated circuit element according to
claim 11, wherein the unit capacity cell has a MOSFET structure, in which a drain,
a source and a back gate are short-circuited, and the unit capacitor is constructed
between them and a gate.
14. A design method of a semiconductor integrated circuit element, in a method
of designing a semiconductor integrated circuit element in an element region, comprising:
determining arrangement of an input/output block;
determining arrangement of all function blocks;
arranging a plurality of unit capacity cell blocks in adjacency to each other
in a latticed pattern, in an interstice between the input/output block and the
function block or in an interstice between the function blocks within that open
region of the element region which does not belong to either the input/output block
or the function blocks; the unit capacity cell blocks symbolizing unit capacity
cells each of which includes a unit capacitor composed of a first electrode to
be set at a first power source potential, a dielectric layer, and a second electrode
opposing to the first electrode through the dielectric layer and to be set at a
second power source potential, and which have such a connection wiring pattern
that, when the unit capacity cells are arranged in adjacency to each other, the
first electrodes of the adjacent unit capacity cells can be electrically connected
to each other, while the second electrodes thereof can be electrically connected
to each other, wherein the unit capacity cell is a rectangular-shaped unit capacity
cell which is shaped rectangular when viewed in plan, and in which the first electrode
and the second electrode are electrically lead out to every side, and lead-out
positions of the first electrode and the second electrode are held in a relationship
of a mirror image between opposing sides, and arranging the rectangular-shaped
unit capacity cell blocks symbolizing a plurality of such rectangular-shaped unit
capacity cells, in adjacency to each other in the latticed pattern;
determining arrangement of wiring lines between the input/output block and the
function blocks and wiring lines between the function blocks; and
determining arrangement of at least one first via-conductor which is electrically
connected with the first electrode while extending from at least one first power
source wiring line to be set at the first power source potential, among the wiring
lines, and at least one second via-conductor which is electrically connected with
the second electrode while extending from at least one second power source wiring
line to be set at the second power source potential, among the wiring lines.
15. A design method of a semiconductor integrated circuit element according to
claim 14, wherein:
the determining the arrangement of all function blocks includes:
tentatively arranging the function blocks;
extracting a capacity insertion region in which the plurality of unit capacity
cell blocks are arranged;
calculating a combined capacitance value which is obtained in case of arranging
the unit capacity cell blocks in the capacity insertion region; and
comparing the combined capacitance value with a predetermined demanded capacitance
value, for returning to tentatively arranging the function blocks when the combined
capacitance value is smaller than the demanded capacitance value, and for determining
a position of the tentative arrangement as a position of the function block when
the combined capacitance value is, same as or larger than the demanded capacitance
value; and
arranging the unit capacity cell blocks in the capacity insertion region.
16. A design method of a semiconductor integrated circuit element according to
claim 14, wherein the unit capacity cell has a MOSFET structure, in which a drain,
a source and a back gate are short-circuited, and the unit capacitor is constructed
between them and a gate.
17. A semiconductor integrated circuit element which is formed on a substrate,
and which has an input/output block and a plurality of function blocks partitioned
in a direction of a plane of the substrate, comprising:
a plurality of unit capacity cells which are arranged adjacency to each other
in a latticed pattern within an open region that does not belong to either the
input/output block or the function blocks; each of the unit capacity cells including
a unit capacitor which is composed of a first electrode to be set at a first power
source potential, a dielectric layer, and a second electrode opposing to the first
electrode through the dielectric layer and to be set at a second power source potential;
the unit capacity cells having such a connection wiring pattern that, when the
unit capacity cells are arranged in adjacency to each other in the direction of
the plane, the first electrodes of the adjacent unit capacity cells can be electrically
connected to each other, while the second electrodes thereof can be electrically
connected to each other; the first electrodes and the second electrodes of the
adjacent unit capacity cells being electrically connected to each other, respectively,
wherein
the unit capacity cell is a rectangular-shaped unit capacity cell which is shaped
rectangular when viewed in plan, and in which the first electrode and the second
electrode are electrically lead out to every side, and lead-out positions of the
first electrode and the second electrode are held in a relationship of a mirror
image between opposing sides, and a plurality of such rectangular-shaped unit capacity
cells are arranged in adjacency to each other in the latticed pattern, within the
open region.
18. A semiconductor integrated circuit element according to claim 17, wherein:
at least one first power source wiring line which is set at the first power source
potential, and at least one second power source wiring line which is set at the
second power source potential, are formed on a front surface side of the substrate
in a thickness direction thereof with respect to the plurality of unit capacity
cells; and
the first electrodes of the plurality of unit capacity cells are set at the first
power source potential by at least one first via-conductor which extends from the
first power source wiring line, while the second electrodes thereof are set at
the second power source potential by at least one second via-conductor which extends
from the second power source wiring line.
19. A semiconductor integrated circuit element according to claim 17, wherein
the unit capacity cell has a MOSFET structure, in which a drain, a source and a
back gate are short-circuited, and the unit capacitor is constructed between them
and a gate.
20. A semiconductor integrated circuit element according to claim 18, wherein:
the plurality of unit capacity cells are formed in, at least, a region adjacent
to an analog-signal-circuit block selected from the open region which is; and
the first power source wiring line and the second power source wiring line are
wiring lines which supply the power source potentials from the input/output block
to the analog-signal-circuit block.
21. A semiconductor integrated circuit element according to claim 20, wherein
the plurality of unit capacity cells are formed in, at least, that region held
between the analog-signal-circuit block and the input/output block, which is a
part of the open region.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from each
of the prior Japanese patent Application No. 2002-57530 filed in Mar. 4, 2002,
the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the design system of a semiconductor integrated
circuit element, a program and a program product for causing a computer to function
as the design system, the design method of a semiconductor integrated circuit element,
and a semiconductor integrated circuit element.
2. Description of Related Art
With the microfabrication of semiconductor integrated circuits in recent years,
measures against the noise of a semiconductor integrated circuit element have become
important. Mentioned as a technique for the measures is one wherein a decoupling
capacitor is inserted into the power source circuit (between the power source wiring
and ground wiring) of the integrated circuit, thereby to stabilize the potentials
of the power source circuit and to attain the stable operation and enhanced characteristics
of the integrated circuit.
Especially in the integrated circuit in which an analog circuit and a
digital circuit are coexistent, it is effective to insert the capacitor between
the power source wiring in the analog circuit (power source wiring for the analog
circuit) and the ground wiring.
Meanwhile, in designing a semiconductor integrated circuit element, a
chip layout is first determined. More specifically, as shown in the flow chart
of FIG. 1, an input/output block is arranged at a step S101. Thereafter,
the arrangement of analog-signal-circuit blocks which afford functions and characteristics
to be achieved by the integrated circuit element, and function blocks such as a
CPU core, is determined (step S102). Subsequently, the arrangement of the
wiring lines between the input/output block and the analog-signal-circuit blocks
is determined (step S103). The wiring lines for transferring analog signals
need to be laid in consideration of the influence of noise, and impedance matching,
and the parts are sometimes determined by the manual work of a designer. Thereafter,
at a step S104, unit cells which are formed of logic circuits such as NAND,
NOR, INV and FF are arranged between the function blocks. Further, at a step S105,
the wiring lines between the unit cells, between the input/output block and the
function blocks, between the function blocks, between the function blocks and the
unit cells, etc. are determined. Thus, the arrangement and wiring of the layout
pattern of an IC chip is completed.
In case of inserting the capacitor stated above, the capacitor is manually inserted
and formed in an open space after the determination of the chip layout or amidst
the above layout operations, and the capacitor and the power source wiring are
often connected manually. More specifically, as shown in FIG. 1 by way of example,
at a step S106, the capacitor is formed in the open space which belongs
to neither the input/output block nor the function blocks, such as the interstice
between the input/output block and the function block or the interstice between
the function blocks, and the capacitor and the power source wiring are connected
(step S107), whereby the layout pattern of the IC chip is finished up.
On the other hand, the chip layout has recently been automated, and an automatic
layout tool is often employed especially for a large-scale integrated circuit.
In case of employing the automatic layout tool in this manner, the arrangement
of the capacitor is inevitably done after the completion of the layout as shown
in the flow chart of FIG. 1.
Since, however, the arrangement of the input/output block and the function
blocks is preferred at the stage of design, the open space in which the capacitor
can be formed differs in shape and size variously. It is troublesome and has increased
the cost of the design to design and arrange the capacitor manually in adaptation
to the open space. Especially when the capacitor is manually arranged after the
completion of the layout, a large number of restraints are involved, and long working
hours are expended in appropriately arranging the capacitor in the open space so
as to ensure a larger capacity. Nevertheless, a demand for shortening a design
and development period is making it difficult more and more to secure sufficient
working hours. Moreover, since skill is required for the way of arrangement, etc.,
the electrostatic capacitance of the capacitor obtained is often different depending
also upon the degree of skill of an operator, and it is sometimes difficult to
appropriately form the capacitor having the large electrostatic capacitance.
SUMMARY OF THE INVENTION
The present invention has been made in order to solve the problems as mentioned
above, and has for its object to provide a design system which can easily design
a semiconductor integrated circuit element having a decoupling capacitor, a program
product which causes a computer to function as the design system, a design method
which can facilitate the design of a semiconductor integrated circuit element having
a decoupling capacitor, and the semiconductor integrated circuit element thus designed.
In order to accomplish the object, the design system of a semiconductor integrated
circuit element according to one aspect of the present invention consists in a
design system of a semiconductor integrated circuit element, comprising input/output-block
arrangement unit for determining arrangement of an input/output block; function-block
arrangement unit for determining arrangement of all function blocks which include
an analog-signal-circuit block; unit-capacity-cell arrangement unit for arranging
a plurality of unit capacity cell blocks in adjacency to each other in, at least,
an interstice between the input/output block and the analog-signal-circuit block
within that open region of an element region which does not belong to any of the
input/output block and the function blocks; the unit capacity cell blocks symbolizing
unit capacity cells each of which includes a unit capacitor composed of a first
electrode to be set at a first power source potential, a dielectric layer, and
a second electrode opposing to the first electrode through the dielectric layer
and to be set at a second power source potential, and which have such a connection
wiring pattern that, when the unit capacity cells are arranged in adjacency to
each other, the first electrodes of the adjacent unit capacity cells can be electrically
connected to each other, while the second electrodes thereof can be electrically
connected to each other; analog-wiring arrangement unit for determining arrangement
of wiring lines between the input/output block and the analog-signal-circuit block;
and via-conductor arrangement unit for determining arrangement of at least one
first via-conductor which is electrically connected with the first electrode while
extending from at least one first power source wiring line to be set at the first
power source potential, among the wiring lines, and at least one second via-conductor
which is electrically connected with the second electrode while extending from
at least one second power source wiring line to be set at the second power source
potential, among the wiring lines.
According to this design system, the input/output block and the function
blocks including the analog-signal-circuit block are arranged, and the plurality
of unit capacity cell blocks are arranged in the interstice between the input/output
block and the analog-signal-circuit block, so that a place for the arrangement
of a decoupling capacitor constituted by the plurality of unit capacity cells can
be easily held in the element region. Besides, since the arrangement of the first
via-conductor and the second via-conductor is determined by the via-conductor arrangement
unit, the semiconductor integrated circuit element can be easily designed so that
the plurality of unit capacity cells, accordingly the decoupling capacitor, may
be connected to the first power source wiring line and the second power source
wiring line. Thus, the design system is permitted to easily design the semiconductor
integrated circuit element having the decoupling capacitor. Besides, since the
decoupling capacitor based on the unit capacity cell blocks is arranged in the
interstice between the input/output block and the analog-signal-circuit block,
the stable operation of especially the analog-signal-circuit block can be attained
by the semiconductor integrated circuit element designed. Besides, since the unit
capacity cell blocks are employed, the decoupling capacitor which is suited to
the shape of the interstice between the input/output block and the analog-signal-circuit
block, or the like can be constructed with ease.
Here in this specification, the first power source potential and the second
power source potential shall cover also a case where one of them is a power source
potential, while the other is a ground potential.
Besides, the "relationship of a mirror image" concretely signifies such
a relationship that, when a rectangle is bent so as to place its two opposing sides
on each other, the lead-out positions of the first electrodes are placed on each
other and so are those of the second electrodes. Accordingly, the right side and
left side of the rectangle become laterally symmetric, and the upper side and lower
side thereof become vertically symmetric.
In order to accomplish the object, the design system of a semiconductor integrated
circuit element according to another aspect of the present invention consists in
a design system of a semiconductor integrated circuit element, comprising input/output-block
arrangement unit for determining arrangement of an input/output block; function-block
arrangement unit for determining arrangement of all function blocks; unit-capacity-cell
arrangement unit for arranging a plurality of unit capacity cell blocks in adjacency
to each other in an interstice between the input/output block and the function
block or in an interstice between the function blocks within that open region of
the element region which does not belong to any of the input/output block and the
function blocks; the unit capacity cell blocks symbolizing unit capacity cells
each of which includes a unit capacitor composed of a first electrode to be set
at a first power source potential, a dielectric layer, and a second electrode opposing
to the first electrode through the dielectric layer and to be set at a second power
source potential, and which have such a connection wiring pattern that, when the
unit capacity cells are arranged in adjacency to each other, the first electrodes
of the adjacent unit capacity cells can be electrically connected to each other,
while the second electrodes thereof can be electrically connected to each other;
wiring arrangement unit for determining arrangement of wiring lines between the
input/output block and the function block and wiring lines between the function
blocks; and via-conductor arrangement unit for determining arrangement of at least
one first via-conductor which is electrically connected with the first electrode
while extending from at least one first power source wiring line to be set at the
first power source potential, among the wiring lines, and at least one second via-conductor
which is electrically connected with the second electrode while extending from
at least one second power source wiring line to be set at the second power source
potential, among the wiring lines.
According to this design system, the input/output block and the function
blocks are arranged, and the plurality of unit capacity cell blocks are arranged
in the interstice between the input/output block and the function block or between
the function blocks, so that a place for the arrangement of a decoupling capacitor
constituted by the plurality of unit capacity cells can be easily held in the element
region. Besides, since the arrangement of the first via-conductor and the second
via-conductor is determined by the via-conductor arrangement unit, the semiconductor
integrated circuit element can be easily designed so that the plurality of unit
capacity cells, accordingly the decoupling capacitor, may be connected to the first
power source wiring line and the second power source wiring line. Thus, the design
system is permitted to easily design the semiconductor integrated circuit element
having the decoupling capacitor. Besides, since the unit capacity cell blocks are
employed, the decoupling capacitor which is suited to the shape of the interstice
between the input/output block and the function block, or the like can be constructed
with ease.
By the way, it is also possible for accomplishing the object to employ a program
which causes a computer to function as the respective unit in the above design
system of the semiconductor integrated circuit element.
According to this program, the computer can be caused to function as the
respective unit in the foregoing design system of the semiconductor integrated
circuit element, and the semiconductor integrated circuit element can be designed
with ease.
Alternatively, it is also possible for accomplishing the object to
employ a computer-readable program product in which a program for causing a computer
to function as the respective unit in the above design system of the semiconductor
integrated circuit element is held recorded.
According to this program product, it is facilitated to provide the program
which can cause the computer to function as the respective unit in the foregoing
design system of the semiconductor integrated circuit element.
Further, in order to accomplish the object, the design method of a semiconductor
integrated circuit element according to still another aspect of the present invention
consists in a method of designing a semiconductor integrated circuit element in
an element region, comprising the input/output-block arrangement step of determining
arrangement of an input/output block; the function-block arrangement step of determining
arrangement of all function blocks which include an analog-signal-circuit block;
the unit-capacity-cell arrangement step of arranging a plurality of unit capacity
cell blocks in adjacency to each other in, at least, an interstice between the
input/output block and the analog-signal-circuit block within that open region
of the element region which does not belong to any of the input/output block and
the function blocks; the unit capacity cell blocks symbolizing unit capacity cells
each of which includes a unit capacitor composed of a first electrode to be set
at a first power source potential, a dielectric layer, and a second electrode opposing
to the first electrode through the dielectric layer and to be set at a second power
source potential, and which have such a connection wiring pattern that, when the
unit capacity cells are arranged in adjacency to each other, the first electrodes
of the adjacent unit capacity cells can be electrically connected to each other,
while the second electrodes thereof can be electrically connected to each other;
the analog-wiring arrangement step of determining arrangement of wiring lines between
the input/output block and the analog-signal-circuit block; and the via-conductor
arrangement step of determining arrangement of at least one first via-conductor
which is electrically connected with the first electrode while extending from at
least one first power source wiring line to be set at the first power source potential,
among the wiring lines, and at least one second via-conductor which is electrically
connected with the second electrode while extending from at least one second power
source wiring line to be set at the second power source potential, among the wiring lines.
According to this design method, the input/output block and the function
blocks including the analog-signal-circuit block are arranged, and the plurality
of unit capacity cell blocks are arranged in the interstice between the input/output
block and the analog-signal-circuit block, so that a place for the arrangement
of a decoupling capacitor constituted by the plurality of unit capacity cells can
be easily held in the semiconductor integrated circuit element, especially in the
interstice between the input/output block and the analog-signal-circuit block.
Besides, since the arrangement of the first via-conductor and the second via-conductor
is determined by the via-conductor arrangement step, the semiconductor integrated
circuit element can be easily designed so that the plurality of unit capacity cells,
accordingly the decoupling capacitor, may be connected to the first power source
wiring line and the second power source wiring line. Thus, the design method is
permitted to easily design the semiconductor integrated circuit element having
the decoupling capacitor. Besides, since the decoupling capacitor based on the
unit capacity cell blocks is arranged in the interstice between the input/output
block and the analog-signal-circuit block, the stable operation of especially the
analog-signal-circuit block can be attained by the semiconductor integrated circuit
element designed. Besides, since the unit capacity cell blocks are employed, the
decoupling capacitor which is suited to the shape of the interstice between the
input/output block and the analog-signal-circuit block, or the like can be constructed
with ease.
Further, in order to accomplish the object, the design method of a semiconductor
integrated circuit element according to yet another aspect of the present invention
consists in a method of designing a semiconductor integrated circuit element in
an element region, comprising the input/output-block arrangement step of determining
arrangement of an input/output block; the function-block arrangement step of determining
arrangement of all function blocks; the unit-capacity-cell arrangement step of
arranging a plurality of unit capacity cell blocks in adjacency to each other in
an interstice between the input/output block and the function block or in an interstice
between the function blocks within that open region of the element region which
does not belong to any of the input/output block and the function blocks; the unit
capacity cell blocks symbolizing unit capacity cells each of which includes a unit
capacitor composed of a first electrode to be set at a first power source potential,
a dielectric layer, and a second electrode opposing to the first electrode through
the dielectric layer and to be set at a second power source potential, and which
have such a connection wiring pattern that, when the unit capacity cells are arranged
in adjacency to each other, the first electrodes of the adjacent unit capacity
cells can be electrically connected to each other, while the second electrodes
thereof can be electrically connected to each other; the wiring arrangement step
of determining arrangement of wiring lines between the input/output block and the
function block and wiring lines between the function blocks; and the via-conductor
arrangement step of determining arrangement of at least one first via-conductor
which is electrically connected with the first electrode while extending from at
least one first power source wiring line to be set at the first power source potential,
among the wiring lines, and at least one second via-conductor which is electrically
connected with the second electrode while extending from at least one second power
source wiring line to be set at the second power source potential, among the wiring lines.
According to this design method, the input/output block and the function
blocks are arranged, and the plurality of unit capacity cell blocks are arranged
in the interstice between the input/output block and the function block or between
the function blocks, so that a place for the arrangement of a decoupling capacitor
constituted by the plurality of unit capacity cells can be easily held in the semiconductor
integrated circuit element. Besides, since the arrangement of the first via-conductor
and the second via-conductor is determined by the via-conductor arrangement step,
the semiconductor integrated circuit element can be easily designed so that the
plurality of unit capacity cells, accordingly the decoupling capacitor, may be
connected to the first power source wiring line and the second power source wiring
line. Thus, the design method is permitted to easily design the semiconductor integrated
circuit element having the decoupling capacitor. Besides, since the unit capacity
cell blocks are employed, the decoupling capacitor which is suited to the shape
of the interstice between the input/output block and the function block, or the
like can be constructed with ease.
Further, in order to accomplish the object, a semiconductor integrated circuit
element according to another aspect of the present invention consists in a semiconductor
integrated circuit element which is formed on a substrate, and which has an input/output
block and a plurality of function blocks partitioned in a direction of a plane
of the substrate, comprising a plurality of unit capacity cells which are arranged
in adjacency to each other within an open region that does not belong to any of
the input/output block and the function blocks; each of the unit capacity cells
including a unit capacitor which is composed of a first electrode to be set at
a first power source potential, a dielectric layer, and a second electrode opposing
to the first electrode through the dielectric layer and to be set at a second power
source potential; the unit capacity cells having such a connection wiring pattern
that, when the unit capacity cells are arranged in adjacency to each other in the
direction of the plane, the first electrodes of the adjacent unit capacity cells
can be electrically connected to each other, while the second electrodes thereof
can be electrically connected to each other; the first electrodes and the second
electrodes of the adjacent unit capacity cells being electrically connected to
each other, respectively.
According to this semiconductor integrated circuit element, the plurality
of unit capacity cells are arranged in adjacency to each other within the open
region. The unit capacity cells can have their first electrodes and second electrodes
electrically connected to each other, respectively, between the adjacent unit capacity
cells. Therefore, when the first electrode of any of the unit capacity cells is
connected to the first power source potential, the first electrodes of all the
adjacent unit capacity cells can be set at the first power source potential. Likewise,
when the second electrode of any of the unit capacity cells is connected to the
second power source potential, the second electrodes of all the adjacent unit capacity
cells can be set at the second power source potential. Accordingly, the positions
of connections with the first and second power source potentials are easily selected.
Moreover, since the plurality of unit capacity cells can be arranged in accordance
with the shape of the open region, the semiconductor integrated circuit element
can be designed easily without requiring a skill. Therefore, the cost of manufacture
can be curtailed to make the semiconductor integrated circuit element inexpensive.
Besides, since the arrangement of the unit capacity cells can be adjusted so as
to be suited to the shape of the open region, the whole open region can be effective
utilized to endow the element with a decoupling capacitor of large electrostatic capacitance.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a flow chart showing the design procedure of an IC chip in the related art.
FIG. 2 is an architectural diagram of the design system of an IC chip in an
embodiment, etc.
FIG. 3 is a flow chart showing the design procedure of the IC chip in the embodiment.
FIG. 4 is an explanatory diagram showing a state where an input/output block,
analog-signal-circuit blocks, memory blocks, a CPU core and other function blocks
are arranged on the IC chip.
FIG. 5 is an explanatory diagram showing a state where a large number of unit
capacity cell blocks are arranged in adjacency to one another in that open region
of the IC chip in which the function blocks are not arranged.
FIG. 6 is an explanatory view showing the plan structure of a unit capacity cell.
FIG. 7 is an explanatory view showing the structure of the unit capacity cell
taken along a section A-A′ in FIG. 6.
FIG. 8 is an explanatory view showing the structure of the unit capacity cell
taken along a section B-B′ in FIG. 6.
FIG. 9 is an explanatory diagram schematically showing the circuit arrangement
of the unit capacity cell.
FIG. 10 is an explanatory view showing a state where a plurality of unit capacity
cells are arranged in a latticed pattern so as to be adjacent to one another.
FIG. 11 is an explanatory view showing a state where wiring lines are formed
between the input/output block and the analog-signal-circuit blocks in the IC chip.
FIG. 12 is an explanatory view showing a state where via-conductors are arranged
between VD wiring lines as well as VS wiring lines and the unit capacity cells.
FIG. 13 is an explanatory view showing a state where unit cells are arranged
in that open region of the IC chip in which the function blocks and the unit capacity
cell blocks are not arranged.
FIG. 14 is an explanatory view showing a state where the wiring lines are formed
between the function blocks such as between the input/output block and the memory
blocks, the CPU core and other function blocks and between the analog-signal-circuit
blocks and the CPU core and memory blocks, between the function blocks and the
unit cells, and so forth in the IC chip.
FIG. 15 is a flow chart showing the design procedure of an IC chip according
to Modification 1.
FIG. 16 is an explanatory view showing a state where unit cells are arranged
in that open region of the IC chip in which function blocks and unit capacity cell
blocks are not arranged.
FIG. 17 is a flow chart showing the design procedure of an IC chip according
to Modification 2.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
(Embodimen
