Digital data driver and LCD using the same Number:7,176,871 from the United States Patent and Trademark Office (PTO) owispatent A digital data driver and LCD using the same. In the digital data driver, a plurality of data lines, each transfer first data during a first period and second data during a second period. A first shift register outputs a first enable signal during the first period, a second shift register outputs a second enable signal during the second period. Transmission controllers are coupled to the data lines respectively, each outputs the first data and the second data to two different DAC according to the first and second enable signals and two external signals. The present invention, by sharing latches and DACs, prevents layout and wire routing difficulty caused by the increased lateral layout area required by increased LCD resolution.<H Digital, driver, Digital, data, dr, 7176871.html, Patent, pto, 7176871

Title: Digital data driver and LCD using the same

Abstract: A digital data driver and LCD using the same. In the digital data driver, a plurality of data lines, each transfer first data during a first period and second data during a second period. A first shift register outputs a first enable signal during the first period, a second shift register outputs a second enable signal during the second period. Transmission controllers are coupled to the data lines respectively, each outputs the first data and the second data to two different DAC according to the first and second enable signals and two external signals. The present invention, by sharing latches and DACs, prevents layout and wire routing difficulty caused by the increased lateral layout area required by increased LCD resolution.

Patent Number: 7,176,871 Issued on 02/13/2007 to Yeh

Inventors: Yeh; Shin-Hung (Taipei, TW)
Assignee: Au Optronics Corp. (Hsinchu, TW)

Appl. No.: 10/699,363

Filed: October 31, 2003

Foreign Application Priority Data


May 15, 2003 [TW]			92113173 A

Current U.S. Class: 345/98 ; 345/100; 345/99

Current International Class: G09G 3/36 (20060101)

Field of Search: 345/98,99,100

References Cited [Referenced By]

U.S. Patent Documents


6256024	July 2001	Maekawa
6356223	March 2002	Tanaka
6693616	February 2004	Koyama et al.
6873312	March 2005	Matsueda

Primary Examiner: Awad; Amr A.
Assistant Examiner: Pervan; Michael
Attorney, Agent or Firm: Thomas, Kayden, Horstemeyer & Risley

Claims

What is claimed is:

1. A digital data driver, comprising: a plurality of data lines, each transferring first data during a first period and second data during a second period; a first shift register outputting a first enable signal during the first period; a second shift register outputting a second enable signal during the second period; and a plurality of transmission controllers coupled to the plurality of data lines respectively, each having first to fourth latches connected in series and a first inverter; wherein each transmission controller stores the first data and the second data in the second latch and the first latch respectively according to the first enable signal and the second enable signal; each transmission controller outputs the first data stored in the second latch to the fourth latch and outputs to a first DAC according to a third enable signal; each transmission controller outputs the second data stored in the first latch to the third latch and outputs to a second DAC through the first inverter according to a fourth enable signal.

2. The digital data driver as claimed in claim 1, wherein the transmission controller further comprises: parallel first and second switching devices, each having a first terminal coupled to one of the data lines and a second terminal coupled to an input terminal of the first latch; parallel third and fourth switching devices, each having a first terminal coupled to an output terminal of the first latch and a second terminal coupled to an input terminal of the second latch; parallel fifth and sixth switching devices, each having a first terminal coupled to an output terminal of the second latch and a second terminal coupled to an input terminal of the third latch; and a seventh switching device having a first terminal coupled to an output terminal of the third latch and a second terminal coupled to an input terminal of the fourth latch, wherein the first inverter has an input terminal coupled to the output terminal of the third latch.

3. The digital data driver as claimed in claim 2, wherein the first and third switching devices are turned on to store the first data in the second latch according to the first enable signal, the second switching device is turned on to store the second data in the first switching device according to the second enable signal, the fifth switching device and the seventh switching device are turned on to output the first data to the first DAC according to the third enable signal, and the fourth switching device and the sixth switching device are turned on to output the second data to the second DAC through the first inverter according to the fourth enable signal.

4. The digital data driver as claimed in claim 2, wherein the first to seventh switching devices are transmission gates.

5. The digital data driver as claimed in claim 2, wherein the first to seventh switching devices are switching transistors.

6. The digital data driver as claimed in claim 2, wherein the third enable signal and the fourth enable signal are produced in a third period and a fourth period in a blanking period, wherein the third enable signal controls the fifth switching device and the seventh switching device, the fourth enable signal controls the fourth switching device and the sixth switching device.

7. A liquid crystal display, comprising: a plurality of pixels arranged in a matrix; a scan driver turning on each row of pixels arranged in the matrix sequentially; and a digital data driver outputting data to the corresponding pixels, each comprising: a plurality of data lines, each transferring first data during a first period and second data during a second period; a first shift register outputting a first enable signal during the first period; a second shift register outputting a second enable signal during the second period; and a plurality of transmission controllers coupled to the plurality of data lines respectively, each having first to fourth latches connected in series and a first inverter; wherein each transmission controller stores the first data and the second data in the second latch and the first latch respectively according to the first enable signal and the second enable signal; each transmission controller outputs the first data stored in the second latch to the fourth latch and outputs to a first DAC according to a third enable signal; each transmission controller outputs the second data stored in the first latch to the third latch and outputs to a second DAC through the first inverter according to a fourth enable signal.

8. The liquid crystal display as claimed in claim 7, wherein the transmission controller further comprises: parallel first and second switching devices, each having a first terminal coupled to one of the data lines and a second terminal coupled to an input terminal of the first latch; parallel third and fourth switching devices, each having a first terminal coupled to an output terminal of the first latch and a second terminal coupled to an input terminal of the second latch; parallel fifth and sixth switching devices, each having a first terminal coupled to an output terminal of the second latch and a second terminal coupled to an input terminal of the third latch; and a seventh switching device having a first terminal coupled to an output terminal of the third latch and a second terminal coupled to an input terminal of the fourth latch, wherein the first inverter has an input terminal coupled to the output terminal of the third latch.

9. The liquid crystal display as claimed in claim 8, wherein the first and third switching devices are turned on to store the first data in the second latch according to the first enable signal, the second switching device is turned on to store the second data in the first switching device according to the second enable signal, the fifth switching device and the seventh switching device are turned on to output the first data to the first DAC according to the third enable signal, and the fourth switching device and the sixth switching device are turned on to output the second data to the second DAC through the first inverter according to the fourth enable signal.

10. The liquid crystal display as claimed in claim 8, wherein the first to seventh switching devices are transmission gates.

11. The liquid crystal display as claimed in claim 8, wherein the first to seventh switching devices are switching transistors.

12. The liquid crystal display as claimed in claim 8, wherein the third enable signal and the fourth enable signal are produced in a third period and a fourth period during a blanking period, wherein the third enable signal controls the fifth switching device and the seventh switching device, the fourth enable signal controls the fourth switching device and the sixth switching device.

13. The liquid crystal display as claimed in claim 9, wherein the first DAC and second DAC convert the first data and the second data into a first analog data and a second analog data and output to corresponding pixels respectively after receiving the first data and the second data.

14. The digital data driver as claimed in claim 1, wherein the transmission controller outputs the first data to the fourth latch through the third latch and outputs the second data to the third latch through the second latch.

15. The liquid crystal display as claimed in claim 7, wherein the transmission controller outputs the first data to the fourth latch through the third latch and outputs the second data to the third latch through the second latch.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to data drivers, and more particularly, to a digital data driver and a liquid crystal display using the same.

2. Description of the Related Art

Conventionally, digital drivers of active matrix liquid crystal display (AMLCD) use storage registers (digital latches) as line buffers to store the digital video signal in line time and to drive the Digital to Analog Converter (DAC) in a line-at-a-time mode. FIGS. 1A and 1B show the architecture of a conventional 6-bit digital data driver operating in line-at-a-time mode. According to this kind of architecture, the digital video data signals R[5].about.B[0] are loaded into the first level corresponding latches (Latch11) by the enable signal from the shift register SRn during each horizontal scanning period. Thereafter, all video signals R[5].about.B[0] stored in the first level latches (Latch11) are written to the second level latches (Latch12), and input to the DACs (DAC-Rn, DAC-Gn and DAC-Bn) simultaneously by the signal LB. According to the enable signal from the next shift register SRn.sub.+1, the digital video data signals R[5].about.B[0] on the data lines at present are loaded into the first level corresponding latches (Latch21). Next, all video signals R[5].about.B[0] stored in the first level latches (Latch21) are written to the second level latches (Latch22), and input to the DACs(DAC-Rn.sub.+1, DAC-Gn.sub.+1 and DAC-Bn.sub.+1) simultaneously by the signal LB. As resolution of AMLCD is increased the bit numbers of the data also increases such that the numbers of the digital data driver occupy a larger layout area. In the conventional arrangement, however, the high resolution AMLCD suffers from the limited lateral layout area in the digital data driver. Thus, when the resolution of the AMLCD is increased, layout difficulty in wire routing caused by additional latches and DACs.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to avoid layout difficulty in wire routing caused by increased lateral layout area because of an increase in LCD resolution.

According to the above mentioned object, the present invention provides a digital data driver and an LCD that prevents layout difficulty in wire routing caused by increased lateral layout area because of an increase in LCD resolution, by sharing latches and DACs.

In the digital type data driver of the present invention, a plurality of data lines, each transfer first data during a first period and second data during a second period. A first shift register outputs a first enable signal during the first period, a second shift register outputs a second enable signal during the second period. Transmission controllers are coupled to the data lines respectively. Each outputs the first data and the second data to two different DAC according to the first and second enable signals and two external signals as third and fourth enable signals.

In each transmission controller, first and second switching devices are connected in parallel, each has a first terminal coupled to one of the data lines and a second terminal coupled to an input terminal of the first latch. Third and fourth switching devices are connected in parallel, each has a first terminal coupled to an output terminal of the first latch and a second terminal coupled to an input terminal of the second latch. Fifth and sixth switching devices are connected in parallel, each has a first terminal coupled to an output terminal of the second latch and a second terminal coupled to an input terminal of the third latch. A seventh switching device has a first terminal coupled to an output terminal of the third latch and a second terminal coupled to an input terminal of the fourth latch. A first inverter has an input terminal coupled to the output terminal of the third latch.

The first and third switching devices are turned on to store the first data in the second latch according to the first enable signal, the second switching device is turned on to store the second data in the first switching device according to the second enable signal, the fifth switching device and the seventh switching device are turned on to output the first data to the first DAC according to the third enable signal, and the fourth switching device and the sixth switching device are turned on to output the second data to the second DAC through the first inverter according to the fourth enable signal.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention can be more fully understood by the subsequent detailed description and examples with reference made to the accompanying drawings, wherein:

FIGS. 1A and 1B show the architectures of conventional digital data drivers;

FIG. 2 is a diagram of the LCD according to the present invention;

FIG. 3 is a diagram of the digital type data driver according to the present invention;

FIGS. 4A.about.4D show the operation of the transmission controller in the digital data driver according to the present invention;

FIG. 5 is a wave diagram of the transmission controller according to the present invention; and

FIG. 6 shows the architecture of the digital data driver according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2 shows a liquid crystal display 200 with a digital data driver 203 of the present invention. As shown in FIG. 2, the liquid crystal display 200 has at least an active matrix region 201 consisting of a plurality of pixels, a scan driver 202, and a digital data driver 203. The scan driver 202 turns on one row of the pixels in the active matrix region 201 sequentially. The digital data driver 203 outputs data signals to corresponding pixels.

As shown in FIG. 3, the digital data driver 203 includes a plurality of data lines DL1.about.DLn, a plurality of shift registers (SR.sub.1 and SR.sub.2), and a plurality of transmission controller TTC1.about.TTCn.

The plurality of shift registers output an enable signal sequentially. In this case, the first shift register SR1 outputs a first enable signal E.sub.n1 in the first period, and the second shift register SR.sub.2 outputs a second enable signal En2 in the next period (the second period). The first period and the second period are in the same line period. Each of the data lines DL.sub.1.about.DL.sub.n transmits first data in the first period, and transmits second data in the second period. Each of the transmission controllers TTC1.about.TCCn is coupled to a corresponding data line.

In each transmission controller TTC1.about.TCCn, first and second switching devices T.sub.1 and T.sub.2 are connected in parallel, each has a first terminal coupled to one of the data lines DL1.about.DLn and a second terminal coupled to an input terminal of the first latch L1. Third and fourth switching devices T.sub.3 and T.sub.4 are connected in parallel, each has a first terminal coupled to an output terminal of the first latch L1 and a second terminal coupled to an input terminal of the second latch L2. Fifth and sixth switching devices T.sub.5 and T.sub.6 are connected in parallel, each has a first terminal coupled to an output terminal of the second latch L2 and a second terminal coupled to an input terminal of the third latch L3. A seventh switching device T.sub.7 has a first terminal coupled to an output terminal of the third latch L3 and a second terminal coupled to an input terminal of the fourth latch L4, wherein the output terminal of the fourth latch L4 is coupled to the first digital to digital converter DAC1. A first inverter INV1 has an input terminal coupled to the output terminal of the third latch L3 and an output terminal coupled to the second DAC DAC2.

FIGS. 4A.about.4D show the operation of the transmission controller in the digital data driver according to the present invention. FIG. 5 is a wave diagram of the transmission controller according to the present invention. The operation of the transmission controller in the digital data driver is described above with reference to FIGS. 4A.about.4D and 5.

The first shift register SR1 outputs a first enable signal E.sub.n1 in the first period of Nth display period, and the first and switching device T.sub.1 and T.sub.3 are then turned on. Consequently, the first data D0 [0] on the data line DL0 is stored in latches L1 and L2.

The second shift register SR.sub.2 outputs a second enable signal E.sub.n2 in the next period (second period) of the Nth display period, and the first latch L1 is then turned on. Consequently, the second data D0 [1] on the data line DL0 is stored into the latch L1.

Typically, there is a blanking period (blanking) between the Nth display period and the Nth+1 display period.

The fifth and seventh switching devices T.sub.5 and T.sub.7 are turned on according to a third enable signal E.sub.n3 from an external circuit in a period (B1) of a blanking period. The first data stored in the second latch L2 is then stored in the third and fourth latch L3 and L4, and outputs to a first DAC DAC1.

The fourth and sixth switching devices T.sub.4 and T.sub.6 are turned on according to a fourth enable signal E.sub.n4 from an external circuit in the next period (B2) of the blanking period. The second data stored in the first latch L1 is then stored in the second and third latch L2 and L3, and outputs to a second DAC DAC1 through a first inverter INV1. In the present invention, the operation of the transmission controllers TCC2.about.TCCn is the same as the transmission controller TCC1 and for the sake of brevity the operation of the transmission controllers TCC2.about.TCCn is omitted here. Consequently, in the present invention, the digital data driver 203 can output digital data to the corresponding DACs DAC-R1.about.DAC-Rn, DAC-G1.about.DAC-Gn and DAC-B1.about.DAC-Bn according to the output signals from the shift registers SR.sub.1.about.SR.sub.n.

Therefore, the conventional digital data driver shown in FIGS. 1A and 1B can be replaced by the digital data driver of the present invention, as shown in FIG. 6, wherein the detailed circuit of the transmission controllers TCC1.about.TCCn are the same as those shown in FIG. 3.

According to the architecture of the present invention, the digital video data signals R[5].about.B[0] (the first data) on the data lines are loaded into the corresponding second latches L2 by the enable signal from the shift register SR.sub.n in the first period of each horizontal scanning period. Next, the digital video data signals R1 [5].about.B1 [0] (the second data) on the data lines are loaded into the corresponding first latches L1 by the enable signal from the shift register SR.sub.n+1 in the second period of each horizontal scanning period. Thereafter, all the video signals R[5].about.B[0] stored in the second latches (L2) are written to the fourth latches (L4), and input to the DACs (DAC-R.sub.n, DAC-G.sub.n and DAC-B.sub.n) simultaneously according to a third enable signal from an external circuit in the period (B1) of the blanking period. Next, all the video signals R1 [5].about.B1 [0] stored in the first latches (L1) are written to the third latches (L3), and input to the DACs (DAC-R.sub.n+1, DAC-G.sub.n+1 and DAC-B.sub.n+1) simultaneously through inverters according to a fourth enable signal from the external circuit in the nest period (B2) of the blanking period.

Therefore, by sharing latches and DACs, the digital data driver and LCD of the present invention prevents layout and wire routing difficulties caused by the increased lateral layout required by the increase in LCD resolution.

While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

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