Digital-to-analog converter, analog-to-digital converter, and semiconductor device Number:7,522,082 from the United States Patent and Trademark Office (PTO) owispatent A DA conversion device includes the following elements. A higher-bit current source cell portion includes uniformly weighted higher-bit current source cells to generate an identical constant current. A lower-bit current source cell portion includes a lower-bit current source cells that are weighted to generate 1/two-to-the-power-of-certain-numbers constant currents. A constant current source selection controller includes a lower-bit controller having a scaler that uses clocks scaled down to 1/two-to-the-power-of-certain-numbers to select the lower-bit current source cells, and a higher-bit controller having shift registers and using a signal indicating a carry bit or a borrow bit used in the lower-bit controller to sequentially activate shift outputs of the shift registers, and uses the shift outputs to select the higher-bit current source cells. Constant current outputs of the selected current source cells are added and output so that an output current corresponding to the digital input signal is obtained.<H semiconductor, converter, Digital, to, anal, 7522082.html, Patent, pto, 7522082

Title: Digital-to-analog converter, analog-to-digital converter, and semiconductor device

Abstract: A DA conversion device includes the following elements. A higher-bit current source cell portion includes uniformly weighted higher-bit current source cells to generate an identical constant current. A lower-bit current source cell portion includes a lower-bit current source cells that are weighted to generate 1/two-to-the-power-of-certain-numbers constant currents. A constant current source selection controller includes a lower-bit controller having a scaler that uses clocks scaled down to 1/two-to-the-power-of-certain-numbers to select the lower-bit current source cells, and a higher-bit controller having shift registers and using a signal indicating a carry bit or a borrow bit used in the lower-bit controller to sequentially activate shift outputs of the shift registers, and uses the shift outputs to select the higher-bit current source cells. Constant current outputs of the selected current source cells are added and output so that an output current corresponding to the digital input signal is obtained.

Patent Number: 7,522,082 Issued on 04/21/2009 to Asayama, et al.

Inventors: Asayama; Go (Kanagawa, JP), Fukushima; Noriyuki (Kanagawa, JP), Nitta; Yoshikazu (Tokyo, JP), Muramatsu; Yoshinori (Kanagawa, JP), Amano; Kiyotaka (Tokyo, JP)
Assignee: Sony Corporation (Tokyo, JP)

Appl. No.: 11/974,266

Filed: October 12, 2007

Related U.S. Patent Documents


Application Number	Filing Date	Patent Number	Issue Date
11526512	Sep., 2006	7324033

Foreign Application Priority Data


Sep 26, 2005 [JP]			P2005-277190

Current U.S. Class: 341/145 ; 341/144; 341/155

Current International Class: H03M 1/66 (20060101)

Field of Search: 341/144,145,155,150,118,172

References Cited [Referenced By]

U.S. Patent Documents


4498141	February 1985	Cooper
4868571	September 1989	Inamasu
5914682	June 1999	Noguchi
6268817	July 2001	Min et al.
6411237	June 2002	Lautzenhiser
6906653	June 2005	Uno

Foreign Patent Documents


05-191290	Jul., 1993	JP
11-017545	Jan., 1999	JP
2000-152082	May., 2000	JP
2002-232291	Aug., 2002	JP

Primary Examiner: Jeanglaude; Jean B
Attorney, Agent or Firm: Depke; Robert J. Rockey, Depke & Lyons, LLC.

Parent Case Text

CROSS REFERENCES TO RELATED APPLICATIONS

The subject matter of application Ser. No. 11/526,512 is incorporated herein by reference. The present application is a continuation of U.S. application Ser. No. 11/526,512, filed Sep. 25, 2006 now U.S. Pat. No. 7,324,033, which claims priority to Japanese Patent Application JP 2005-277190 filed in the Japanese Patent Office on Sep. 26, 2005, the entire contents of which are incorporated herein by reference.

Claims

What is claim is:

1. A digital-to-analog conversion device comprising: a higher-bit current source cell portion including a plurality of higher-bit current source cells that are uniformly weighted to generate a substantially identical constant current; a lower-bit current source cell portion including a plurality of lower-bit current source cells that are weighted to generate substantially constant currents; and a constant current source selection controller operable to select the higher-bit current source cells of the higher-bit current source cell portion and the lower-bit current source cells of the lower-bit current source cell portion in accordance with a data value of a digital input signal comprised of n number of bits, wherein the constant current source selection controller includes a lower-bit controller and a higher-bit controller, and wherein the lower-bit controller includes a scaler that performs a scaling operation based on an input count clock and the higher-bit controller uses, as a shift clock, a signal indicating a carry bit or a borrow bit used in the scaling operation controlled by the lower-bit controller to sequentially activate shift outputs of shift registers, and uses the shift outputs as a selection control signal to select the higher-bit current source cells, and wherein constant current outputs of the selected lower-bit current source cells and the higher-bit current source cells are added and output so that an output current corresponding to the digital input signal is obtained.

2. The digital-to-analog conversion device according to claim 1, wherein the higher-bit current source cell portion includes the number of the higher-bit current source cells corresponding to the data value of the higher bits of the digital input signal, and the lower-bit current source cell portion includes the number of the lower-bit current source cells corresponding to the bit number of the lower bits of the digital input signal.

3. The digital-to-analog conversion device according to claim 2, wherein the higher-bit controller stops a shift operation performed by the shift registers when the shift output of the shift register reaches the data value of the higher bits of the digital input signal.

4. The digital-to-analog conversion device according to claim 3, wherein the lower-bit controller stops the scaling operation performed by the scaler when the clock scaled down to 1/two-to-the-power-of-certain-number reaches the bit number of the lower bits of the digital input signal.

5. The digital-to-analog conversion device according to claim 1, wherein each of the lower-bit current source cells and the higher-bit current source cells includes a constant current source and a differential switch that switches an output current of the constant current source based on a complementary signal, and at least one of the higher-bit controller and the lower-bit controller includes delay means for inverting the logical level of an input signal to generate an inverted signal and for delaying the inverted signal by a predetermined period, and means for supplying the input signal that is not delayed by the delay means and the inverted signal that is delayed by the delay means to the differential switch as the complementary signal.

6. The digital-to-analog conversion device according to claim 1, wherein the shift register at a first stage is disposed near a position at which the shift clock is output from the lower-bit controller, and the remaining shift registers are disposed in a two-dimensional matrix such that the shift registers in a first row containing the first stage are arranged in a first direction, and the shift registers in a second row containing subsequent stages are arranged in an opposite direction.

7. The digital-to-analog conversion device according to claim 6, wherein the length of a wiring pattern between each of the shift registers and the other shift registers is the same according to an isometric wiring pattern.

8. An analog-to-digital conversion device comprising: a reference signal generator operable to generate a reference signal for converting an analog signal into a digital signal; a comparator operable to compare the analog signal with the reference signal generated by the reference signal generator; and a counter operable to perform a counting operation with a predetermined count clock, simultaneously with a comparison operation performed by the comparator, and to store a count value at a time when the comparison operation is finished, wherein the reference signal generator includes a higher-bit current source cell portion including a plurality of higher-bit current source cells that are uniformly weighted to generate a substantially identical constant current, a lower-bit current source cell portion including a plurality of lower-bit current source cells that are weighted to generate substantially constant currents, and a constant current source selection controller operable to select the higher-bit current source cells of the higher-bit current source cell portion and the lower-bit current source cells of the lower-bit current source cell portion in accordance with a data value of a digital input signal comprised of n number of bits, wherein the constant current source selection controller includes a lower-bit controller and a higher-bit controller, and wherein the lower-bit controller includes a scaler that performs a scaling operation based on an input count clock, and the higher-bit controller uses, as a shift clock, a signal indicating a carry bit or a borrow bit used in the scaling operation controlled by the lower-bit controller to sequentially activate shift outputs of shift registers, and uses the shift outputs as a selection control signal to select the higher-bit current source cells, and wherein constant current outputs of the selected lower-bit current source cells and the higher-bit current source cells are added and output so that an output current corresponding to the digital input signal is obtained.

9. A physical-quantity-distribution detecting semiconductor device comprising: an effective area including, in a unit element, a charge generator that generates charge in response to an incident electromagnetic wave and a unit signal generator that generates an analog unit signal corresponding to the charge generated by the charge generator; a reference signal generator operable to generate a reference signal for converting the analog unit signal into a digital signal; a comparator operable to compare the analog signal with the reference signal generated by the reference signal generator; and a counter operable to perform a counting operation with a predetermined count clock, simultaneously with a comparison operation performed by the comparator, and to store a count value at a time when the comparison operation is finished, wherein the reference signal generator includes a higher-bit current source cell portion including a plurality of higher-bit current source cells that are uniformly weighted to generate a substantially identical constant current, a lower-bit current source cell portion including a plurality of lower-bit current source cells that are weighted to generate substantially constant currents, and a constant current source selection controller operable to select the higher-bit current source cells of the higher-bit current source cell portion and the lower-bit current source cells of the lower-bit current source cell portion in accordance with a data value of a digital input signal comprised of n number of bits, wherein the constant current source selection controller includes a lower-bit controller and a higher-bit controller, and wherein the lower-bit controller includes a scaler that performs a scaling operation based on an input count clock, and the higher-bit controller uses, as a shift clock, a signal indicating a carry bit or a borrow bit used in the scaling operation controlled by the lower-bit controller to sequentially activate shift outputs of shift registers, and uses the shift outputs as a selection control signal to select the higher-bit current source cells, and wherein constant current outputs of the selected lower-bit current source cells and the higher-bit current source cells are added and output so that an output current corresponding to the digital input signal is obtained.

10. The digital-to-analog conversion device according to claim 1, wherein the lower-bit controller receives j number of bits of the digital input signal, where j>=1, and the higher-bit controller receives i number of bits of the digital input signal, where i is >=to 1, and i+j=n.

11. The digital-to-analog conversion device according to claim 10, wherein i is >=to 5.

12. The analog-to-digital conversion device according to claim 8, wherein the lower-bit controller receives j number of bits of the digital input signal, where j>=1, and the higher-bit controller receives i number of bits of the digital input signal, where i is >=to 1, and i+j=n.

13. The analog-to-digital conversion device according to claim 12, wherein i is >=to 5.

14. The physical-quantity-distribution detecting semiconductor device according to claim 9, wherein the lower-bit controller receives j number of bits of the digital input signal, where j>=1, and the higher-bit controller receives i number of bits of the digital input signal, where i is >=to 1, and i+j=n.

15. The physical-quantity-distribution detecting semiconductor device according to claim 14, wherein i is >=to 5.

16. A method of converting an input digital signal comprising n number of bits to an analog signal, the method comprising the steps of: providing a higher-bit current source cell portion including a plurality of higher-bit current source cells that are uniformly weighted to generate an identical constant current; providing a lower-bit current source cell portion including a plurality of lower-bit current source cells that are weighted to generate constant currents; providing a constant current source selection controller operable to select the higher-bit current source cells of the higher-bit current source cell portion and the lower-bit current source cells of the lower-bit current source cell portion in accordance with a data value of a digital input signal comprised of n number of bits, the constant current source selection controller including a lower-bit controller and a higher-bit controller, wherein the lower-bit controller includes a scaler circuit, and driving the higher-bit controller at least partially using a shift clock output from the scaler circuit of the lower-bit controller as a signal indicating a carry bit or a borrow bit, and outputting a an analog signal corresponding to the digital input signal.

17. The method of converting an input digital signal according to claim 16, further wherein the higher-bit controller uses the shift clock outputs from the lower-bit controller as a selection control signal to select the higher-bit current source cells, and wherein constant current outputs of the selected lower-bit current source cells and the higher-bit current source cells are added and output as the output analog signal.

18. The method of converting an input digital signal according to claim 17, further comprising the step of providing j number of bits of the digital input signal to the lower-bit controller, where j>=1, and providing i number of bits of the digital input signal to the higher-bit controller, where i is >=to 1, and i+j=n.

19. The method of converting an input digital signal according to claim 18, wherein i is >=to 5.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a digital-to-analog (DA) converter for converting digital signals into analog signals, an analog-to-digital (AD) converter including this DA converter, and a semiconductor device, such as an imaging device. More particularly, the invention relates to a DA conversion mechanism using a current source cell matrix including an array-structured current source cells.

2. Description of the Related Art

Various DA converters for converting digital signals into analog signals are used in electronic apparatuses.

Physical-quantity-distribution detecting semiconductor devices including a plurality of unit elements (for example, pixels) which are disposed in a line or a matrix and which are responsive to electromagnetic waves, such as light or radiation, input from an external source are used in various fields.

For example, in the field of video equipment, charge-coupled device (CCD), metal oxide semiconductor (MOS), or complementary metal-oxide semiconductor (CMOS)-type solid-state imaging devices for detecting light, which is one example of physical quantities, are used. Such imaging devices read a physical quantity distribution obtained by converting light into an electric signal by using the unit elements (pixels in the solid-state imaging apparatuses). In the solid-state imaging devices, "solid-state" means that the imaging devices are formed of semiconductor.

One type of solid-state imaging device is an amplifying solid-state imaging device including active pixel sensors (APS), which are also referred to as "gain cells", each active pixel sensor using an amplifying transistor in an image signal generator for generating pixel signals in accordance with signal charge generated by a charge generator. Many CMOS-type solid-state imaging devices have this type of structure.

In such an amplifying solid-state imaging device, to read out pixel signals to the exterior from the imaging device, address control is performed on a pixel portion including a plurality of unit pixels so that pixel signals can be selected from the corresponding unit pixels. That is, the amplifying solid-state imaging device is one example of address-control solid-state imaging device.

For example, in an amplifying solid-state imaging device, which is one type of X-Y address solid-state imaging device including unit pixels disposed in a matrix, MOS active elements (MOS transistors) are used for forming the pixels so that the pixels have an amplifying function by themselves. That is, signal charge (photoelectrons) stored in photodiodes, which are photoelectric transducers, is amplified by the active elements and is read as image information.

In this type of X-Y address solid-state imaging device, many pixel transistors are disposed in a two-dimensional matrix to form a pixel portion. Signal charge corresponding to incident light is stored line by line or pixel by pixel, and current or voltage signals in accordance with the stored signal charge are sequentially read out from the individual pixels by addressing. In most of the MOS (including CMOS)-type solid-state imaging devices, unit pixels are accessed line by line and pixel signals in one line are read out from the pixel portion to the exterior. In some of the MOS (or CMOS)-type solid-state imaging devices, analog pixel signals read out from the pixel portion are converted into digital signals by an AD converter before being output to the exterior (see, for example, Japanese Unexamined Patent Application Publication Nos. 2000-152082 and 2002-232291).

As disclosed in the above-described publications, there are various methods for performing AD conversion in terms of the circuit scale, processing speed, and resolution. One of the AD conversion methods is so-called "single-slope-integrating or ramp-signal-comparison AD conversion method". In this method, an analog unit signal is compared with a reference signal which varies monotonously and used for digital signal conversion, and simultaneously with this comparison operation, counting is started. Then, based on the count value when the comparison operation is finished, a digital signal is obtained. In this type of AD conversion method, a DA converter is sometimes used for generating the reference signal.

There are also various methods for performing DA conversion in terms of the circuit scale, processing speed, and resolution. In one of the DA conversion methods, many current source cells weighted with predetermined current values are used, and among those current source cells, predetermined current source cells are selected based on a multi-bit digital input signal, and then, constant current outputs of the selected current source cells are added to each other. As a result, an analog current output corresponding to a digital input signal can be obtained.

In this type of DA converter, various modes can be employed in selecting current source cells corresponding to a digital input signal. One mode is a decoding mode (see Japanese Unexamined Patent Application Publication No. 5-191290). In the decoding mode, many current source cells uniformly weighted with a predetermined current value are used, and a multi-bit digital input signal is decoded into a decimal number. Then, current source cells are selected in accordance with the decimal number. Another mode is a binary mode in which a plurality of current source cells for outputting currents weighted with two to the power of certain numbers (or 1/two-to-the-power-of-certain-numbers) are used, and current source cells in accordance with the bit value of a multi-bit digital input signal are selected. Another mode is a composite mode (see Japanese Unexamined Patent Application Publication No. 11-17545). In the composite mode, a multi-bit digital input signal is divided into higher bits and lower bits, and the decoding mode is applied to the higher bits and the binary mode is applied to the lower bit.

In the composite mode, in the case of the higher bits, many current source cells uniformly weighted with a predetermined current value are prepared, and then, the higher bits of the multi-bit digital input signal are decoded into a decimal number, and the decimal number is latched. Then, current source cells are selected in accordance with the decimal number. In the case of the lower bits, many current source cells uniformly weighted with 1/two-to-the-power-of-certain-numbers of the current value weighted for the current source cells corresponding to the higher bits are prepared, and then, the lower bits of the multi-bit digital input signal are latched. Then, current source cells are selected in accordance with the lower bits. Subsequently, by adding the output currents of the current source cells selected for the higher bits and the lower bits on the basis of the latched values, an analog current output corresponding to the digital input signal value can be obtained. For the decoding of the higher bits, full decoding is performed.

SUMMARY OF THE INVENTION

In the known composite mode, however, higher bits subjected to the full decoding mode and lower bits subjected to the binary mode are operated independently. Even if the latching timing is the same between the higher bits and the lower bits, if a digital signal is input at high speed, it becomes difficult to perform decoding and latching reliably and speedily to select current source cells even though the full decoding mode and the binary mode are operated at the same time. The reason for this is that, in particular, the full decoding mode is not suitable for high speed, and as a result, glitch or erroneous coding occurs and it is difficult to obtain stable analog signals.

It is thus desirable to provide a DA conversion mechanism that can solve the problem of the occurrence of glitch or erroneous coding, for example, a DA conversion mechanism suitable for generating a reference signal which monotonously varies and which is used for single-slope integrating AD conversion method.

In an embodiment of the present invention, as in the invention disclosed in Japanese Unexamined Patent Application Publication No. 11-17545, a digital input is first divided into higher bits and lower bits, and then, the selection of current source cells is controlled for each of the higher bits and the lower bits. Accordingly, in a higher-bit current source cell portion controlled by a higher-bit controller, a plurality of higher-bit current source cells that are uniformly weighted to generate an identical constant current are disposed. In a lower-bit current source cell portion controlled by a lower-bit controller, a plurality of lower-bit current source cells that generate bit-weighted constant currents are disposed.

The lower-bit controller includes a scaler that performs a scaling operation, i.e., a binary counter operation, based on an input count clock and that uses clocks scaled down to 1/two-to-the-power-of-certain-numbers obtained by the scaling operation as a selection control signal to select the lower-bit current source cells weighted with the corresponding current values. The higher-bit controller includes the same number of shift registers as the number of higher-bit current source cells and uses, as a shift clock, a signal indicating a carry bit or a borrow bit used in the scaling operation controlled by the lower-bit controller to sequentially activate shift outputs of the shift registers, and uses the shift outputs as a selection control signal to select the higher-bit current source cells.

The lower-bit controller performs the scaling operation based on the count clock, and the higher-bit controller performs the shift operation by using, as a shift clock, a signal indicating a carry bit or a borrow bit generated while the scaling operation is performed. Accordingly, the lower-bit controller and the higher-bit controller perform the operations, not independently, but cooperatively (synchronously). Then, the higher-bit controller can reliably select the current source cells corresponding to the subsequent bit data.

With this configuration, the occurrence of glitch or erroneous coding, which would be caused by the independent operation of higher bits subjected to the decoding mode and lower bits subjected to the binary mode, can be prevented. As a result, it is possible to provide a DA conversion device suitable for single-slope-integrating AD conversion that requires a reference signal presenting monotonous changing characteristics.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram illustrating a CMOS-type solid-state imaging device according to an embodiment of the present invention;

FIG. 2 illustrates functions of a DA conversion circuit of a reference signal generator used in a solid-state imaging device;

FIG. 3 is a timing chart illustrating signal difference processing, which is a basic operation, in a column AD circuit of the solid-state imaging device shown in FIG. 1;

FIG. 4 is a block diagram illustrating a specific configuration of a reference signal generator;

FIG. 5 is a timing chart illustrating the overall operation of a DA converter, mainly a lower-bit controller and a higher-bit controller;

FIG. 6 illustrates a basic configuration of each current source cell disposed in a current source cell portion;

FIG. 7 illustrates a detailed configuration of a current source cell portion;

FIG. 8 illustrates a detailed configuration of a scaling processor;

FIG. 9 illustrates a detailed configuration of a shift register unit;

FIGS. 10A and 10B respectively illustrate a detailed configuration and an operation of a glitch suppression processor;

FIGS. 11A and 11B illustrate a first example of the layout of a DA converter;

FIGS. 12A and 12B illustrate a second example of the layout of the DA converter;

FIG. 13 illustrates the principle that the slope of a reference signal is changed;

FIG. 14 illustrates an increase in the dynamic range; and

FIG. 15 illustrates gamma correction by changing the slope of a reference signal to increase the dynamic range.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

An embodiment of the present invention is described in detail below with reference to the accompanying drawings in the context of a CMOS-type imaging device, which is an example of an X-Y address solid-state imaging device. A description is given below, assuming that all pixels used in the CMOS-type imaging device are NMOS or PMOS pixels.

The CMOS-type imaging device is an example only, and the type of device used in the following embodiment is not restricted to a MOS imaging device, and the following embodiment is applicable to all physical-quantity-distribution detecting semiconductor devices including a plurality of unit elements which are disposed in a line or matrix and which are responsive to electromagnetic waves, such as light or radiation, input from an external source.

Configuration of Solid-State Imaging Device

FIG. 1 is a schematic diagram illustrating a CMOS-type solid-state imaging device (CMOS-type image sensor) 1, which serves as a semiconductor device according to an embodiment of the present invention.

The solid-state imaging device 1 includes a two-dimensional-matrix pixel portion 10. In the pixel portion 10, a plurality of pixels having photodetectors (which serve as a charge generator) that output signals in accordance with the quantity of incident light are disposed in rows and columns, i.e., in a matrix form. A signal output from each pixel serves as a voltage signal. The solid-state imaging device 1 also includes correlated double sampling (CDS) processing functions and AD converters, which are disposed in parallel in the column direction.

More specifically, a plurality of CDS processing functions and AD converters are provided substantially parallel with vertical signal lines 19. When viewed from the top of the solid-state imaging device 1, the plurality of CDS processing functions and AD converters may be disposed only at one edge (output side at the bottom in FIG. 1) of the pixel portion 10, or may be disposed both at one edge (output side at the bottom in FIG. 1) and at the other edge (output side at the top in FIG. 1) of the pixel portion 10. If the CDS processing functions and AD converters are disposed at both the edges of the pixel portion 10, it is preferable that horizontal scanners for reading in the row direction (horizontal scanning) are also disposed at both the edges and are operated independently.

A typical form of arranging CDS processing functions and AD converters is a column type in which a plurality of CDS processing functions and AD converters are provided in a column region disposed at the output side of the imaging portion 10, one CDS processing function and one AD converter being provided for each vertical column, and signals are sequentially read out to the output side. Alternatively, a CDS processing function and an AD converter may be assigned to a plurality of adjacent (for example, two) vertical signal lines (vertical columns) 19, or a CDS processing function and an AD converter may be assigned to N vertical signal lines 19 in every N signal lines 19 (N is a positive integer).

In any form other than the column type, a plurality of vertical signal lines 19 (vertical columns) use the common CDS processing function and the common AD converter. Accordingly, a changeover circuit (switch) is provided for switching pixel signals for a plurality of columns output from the pixel portion 10 to be supplied to a common CDS processing function and a common AD converter. It may be necessary to provide a memory for storing output signals depending on the processing of a subsequent stage.

In any form other than the column type, by applying one CDS processing function and one AD converter to a plurality of vertical signal lines (vertical columns) 19, signal processing can be performed on pixel signals column by column after the pixel signals are read from the pixel columns. Accordingly, compared with performing similar signal processing in each unit pixel, the configuration of a unit pixel can be simplified, and thus, a multi-pixel, smaller, and less expensive image sensor can be implemented.

Additionally, pixel signals for one row can be simultaneously processed in a plurality of column-parallel-structured signal processors (CDS processing functions and AD converters) disposed. Accordingly, compared with a case where pixel signals are processed by a single CDS processing function or a single AD converter in an output circuit or outside the imaging device, the signal processors can be operated at lower speed, which is advantageous in terms of the power consumption, band performance, noise, etc. In other words, if the power consumption and band performance are the same, the entire imaging sensor can be operated at higher speed.

The column type, which can operate at a lower speed, is advantageous in terms of the power consumption, band performance, noise, etc. Additionally, the provision of a change-over circuit (switch) is not necessary. In the following description, it should be assumed that the column type is used unless otherwise stated.

The solid-state imaging device 1 includes, as shown in FIG. 1, the pixel portion (imaging portion) 10 in which a plurality of unit pixels 3 formed generally in the shape of a square are disposed in rows and columns (i.e., in a matrix), a drive controller 7, a column processor 26, a reference signal generator 27 that supplies an AD conversion reference signal to the column processor 26, and an output circuit 28. The drive controller 7, the column processor 26, the reference signal generator 27, and the output circuit 28 are disposed outside the pixel portion 10.

If necessary, at the stage before or after the column processor 26, an auto gain control (AGC) circuit having a signal amplifying function may be provided in the same semiconductor region as the column circuit 26. If AGC is performed before the column processor 26, analog amplification is employed, and if AGC is performed after the column processor 26, digital amplification is employed. If an n-bit digital signal is directly amplified, the grayscale may be impaired. Accordingly, it is preferable that analog amplification is conducted first, and then, the amplified signal is converted into a digital signal.

The drive controller 7 includes control circuit functions of sequentially reading signals from the pixel portion 10. More specifically, the drive controller 7 includes a horizontal scanning circuit (column scanning circuit) 12 for controlling column addressing or column scanning, a vertical scanning circuit (row scanning circuit) 14 for controlling row addressing or row scanning, and a communication/timing controller 20 having a function of generating an internal clock.

As indicated by the broken lines in the vicinity of the communication/timing controller 20 in FIG. 1, a clock converter 23, which is an example of a high-speed clock generator, for generating pulses having a clock frequency higher than an input clock frequency may be disposed. The communication/timing controller 20 generates an internal clock based on an input clock (master clock) CLK0 input through a terminal 5a or a high-speed clock generated in the clock converter 23.

The use of a signal based on a high-speed clock generated in the clock converter 23 achieves fast AD conversion processing. The use of a high-speed clock also makes it possible to perform motion extraction or compression that requires fast computation. Parallel data output from the column processor 26 can be converted into serial data and is output to the exterior of the imaging device 1 as video data D1. With this configuration, a fast operation can be implemented with a smaller number of terminals than the number of bits of a digital signal converted from an analog signal.

The clock converter 23 has a built-in multiplier circuit for generating pulses having a clock frequency higher than the input clock frequency. The clock converter 23 receives a low-speed clock CLK2 from the communication/timing controller 20, and generates a clock having a frequency at least twice as high as the low-speed clock CLK2. If k1 is a factor of the low-speed clock CLK2, a k1 multiplier circuit is provided for the clock converter 23, and known various circuits can be used as the multiplier circuit.

In FIG. 1, for simple representation, not all of the rows and columns are shown. In reality, several tens of to several thousands unit pixels 3 are disposed in each row or each column to form the pixel portion 10. Typically, each unit pixel 3 includes a photodiode, which serves as a photodetector (charge generator), and an inter-pixel amplifier having an amplifying semiconductor element (for example, a transistor).

As the inter-pixel amplifier, a floating diffusion amplifier, may be used. For example, a floating diffusion amplifier including four transistors, which are generally used in a CMOS-type sensor, i.e., a floating diffusion amplifier including a read-out selection transistor, which is an example of a charge reader (transfer gate/read-out gate), a reset transistor, which is an example of a reset gate, a vertical selection transistor, and a source-follower amplifying transistor, which is an example of a detector for detecting a potential change of a floating diffusion, can be used.

Alternatively, an inter-pixel amplifier, such as that disclosed in Japanese Patent No. 2708455, including three transistors, i.e., an amplifying transistor connected to a drain line (DRN) to amplify a signal voltage corresponding to signal charge generated by a charge generator, a reset transistor for resetting the charge generator, and a read-out selection transistor (transfer gate) which is scanned by a vertical shift register via a transfer wiring (TRF), may be used.

The pixel portion 10 includes, not only an effective image area (effective portion) 10a, but also a reference pixel area disposed around the effective image area to optically provide a black color. For example, reference pixels for several lines (for example, one to ten lines) that optically provide a black color are disposed above and below the image area 10a, and several to several tens of reference pixels (for example, 3 to 40 reference pixels) that optically provide a black color are disposed at the left and right sides of the effective image area 10a.

The light-receiving surfaces of the reference pixels are shielded so that light does not enter the charge generators, such as photodiodes. Pixel signals from the reference pixels are used as a reference for a black color of a video signal.

In the solid-state imaging device 1, the pixel portion 10 is configured so that color imaging can be implemented. That is, on the light-receiving surface of each charge generator on which electromagnetic waves (light in this example) are incident, one of a plurality of color filters, which are used for capturing color images, forming a color separation filter is disposed.

In the example shown in FIG. 1, a basic color filter having a Bayer pattern is used. That is, in the pixel portion 10, the same pixel pattern repeats in units of 2.times.2 pixels so that the unit pixels 3 disposed in a square lattice correspond to three color filters, i.e., red (R), green (G), and blue (B) color filters.

For example, first color pixels for sensing a first color (R) are disposed at the odd rows and odd columns; second color pixels for sensing a second color (G) are disposed for the odd row and even columns and even rows and odd columns; and third color pixels for sensing a third color (B) are disposed at the even rows and even columns. In this manner, two different color pixels, i.e., R/G or G/B pixels, are disposed every other line according to the checkerboard pattern.

In such a basic color filter having a Bayer pattern, two patterns of combinations of two colors, i.e., R/G and G/B, alternately repeat in the row direction and in the column direction.

The unit pixels 3 are connected to the vertical scanning circuit 14 through row control lines 15 for selecting rows and are also connected to the column processor 26 through the corresponding vertical signal lines 19. In the column processor 26, a column AD circuit 25 is disposed for each vertical column. The row control lines 15 represent the overall wiring from the vertical scanning circuit 14 to the unit pixels 3.

The horizontal scanning circuit 12 serves as a read-out scanner for reading count values from the column processor 26. The elements forming the drive controller 7, such as the horizontal scanning circuit 12 and the vertical scanning circuit 14, are integrally formed, together with the pixel portion 10, in a semiconductor region, such as single crystal silicon, by using a technique similar to a semiconductor integrated circuit manufacturing technique, and are formed as solid-state imaging elements, which are an example of a semiconductor system.

The horizontal scanning circuit 12 and the vertical scanning circuit 14 include a horizontal decoder 12a and a vertical decoder 14a, respectively, which are discussed below, and start a shifting (scanning) operation in response to control signals CN2 and CN1, respectively, supplied from the communication/timing controller 20. Accordingly, various pulse signals (for example, reset pulse RST, transfer pulse TRF, DRN control pulse DRN, etc.) for driving the unit pixels 3 are transmitted through the row control lines 15.

The communication/timing controller 20 includes a functional block of a timing generator TG, which is an example of a read-out address controller, and a functional block of a communication interface, though they are not shown. The timing generator TG supplies clocks and pulse signals having predetermined timing required for the operation of the elements forming the drive controller 7. The communication interface receives the master clock CLK0 through the terminal 5a or receives data DATA indicating the operation mode through a terminal 5b, and outputs data including information concerning the solid-state imaging device 1.

For example, the communication/timing controller 20 outputs a horizontal address signal to the horizontal decoder 12a or a vertical address signal to the vertical decoder 14a, and the horizontal decoder 12a or the vertical decoder 14a receives the corresponding address signal and selects the corresponding column or row.

In this case, since the unit pixels 3 are disposed in a matrix, the reading of pixel signals and pixel data is facilitated by the following scanning operation. Vertical scanning is first performed such that analog pixel signals generated by a pixel signal generator and output via the vertical signal lines 19 are accessed and read row by row, and then, horizontal scanning is performed such that pixel signals (digital pixel data in this example) are accessed and read in the column direction to the output side. Instead of the above-described scanning operation, random access may be performed by directly addressing the desired unit pixel 3 and by reading information only concerning the required unit pixel 3.

The communication/timing controller 20 supplies a clock CLK1 having the same frequency as the master clock CLK0 input through the terminal 5a and also supplies a low-speed clock which is scaled down to one half the clock CLK1 (i.e., half the frequency the clock CLK1) or lower speed clocks, to, for example, the horizontal scanning circuit 12, the vertical scanning circuit 14, and the column processor 26. Clocks scaled down to one half the master clock CLK0 or lower are collectively referred to as the "low-speed clock CLK2".

The vertical scanning circuit 14 selects rows of the pixel portion 10 and supplies required pulses to the selected rows. The vertical scanning circuit 14 includes the vertical decoder 14a for defining rows of the pixel portion 10 and a vertical drive circuit 14b for supplying pulses to the row control lines 15 corresponding to the rows defined by the vertical decoder 14a to drive the unit pixels 3 of the selected rows. The vertical decoder 14a selects, not only rows from which signals are read, but also, a row used for an electronic shutter.

The horizontal scanning circuit 12 sequentially selects the column AD circuits 25 of the column processor 26 in synchronization with the low-speed clock CLK2, and supplies the signals of the selected column AD circuits 25 to a horizontal signal line (horizontal output lines) 18. The horizontal scanning circuit 12 includes the horizontal decoder 12a for defining columns of the pixel portion 10 (selecting the corresponding column AD circuits 25 of the column processor 26) and a horizontal drive circuit 12b for supplying the signals in the column processor 26 to the horizontal signal line 18 according to the readout addresses defined by the horizontal decoder 12a. The same number of lines forming the horizontal signal line 18 as the number n (n is an integer) of bits handled by the column AD circuits 25 are provided. For example, if the number of bits is 10, the horizontal signal line 18 includes 10 lines.

In the solid-state imaging device 1 configured as described above, pixel signals output from the unit pixels 3 in each vertical column are supplied to the column AD circuit 25 of the corresponding column processor 26 via the vertical signal line 19.

Each column AD circuit 25 of the column processor 26 receives pixel signals for one column and processes them. For example, each column AD circuit 25 has an analog digital converter (ADC) circuit for converting an analog signal into, for example, 10-bit digital data, based on the low-speed clock CLK2.

To perform AD conversion in the column processor 26, analog signals stored in the individual rows are converted into digital signals in parallel by using the corresponding column AD circuits 25 disposed in the column direction. In this case, the single-slope-integrating (or ramp-signal-comparison) AD conversion technique disclosed in, for example, Japanese Patent No. 2532374 or literature "Column-kan FPN no nai column-gata AD-henkanki wo tousaishita CMOS image sensor (CMOS-type Image Sensor with Column-type ADCs without Inter-column FPN)", The Institute of Image Information and Television Engineers, IPU2000-57, pp. 79-84. Since this technique can implement an AD converter with a simple structure, the circuit scale is not increased even if AD converters are disposed in parallel.

The configuration of the ADC circuit is briefly discussed, though details thereof are described later. A subject analog signal is converted into a digital signal based on a time from the start of AD conversion until the voltage of the analog signal coincides with a reference voltage RAMP. The mechanism for implementing this is, in principle, as follows. A ramp reference signal RAMP is supplied to a comparator (voltage comparator), and at the same time, counting is started with clock signals. Counting is continued until a pulse signal is obtained as a result of comparing an analog pixel signal input via the vertical signal line 19 with the reference voltage RAMP.

In this case, by modifying the circuit configuration, for a voltage-mode pixel signal input via the vertical signal line 19, the difference between the signal level (noise level) immediately after resetting the pixel and the true signal level Vsig (based on the quantity of light received) can be calculated in addition to AD conversion. With this arrangement, noise signal components, such as fixed pattern noise (FPN) or reset noise, can be eliminated.

Pixel data digitized in each column AD circuit 25 is transferred to the horizontal signal line 18 via a horizontal selection switch (not shown) driven by a horizontal selection signal supplied from the horizontal scanning circuit 12, and is then input into the output circuit 28. In this case, the number of bits of a digital signal is 10, but this is an example only. The number of bits may be less than 10 (for example, 8) or more than 10 (for example, 14 bits).

With this configuration, from the pixel portion 10 including the photodetectors, which serve as charge generators, disposed in a matrix, pixel signals of the associated vertical columns are sequentially output row by row. Then, an image corresponding to the pixel portion 10, i.e., a frame image, can be represented by a set of pixel signals of the entire pixel portion 10.

Details of Column Ad Circuit and Reference Signal Generator

The reference signal generator 27 includes a DA conversion circuit (DA converter (DAC)), which has a function of generating a reference signal for AD conversion, according to the types or pattern of the colors of color filters forming the color separation filter of the pixel portion 10. In this embodiment, the reference signal generator 27 uses a current-output-type DA conversion circuit, and details thereof are given below.

Once the pixel portion 10 to be used is determined, the types or pattern of colors of the color filters forming the color separation filter are determined, and the types of colors of the color filters located at certain positions of the two-dimensional lattice are also uniformly determined. The repeating cycle (same pattern) of the pixels of the color filters in the row direction and in the column direction is also uniformly determined by the pattern of the color filters. In one row to be processed by each column AD circuit 25, not pixel signals having all colors used in the color separation filter, but pixel signals having a combination of a smaller number of predetermined colors determined by the repeating cycle are contained.

In this embodiment, by focusing on this characteristic of the color filters, in an AD conversion circuit including a comparator circuit and a counter, DA conversion circuits, which are functional elements for generating an AD conversion reference signal to be supplied to the comparator circuit and which are an example of color-dependent reference signal output units, are formed in the following manner. Instead of providing DA conversion circuits having the same number of all colors used in the color separation filter, the same number of DA conversion circuits as the number of predetermined colors existing in the repeating cycle of a combination of color filters in one row, which is the unit for reading pixel signals, are provided. With this arrangement, the number of DA conversion circuits becomes smaller than the number of all colors of the color filters existing in the repeating cycles of the color filters in the two-dimensional matrix. When processing a row, if x colors exist (x is a positive integer of two or greater) in that row, it is sufficient if reference signals associated with the x colors are supplied to the comparator circuits, and it is therefore sufficient if x DA conversion circuits are provided.

From the viewpoint of supplying individual reference signals indicating variation characteristics and initial values of the individual colors to the comparator circuits, it is necessary to switch the row to be processed. It is thus preferable that a switching mechanism for supplying a reference signal corresponding to a color to be processed in the column direction, which is orthogonal to the row direction, be provided for each of the x DA conversion circuits.

That is, in the direction different from the row direction, which is the unit for reading pixel signals, i.e., in the vertical column direction, the same number of color-dependent reference signal generators as the predetermined number of colors of a combination of color filters existing in the repeating cycle in the vertical column direction are provided for the corresponding DA conversion circuits (reference signal output units). A reference signal generated by the color-dependent reference signal generator has a variation characteristic (more specifically, the slope) corresponding to the color characteristic of the color pixels and an initial value defined based on black references or circuit offset components, which are irrelevant to the color characteristics. A selector is provided for selecting one of the reference signals generated in the reference signal generators and for supplying the selected reference signal to the comparator circuit.

In this case, if the same color filter exits in the repeating cycle of the two-dimensional color filters, such as in a Bayer pattern, the DA conversion circuits (reference signal output units) may use the single color-dependent reference signal generator for that same color filter.

Regardless of the configuration of the DA conversion circuits, every time a row to be processed is switched, a combination of predetermined colors in that row is also switched. In response to this, each DA conversion circuit switches the variation characteristic (more specifically, the slope) of the reference signal (analog reference voltage) generated by the DA conversion circuit in accordance with the characteristics of the switched color filters, i.e., analog pixel signals, and outputs the switched variation characteristics. The initial values are set based on, for example, black references and offset components, which are irrelevant to the color characteristics.

With this arrangement, the number of reference voltage generators (corresponding to the DA conversion circuits in this embodiment) or the number of wiring patterns extending from the reference voltage generators can be reduced to be smaller than the number of color filters forming the color separation filter. Additionally, selectors (multiplexers) disposed for the individual vertical columns to selectively output analog reference voltages (corresponding to reference signals in this embodiment) supplied from the reference voltage generators, which are necessary in a case where a reference voltage generator is provided for each color filter (see Japanese Unexamined Patent Application Publication No. 2000-152082), becomes unnecessary. As a result, the circuit scale can be reduced. In addition, the number of signal lines for transmitting the reference signals based on the color pixels to the input sides of the comparator circuits can be reduced to be smaller than the number of color components of the color filters.

Alternatively, when a row to be processed is switched, the communication/timing controller 20 may set variation characteristics (slope) corresponding to the color characteristics of the color pixels and the initial value, such as black references and circuit offset components, in accordance with a change in a combination of colors forming the repeating cycle of the color filters. With this modification, the provision of a color-dependent reference signal generator for each DA conversion circuit (reference signal output unit) or the provision of a selector for selecting a color-dependent reference signal generator becomes unnecessary.

That is, in this modification, every time a row to be processed is switched, variation characteristics (slope) and an initial value are set in the corresponding DA conversion circuit in accordance with a change in a combination of colors forming the repeating cycle of the color filters. Then, it is not necessary to provide a color-dependent reference signal generator for each DA conversion circuit or to provide a selector for selecting a color-dependent reference signal generator in accordance with a row to be switched. Then, the scale of the overall reference signal generator 27 can further be reduced. In this case, however, the processing performed by a control system for the reference signal generator 27 may become complicated.

In this embodiment, in the solid-state imaging device 1, a Bayer basic pattern is used. As stated above, the same pattern repeats in units of 2.times.2 pixels. Pixel signals are read row by row and are input into the corresponding column-parallel-structured column AD circuits 25 via the corresponding vertical signal lines 19. Accordingly, in one row to be processed, pixel signals including only two colors, i.e., R/G or G/B, are contained. Thus, in this embodiment, two DA conversion circuits, i.e., a DA conversion circuit 27a corresponding to the odd columns and a DA conversion circuit 27b corresponding to the even columns, are provided.

Reference signals RAMPa and RAMPb output from the DA conversion circuits 27a and 27b, respectively, are transmitted to a voltage comparator unit 252 via common reference signal lines 251a and 251b (may be collectively referred to as the "common reference signal line 251"), respectively, which are independent of each other. The voltage comparator unit 252 includes a plurality of voltage comparators 252a (for the odd columns) and a plurality of voltage comparators 252b (for the even columns) connected to the common reference signal lines 251a and 251b, respectively.

In this case, the reference signals RAMPa and RAMPb are substantially directly transmitted to the plurality of voltage comparators 252a and 252b, respectively, via the independent common reference signal lines 251a and 251b, respectively. Each of a set of voltage comparators 252a and 252b corresponds to color filters having the same color characteristics. Substantially directly transmitting via the common reference signal lines 251a and 251b means that selectors, such as multiplexers, are not disposed between the common reference signal lines 251a and 251b and the corresponding voltage comparators 252a and 252b. This configuration is very different from that disclosed in Japanese Unexamined Patent Application Publication No. 2000-152082. In this configuration, a reference signal output from each analog reference voltage generator is transmitted to the input side of a comparator provided for each vertical column, and a selector (multiplexer) is provided immediately before the input side of each comparator to selectively output one of the reference signals from the corresponding analog reference voltage generator.

The DA conversion circuits 27a and 27b generate stepped-ramp saw tooth waves (ramp voltages) from initial values indicated by control data CN4 (CN4a and CN4b) supplied from the communication/timing controller 20 in synchronization with count clocks CKdaca and CKdacb (may be the count clock CK0), respectively, output from the communication/timing controller 20, and supplies the generated stepped-ramp saw tooth waves to the corresponding column AD circuits 25 of the column processor 26 as the AD conversion reference signals (ADC reference signals) RAMPa and RAMPb, respectively. It is preferable that a noise suppression filter be provided, though it is not shown.

In this embodiment, when performing AD conversion on a signal component Vsig of a pixel signal Vx located at a predetermined position by using the voltage comparators 252 and counters 254, the DA conversion circuit 27a or 27b sets the initial voltage of the reference signal RAMPa or RAMPb generated by the DA conversion circuit 27a or 27b, respectively, to a value different from that when AD conversion is performed on a reset component .DELTA.V by reflecting the characteristics of the pixel and variations in the circuit. The DA conversion circuit 27a or 27b also sets the slope .beta.a or .beta.b, respectively, by considering the pattern of the color filters so that the variation characteristics match the pixel characteristics.

More specifically, the initial values Vas and Vbs of the reference signals RAMPa and RAMPb for the signal component Vsig are calculated based on a signal obtained from a plurality of predetermined black references. The pixels for generating black references are pixels covered with a light-shielding layer, such as photodiodes, which serve as photoelectric transducers, forming charge generators disposed around the color pixels. The positions and the number of pixels for generating black references and the type of light-shielding layer are not particularly restricted, and a known technique may be employed.

The initial voltage includes variations unique to the DA conversion circuit 27a or 27b. Generally, the initial voltage Vas or Vbs is set to be lower than the initial voltage Var or Vbr of the reference signal RAMPa or RAMPb for the reset component .DELTA.V by an offset OFFa or OFFb, respectively.

Even if the initial voltages Var and Vbr of the reference signal RAMPa or RAMPb for the reset component .DELTA.V are set to be equal to each other, the initial voltages Vas and Vbs of the reference signals RAMPa and RAMPb for the signal component Vsig become different from each other since the offsets OFFa and OFFb are different.

The initial voltages Vas and Vbs of the reference signals RAMPa and RAMPb for the signal component Vsig may contain offsets other than those contained in pixels for generating black references.

The DA conversion circuits 27a and 27b of the reference signal generator 27 may control the offsets OFFa and OFFb in the following manner. The function of calculating initial values based on a signal obtained from reference pixels for generating a plurality of black references is provided for the communication/timing controller 20, and the communication/timing controller 20 outputs control data CN4 representing initial values. Then, the DA conversion circuits 27a and 27b may control the offsets OFFa and OFFb based on the