Display device and manufacturing method thereof Number:7,417,256 from the United States Patent and Trademark Office (PTO) owispatent

Title: Display device and manufacturing method thereof

Abstract: It is an object of the present invention to prevent an influence of voltage drop due to wiring resistance, trouble in writing of a signal into a pixel, and trouble in gray scales, and provide a display device with higher definition, represented by an EL display device and a liquid crystal display device. In the present invention, a wiring including Cu is provided as an electrode or a wiring used for the display device represented by the EL display device and the liquid crystal display device. Besides, sputtering is performed with a mask to form the wiring including Cu. With such structure, it is possible to reduce the voltage drop and a deadened signal.

Patent Number: 7,417,256 Issued on 08/26/2008 to Yamazaki,   et al.

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Inventors:	Yamazaki; Shunpei (Setagaya, JP), Osame; Mitsuaki (Atsugi, JP)
Assignee:	Semiconductor Energy Laboratory Co., Ltd. (Kanagawa-ken, JP)
Appl. No.:	11/511,453
Filed:	August 29, 2006

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Related U.S. Patent Documents

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	Application Number	Filing Date	Patent Number	Issue Date
	10664962	Sep., 2003	7102231

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Foreign Application Priority Data

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Sep 20, 2002 [JP]			2002-276295

Current U.S. Class:	257/79 ; 257/347; 257/762; 257/93
Current International Class:	H01L 27/15 (20060101)
Field of Search:	257/79,88,91,93,347,688,700,762,355-363 349/40,56,148

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Primary Examiner: Nguyen; Tuan H
Attorney, Agent or Firm: Robinson; Eric J. Robinson Intellectual Property Law Office, P.C.

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Parent Case Text

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This application is a division of U.S. patent application Ser. No. 10/664,962, filed Sept. 22, 2003, now U.S. Pat. No. 7,102,231.

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Claims

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What is claimed is:

1. A display device comprising: a pixel portion over a substrate; a protective circuit over the substrate; a first wiring and a second wiring over the substrate, the first wiring being over the second wiring; and a wiring containing Cu over the first wiring, wherein the protective circuit includes a film forming an alternating stripe pattern, and wherein one end of the film is connected to the first wiring through a first contact and the other end of the film is connected to the second wiring through a second contact.

2. A display device according to claim 1, wherein the first wiring is connected to an electrode of a light emitting element in the pixel portion.

3. A display device according to claim 1, wherein the first wiring is connected to a wiring in a driving circuit portion.

4. A display device according to claim 1, wherein the first wiring is over the second wiring and extends across the second wiring.

5. A display device according to claim 1, wherein the film is a semiconductor film.

6. A display device according to claim 1, wherein the protective circuit is provided between an input terminal portion and a signal line driving circuit.

7. A display device comprising: a pixel portion over a substrate; a film forming an alternating stripe pattern over the substrate at the periphery of the pixel portion; a first wiring and a second wiring over the substrate, the first wiring being over the second wiring; and a wiring containing Cu over the first wiring, wherein one end of the film is connected to the first wiring through a first contact and the other end of the film is connected to the second wiring through a second contact.

8. A display device according to claim 7, wherein the first wiring is connected to an electrode of a light emitting element in the pixel portion.

9. A display device according to claim 7, wherein the first wiring is connected to a wiring in a driving circuit portion.

10. A display device according to claim 7, wherein the first wiring is over the second wiring and extends across the second wiring.

11. A display device according to claim 7, wherein the film is a semiconductor film.

12. A display device comprising: a pixel portion over a substrate; a protective circuit over the substrate; a first wiring and a second wiring over the substrate, the first wiring being over the second wiring; a wiring containing Cu over the first wiring; and an insulating layer over the wiring containing Cu, wherein the protective circuit includes a film forming an alternating stripe pattern, and wherein one end of the film is connected to the first wiring through a first contact and the other end of the film is connected to the second wiring through a second contact.

13. A display device according to claim 12, wherein the first wiring is connected to an electrode of a light emitting element in the pixel portion.

14. A display device according to claim 12, wherein the first wiring is connected to a wiring in a driving circuit portion.

15. A display device according to claim 12, wherein the first wiring is over the second wiring and extends across the second wiring.

16. A display device according to claim 12, wherein the film is a semiconductor film.

17. A display device according to claim 12, wherein the protective circuit is provided between an input terminal portion and a signal line driving circuit.

18. A display device comprising: a pixel portion over a substrate; a film forming an alternating stripe pattern over the substrate at the periphery of the pixel portion; a first wiring and a second wiring over the substrate, the first wiring being over the second wiring; a wiring containing Cu over the first wiring; and an insulating layer over the wiring containing Cu, wherein one end of the film is connected to the first wiring through a first contact and the other end of the film is connected to the second wiring through a second contact.

19. A display device according to claim 18, wherein the first wiring is connected to an electrode of a light emitting element in the pixel portion.

20. A display device according to claim 18, wherein the first wiring is connected to a wiring in a driving circuit portion.

21. A display device according to claim 18, wherein the first wiring is over the second wiring and extends across the second wiring.

22. A display device according to claim 18, wherein the film is a semiconductor film.

23. A display device comprising: a pixel portion over a substrate; a protective circuit over the substrate; a first wiring and a second wiring over the substrate, the first wiring being over the second wiring; a conductive barrier film over the first wiring; and a wiring containing Cu over the conductive barrier film, wherein the protective circuit includes a film forming an alternating stripe pattern1 and wherein one end of the film is connected to the first wiring through a first contact and the other end of the film is connected to the second wiring through a second contact.

24. A display device according to claim 23, wherein the first wiring is connected to an electrode of a light emitting element in the pixel portion.

25. A display device according to claim 23, wherein the first wiring is connected to a wiring in a driving circuit portion.

26. A display device according to claim 23, wherein the first wiring is over the second wiring and extends across the second wiring.

27. A display device according to claim 23, wherein the film is a semiconductor film.

28. A display device according to claim 23, wherein the protective circuit is provided between an input terminal portion and a signal line driving circuit.

29. A display device comprising: a pixel portion over a substrate; a film forming an alternating stripe pattern over the substrate at the periphery of the pixel portion; a first wiring and a second wiring over the substrate, the first wiring being over the second wiring; a conductive barrier film over the first wiring; and a wiring containing Cu over the conductive barrier film, wherein one end of the film is connected to the first wiring through a first contact and the other end of the film is connected to the second wiring through a second contact.

30. A display device according to claim 29, wherein the first wiring is connected to an electrode of a light emitting element in the pixel portion.

31. A display device according to claim 29, wherein the first wiring is connected to a wiring in a driving circuit portion.

32. A display device according to claim 29, wherein the first wiring is over the second wiring and extends across the second wiring.

33. A display device according to claim 29, wherein the film is a semiconductor film.

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Description

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BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device that has a semiconductor element (specifically, a thin film transistor), and also relates to display devices such as an EL display device (a light emitting device) provided with a light emitting element and a liquid crystal display device and a manufacturing method there of, especially, to a large-sized display device and a manufacturing method thereof.

2. Description of the Related Art

These days, it has been proceeded to make a screen have a large size and a high definition in active matrix semiconductor devices such as an EL display device and a liquid crystal display device, and the number of wirings such as signal lines and scan lines tends to increase as well as a length of the wiring. Therefore, it is required to prevent voltage drop due to wiring resistance, trouble in writing of a signal into a pixel, and trouble in gray scales.

In the EL display device, a driving method for displaying an image with multiple gray scales has a voltage input system of inputting voltage from a signal line and a current input system of inputting current from a signal line, and further, the voltage input system has a current writing system of writing data in current format (driving current) into a light emitting element for controlling luminance and a voltage writing system of writing data in voltage format into a light emitting element for controlling luminance while the current input system has the current writing system. Such driving method especially has trouble caused due to wiring resistance. The wiring resistance causes delay in transmission of a signal to a terminal of a signal line, and the voltage drop of a power source line (specifically, a current supply line) makes it difficult to supply predetermined current or voltage. Then, fluctuation in displaying is caused as the result since luminance of light emitted from the light emitting element is proportional to a value of the current or voltage supplied through the signal line. Further, due to the voltage drop, the EL display device and the liquid crystal display device have trouble of waveform distortion of a pulse signal input through the wiring.

In the case of using copper as a material with low resistance for forming a wiring, there is a means of forming a plugged wiring (a structure formed with damascene). In the damascene, however, an insulating film is provided at the position of a wiring to be formed, a groove for forming the wiring is formed in the insulating film, and then a Cu wiring is formed in the groove (for example, Japanese Patent Laid-Open 2000-58650).

Therefore, in conventional display devices, beaten-copper with low resistance is used for a PWB-side wiring of a printed-wiring board (PWB) in electrically connecting the PWB-side wiring to an element-side wiring with an isotropic conductive film instead of a wiring to suppress voltage drop of the element-side wiring and signal delay (for example, Japanese Patent Laid-Open 2001-236025).

SUMMARY OF THE INVENTION

It is an object of the present invention to prevent the above-mentioned influence of the voltage drop due to the wiring resistance, the trouble in writing of driving current into a pixel, and the trouble in gray scales and to provide semiconductor devices with higher definition, represented by an EL display device and a liquid crystal display device. In addition, it is also an object of the present invention to form a wiring with wiring resistance reduced in accordance with fewer processes and provide a semiconductor device that has the wiring with low resistance.

In order to achieve the above objects, a wiring including Cu is formed in the present invention as a wiring or an electrode used for display devices represented by an EL display device and a liquid crystal display device. It is noted that the wiring including Cu includes a wiring in which a wiring containing Cu as its main component (Hereinafter, a Cu wiring) is laminated on a wiring or an electrode with a single-layer structure. Also, it is noted that the wiring including Cu includes a wiring in which a Cu wiring is laminated on a wiring or an electrode with a laminate structure, and includes a structure in which one of layers of a wiring or an electrode with the laminate structure is a Cu wiring. Specifically, a signal line, a scan line, a current supply line, a power source line, a source electrode, a drain electrode, and a gate electrode are included in the wiring or the electrode.

A conductive film named functionally is the wiring or the electrode, for example, assuming a gate electrode, a source electrode, and a drain electrode of a thin film transistor (Hereinafter TFT), a signal line, a scan line, a current supply line, or the like. Since the wiring and the electrode can be obtained when a conductive film is subjected to patterning into a predetermined shape, the wiring and the electrode also collectively mean a conductive film. It is noted that the electrode is not clearly distinguished from the wiring since a portion of the signal line, the scan line, or the current supply line is an electrode.

Such a wiring material Cu diffuses into a semiconductor film and an interlayer insulating film and has a harmful influence on electric characteristics of a TFT. In the present invention, therefore, a barrier film (a barrier layer) is provided at least between an active layer and the Cu wiring in order to prevent penetration of Cu into the active layer (a semiconductor film subjected to patterning into an island-shape) of a TFT.

Such barrier film is formed of a conductive film containing nitrogen or carbon (a conductive barrier film), and one kind or plural kinds of materials selected from tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), tantalum carbide (TaC), and titanium carbide (TiC) may be used. In addition, a ternary-system amorphous barrier film containing Si may be used for the conductive barrier film. The conductive barrier film may be one of layers of the wiring or the electrode.

More preferably, a barrier film formed of an insulating film (an insulating barrier film) containing nitrogen is formed for covering the Cu wiring. One kind or plural kinds of materials selected from silicon nitride (SiN), silicon oxynitride (SiNO), and aluminum nitride (AlN or Al.sub.xN.sub.y), for example, may be used to form the insulating barrier film containing nitrogen.

Further, the Cu wiring of the present invention is formed with sputtering. It is preferable to form at least the conductive barrier film, the Cu wiring, and the insulating barrier film sequentially film with sputtering.

FIGS. 11A to 11D show examples of specific structures of the wiring or the electrode of the present invention, and an explanation will be given with FIGS. 11A to 11D on a structure in which a Cu wiring formed on a conductive barrier film is covered with an insulating barrier film.

A wiring shown in FIG. 11A has a structure in which a conductive film containing Ti, a conductive barrier film containing TiN, and Cu wiring are laminated in order from a substrate side, and an insulating barrier film containing SiN is provided for covering the Cu wiring. Hereinafter, the laminate structure is denoted as Ti/TiN/Cu/SiN from the substrate side. In the case of FIG. 11A, patterning is performed to the conductive film containing Ti and the conductive barrier film containing TiN at the same time, the Cu wiring is formed, and the insulating barrier film containing SiN is formed. Accordingly, a width of the conductive film containing Ti is the same as that of the conductive barrier film containing TiN, and a width of the Cu wiring is shorter than that of the conductive film containing Ti and the conductive barrier film containing TiN. It is noted that the width means a length in a channel length direction.

A wiring shown in FIG. 11B has a structure in which a conductive barrier film containing TiN and an insulating barrier film containing SiN are provided and conductive films of the wiring are laminated. The laminate structure is denoted as Ti/Al/TiN/Cu/SiN from the substrate side. In the case of FIG. 11B, patterning is performed to the conductive film containing Ti, the conductive film containing Al, and the conductive barrier film containing TiN at the same time, the Cu wiring is formed, and the insulating barrier film containing SiN is formed. Accordingly, the conductive film containing Ti, the conductive film containing Al, and the conductive barrier film containing TiN have the same width, and a width of the Cu wiring is shorter than that of the conductive film containing Ti, the conductive film containing Al, and the conductive barrier film containing TiN.

A wiring shown in FIG. 11C has a structure in which a conductive barrier film containing TaN and an insulating barrier film containing SiN are provided, and the laminate structure is denoted as Ti/TaN/Cu/SiN from the substrate side. In the case of FIG. 11C, patterning is performed to the conductive film containing Ti and the conductive barrier film containing TaN at the same time, the Cu wiring is formed, and the insulating barrier film containing SiN is formed. Accordingly, a width of the conductive film containing Ti is the same as that of the conductive barrier film containing TaN, and a width of the Cu wiring is shorter than that of the conductive film containing Ti and the conductive barrier film containing TaN.

A wiring shown in FIG. 11D has a structure in which a conductive barrier film containing WN and an insulating barrier film containing SiNO are provided, and the laminate structure is denoted as Ti/WN/Cu/SiNO from the substrate side. In the case of FIG. 11D, patterning is performed to the conductive film containing Ti and the conductive barrier film containing WN at the same time, the Cu wiring is formed, and the insulating barrier film containing SiNO is formed. Accordingly, a width of the conductive film containing Ti is the same as that of the conductive barrier film containing WN, and a width of the Cu wiring is shorter than that of the conductive film containing Ti and the conductive barrier film containing WN.

In short, the wiring of the present invention is formed in order that the conductive film and the conductive burrier film have the same width and the width of the Cu wiring is shorter than that of the conductive film and the conductive barrier film. The width of the conductive film and the conductive barrier film is on the order of 30 to 40 .mu.m in a pixel portion, and it is preferable that the Cu wiring has a width on the order of 5 to 20 .mu.m and a height on the order of 0.1 to 1 .mu.m.

The wiring including Cu may be used as a source electrode and a drain electrode of a TFT. In this case, a similar structure to the structures of the wirings shown in FIGS. 11A to 11D may be used. Particularly, it is preferred that the wiring including Cu is used for a source electrode and a drain electrode of a TFT for supplying large current (for example, a buffer TFT of a driving circuit portion).

The wiring including Cu may also be used as a gate electrode. In this case, the Cu wiring may be formed on the conductive barrier film to become a part of the gate electrode. It is noted that a scan line formed at the same time as the gate electrode may also be of the wiring including Cu and the Cu wiring may be formed on the conductive barrier film.

Namely, the wiring including Cu of the present invention is applicable to any of wirings and electrodes such as a signal line, a scan line, a current supply line, a source electrode, a drain electrode, and a gate electrode. Since Cu has low resistance and makes it possible to flow large current, it is possible to reduce voltage drop and a deadened signal waveform when the wiring including Cu is used for the wirings and electrodes. In addition, a display device that has a Cu wiring with low resistance can have an area of a wiring and an electrode reduced, and it is possible to achieve a narrowed frame. Further, it is necessary to flow large current into a wiring in a middle-sized and a large sized (5 inch or more) EL display devices and liquid crystal display devices, and therefore the present invention is useful.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIGS. 1A and 1B are diagrams that show a pixel of a display device according to the present invention;

FIGS. 2A to 2C are diagrams that show sectional views of a pixel of a display device according to the present invention;

FIGS. 3A to 3D are diagrams that show sectional views of the pixel of the display device according to the present invention;

FIGS. 4A to 4C are diagrams that show sectional views of the pixel of the display device according to the present invention;

FIGS. 5A to 5C are diagrams that show a display device according to the present invention and a sectional view thereof;

FIGS. 6A to 6C are diagrams that show a display device according to the present invention and a sectional view thereof;

FIGS. 7A to 7C are diagrams that show a display device according to the present invention;

FIG. 8 is a diagram that shows a deposition system for forming a wiring according to the present invention;

FIG. 9 is a diagram that shows a mask for forming a wiring according to the present invention;

FIG. 10 is a diagram that shows a deposition system for forming a wiring according to the present invention;

FIGS. 11A to 11D are diagrams that show wirings according to the present invention;

FIGS. 12A to 12C are diagrams that show electronic devices that use a display device according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiment modes of the present invention will be described below with drawings. In the description below, a transistor has three terminals of a gate electrode, a source electrode, and a drain electrode. However, it is difficult to clearly distinguish between the source electrode and the drain electrode considering a structure of the transistor. In describing a connection between elements, therefore, one of the source electrode and the drain electrode is denoted as a first electrode, and the other is denoted as a second electrode.

Embodiment Mode 1

In the present embodiment mode, the case of applying a wiring including Cu to a signal line and a current supply line will be described with reference to FIGS. 1A to 4C.

FIG. 1A shows an equivalent circuit of a pixel of an EL display device. As shown in FIG. 1A, the pixel has at least a signal line 101, a current supply line 102, a scan line 103, plural TFTs 104 and 105, a capacitor 106, and a light emitting element 107. The TFTs 104 and 105 may have a multi-gate structure such as a double-gate structure or a triple-gate structure instead of a single-gate structure. It is unnecessary to provide the capacitor 106 in the case of having large gate capacities of the TFTs 104 and 105 and leakage current within the allowable range.

Here, it is the signal line 101, the current supply line 102, and the scan line 103 that have trouble due to wiring resistance. It is necessary to consider voltage drop due to the wiring resistance in the signal line 101 and the current supply line 102 particularly as a display device has a larger size. In the present embodiment mode, a wiring including Cu is used as at least the signal line 101 and the current supply line 102.

FIG. 1B shows a top view of FIG. 1A with a pixel electrode (a first electrode of the light emitting element) 107' formed, a Cu wiring 108 is laminated on the signal line 101 and the current supply line 102. The TFT 104 has a first electrode connected to the signal line 101 and a second electrode connected to the capacitor 106 and a gate electrode of the TFT 105, and a portion of the scan line 103 is a gate electrode of the TFT 104. The TFT 105 has a first electrode connected to the pixel electrode 107' and a second electrode connected to the current supply line 102. The capacitor 106 is formed in a region in which the current supply line 102 and a semiconductor film are laminated.

Next, an explanation will be given with FIG. 2A on a structure of a sectional view along A-A' shown in FIG. 1B. FIG. 2A shows a substrate 111 with an insulating surface, and it is possible to use any of a glass substrate, a ceramic substrate, a quartz substrate, a silicon substrate, and a plastic substrate (including a plastic film) as the substrate 111. On the substrate 111, a silicon oxynitride film 112a and a silicon oxynitride film 112b are laminated as a base film. Of course, it is not necessary to limit a material of the base film to silicon oxynitride. Further, a semiconductor film 113 for an active layer of the TFT 105 and for the capacitor 106 is provided on the silicon oxynitride film 112b.

The semiconductor film 103 of the TFT 105 is covered with a gate insulating film 114, and a gate electrode of a laminate of tantalum nitride (TaN) 115 and tungsten (W) 116 is provided thereon. Although a silicon oxynitride film is used as the gate insulating film 114 in the present embodiment mode, it is useful in terms of improving an integration level to use a nitrided insulating film with a high relative dielectric constant such as an aluminum nitride film since an element space required can be reduced. Although the metal films of the gate electrode have large selection ratios each other, such structure becomes possible when etching conditions are optimized. With respect to the etching conditions, it may be possible to refer to Japanese Patent Laid-Open 2001-313397 by the present applicant. The gate electrode or resist is used as a mask to form a source region, a drain region, and a channel forming region in the semiconductor film 113. In addition, an LDD region and a GOLD region overlapped with the gate electrode may appropriately be formed. It is noted that the source region, the drain region, the LDD region, or the GOLD region, into which an impurity is doped, is denoted as an impurity region. Further, a heating furnace or laser is used to activate the impurity region.

Besides, a silicon nitride film or silicon oxynitride film is provided as an insulating film 117 covering the gate electrode. In the present embodiment mode, a silicon oxynitride film is formed with plasma CVD. In addition, for planarization, a photosensitive or non-photosensitive organic material (polyimide, acrylic, polyamide, polyimideamide, resist, or benzocyclobutene), an inorganic material (such as silicon oxide, silicon nitride, or silicon oxynitride) formed with sputtering, CVD, or coating, or a laminate thereof is used to form a first insulating film 118 as an interlayer insulating film on the insulating film 117.

On the first insulating film 118, a first passivation film 119 including a nitrided insulating film (typically, a silicon nitride film or a silicon oxynitride film) is formed. In the present embodiment mode, a silicon nitride film is used for the first passivation film 119. After that, a contact (an opening portion) in the first passivation film 119, the first insulating film 118, the insulating film 117, and the gate insulating film 114 with wet etching or dry etching.

It is noted that the contact shown in FIG. 2A and provided in the interlayer insulating film has a tapered shape in which a diameter becomes smaller toward the bottom and an angle made by a top surface of the interlayer insulating film and a slope of the contact (a corner portion of the contact) is on the order of 95 to 135 degree. In the contact, a drain electrode or a source electrode (Hereinafter, an electrode collectively) 120 is formed to be connected a source region or a drain region. At this time, patterning of the same layer is performed to form the signal line 101 and the current supply line 102 at the same time. In the present embodiment mode, the electrode, the signal line, and the current supply line are formed of a laminate film of Ti/Al/TiN, and the conductive film including TiN functions as a conductive barrier film.

Then, DC sputtering with a mask is employed to form the Cu wiring 108 on the signal line 101 and the current supply line 102. Note that it is possible to refer to Embodiment Mode 4 on detailed forming processes.

As mentioned above, the Cu wiring is formed on the signal line and the current supply line to obtain the wring including Cu as the signal line and the current supply line.

FIG. 2B shows a different structure from that of FIG. 2A in which the corner portion of the contact has the tapered shape with the angle. In FIG. 2B, a contact has a corner portion rounded and a diameter that becomes smaller toward the bottom. As a material of an interlayer insulating film in this case, a photosensitive or non-photosensitive organic material (polyimide, acrylic, polyamide, polyimideamide, resist, or benzocyclobutene) may be used. Then, wet etching or dry etching may be performed after exposure to form the structure with the contact. In the case of using the photosensitive organic material, however, exposure is carrier out to form the contact without etching. After providing the contact in the interlayer insulating film, the first passivation film 119 is formed.

Further, FIG. 2C has a contact with another different tapered shape, and the contact has a corner portion rounded and a slope with two or more different curvature radiuses. As a material of an interlayer insulating film in this case, a photosensitive or non-photosensitive organic material (polyimide, acrylic, polyamide, polyimideamide, resist, or benzocyclobutene) may be used. Then, wet etching or dry etching may be performed after exposure to form the structure with the contact. In the case of using the photosensitive organic material, however, exposure is carried out to form the contact without etching. After providing the contact in the interlayer insulating film, the first passivation film 119 is formed.

The shape of the contact in the interlayer insulating film, shown in each of FIGS. 2A to 2C, makes it possible to prevent breaking of the wiring 102 of the capacitor 106 and the wiring 120 provided for the TFT 105.

Then, an insulating barrier film 204 for covering the Cu wiring 108 is preferably formed as shown in FIG. 3A. In order to form the insulating barrier film 204, a material such as silicon nitride (SiN) or silicon oxynitride (SiNO) may be used. In the present embodiment mode, a film containing silicon nitride is formed with high frequency sputtering. Note that it is possible to refer to Embodiment Mode 4 on detailed forming processes. Since the Cu wiring is covered with the insulating barrier film 204, the risk of diffusion of Cu into the semiconductor film is further reduced.

Then, a photomask is used to form an opening portion in the insulating barrier film 204, and the pixel electrode 107' is formed to cover the opening portion. The pixel electrode 107' is connected to the wiring 120 through the opening portion.

It is noted that structures shown in FIG. 3B and FIG. 3C are different from that of FIG. 3A in a forming order of the wiring 120, the insulating barrier film 204 and the pixel electrode 107' or a forming process of the opening portion in the insulating barrier film 204.

The structure shown in FIG. 3B is different from that of FIG. 3A in the forming order. In the case of forming the structure of FIG. 3B, the wiring 120, the signal line 101, and the current supply line 102 are formed after providing the pixel electrode 107', the Cu wiring 108 is formed on the signal line 101 and the current supply line 102, the insulating barrier film 204 is formed next, and then the opening portion is provided in the insulating barrier film 204 lastly.

In the case of forming the structure of FIG. 3C, along with the case of forming the structure of FIG. 3A, the wiring 120, the signal line 101, and the current supply line 102 are formed, the Cu wiring 108 is formed on the signal line 101 and on the current supply line 102, and the insulating barrier film 204 is formed. After that, differently from the case of FIG. 3A, an insulating film 118' as a second interlayer insulating film is formed and a second passivation film 119' is formed on the insulating film 118'. Then, an opening portion is provided in the insulating film 118' and the second passivation film 119', the pixel electrode 107' is provided in the opening portion to be connected to the wiring 120. It is noted that the insulating film 118' may be formed of the same material with the same means as the first insulating film 118 and the second passivation film 119' may be formed of the same material with the same means as the first passivation film 119.

Further, a structure shown in FIG. 3D is different from those of FIGS. 3A to 3C since a manufacturing method of the insulating barrier film 204 in FIG. 3A is different from that of the insulating barrier film 204 in FIGS. 3A to 3C. In the case of forming the structure shown in FIG. 3D, the insulating barrier film 204 is formed with a mask to cover at least the Cu wiring 108 after forming the Cu wiring 108. Accordingly, it is unnecessary to provide the opening portion in the insulating barrier film 204 with the photomask.

In the case of the structure of FIG. 3D, a conductive barrier film may be used instead of the insulating barrier film 204. This is because insulation between the pixel electrode and the conductive barrier film is ensured with a second insulating film later formed. Since the conductive barrier film has smaller capacitance compared to the insulating barrier film, the Cu wiring covered with the conductive barrier film entirely is suitable for a high-speed operation.

It is noted that it is possible to apply the above-mentioned structure of the insulating barrier film 204 shown in FIG. 3D and the manufacturing method thereof to the cases of FIGS. 3A to 3C, and it becomes possible to use a conductive barrier film instead of the insulating barrier film 204.

Next, an explanation will be given with reference to FIGS. 4A to 4C on processes of providing a second insulating film that functions as a bank (also called a partition, or a barrier), forming an opening portion in the second insulating film on the pixel electrode, and providing a light emitting layer and the second electrode in the pixel electrode.

In FIG. 4A, a second insulating film 205 is formed at both ends of the pixel electrode 107' of the structure shown in FIG. 3A. A photosensitive or non-photosensitive organic material (polyimide, acrylic, polyamide, polyimideamide, resist, or benzocyclobutene), an inorganic material (such as silicon oxide, silicon nitride, or silicon oxynitride) formed with sputtering, CVD, or coating, or a laminate thereof is used to form the second insulating film 205. In the case of a photosensitive organic material for the second insulating film 205, one of two kinds of photosensitive organic materials classified roughly, a negative photosensitive organic material that becomes insoluble in an etchant with light or a positive photosensitive organic material that becomes soluble in an etchant with light, is appropriately used, an opening portion is formed on the pixel electrode 107', and the second insulating film 205 is formed at both ends of the pixel electrode 107'.

After that, a light emitting layer 206 including an organic compound is formed in the opening portion, and a second electrode 207 is formed on the light emitting layer 206. It is preferable to perform heating under vacuum for degassing before or after forming the light emitting layer 206 including the organic compound. Also, it is preferable that a surface of the first electrode is planarized since the light emitting layer 206 including the organic compound is extremely thin, and for example, planarization may be performed with treatment of chemical mechanical polishing (typically, CMP) before or after patterning of the first electrode. In addition, cleaning (brush cleaning or bellclean cleaning) for cleaning foreign particles (such as dusts) may be performed in order to improve cleanness of the surface of the pixel electrode.

It is noted that the opening portion (contact) of the second insulating film 205, shown in FIG. 4A, has a tapered shape in which a diameter become smaller toward the bottom and an angle made by a top surface of the second insulating film 205 and a slope of the contact (a corner portion of the contact) is on the order of 95 to 135 degree.

A structure shown in FIG. 4B is different from that in FIG. 4A in which the corner portion of the contact has the tapered shape with the degree. In FIG. 4B, a contact has a corner portion rounded and a diameter that becomes smaller toward the bottom. As a material of the second insulating film 205, a photosensitive or non-photosensitive organic material (polyimide, acrylic, polyamide, polyimideamide, resist, or benzocyclobutene) may be used. Then, wet etching or dry etching may be employed after exposure to form the contact. In the case of using the photosensitive organic material, however, exposure is performed to form the contact without etching.

Further, another different tapered shape of a contact is shown in FIG. 4C. The contact has a corner portion rounded and a slope with at least two different curvature radiuses R1 and R2. As a material of the second insulating film 205, a photosensitive or non-photosensitive organic material (polyimide, acrylic, polyamide, polyimideamide, resist, or benzocyclobutene) may be used. Then, wet etching or dry etching may be employed after exposure to form the contact. In the case of using the photosensitive organic material, however, exposure is performed to form the contact without etching.

Although FIGS. 4A to 4C is described based on the structure shown in FIG. 3A, it is possible to combine any of the structures shown in FIGS. 3B to 3D, and further FIGS. 2B and 2C.

Although the case of the display device that has the light emitting element is described in the present embodiment mode, it is needless to say that the wiring including Cu may be used as a signal line, an electrode, and other wiring in a display device that has a liquid crystal element.

As mentioned above, in the present embodiment mode, the wiring including Cu is used as the wiring represented by the signal line or current supply line, specifically, the wiring structure in which the Cu wiring is provided on the wiring is used. Accordingly, the Cu wiring is allocable to structures and manufacturing processes of all TFTs, pixel electrodes, and wirings.

Further, when the wiring including Cu is used in the present embodiment mode, it becomes possible to reduce voltage drop and around of a signal waveform. Additionally, it is possible to reduce an area of the wiring and the electrode and to achieve a narrowed frame in the display device that has the wiring including Cu with low resistance.

Embodiment Mode 2

In the present embodiment mode, an example in which a wiring including Cu is applied to a gate electrode will be described with reference to FIG. 5A to 5C.

FIG. 5A shows an equivalent circuit of a pixel in an EL display device. As shown in FIG. 5A, the pixel has at least a signal line 601, a current supply line 602, a scan line 603, plural TFTs 604 and 605, a capacitor 606, and a light emitting element 607. It is noted that the TFTs 604 and 605 may have a multi-gate structure such as a double-gate structure or a triple-gate structure instead of a single-gate structure.

Further, FIG. 5B shows a top view of FIG. 5A in which a pixel electrode (a first electrode of the light emitting element) 607' is formed, and has the signal line 601, the current supply line 602, the scan line 603, TFTs 604 and 605, the capacitor 606, and the pixel electrode 607' of the light emitting element. A Cu wiring 608 is provided on the can line 603 and a gate electrode of the TFT 604, that is on the wiring formed of the same layer as the gate electrode.

FIG. 5C shows a sectional view along B-B' in FIG. 5B. Similarly to FIG. 2C, a substrate with an insulating surface 611, a silicon oxynitride film 612a and a silicon oxynitride film 612b as a base film, a semiconductor film 613 of the TFTs 604 and 605 are provided. Then, a gate insulating film 614 is provided to cover the semiconductor film 613, and a conductive barrier film 615 and the Cu wiring 608 are formed over the semiconductor film 613. Namely, the present embodiment mode is characterized in that the wiring including Cu is used as the gate electrode. It is be possible to refer to Embodiment Mode 4 on forming processes of the wiring including Cu. The conductive barrier film 615 is formed using one selected from tantalum nitride (TaN), titanium nitride (TiN), and tungsten nitride (WN) or a laminate film of plurality thereof, and has a function as a protective film for preventing penetration of Cu due to diffusion into the semiconductor film 613. The same layer as the gate electrode is subjected to patterning to form the scan line 603 at the same time in addition to the gate electrode. That is, the scan line 603 has a laminate structure of the conductive barrier film and the Cu wiring.

Then, a source region, a drain region, and a channel forming region are formed in the semiconductor film 613 with gate electrode or resist as a mask. Additionally, an LDD region and a GOLD region overlapped with the gate electrode may appropriately be formed. It is noted that the source region, the drain region, the LDD region, or the GOLD region, into which an impurity is doped, is denoted as an impurity region. As an insulating film 617 covering the gate electrode, a silicon nitride film or a silicon oxynitride film is provided. The insulating film 617 functions as an insulating barrier film.

In order to activate the impurity regions, heating furnace or laser is used. At this time, it is preferable to irradiate laser (for example, excimer laser) from a back surface (a backside of the side with the semiconductor film formed) of the substrate for the activation in order to prevent Cu from diffusing to penetrate into the semiconductor film due to heating in the activation. More preferably, the impurity regions are formed after forming the conductive barrier film 615, the heating furnace or laser is used to activate the impurity regions, and then the Cu wiring 608 is formed.

In addition, for planarization, a photosensitive or non-photosensitive organic material (polyimide, acrylic, polyamide, polyimideamide, resist, or benzocyclobutene), an inorganic material (such as silicon oxide, silicon nitride, or silicon oxynitride) formed with sputtering, CVD, or coating, or a laminate thereof is used to form an interlayer insulating film 618 on the insulating film 617.

On the interlayer insulating film 618, a first passivation film 619 including a nitrided insulating film (typically, a silicon nitride film or a silicon oxynitride film) is formed. In the present embodiment