Title: Display panel driving method with selectable driving pattern
Abstract: A display panel driving method that is capable of displaying images with false contours suppressed and without the occurrence of flicker, even when the vertical sync frequency of the input image signal is low. When an image signal with a low mean brightness level is input, or when an image signal having a comparatively high vertical sync frequency is input, light emission elements comprised by pixels are caused to emit light in a number of continuous subfields corresponding to the brightness level expressed by the input image signal in one field. If an image signal is input in which the mean brightness level is high, and in addition the vertical sync frequency is comparatively low, light emission elements are caused to emit light in a number of continuous subfields corresponding to the brightness level expresses by the image signal, in each of the first half and the second half of a field.
Patent Number: 6,982,732 Issued on 01/03/2006 to Suzuki
| Inventors:
|
Suzuki; Masahiro (Yamanashi, JP)
|
| Assignee:
|
Pioneer Corporation (Tokyo, JP);
Shizuoka Pioneer Corporation (Shizuoka, JP)
|
| Appl. No.:
|
163593 |
| Filed:
|
June 7, 2002 |
Foreign Application Priority Data
| Jun 15, 2001[JP] | 2001-181109 |
| Current U.S. Class: |
345/693; 345/691; 345/690 |
| Current Intern'l Class: |
G09G 5/02 (20060101) |
| Field of Search: |
345/60,63,87-89,690-693
|
References Cited [Referenced By]
U.S. Patent Documents
Primary Examiner: Chow; Dennis-Doon
Assistant Examiner: Sheng; Tom
Attorney, Agent or Firm: Sughrue Mion, PLLC
Claims
What is claimed is:
1. A display panel driving method for performing emission driving of each of
light emission elements in a display panel in which the display screen is formed
by a plurality of said light emission elements in each of N subfields constituting
one field interval of the input image signal; wherein light emissions in said N
subfields are performed in such a way that a light emitting state is produced in
said N subfields in an ascending order of weightings of the subfields, in which
in order to realize an m-th grayscale level (where m is a natural number from 1
to N+1), light emission is performed in one subfield in addition to subfields in
which light emission is performed to realize an (m-1)th grayscale level, and according
to at least one of the magnitude of the vertical sync frequency of said input image
signal and the mean brightness of the screen expressed by said input image signal,
switching between first and second emission driving sequences is performed, wherein
said first emission driving sequence begins with a reset step provided in a head
subfield, to display intermediate brightnesses in N+1 stages, from a first grayscale
to an (N+1)th grayscale, by causing emission of said light emission elements in
each of n (where n is an integer from 0 to N) of said subfields continuously within
said field interval, in a number corresponding to the brightness level expressed
by said input image signal, and
said second emission driving sequences comprises first and second halves of said
field interval each of which begins with a reset step provided in a head subfield,
in which at least a pair of subfields, which have weighting values adjoining in
an order of the subfields' weightings, are arranged at an interval of nearly one-half
of said field interval, and in which, after causing emission of said light emission
elements in each of said continuous subfields in the first half of said field interval,
in a number corresponding to the brightness level expressed by said input image
signal, said light emission elements are caused to emit in each of said continuous
subfields in the second half of said field interval, in a number corresponding
to the brightness level expressed by said input image signal, whereby intermediate
brightness is displayed in N+1 stages, from a first grayscale to an (N+1)th grayscale.
2. The display panel driving method according to claim 1, wherein the time between
the moment of initiation of emission in said first-half interval, and the moment
of initiation of emission in said second-half interval, is substantially one-half
of said field interval.
3. The display panel driving method according to claim 1, wherein, said first
emission driving sequence is executed when said vertical sync frequency of said
input image signal is higher than a prescribed frequency, or when said mean brightness
is lower than a prescribed brightness, and when said vertical sync frequency is
lower than said prescribed frequency and in addition said mean brightness is higher
than said prescribed brightness, said second emission driving sequence is executed.
4. The display panel driving method according to claim 1, wherein said second
emission driving sequence comprises:
a first reset sequence, which initializes all of said light emission elements
to the lit state only in said leading subfield in said first-half interval; a first
address sequence, which sets each of said light emission elements to either said
lit state or to the extinguished state in one of said subfields within said first-half
interval according to said input image signal; a first emission sustain sequence,
in which, in each of said subfields in said first-half interval, only those of
said light emission elements which are in said lit state are caused to emit a number
of times corresponding to the weighting of said subfield;
a second reset sequence, which initializes all of said light emission elements
to the lit state only in said leading subfield in said second-half interval; a
second address sequence, which sets each of said light emission elements to either
said lit state or to the extinguished state in one of said subfields within said
second-half interval according to said input image signal; and a second emission
sustain sequence, in which, in each of said subfields in said second-half interval,
only those of said light emission elements which are in said lit state are caused
to emit a number of times corresponding to the weighting of said subfield.
5. The display panel driving method according to claim 1, wherein:
when said number N is an even number, at said first grayscale said light emission
elements are not caused to emit in any of said subfields; at the second grayscale,
said light emission elements are caused to emit only in said leading subfield of
either said first-half interval or said second-half interval; at the third grayscale,
said light emission elements are caused to emit, in addition to the subfield executed
at the second grayscale, only in said leading subfield of the other half, among
said first-half interval and said second-half interval; at the fourth grayscale,
said light emission elements are caused to emit, in addition to the subfields executed
at the third grayscale, in the subfield arranged second in either said first-half
interval or in said second-half interval; at the Nth grayscale, said light emission
elements are caused to emit, in addition to the subfields executed at the (N-1)th
grayscale, in the last of said subfields in either said first-half interval or
in said second-half interval; and at the (N+1)th grayscale, said light emission
elements are caused to emit, in addition to the subfields executed at the Nth grayscale,
in the last of said subfields of the other half, among said first-half interval
and said second-half interval; and,
when said number N is an odd number, at said first grayscale said light emission
elements are not caused to emit in any of said subfields; at the second grayscale,
said light emission elements are caused to emit only in said leading subfield of
either said first-half interval or said second-half interval; at said third grayscale,
said light emission elements are caused to emit, in addition to the subfield executed
at said second grayscale, only in said leading subfield of the other half, among
said first-half interval and said second-half interval; at the fourth grayscale,
said light emission elements are caused to emit, in addition to the subfields executed
at said third grayscale, in the subfield arranged second in either said first-half
interval or in said second-half interval; at the Nth grayscale, said light emission
elements are caused to emit, in addition to the subfields executed at the (N-1)th
grayscale, in the last of said subfields in one of said first-half interval or
said second-half interval; and at the (N+1)th grayscale, said light emission elements
are caused to emit, in addition to the subfields executed at the Nth grayscale,
in the last of said subfields of the other half, among said first-half interval
and said second-half interval.
6. The display panel driving method according to claim 1, wherein:
when said number N is an even number, at said first grayscale said light emission
elements are not caused to emit in any of said subfields; at the second grayscale,
said light emission elements are caused to emit only in the last subfield of either
said first-half interval or said second-half interval; at the third grayscale,
said light emission elements are caused to emit, in addition to the subfield executed
at the second grayscale, only in the last subfield of the other half, among said
first-half interval and said second-half interval; at the fourth grayscale, said
light emission elements are caused to emit, in addition to the subfields executed
at the third grayscale, in the subfield arranged second to last in either said
first-half interval or in said second-half interval; at the Nth grayscale, said
light emission elements are caused to emit, in addition to the subfields executed
at the (N-1)th grayscale, in the first of said subfields in either said first-half
interval or in said second-half interval; and at the (N+1)th grayscale, said light
emission elements are caused to emit, in addition to the subfields executed at
the Nth grayscale, in the first of said subfields of the other half, among said
first-half interval and said second-half interval; and,
when said number N is an odd number, at said first grayscale said light emission
elements are not caused to emit in any of said subfields; at the second grayscale,
said light emission elements are caused to emit only in the last subfield of either
said first-half interval or said second-half interval; at the third grayscale,
said light emission elements are caused to emit, in addition to the subfield executed
at said second grayscale, only in the last subfield of the other half, among said
first-half interval and said second-half interval; at the fourth grayscale, said
light emission elements are caused to emit, in addition to the subfields executed
at said third grayscale, in the subfield arranged second to last in either said
first-half interval or in said second-half interval; at the Nth grayscale, said
light emission elements are caused to emit, in addition to the subfields executed
at the (N-1)th grayscale, in the first of said subfields in one of said first-half
interval or said second-half interval; and at the (N+1)th grayscale, said light
emission elements are caused to emit, in addition to the subfields executed at
the Nth grayscale, in the first of said subfields of the other half, among said
first-half interval and said second-half interval.
7. The display panel driving method according to claim 1, wherein said first
emission driving sequence begins with said reset step provided only in said head subfield.
8. The display panel driving method according to claim 1, wherein said N is a
constant value.
9. A method for driving light emission elements in a display panel, wherein N
subfields constitutes one field interval of an input image signal, comprising:
performing light emission in said N subfields in an ascending order of weightings
of the subfields;
realizing an m-th grayscale level (where m is a natural number from 1 to N+1)
by performing light emission in one subfield in addition to performing light emission
in subfields to realize an (m-1)th grayscale level;
switching between first and second emission driving sequences according to at
least one of a magnitude of a vertical sync frequency of said input image signal
and a mean brightness of the display panel expressed by said input image signal,
wherein said first emission driving sequence comprises resetting a head subfield
to display intermediate brightnesses in N+1 stages, from a first grayscale to an
(N+1)th grayscale, by performing light emission in each of n of said subfields
continuously within said field interval, in a number corresponding to the brightness
level expressed by said input image signal,
wherein n is an integer from 0 to N), and
wherein said second emission driving sequence comprises:
in a first half of said field interval, resetting a head subfield, in which at
least a pair of subfields, which have weighting values adjoining in an order of
the subfields' weightings, are arranged at an interval of nearly one-half of said
field interval,
performing light emission in each of said continuous subfields in the first half
of said field interval, in a number corresponding to the brightness level expressed
by said input image signal,
after performing said light emission in each of said continuous subfield in said
second emission driving sequence, performing light emission in each of said continuous
subfields in the second half of said field interval, in a number corresponding
to the brightness level expressed by said input image signal, wherein intermediate
brightness is displayed in N+1 stages, from a first grayscale to an (N+1)th grayscale.
10. The display panel driving method according to claim 9, wherein the time between
the moment of initiation of emission in said first-half interval, and the moment
of initiation of emission in said second-half interval, is substantially one-half
of said field interval.
11. The display panel driving method according to claim 9, wherein said first
emission driving sequence is executed when said vertical sync frequency of said
input image signal is higher than a prescribed frequency, or when said mean brightness
is lower than a prescribed brightness, and when said vertical sync frequency is
lower than said prescribed frequency and said mean brightness is higher than said
prescribed brightness, said second emission driving sequence is executed.
12. The display panel driving method according to claim 9, wherein said second
emission driving sequence comprises:
a first reset sequence, which initializes all of said light emission elements
to the lit state only in said leading subfield in said first-half interval;
a first address sequence, which sets each of said light emission elements to
either said lit state or to the extinguished state in one of said subfields within
said first-half interval according to said input image signal;
a first emission sustain sequence, in which, in each of said subfields in said
first-half interval, only those of said light emission elements which are in said
lit state are caused to emit a number of times corresponding to the weighting of
said subfield;
a second reset sequence, which initializes all of said light emission elements
to the lit state only in said leading subfield in said second-half interval;
a second address sequence, which sets each of said light emission elements to
either said lit state or to the extinguished state in one of said subfields within
said second-half interval according to said input image signal; and
a second emission sustain sequence, in which, in each of said subfields in said
second-half interval, only those of said light emission elements which are in said
lit state are caused to emit a number of times corresponding to the weighting of
said subfield.
13. The display panel driving method according to claim 9, wherein:
when said number N is an even number, at said first grayscale said light emission
elements are not caused to emit in any of said subfields; at the second grayscale,
said light emission elements are caused to emit only in said leading subfield of
either said first-half interval or said second-half interval; at the third grayscale,
said light emission elements are caused to emit, in addition to the subfield executed
at the second grayscale, only in said leading subfield of the other half, among
said first-half interval and said second-half interval; at the fourth grayscale,
said light emission elements are caused to emit, in addition to the subfields executed
at the third grayscale, in the subfield arranged second in either said first-half
interval or in said second-half interval; at the Nth grayscale, said light emission
elements are caused to emit, in addition to the subfields executed at the (N-1)th
grayscale, in the last of said subfields in either said first-half interval or
in said second-half interval; and at the (N+1)th grayscale, said light emission
elements are caused to emit, in addition to the subfields executed at the Nth grayscale,
in the last of said subfields of the other half, among said first-half interval
and said second-half interval; and,
when said number N is an odd number, at said first grayscale said light emission
elements are not caused to emit in any of said subfields; at the second grayscale,
said light emission elements are caused to emit only in said leading subfield of
either said first-half interval or said second-half interval; at said third grayscale,
said light emission elements are caused to emit, in addition to the subfield executed
at said second grayscale, only in said leading subfield of the other half, among
said first-half interval and said second-half interval; at the fourth grayscale,
said light emission elements are caused to emit, in addition to the subfields executed
at said third grayscale, in the subfield arranged second in either said first-half
interval or in said second-half interval; at the Nth grayscale, said light emission
elements are caused to emit, in addition to the subfields executed at the (N-1)th
grayscale, in the last of said subfields in one of said first-half interval or
said second-half interval; and at the (N+1)th grayscale, said light emission elements
are caused to emit, in addition to the subfields executed at the Nth grayscale,
in the last of said subfields of the other half, among said first-half interval
and said second-half interval.
14. The display panel driving method according to claim 9, wherein:
when said number N is an even number, at said first grayscale said light emission
elements are not caused to emit in any of said subfields; at the second grayscale,
said light emission elements are caused to emit only in the last subfield of either
said first-half interval or said second-half interval; at the third grayscale,
said light emission elements are caused to emit, in addition to the subfield executed
at the second grayscale, only in the last subfield of the other half, among said
first-half interval and said second-half interval; at the fourth grayscale, said
light emission elements are caused to emit, in addition to the subfields executed
at the third grayscale, in the subfield arranged second to last in either said
first-half interval or in said second-half interval; at the Nth grayscale, said
light emission elements are caused to emit, in addition to the subfields executed
at the (N-1)th grayscale, in the first of said subfields in either said first-half
interval or in said second-half interval; and at the (N+1)th grayscale, said light
emission elements are caused to emit, in addition to the subfields executed at
the Nth grayscale, in the first of said subfields of the other half, among said
first-half interval and said second-half interval; and,
when said number N is an odd number, at said first grayscale said light emission
elements are not caused to emit in any of said subfields; at the second grayscale,
said light emission elements are caused to emit only in the last subfield of either
said first-half interval or said second-half interval; at the third grayscale,
said light emission elements are caused to emit, in addition to the subfield executed
at said second grayscale, only in the last subfield of the other half, among said
first-half interval and said second-half interval; at the fourth grayscale, said
light emission elements are caused to emit, in addition to the subfields executed
at said third grayscale, in the subfield arranged second to last in either said
first-half interval or in said second-half interval; at the Nth grayscale, said
light emission elements are caused to emit, in addition to the subfields executed
at the (N-1)th grayscale, in the first of said subfields in one of said first-half
interval or said second-half interval; and at the (N+1)th grayscale, said light
emission elements are caused to emit, in addition to the subfields executed at
the Nth grayscale, in the first of said subfields of the other half, among said
first-half interval and said second-half interval.
15. The display panel driving method according to claim 9, wherein said first
emission driving sequence begins with said reset step provided only in said head subfield.
16. The display panel driving method according to claim 9, wherein said N is
a constant value.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method for driving a display panel in which are
arranged light emission (hereinafter, simply referred to as "emission") elements
having only two states, emitting and non-emitting.
2. Description of the Related Art
With the rend toward display device with larger screens in recent years, displays
with thinner shapes have been sought. AC-discharge type plasma display panels have
attracted attention as one thin-type display device.
FIG. 1 shows in summary the configuration of a plasma display device equipped
with such a plasma display panel.
In FIG. 1, the plasma display panel PDP
10 comprises m column electrodes
D
1 to D
m, as data electrodes, and n row electrodes X
1
to X
n and Y
1 to Y
n, arranged to intersect
each of the column electrodes. Each of the pairs X and Y of row electrodes corresponds
to a row of the screen. These column electrodes D and row electrodes X and Y are
formed on two glass substrate s, arranged in opposition and enclosing a discharge
space into which is injected a discharge gas. At the portions of intersection of
each of the row electrodes and column electrodes, discharge cells serving as display
elements corresponding to individual pixels are formed.
Because the discharge cells utilize a discharge phenomenon, they have only
two states, "emitting" and "non-emitting". That is, discharge cells are capable
of representing only the brightnesses of two grayscales, at the minimum brightness
(the non-emitting state) and at the maximum brightness (the emitting state). The
driving device
100 executes grayscale driving of the above PDP
10,
in which such discharge cells are arranged in a matrix shape, using a subfield
method in which intermediate grayscale brightnesses corresponding to input image
signals are represented.
In the subfield method, the display interval for one subfield is divided into,
for example, eight subfields SF
1 to SF
8, as shown in FIG. 2. To each
of these subfields SF
1 to SF
8 is allocate d a number of times emission
is to be executed within that subfield. Hence by changing the combination of the
subfields during which emission is executed and the subfields during which emission
is not executed based on the input image signal, emission is executed, within the
display interval of one field, a number of times corresponding to the brightness
level of the input image signal. As a result, an intermediate brightness is perceived
corresponding to the total number of emissions executed within the field display
interval in question.
FIG. 3 is a figure showing one example of emission driving pattern is, indicating
combinations of subfields for which emission is executed and subfields for which
emission is not executed.
The driving device
100 selects one emission driving pattern from among
the nine types shown in FIG. 3, according to the input image signal. The different
driving pulses are applied to the column electrodes D and row electrodes X and
Y of the PDP
10 so as to execute emission for the number of times shown
in FIG. 2 only in those subfields indicated by white circles in the selected emission
driving pattern.
Through the nine types of emission driving patterns shown in FIG. 3, images
can be displayed having nine intermediate brightnesses, with emission brightness
ratios of 0, 1, 7, 23, 47, 82, 128, 185, and 255.
Here, by means of the emission driving patterns shown in FIG. 3, after first
putting a discharge cell in the non-emitting state in one subfield within a field
interval, emission is not executed again in subsequent subfields. That is, as indicated
by the white circles, emission driving patterns wherein subfields in which emission
is executed continuously (hereafter called the "continuous emission state") and
subfields in which the extinguished state is continuous (hereafter called the "continuous
extinguished state") alternate within a single field interval are excluded. As
a result, so-called false contours, occurring on the boundaries of two image regions
in which the above continuous emission state and the above continuous extinguished
state alternate, is suppressed.
In an emission driving pattern like that shown in FIG. 3, the frequency of switching
between the above continuous emission state and the above continuous extinguished
state is equal to the vertical sync frequency which determines the display interval
for a single field. Hence there is concern that when a PAL television signal, which
has only a 50 Hz vertical sync frequency, may be supplied as the input image signal,
and when the brightness levels represented by this image signal are comparatively
high, flicker may occur.
SUMMARY OF THE INVENTION
The present invention was devised in consideration of this problem, and has as
an object the provision of a display panel driving method which is capable of image
display with false contours suppressed, without the occurrence of flicker even
when the vertical sync frequency of the input image signal is low.
The display panel driving method of this invention is a method for driving a
display panel in which, in a display panel which forms a display screen by means
of a plurality of emission elements, each of the above emission elements is driven
to emit light in each of N subfields constituting one field interval of an input
image signal. In this method, depending on the vertical sync frequency of the above
input image signal and the mean image brightness represented by the above input
image signal, either a first emission driving sequence is executed, in which intermediate
brightnesses are represented for each of N+1 gradations, from the first grayscale
to the (N+1)th grayscale, by causing the above emission elements to emit in n (where
n is an integer from 0 to N) of the above subfields which are continuous within
the above one field interval, corresponding to the brightness level represented
by the above input image signal; or, a second emission driving sequence is executed,
in which intermediate brightnesses are represented for each of N+1 gradations,
from the first grayscale to the (N+1)th grayscale, by using the above emission
elements to emit during the first half of the above field period in each of the
above subfields which are continuous, corresponding to the brightness level represented
by the above input image signal, and then, in the second half of the field period,
causing the above emission elements to emit in each of the above subfields which
are continuous, corresponding to the brightness level represented by the above
input image signal.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a figure showing in summary the configuration of a plasma display device;
FIG. 2 is a figure showing one example of an emission driving format, based
on the subfield method;
FIG. 3 is a figure showing one example of an emission driving pattern;
FIG. 4 is a figure showing the configuration of a plasma display device which
drives a plasma display panel according to a driving method of this invention;
FIG. 5 is a figure showing the internal configuration of the data conversion
circuit 30;
FIG. 6 is a figure showing the data conversion characteristic in the first data
conversion circuit 32;
FIG. 7 is a figure showing one example of a data conversion table, based on
the data conversion characteristic shown in FIG. 6;
FIG. 8 is a figure showing one example of a data conversion table, based on
the data conversion characteristic shown in FIG. 6;
FIG. 9 is a figure showing the internal configuration of the multi-graycale
processing circuit 33;
FIG. 10 is a figure used to explain the operation of the error diffusion processing
circuit 330;
FIG. 11 is a figure showing the internal configuration of the dither Processing
circuit 350;
FIG. 12 is a figure used to explain the operation of the dither processing circuit 350;
FIG. 13 is a figure showing a data conversion table used in the second data
conversion circuit 34, and an emission driving pattern;
FIG. 14 is a figure showing a data conversion table used in the second data
conversion circuit 35, and an emission driving pattern;
FIG. 15 is a figure showing one example of an emission driving format (based
on the selective erasing address method) during first emission driving, adopted
when the vertical sync frequency of the input image signal is equal to or higher
than a prescribed frequency, or when the brightness level of the input image signal
is comparatively low;
FIG. 16 is a figure showing on example of an emission driving format (based
on the selective erasing address method) during second emission driving, adopted
when the vertical sync frequency of the input image signal is lower than a prescribed
frequency, and the brightness level of the input image signal is comparatively high;
FIG. 17 is a figure showing the various driving pulses applied to the PDP 10,
and the application timing;
FIG. 18 is a figure showing the data conversion table used in the second data
conversion circuit 35, and another example of an emission driving pattern;
FIG. 19 is a figure showing another example of an emission driving format (based
on the selective erasing address method) during the second emission driving;
FIG. 20 is a figure showing the data conversion table used in the second data
conversion circuit 35, and another example of an emission driving pattern;
FIG. 21 is a figure showing an example of an emission driving format (based
on the selected writing address method) during the first emission driving;
FIG. 22 is a figure showing another example of an emission driving format (based
on the selected writing address method) during the second emission driving;
FIG. 23 is a figure showing the data conversion table used in the second data
conversion circuit 34 when performing the first emission driving based on
the emission driving format shown in FIG. 21, and the emission driving pattern;
FIG. 24 is a figure showing the data conversion table used in the second data
conversion circuit 35 when performing the second emission driving based
on the emission driving format shown in FIG. 22, and the emission driving pattern;
FIG. 25 is a figure showing a modified example of the emission driving format
shown in FIG. 16;
FIG. 26 is a figure showing the data conversion table used in the second data
conversion circuit 35 when performing driving based on the emission driving
format shown in FIG. 25, and the emission driving pattern;
FIG. 27 is a figure showing a modified example of the emission driving format
shown in FIG. 22;
FIG. 28 is a figure showing the data conversion table used by the second data
conversion circuit 35 when performing driving based on the emission driving
format shown in FIG. 27, and the emission driving pattern;
FIG. 29 is a figure showing an example of the emission driving pattern adopted
when one field is divided into 13 subfields, and grayscale driving is executed
based on the selective erasing address method; and,
FIG. 30 is a figure showing an example of the emission driving pattern adopted
when one field is divided into 13 subfields, and grayscale driving is executed
based on the selected writing address method.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Below, embodiments of this invention are explained, referring to the drawings.
FIG. 4 is a figure showing the configuration of a plasma display device which
drives a plasma display panel according to a driving method of this invention.
As shown in FIG. 4, this plasma display device comprises a plasma display panel
PDP
10, and driving circuitry, comprising functional modules as described
below. As shown in FIG. 4, the driving circuitry comprises a synchronization detection
circuit
1; driving control circuit
2; vertical sync frequency detection
circuit
3; A/D converter
4; memory
5; address driver
6;
first sustaining driver
7; second sustaining driver
8; data conversion
circuit
30; and mean brightness detection circuit
40.
The PDP
10 comprises m column electrodes D
1 to D
m as
address electrodes, and n each row electrodes X
1 to X
n and
Y
1 to Y
n arranged to intersect each of the column electrodes.
Here, row electrodes corresponding to one row in the PDP
10 are formed by
one pair of the row electrodes X and Y. The column electrodes D and the row electrodes
X and Y are formed on two glass substrates, arranged in opposition and enclosing
a discharge space into which is injected a discharge gas. Discharge cells, serving
as display elements corresponding to individual pixels, are formed at the portions
of intersection of each of the row electrode pairs with the column electrodes.
When the synchronization detection circuit
1 detects a vertical sync
signal in the input image signal, it generates a vertical synchronization detection
signal V and supplies this signal to the driving control circuit
2 and the
vertical sync frequency detection circuit
3. Also, when the synchronization
detection circuit
1 detects a horizontal sync signal in the above input
image signal, it generates a horizontal synchronization detection signal H and
supplies this signal to the driving control circuit
2. The vertical sync
frequency detection circuit
3 measures the period of the above vertical
synchronization detection signal V, and by this means determines the vertical sync
frequency in the above input image signal, and supplies to the driving control
circuit
2 and data conversion circuit
30 a vertical sync frequency
signal VG which indicates this frequency value. The A/D converter
4 samples
the above input image signal, according to a clock signal provided by the driving
control circuit
2, and converts this into pixel data D with, for example,
8 bits per pixel; this is supplied to the data conversion circuit
30 and
the mean brightness detection circuit
40.
The mean brightness detection circuit
40 determines the mean brightness
level of the input image signal based on the above pixel data D, supplied in order
by the A/D converter
4, and supplies a mean brightness signal AB indicating
this mean brightness level to the driving control circuit
2.
The data conversion circuit
30 executes multi-grayscale processing on
the above pixel data D, and within one field interval, converts the results into
pixel driving data GD to drive the emission of individual discharge cells.
FIG. 5 is a figure showing the internal configuration of the data conversion
circuit
30.
In FIG. 5, the first data conversion circuit
32 provides the results of
conversion of the above pixel data D into (14×16)/255, based on conversion
characteristics as shown in FIG. 6, to the multi-grayscale processing circuit
33
as converted pixel data D
H. That is, the first data conversion circuit
32 converts pixel data D, capable of representing the brightnesses of 256
grayscales from 0 to 255 in 8 bits, into converted pixel data D
H capable
of representing the brightnesses of 225 grayscales from 0 to 224 in 8 bits. Specifically,
the first data conversion circuit
32 converts the above pixel data D into
converted pixel data D
H, based on the conversion tables in FIG. 7 and
FIG. 8, which conform to the conversion characteristic shown in FIG. 6. The conversion
characteristic is set according to the number of bits of the pixel data, the number
of compressed bits resulting from conversion to multiple grayscales, described
below, and the number of display grayscales. In this way, before executing the
multi-grayscale processing described below, conversion is performed by the first
data conversion circuit
32, taking into account the number of display grayscales
and the number of compressed bits resulting from multi-grayscale processing. As
a result of this data conversion, the occurrence of brightness saturation in the
multi-grayscale processing described below, and the occurrence of flat portions
in the display characteristic (that is, the occurrence of grayscale distortion)
arising when there are no display grayscales at bit boundaries, are prevented.
FIG. 9 is a figure showing the internal configuration of the multi-graycale
processing circuit
33, which executes multi-grayscale processing.
As shown in FIG. 9, the multi-grayscale processing circuit
33 comprises
an error diffusion processing circuit
330 and dither processing circuit
350.
The data separation circuit
331 in the error diffusion processing circuit
330 separates the lower 2 bits of the 8 bits of converted pixel data D
H
provided by the above first data conversion circuit
32 as error data, and
the upper 6 bits as display data. The adder
332 adds this error data, delay
output from the delay circuit
334, and multiplication output from the coefficient
multiplier
335, and provides the result of addition to the delay circuit
336. The delay circuit
336 supplies the addition result from the
adder
332, delayed by the time duration of one clock period of pixel data
(hereafter called delay time D), to the above coefficient multiplier
335
and delay circuit
337 as the delayed addition signal AD
1. The
coefficient multiplier
335 supplies to the above adder
332 the result
of multiplying the above delayed addition signal AD
1 by a prescribed
coefficient K
1 (for example " 7/16"). The delay circuit
337 supplies
to the delay circuit
338 the above delayed addition signal AD
1,
further delayed by an amount of time (1 horizontal scan interval-above delay time
D×4), as the delayed addition signal AD
2. The delay circuit
338
supplies to the coefficient multiplier
339 this delayed addition signal
AD
2, further delayed by the above delay time D, as the delayed addition
signal AD
3. The delay circuit
338 also supplies to the coefficient
multiplier
340 the above delayed addition signal AD
2, delayed
by an amount of time (delay time D×2), as the delayed addition signal AD
4.
Besides, the delay circuit
338 supplies to the coefficient multiplier
341
the above delayed addition signal AD
2, delayed by an amount of time
(delay time D×3), as the delayed addition signal AD
5. The coefficient
multiplier
339 supplies to the adder
342 the result of multi plying
the above delayed addition signal AD
3 by a prescribed coefficient K
2
(for example, " 3/16"). The coefficient multiplier
340 supplies to
the adder
342 the result of multiplying the above delayed addition signal
AD
4 by a prescribed coefficient K
3 (for example, " 5/16").
The coefficient multiplier
341 supplies to the adder
342 the result
of multiplying the above delayed addition signal AD
5 by a prescribed
coefficient K
4 (for example, " 1/16"). The adder
342 supplies
to the above delay circuit
334 the addition signal obtained by adding the
multiplication results supplied by the above coefficient multipliers
339,
340 and
341. The delay circuit
334 supplies the addition signal,
delayed by an amount of time equal to the above delay time D, to the above adder
332. The adder
332 supplies to the adder
333 the above error
data, the delayed output from the delay circuit
334, and a carry-out signal
C
o which is at logical level "0" if there is no carry digit when adding
with the multiplication output of the coefficient multiplier
335, and is
at logical level "1" if there is a carry digit. The adder
333 outputs the
result of addition of the above carryout signal C
o to the display data
which is the upper 6 bits of the above converted pixel data D
H as 6
bits of error diffusion processed pixel data ED.
Below, operation of an error diffusion processing circuit
330 with
the configuration described is explained.
For example, when determining the error diffusion processed pixel data ED corresponding
to the pixel G(j,k) of the PDP
10, as shown in FIG. 10, first, prescribed
coefficients K
1 to K
4 as described above are used to weight
by addition the error data corresponding to the pixel G(j,k-1) on the left of the
pixel G(j,k) in question; the pixel G(j-1,k-1) on the upper left; the pixel G(j-1,k)
directly above; and the pixel G(j-1,k+1) on the upper right, as follows:
Error data corresponding to pixel G(j,k-1): Delayed addition signal AD
1
Error data corresponding to pixel G(j-1,k+1): Delayed addition signal AD
3
Error data corresponding to pixel G(j-1,k): Delayed addition signal AD
4
Error data corresponding to pixel G(j-1,k-1): Delayed addition signal AD
5
Next, to these addition results are added the lower 2 bits of the converted
pixel data HD
P, that is, the error data corresponding to the pixel G(j,k);
the 1-bit carry-out signal C
o obtained in this operation added to the
upper 6 bits of converted pixel data D
H that is, the display data corresponding
to the pixel G(j,k), is then taken to be the error diffusion processed pixel data ED.
By means of this configuration, in the error diffusion processing circuit
330,
the upper 6 bits of the converted pixel data D
H is taken to be the display
data and the remaining lower 2 bits to be the error data, and the weighted error
data for each of the peripheral pixels {G(j,k-1), G(j-1,k+1), G(j-1,k), G(j-1,k-1)}
is reflected in the above display data. Through this operation, the brightness
of the lower 2 bits at the origin pixel {G(j,k)} is approximately represented by
the above peripheral pixels, and consequently, 6 bits' worth of display data, fewer
than 8 bits' worth, can be used to represent brightness grayscales equivalent to
8 bits' worth of pixel data.
If the coefficients of this error diffusion are added uniformly for each pixel,
in some cases noise due to error diffusion patterns may be perceived visually,
so that image quality will be degraded. Hence the error diffusion coefficients
K
1 to K
4 to be allocated to each of the four peripheral pixels
may be changed for each field.
The dither processing circuit
350 performs dither processing of error
diffusion processed pixel data ED supplied by the error diffusion processing circuit
330. In this dither processing, one intermediate display level is represented
by a plurality of neighboring pixels. For example, when the upper 6 bits of pixel
data among 8 bits of pixel data are used for grayscale representation equivalent
to 8 bits, the four pixels adjacent on the left and right, and above and below,
are taken to be one set, and four dither coefficients a to d, which are different
coefficient values, are allocated and added to each of the pixel data values corresponding
to each of the pixels of this set. Through this dither processing, four pixels
can produce combinations of four different intermediate display levels. Hence even
if there are only 6 bits of pixel data, the number of levels of brightness grayscales
which can be represented is increased fourfold, that is, intermediate grayscales
equivalent to 8 bits can be displayed.
However, if a dither pattern with dither coefficients a through d is added
uniformly to each pixel, there are cases in which noise due to this dither pattern
is perceived visually, and the image quality is degraded.
Hence in the dither processing circuit
350, the dither coefficients
a to d to be allocated to each of the four pixels are changed for each field.
FIG. 11 is a figure showing the internal configuration of the dither processing
circuit
350.
In FIG. 11, the dither coefficient generation circuit
352 generates four
dither coefficients a, b, c, d for each of four adjacent pixels [G(j,k), G(j,k+1),
G(j+1,k), G(j+1,k+1)] as shown in FIG. 12, and supplies these in order to the adder
351. Further, the dither coefficient generation circuit
352 changes,
for each field, the allocation of the dither coefficients a through d generated
corresponding to each of the four pixels, as shown in FIG. 12.
In other words, dither coefficients a through d are generated in cyclic repetition
and supplied to the adder
351, with the following allocations.
In the first field,
pixel G(j,k): dither coefficient a
pixel G(j,k+1): dither coefficient b
pixel G(j+1,k): dither coefficient c
pixel G(j+1,k+1): dither coefficient d
In the second field,
pixel G(j,k): dither coefficient b
pixel G(j,k+1): dither coefficient a
pixel G(j+1,k): dither coefficient d
pixel G(j+1,k+1): dither coefficient c
In the third field,
pixel G(j,k): dither coefficient d
pixel G(j,k+1): dither coefficient c
pixel G(j+1,k): dither coefficient b
pixel G(j+b
1,k+1): dither coefficient a
And in the fourth field,
pixel G(j,k): dither coefficient c
pixel G(j,k+1): dither coefficient d
pixel G(j+1,k): dither coefficient a
pixel G(j+1,k+1): dither coefficient b
The dither coefficient generation circuit
352 repeatedly executes the
operation for the first through fourth fields as described above. That is, after
completing the operation to generate dither coefficients in the fourth field, the
circuit returns to the operation for the above first field, and repeats the operation
described above.
The adder
351 adds the dither coefficients a through d allocated for each
field as described above to the error diffusion processed pixel data ED corresponding
to the above pixel G(j,k), pixel G(j,k+1), pixel G(j+1,k), and pixel G(j+1,k+1),
su plied from the above error diffusion processing circuit
330. The dither
added pixel data obtained is supplied to the upper bit extraction circuit
353.
For example, in the first field shown in FIG. 12, the following are supplied
in order as dither added pixel data to the upper bit extraction circuit
353:
Error diffusion processed pixel data ED corresponding to the pixel G(j,k)+dither
coefficient a,
Error diffusion processed pixel data ED corresponding to the pixel G( j,k+1)+dither
coefficient b,
Error diffusion processed pixel data ED corresponding to the pixel G(j+1,k)+dither
coefficient c, and Error diffusion processed pixel data ED corresponding to the
pixel G(j+1,k+1)+dither coefficient d.
In this process, when a plurality of pixels are viewed as a single pixel unit,
as shown in FIG. 10, through addition of the above dither coefficients, brightness
equivalent to 8 bits can be rep resented even with only the upper 4 bits of the
above dither added pixel data. Hence the upper bit extraction circuit
353
of the next stage extracts the upper 4 bits of the dither added pixel data, and
these are supplied to the second data conversion circuits
34 and
35
shown in FIG. 5 as multi-grayscale pixel data D
S.
The second data conversion circuit
34 converts the multi-grayscale pixel
data D
S into 14-bit pixel driving data GD
a according to the
data conversion table shown in FIG. 13, and supplies this to the selector
36.
On the other hand, the second data conversion circuit
35 converts the
above
multi-grayscale pixel data D
S into 14-bit pixel driving data GD
b
according to the data conversion table shown in FIG. 14, and supplies the
result to the selector
36. When a flicker suppression signal FS at logical
level "0" is supplied from the driving control circuit
2, the selector
36
selects GD
a from among the above pixel driving data GD
a and GD
b
for use as pixel driving data GD, and supplies this to the memory
5
shown in FIG. 4. On the other hand, when a flicker suppression signal FS with logical
level "1" is supplied, the selector
36 selects the above pixel driving data
GD
b, and supplies this to the memory
5 as pixel driving data GD.
The memory
5 writes in order this pixel driving data GD, according to
write signals supplied from the driving control circuit
2. When, by means
of this write operation, one screen's worth (n rows, m columns) of writing is completed,
the memory
5 reads out the written data according to read signals supplied
from the driving control circuit
2. That is, in the memory
5, one
screen's worth of the written pixel driving data GD
11 to GD
nm is
taken to be pixel driving data bit groups DB
1 to DB
14, grouped by
the bit digit (from the first to the 14th bit).
The pixel driving data bit groups DB
1 to DB
14 are as follows.
DB
1: 1st bit of each of GD
11 to GD
nm
DB
2: 2nd bit of each of GD
11 to GD
nm
DB
3: 3rd bit of each of GD
11 to GD
nm
DB
4: 4th bit of each of GD
11 to GD
nm
DB
5: 5th it of each of GD
11 to GD
nm
DB
6: 6th bit of each of GD
11 to GD
nm
DB
7: 7th bit of each of GD
11 to GD
nm
DB
8: 8th bit of each of GD
11 to GD
nm
DB
9: 9th bit of each of GD
11 to GD
nm
DB
10: 10th bit of each of GD
11 to GD
nm
DB
11: 11th bit of each of GD
11 to GD
nm
DB
12: 12th bit of each of GD
11 to GD
nm
DB
13: 13th bit of each of GD
11 to GD
nm
DB
14: 14th bit of each of GD
11 to GD
nm
The memory
5 reads out in order, one display line at a time, each of these
pixel driving data bit groups DB
1 to DB
14, corresponding to each
of the subfields SF
1 to SF
14 described below.
The driving control circuit
2 executes emission driving control as follows,
according to the above vertical sync frequency signal VF and mean brightness signal AB.
When the vertical sync frequency indicated by the above vertical sync frequency
signal VF is equal to or greater than, for example, 60 Hz, or when the mean brightness
level indicated by the mean brightness signal AB is lower than a prescribed level,
the driving control circuit
2 first supplies a logical level "0" flicker
suppression signal FS to the data conversion circuit
30. In this process,
the selector
36 of the data conversion circuit
30 supplies pixel
driving data GD
a, converted by the second data conversion circuit
34,
to memory
5 in response to this logical level "0". flicker suppression signal
FS. The driving control circuit
2 then supplies, to the address driver
6,
first sustaining driver
7 and second sustaining driver
8, various
timing signals so as to cause emission driving of the PDP
10 according to
the emission driving format shown in FIG. 15.
That is, w hen the brightness level of the input image signal is low, or when
for example an NTSC format television signal or other signal with vertical sync
frequency at 60 Hz or higher is supplied as the input image signal, emission driving
is executed as shown in FIG. 13 and FIG. 15.
On the other hand, when the vertical sync frequency indicated by the above vertical
sync frequency signal VF is less than 60 Hz, and in addition the mean brightness
level indicated by the mean brightness signal AB is higher than a prescribed level,
the driving control circuit
2 first supplies a logical level "1" flicker
suppression signal FS to the data conversion circuit
30. In this process,
the selector
36 of the data conversion circuit
30 supplies to the
memory
5 pixel driving data GD
b converted by the second data
conversion circuit
35 in response to this logical level "1" flicker suppression
signal FS. The driving control circuit
2 then supplies, to the address driver
6, first sustaining driver
7 and second sustaining driver
8,
various timing signals so as to cause emission driving of the PDP
10, according
to the emission driving format shown in FIG. 16.
In other words, if as the input image signal a PAL format television signal or
other signal with a vertical sync frequency less than 60 Hz is supplied, and in
addition the mean brightness is high, then emission driving is executed as shown
in FIG. 14 and FIG. 16.
In the emission driving format shown in FIG. 15 and FIG. 16, the display interval
of one field (hereafter this expression also refers to one frame) is divided into
14 subfields SF
1 to SF
14. Within each subfield, executed are an address
sequence Wc, in which each of the discharge cells of the PDP
10 is set to
either the "lit discharge cell state" or the "extinguish discharge cell state",
and an emission sustain sequence Ic which causes only discharge cells in the above
"lit discharge cell state" to emit repeatedly the number of times indicated in
FIG. 15 (or in FIG. 16). Also, in the leading subfield SF
1, a simultaneous
reset sequence Rc is executed which initializes the wall charge within all the
discharge cells of the PDP
10; and in the final subfield SF
14, an
erasing sequence E is executed which simultaneously eliminates the wall charge
within all the discharge cells.
In the emission driving format shown in FIG. 16, the emission driving in the
subfields
SF
1, SF
3, SF
5, SF
7, SF
9, SF
11, SF
13
in the emission driving format of FIG. 15 is executed in the first half of the
one-field display interval, and the emission driving in the subfields SF
2,
SF
4, SF
6, SF
8, SF
10, SF
12, SF
14 is executed
in the second half. Here, the above erasing sequence E is executed in the final
subfield SF
13 of the first half, and the above simultaneous reset sequence
Rc is executed in the leading subfield SF
2 of the second half.
The address driver
6, first sustaining driver
7 and second sustaining
driver
8 apply various driving pulses in order to realize the operations
of each of the above sequences to the electrodes of the PDP
10, with timing
determined by the timing signals supplied by the driving control circuit
2.
FIG. 17 shows the timing of the application of various driving pulses applied
to the column electrodes D and the row electrodes X and Y of the PDP
10
by the above drivers, during the above simultaneous reset sequence Rc, address
sequence Wc, emission sustain sequence Ic, and erasing sequence E.
First, in the above simultaneous reset sequence Rc, the first sustaining driver
7 and second sustaining driver
8 each simultaneously apply reset
pulses RP
X and RP
Y to the row electrodes X
1 to
X
n and Y
1 to Y
n, as shown in FIG. 17. In response
to the application of these reset pulses RP
X and RP
Y, all
the discharge cells in the PDP
10 undergo reset discharge, and a prescribed
uniform wall charge is formed within each of the discharge cells. By this means,
all the discharge cells are set to the initial "lit discharge cell state".
Next, in the address sequence Wc, the address driver
6 generates pixel
data pulses having voltages corresponding to the logical levels of each pixel driving
data bit in the pixel driving data bit group DB read from the above memory
5.
For example, the address driver
6 generates a high-voltage pixel data pulse
when the logical level of the pixel driving data bit is "1", and generates a low-voltage
(0 volt) pixel data pulse when it is "0". The address driver
6 applies these
pixel data pulses, one display line (m pulses) at a time, to the column electrodes
D
1 to D
m. For example, in the address sequence Wc of the
subfield SF
1, the pixel driving data bit group DB
1 is read from memory
5, as described above. In this process, the address driver
6 first
converts m pixel driving data bits corresponding to the first display line in the
pixel driving data bit group DB
1 into m pixel data pulses having pulse voltages
corresponding to the respective logical levels, and applies these to the column
electrodes D
1 to D
m as the pixel data pulses group DP
1.
Next, the address driver
6 converts the m pixel driving data bits corresponding
to the second display line in the pixel driving data bit group DB
1 into
m pixel data pulses having pulse voltages which correspond to the respective logical
levels, and apply these to the column electrodes D
1 to D
m as
