Title: Electronic assembly with sandwiched capacitors and methods of manufacture
Abstract: To provide high-speed, low inductance capacitive decoupling, an integrated circuit (IC) package includes capacitors positioned within the mounting region between a die and an IC package substrate. A variety of types and sizes of capacitors and substrates can be employed in a variety of geometrical arrangements. In some embodiments, capacitors are sandwiched between die terminals or bumps and the substrate conductors or pads, while in other embodiments, capacitors are positioned between bar-type conductors on the surface of the IC package substrate. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.
Patent Number: 6,900,991 Issued on 05/31/2005 to Patel, et al.
| Inventors:
|
Patel; Priyavadan R. (Chandler, AZ);
Chung; Chee-Yee (Chandler, AZ);
Figueroa; David G. (Mesa, AZ);
Sankman; Robert L. (Phoenix, AZ);
Li; Yuan-Liang (Chandler, AZ);
Xie; Hong (Phoenix, AZ);
Pinello; William P. (Phoenix, AZ)
|
| Assignee:
|
Intel Corporation (Santa Clara, CA)
|
| Appl. No.:
|
006292 |
| Filed:
|
December 3, 2001 |
| Current U.S. Class: |
361/782; 257/724; 361/783 |
| Intern'l Class: |
H05K 007/06 |
| Field of Search: |
361/737,738,760,763,766,780,782,783,794,306.2
257/691,724,777
|
References Cited [Referenced By]
U.S. Patent Documents
| 4879631 | Nov., 1989 | Johnson et al.
| |
| 4882656 | Nov., 1989 | Menzies et al.
| |
| 5010447 | Apr., 1991 | Wallace.
| |
| 5272590 | Dec., 1993 | Hernandez.
| |
| 5504373 | Apr., 1996 | Oh et al.
| |
| 5929646 | Jul., 1999 | Patel et al.
| |
| 5996880 | Dec., 1999 | Chu et al.
| |
| 6040983 | Mar., 2000 | Baudouin et al.
| |
| 6043987 | Mar., 2000 | Goodwin et al.
| |
| 6147876 | Nov., 2000 | Yamaguchi et al.
| |
| 6178082 | Jan., 2001 | Farooq et al.
| |
| 6252760 | Jun., 2001 | Sen.
| |
| 6300677 | Oct., 2001 | Salem.
| |
| 6316828 | Nov., 2001 | Tao et al.
| |
| 6320249 | Nov., 2001 | Yoon.
| |
| 6373714 | Apr., 2002 | Kudoh et al.
| |
| 6404649 | Jun., 2002 | Drake et al.
| |
| 6459561 | Oct., 2002 | Galvagni et al.
| |
| 6556420 | Apr., 2003 | Naito et al.
| |
| 2002/0071258 | Jun., 2002 | Mosley.
| |
Primary Examiner: Vigushin; John B.
Attorney, Agent or Firm: Schwegman, Lundberg, Woessner & Kluth, P.A.
Parent Case Text
RELATED APPLICATION
The present application is related to the following application which is assigned
to the same assignee as the present application and which was filed on even date herewith:
Ser. No. 10/006,188, entitled "Capacitor Having Separate Terminals on Three
or More Sides and Methods of Fabrication".
Claims
1. An integrated circuit (IC) package comprising:
a substrate having a plurality of conductors within an IC mounting region, wherein
the conductors include at least a first conductive bar having a height and a width,
the height exceeding the width;
a plurality of capacitors distributed substantially throughout the IC mounting
region and electrically coupled to the first conductive bar, wherein the plurality
of capacitors comprises a plurality of capacitor arrays; and
an IC electrically coupled to the plurality of conductors via the plurality of
capacitors.
2. The IC package recited in claim 1, wherein selected ones of the plurality
of capacitors are further electrically coupled to a second conductive bar of the
plurality of conductors, wherein the first conductive bar is to couple to a first
potential, and wherein the second conductive bar is to couple to a second potential.
3. The IC package recited in claim 1, wherein each of the plurality of capacitors
has a top and a bottom, and wherein selected ones of the plurality of capacitors
have at least one terminal on their top and at least one terminal on their bottom.
4. The IC package recited in claim 1, wherein each of the capacitor arrays has
a top and a bottom, and wherein selected ones of the capacitor arrays have a plurality
of terminals of first and second polarities on their top and a plurality of terminals
of first and second polarities on their bottom.
5. The IC package recited in claim 1, wherein selected ones of the plurality
of capacitor arrays are interdigitated capacitors.
6. An integrated circuit (IC) package comprising:
a substrate having a plurality of conductors within an IC mounting region, wherein
the conductors include at least a first conductive bar having a height and a width,
the height exceeding the width;
at least one capacitor within the IC mounting region and electrically coupled
to the first conductive bar, wherein the at least one capacitor is mounted atop
the first conductive bar; and
an IC electrically coupled to the plurality of conductors via the at least one
capacitor.
7. The IC package recited in claim 6, wherein the at least one capacitor is further
electrically coupled to a second conductive bar of the plurality of conductors,
wherein the first conductive bar is to couple to a first potential, and wherein
the second conductive bar is to couple to a second potential.
8. The IC package recited in claim 6, wherein the at least one capacitor has
a top and a bottom, and wherein the at least one capacitor has terminals on its
top and bottom.
9. The IC package recited in claim 6 and comprising a plurality of capacitors
distributed substantially throughout the IC mounting region, each capacitor being
in electrical contact with at least one of the conductors.
10. The IC package recited in claim 9, wherein the plurality of capacitors comprises
a plurality of sets of capacitors, each set comprising two or more capacitors having
ends and being aligned substantially end-to-end.
11. An integrated circuit (IC) package comprising:
a substrate having a plurality of conductors within an IC mounting region, wherein
the plurality of conductors are substantially parallel to one another, and wherein
the plurality of conductors include at least a first conductive bar having a height
and a width, the height exceeding the width;
a plurality of capacitors within the IC mounting region and electrically coupled
to the first conductive bar, wherein the plurality of capacitors comprises a plurality
of capacitor arrays; and
an IC electrically coupled to the plurality of conductors via the plurality of
capacitors.
12. The IC package recited in claim 11, wherein selected ones of the plurality
of capacitors are further electrically coupled to a second conductive bar of the
plurality of conductors, wherein the first conductive bar is to couple to a first
potential, and wherein the second conductive bar is to couple to a second potential.
13. The IC package recited in claim 11, wherein each of the plurality of capacitors
has a top and a bottom, and wherein selected ones of the plurality of capacitors
have at least one terminal on their top and at least one terminal on their bottom.
14. The IC package recited in claim 11, wherein each of the capacitor arrays
has a top and a bottom, and wherein selected ones of the capacitor arrays have
a plurality of terminals of first and second polarities on their top and a plurality
of terminals of first and second polarities on their bottom.
15. The IC package recited in claim 11, wherein the plurality of capacitor arrays
are non-orthogonally mounted atop the plurality of conductors.
16. The IC package recited in claim 15, wherein the conductors are diagonal to
the plurality of capacitor arrays.
17. An integrated circuit (IC) package comprising:
a substrate having a plurality of conductors within an IC mounting region, wherein
the plurality of conductors include at least a first conductive bar having a height
and a width, the height exceeding the width;
a capacitor array within the IC mounting region and electrically coupled to the
first conductive bar; and
an IC electrically coupled to the plurality of conductors via the capacitor array.
18. The IC package recited in claim 17, wherein the capacitor array is further
electrically coupled to a second conductive bar of the plurality of conductors,
wherein the first conductive bar is to couple to a first potential, and wherein
the second conductive bar is to couple to a second potential.
19. The IC package recited in claim 18, wherein the at least first and second
conductive bars have a gap to accommodate the capacitor array.
20. The IC package recited in claim 17, wherein the capacitor array is non-orthogonally
mounted atop the plurality of conductors.
21. The IC package recited in claim 17, wherein the capacitor array has a top
and a bottom, and wherein the capacitor array has at least one terminal on its
top and at least one terminal on its bottom.
22. The IC package recited in claim 21, wherein the capacitor array has a plurality
of terminals of first and second polarities on its top and a plurality of terminals
of first and second polarities on its bottom.
23. An integrated circuit (IC) package comprising:
a substrate having a plurality of conductors within an IC mounting region, wherein
the conductors include at least one conductive bar having a height and a width,
the height exceeding the width;
a plurality of capacitors within the IC mounting region, wherein the plurality
of capacitors are mounted beside and in electrical contact with the at least one
conductive bar; and
an IC electrically coupled to the plurality of conductors via the plurality of
capacitors.
24. The IC package recited in claim 23, wherein the plurality of conductors comprises
at least first and second conductive bars, wherein the first conductive bar is
to couple to a first potential, and wherein the second conductive bar is to couple
to a second potential.
25. The IC package recited in claim 23, wherein selected ones of the plurality
of capacitors have a first side and a second side, wherein the first side comprises
at least one terminal of first polarity, and wherein the second side comprises
at least one terminal of second polarity.
26. The IC package recited in claim 23, wherein selected ones of the plurality
of capacitors are mounted beside one of the plurality of conductors.
27. The IC package recited in claim 23, wherein selected ones of the plurality
of capacitors are mounted between two of the plurality of conductors.
28. The IC package recited in claim 23, wherein the at least one conductive bar
has a length, and wherein at least one of the plurality of capacitors has a length
substantially the same as the length of the at least one conductive bar.
29. The IC package recited in claim 23, wherein the plurality of conductors comprises
at least first and second conductive bars having a height and a width, the height
exceeding the width, wherein the first conductive bar is to couple to a first potential,
wherein the second conductive bar is to couple to a second potential, wherein the
first and second conductive bars have a length, wherein at least one of the plurality
of capacitors has a length substantially the same as the length of the first and
second conductive bars and is mounted beside and in electrical contact with the
first and second conductive bars, wherein at least another of the plurality of
capacitors is a capacitor array, and wherein the at least first and second conductive
bars have a gap to accommodate the capacitor array.
30. The IC package recited in claim 29, wherein the capacitor array has a top
and a bottom, wherein the capacitor array has at least one terminal on its top
and at least one terminal on its bottom, and wherein the at least one terminal
on its bottom is coupled to one of the first and second conductive bars.
31. The IC package recited in claim 29, wherein the capacitor array is transverse
to the at least one capacitor.
32. An integrated circuit (IC) package comprising:
a substrate having a plurality of conductive bars within an IC mounting region,
the conductive bars having a height and a width, the height exceeding the width;
a plurality of capacitors within the IC mounting region, wherein the plurality
of capacitors are mounted beside and in electrical contact with selected ones of
the conductive bars; and
an IC electrically coupled to the plurality of conductive bars via the plurality
of capacitors.
33. The IC package recited in claim 32, wherein selected ones of the plurality
of capacitors have a first side and a second side, wherein the first side comprises
at least one terminal of first polarity, and wherein the second side comprises
at least one terminal of second polarity.
34. The IC package recited in claim 33, wherein the IC comprises a plurality
of pads of first and second polarities, wherein the selected ones of the plurality
of capacitors have a top and a bottom, wherein at least one terminal on the top
is of a first polarity, wherein at least one terminal on the top is of a second
polarity, wherein the at least one terminal of first polarity is coupled to at
least one corresponding pad of first polarity, and wherein the at least one terminal
of second polarity is coupled to at least one corresponding pad of second polarity.
35. An integrated circuit (IC) package comprising:
a substrate having a plurality of conductors within an IC mounting region, wherein
the conductors include at least one conductive bar having a height and a width,
the height exceeding the width;
at least one capacitor within the IC mounting region, wherein the at least one
capacitor is mounted beside and in electrical contact with the at least one conductive
bar; and
an IC electrically coupled to the plurality of conductors.
36. The IC package recited in claim 35, wherein the at least one capacitor is
mounted between and electrically coupled to first and second conductive bars.
37. The IC package recited in claim 36, wherein the first conductive bar is to
couple to a first potential, and wherein the second conductive bar is to couple
to a second potential.
38. The IC package recited in claim 36, wherein the capacitor comprises terminals
on two sides, and wherein the terminals are electrically coupled to the first and
second conductive bars, respectively.
39. The IC package recited in claim 35, wherein the plurality of conductors are
substantially parallel to one another.
40. An integrated circuit (IC) package comprising:
a substrate having a plurality of conductors within an IC mounting region, wherein
the plurality of conductors are substantially parallel to one another;
a plurality of capacitors within the IC mounting region and electrically coupled
to at least one of the conductors, wherein the plurality of capacitors comprises
a plurality of capacitor arrays, and wherein the plurality of capacitor arrays
are non-orthogonally mounted atop the plurality of conductors; and
an IC electrically coupled to the plurality of conductors via the plurality of
capacitors.
41. The IC package recited in claim 40, wherein the plurality of conductors are
substantially parallel to one another.
42. The IC package recited in claim 40, wherein the plurality of conductors are
diagonal to the plurality of capacitor arrays.
Description
TECHNICAL FIELD
The inventive subject matter relates generally to electronics packaging. More
particularly, the inventive subject matter relates to an electronic assembly that
includes an integrated circuit (IC) package having a decoupling capacitance situated
between a high performance IC and an IC package substrate for reducing inductance
and for providing improved power delivery, and to manufacturing methods related thereto.
BACKGROUND INFORMATION
Integrated circuits (ICs) are typically assembled into packages by physically
and electrically coupling them to a substrate made of organic or ceramic material.
One or more ICs or IC packages can be physically and electrically coupled to a
substrate such as a printed circuit board (PCB) or card to form an "electronic
assembly". The "electronic assembly" can be part of an "electronic system". An
"electronic system" is broadly defined herein as any product comprising an "electronic assembly".
Examples of electronic systems include computers (e.g., desktops, laptops,
hand-helds, servers, Web appliances, routers, etc.), wireless communications devices
(e.g., cellular phones, cordless phones, pagers, personal digital assistants, etc.),
computer-related peripherals (e.g., printers, scanners, monitors, etc.), entertainment
devices (e.g., televisions, radios, stereos, tape and compact disc players, video
cassette recorders, camcorders, digital cameras, MP3 (Motion Picture Experts Group,
Audio Layer 3) players, video games, watches, etc.), and the like.
In the field of electronic systems there is an incessant competitive pressure
among manufacturers to drive the performance of their equipment up while maintaining
high yield and reliability. This is particularly true regarding the packaging of
ICs on substrates, where each new generation of packaging must provide increased
performance, particularly in terms of an increased number of components and higher
clock frequencies, while generally being smaller or more compact in size.
An IC substrate may comprise a number of insulated metal layers selectively patterned
to provide metal interconnect lines (referred to herein as "traces"), and one or
more electronic components mounted on one or more surfaces of the substrate. The
electronic component or components are functionally connected to other elements
of an electronic system through a hierarchy of electrically conductive paths that
include the substrate traces. The substrate traces typically carry signals that
are transmitted between the electronic components, such as ICs, of the system.
One of the conventional methods for mounting an IC on a substrate is called "controlled
collapse chip connect" (C4). In fabricating a C4 package, the electrically conductive
terminals (generally called "bumps") of an IC component are soldered directly to
corresponding terminals (generally called "pads") on the surface of the substrate
using reflowable solder balls. The C4 process is widely used because of its robustness
and simplicity.
As the internal circuitry of high performance ICs, such as processors, operates
at higher and higher clock frequencies, noise in the power and ground lines increasingly
reaches an unacceptable level. This noise can arise due to inductive and capacitive
parasitics, for example, as is well known. To reduce such noise, capacitors known
as decoupling or by-pass capacitors are often used to provide a stable signal or
stable supply of power to the circuitry.
As electronic devices continue to advance, there is an increasing need for higher
levels of capacitance at reduced inductance levels for decoupling, power dampening,
and supplying charge. In addition, there is a need for capacitance solutions that
do not interfere with package connectors of various types, and which do not limit
the industry to certain device sizes and packing densities. Accordingly, there
is a need in the art for alternative capacitance solutions in the fabrication and
operation of electronic devices and their packages.
For the reasons stated above, and for other reasons stated below which will become
apparent to those skilled in the art upon reading and understanding the present
specification, there is a significant need in the art for methods and structures
for packaging a high performance IC on a substrate that provide decreased inductance
levels, and increased power delivery and signal integrity.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of an electronic system incorporating at least one
electronic assembly with sandwiched capacitors in accordance with an embodiment
of the invention;
FIG. 2 is a cross-sectional view of a prior art IC package showing die side
capacitors (DSCs), land side capacitors (LSCs), and embedded chip capacitors (ECCs);
FIG. 3 illustrates a top view of an IC mounting region of an IC package substrate,
and a plurality of relatively short capacitors overlying the IC mounting region,
in accordance with an embodiment of the invention;
FIG. 4 illustrates a cross-sectional representation of an IC package, including
a die, and a cross-sectional view of the capacitors and IC package substrate shown
in FIG. 3 taken along line 101 of FIG. 3;
FIG. 5 illustrates a top view of an IC mounting region of an IC package substrate,
and a plurality of relatively long capacitors overlying the IC mounting region,
in accordance with an embodiment of the invention;
FIG. 6 illustrates a cross-sectional representation of an IC package, including
a die, and a cross-sectional view of a capacitor and an IC package substrate shown
in FIG. 5 taken along line 201 of FIG. 5;
FIG. 7 illustrates a top view of an IC mounting region of an IC package substrate,
and a plurality of relatively long capacitors overlying the IC mounting region,
in accordance with an embodiment of the invention;
FIG. 8 illustrates a top view of a capacitor array, in accordance with an embodiment
of the invention;
FIG. 9 illustrates a cross-sectional representation of an IC package, including
a die, and a cross-sectional view of the capacitor array shown in FIG. 8 taken
along line 311 of FIG. 8;
FIG. 10 illustrates a top view of an IC mounting region of an IC package substrate,
and a plurality of relatively short capacitors disposed between conductive bars
in the IC mounting region, in accordance with an embodiment of the invention;
FIG. 11 illustrates a cross-sectional representation of an IC package, including
a die, and a cross-sectional view of the capacitors and IC package substrate shown
in FIG. 10 taken along line 401 of FIG. 10;
FIG. 12 illustrates a top view of an IC mounting region of an IC package substrate,
and a plurality of capacitors disposed between conductive bars in the IC mounting
region, in accordance with an embodiment of the invention;
FIG. 13 illustrates a top view of an IC mounting region of an IC package substrate,
and a plurality of relatively long capacitors disposed between conductive bars
in the IC mounting region, in accordance with an embodiment of the invention;
FIG. 14 illustrates a cross-sectional representation of an IC package, including
a die, and a cross-sectional view of the capacitors and IC package substrate shown
in FIG. 13 taken along line 601 of FIG. 13;
FIG. 15 illustrates a top view of a relatively short capacitor as used in an
embodiment of the invention;
FIG. 16 illustrates a top view of one type of relatively long capacitor as used
in an embodiment of the invention;
FIG. 17 illustrates a top view of another type of relatively long capacitor
as used in an embodiment of the invention;
FIG. 18 illustrates a top view of a further type of relatively long capacitor
as used in an embodiment of the invention;
FIG. 19 illustrates a top view of yet another type of relatively long capacitor
as used in an embodiment of the invention;
FIGS. 20, 21, 22, 23, 24, and 25 illustrate
cross-sectional representations illustrating stages of fabricating an IC package
comprising sandwiched capacitors, in accordance with an embodiment of the invention,
in which:
FIG. 20 illustrates fabricating a capacitor assembly by arranging a first layer
of discrete capacitors on a conductive layer;
FIG. 21 illustrates fabricating additional layers of discrete capacitors;
FIG. 22 illustrates segmenting a stack of capacitor assemblies into a capacitor group;
FIG. 23 illustrates mounting capacitor groups on an IC package substrate;
FIG. 24 illustrates filling spaces with a dielectric;
FIG. 25 illustrates mounting a die on a capacitor layer of an IC package substrate;
FIG. 26 illustrates a group of capacitors mounted on a die, in accordance with
an embodiment of the invention;
FIG. 27 illustrates mounting the die shown in FIG. 26 upon an IC package substrate;
FIGS. 28A, 28B, and 28C together illustrate a flow diagram of
various methods of fabricating electronic assemblies, and/or constituents thereof,
utilizing sandwiched capacitors, in accordance with embodiments of the invention; and
FIGS. 29A and 29B together illustrate a flow diagram of various additional
methods of fabricating electronic assemblies, and/or constituents thereof, utilizing
sandwiched capacitors, in accordance with embodiments of the invention.
DETAILED DESCRIPTION
In the following detailed description of embodiments of the inventive subject
matter, reference is made to the accompanying drawings which form a part hereof,
and in which is shown by way of illustration specific preferred embodiments in
which the inventive subject matter may be practiced. These embodiments are described
in sufficient detail to enable those skilled in the art to practice the inventive
subject matter, and it is to be understood that other embodiments may be utilized
and that structural, mechanical, compositional, and electrical changes may be made
without departing from the spirit and scope of the inventive subject matter. The
following detailed description is, therefore, not to be taken in a limiting sense,
and the scope of embodiments of the inventive subject matter is defined only by
the appended claims. Such embodiments of the inventive subject matter maybe referred
to, individually and/or collectively, herein by the term "invention" merely for
convenience and without intending to voluntarily limit the scope of this application
to any single invention or inventive concept if more than one is in fact disclosed.
The present invention provides a solution to performance and reliability problems
that are associated with prior art packaging of integrated circuits (ICs) that
have high circuit density and that operate at high clock speeds and high power
levels. In the present invention, decoupling and/or by-pass capacitors are positioned
within the mounting region between an IC and an IC package substrate, particularly
in the core region containing power conductors. Through this arrangement, capacitors
can be placed close to the IC to minimize loop inductance for power delivery, while
also minimizing resistance losses. In addition, the use of ceramic capacitors between
the IC and the IC package substrate in certain embodiments can provide an improved
CTE (coefficient of thermal expansion) match and improved operational reliability.
Various embodiments are illustrated and described herein.
In an embodiment, a front surface of an IC is flip-chip mounted to a substrate
using "controlled collapse chip connect" (C4) technology, and a large capacitor
array is sandwiched between the IC and the substrate, the capacitor having terminals
of equivalent pitch to those of the IC and substrate.
A "capacitor array", as used herein, means a capacitor comprising at least one
surface having more than one terminal of a given polarity type. Examples are illustrated
in FIGS. 8,
16,
17, and
19 discussed further below.
In other embodiments, a plurality of capacitors are sandwiched between the IC
terminals and the terminals of the package substrate. These terminals can be of
various types.
In further embodiments, the substrate core contains a plurality of conductive,
raised bar-like terminals to connect with suitable terminals in the core area of
the IC, and capacitors are sandwiched between the bars.
The capacitors used in the various embodiments can be of different types and
sizes. Discrete capacitors having only a single pair of terminals of opposite polarity
can be used in different sizes. Capacitors having multiple terminals of two different
polarities can be used in different sizes. Some capacitors have terminals of different
polarity types on multiple surfaces. The particular capacitor type and size are
selected based upon the desired functional and geometrical configuration of the
IC package.
Also described are methods of fabricating an IC package substrate and an IC
package, as well as application of the IC package to an electronic assembly and
to an electronic system.
FIG. 1 is a block diagram of an electronic system
1 incorporating at
least one electronic assembly
4 with sandwiched capacitors in accordance
with an embodiment of the invention. Electronic system
1 is merely one example
of an electronic system in which the present invention can be used. In this example,
electronic system
1 comprises a data processing system that includes a system
bus
2 to couple the various components of the system. System bus
2
provides communications links among the various components of the electronic system
1 and can be implemented as a single bus, as a combination of busses, or
in any other suitable manner.
Electronic assembly
4 is coupled to system bus
2. Electronic
assembly
4 can include any circuit or combination of circuits. In one embodiment,
electronic assembly
4 includes a processor
6 which can be of any
type. A "processor", as used herein, means any type of computational circuit, such
as but not limited to a microprocessor, a microcontroller, a complex instruction
set computing (CISC) microprocessor, a reduced instruction set computing (RISC)
microprocessor, a very long instruction word (VLIW) microprocessor, a graphics
processor, a digital signal processor (DSP), or any other type of processor or
processing circuit.
Other types of circuits that can be included in electronic assembly
4
are a custom circuit, an application-specific integrated circuit (ASIC), or the
like, such as, for example, one or more circuits (such as a communications circuit
7) for use in wireless devices like cellular telephones, pagers, portable
computers, two-way radios, and similar electronic systems. The IC can perform any
other type of function.
Electronic system
1 can also include an external memory
10,
which in turn can include one or more memory elements suitable to the particular
application, such as a main memory
12 in the form of random access memory
(RAM), one or more hard drives
14, and/or one or more drives that handle
removable media
16 such as floppy diskettes, compact disks (CDs), digital
video disk (DVD), and the like.
Electronic system
1 can also include a display device
8,
one or more speakers
9, and a keyboard and/or controller
20, which
can include a mouse, trackball, game controller, voice-recognition device, or any
other device that permits a system user to input information into and receive information
from the electronic system
1.
FIG. 2 is a cross-sectional view of a prior art IC package
40 showing
die side capacitors (DSCs)
54, land side capacitors (LSCs)
56, and
embedded chip capacitors (ECCs)
58.
IC package
40 includes an IC or die
50 mounted in "flip-chip" orientation
with its terminals or bumps (not shown) facing downward to couple with corresponding
terminals or pads (not shown) on the upper surface of an IC package substrate
60
through solder balls
52.
IC package substrate
60 can be a single-layer or multi-layer board, and
it can include additional terminals or lands (not shown) on its opposite surface
for mating with additional packaging structure, such as a printed circuit board
(not shown), through solder balls
62. IC package substrate
60 can
form part of a chip package for packaging die
50.
As mentioned earlier, decoupling capacitors are often used to provide a stable
signal or stable supply of power to the IC circuitry. Capacitors are further utilized
to dampen power overshoot when an electronic device (e.g., an IC-based processor)
is powered up, and to dampen power droop when the device begins using power. For
example, a processor that begins performing a calculation may rapidly need more
current than can be supplied by the on-chip capacitance. In order to provide such
capacitance and to dampen the power droop associated with the increased load, off-chip
capacitance should be available to respond to the current need within a sufficient
amount of time. If insufficient voltage is available to the processor, or if the
response time of the capacitance is too slow, the die voltage may collapse.
The localized portions of a die that require large amounts of current in short
periods of time are often referred to as die "hot spots." Off-chip capacitors,
such as decoupling capacitors and capacitors for dampening power overshoot or droop,
are generally placed as close as practical to a die load or hot spot in order to
increase the capacitors' effectiveness. Often, the off-chip capacitors are surface-mounted
to the die side or land side of the package upon which the die is mounted.
Die side capacitors
54, as their name implies, are mounted on the same
side of the IC package
40 as the die
50. Land side capacitors
56
are mounted on the opposite side of the IC package
40, on the underside
of IC package substrate
60. Embedded chip capacitors
58 are embedded
in IC package substrate
60.
To be effective, the inductance of off-chip capacitors needs to be low. Thus,
it is desirable to minimize the electrical distance between the off-chip capacitors
and the die
50, thus reducing the inductance value. This can be achieved
by placing the off-chip capacitors as electrically close as possible to the die
50.
Still referring to FIG. 2, DSCs
54 are mounted around the perimeter
of the die
50, and provide capacitance to various points on the die through
traces and vias (not shown) and planes in the IC package substrate
60. Because
DSCs
54 are mounted around the perimeter of the die
50, the path
length between a hot spot and a DSC
54 may result in a relatively high inductance
feature between the hot spot and the DSC
54.
In contrast, LSCs
56 can be mounted directly below die
50 on the
underside of IC package substrate
60, and thus directly below some die hot
spots. Thus, in some cases, LSCs
56 can be placed electrically closer to
the die hot spots than can DSCs
54, resulting in a lower inductance path
between the die hot spot and the capacitance. However, the package also includes
terminals (not shown), such as pins or lands, located on its land side. In some
cases, placement of LSCs
56 on the package's land side would interfere with
these land side terminals. Thus, the use of LSCs
56 is not always an acceptable
solution to the inductance problem.
ECCs
58 are embedded in the IC package substrate
60 below the
die
50, and they can generally be placed closer to the die
50 than
either DSCs
54 or LSCs
56. However, an IC package substrate
60
can comprise a complex, extensive infrastructure of conductors, including traces,
vias, conductive plates, reference planes, shunts, and the like. In some cases,
placement of ECCs
58 within IC package substrate
60 would interfere
with this infrastructure, so the use of ECCs
58 is not always feasible.
In addition to the inductance issues described above, additional issues are raised
by the industry's trend to continuously reduce device sizes and packing densities.
Because of this trend, the amount of package real estate available to surface-mounted
capacitors and to embedded capacitors is becoming increasingly smaller.
FIG. 3 illustrates a top view of an IC mounting region
104 of an IC package
substrate
102, and a plurality of relatively short capacitors
110
overlying the IC mounting region
104, in accordance with an embodiment of
the invention. IC package substrate
102 can be of any suitable type and
composition, such as an organic or ceramic material.
"IC mounting region", as used herein, means an area on a surface of a substrate
that contains mounting conductors, terminals, or pads.
IC mounting region
104, outlined by a dashed line, represents the projection
of an IC (such as IC
122 of FIG. 4) upon IC package substrate
102.
IC mounting region
104 comprises a plurality of conductors or terminals
106 and
108. Terminals
106 are of a first polarity type for
coupling to a first potential (e.g. Vcc), and terminals
108 are of a second
polarity type for coupling to a second potential (e.g. ground).
Conductors
106 and
108 can be of any suitable type, geometry,
and composition. In an embodiment shown in FIG. 3, conductors
106 and
108
are conductive bars (also referred to as "C4 bars") that are disposed across the
upper surface of IC package substrate
102.
Although conductors
106 and
108 are illustrated in FIG. 3
as being bar-like in shape, they could be ellipsoid, square, rectangular, or any
other suitable shape. Also, although conductors
106 and
108 are shown
as substantially parallel to one another, they need not necessarily be parallel,
and they can be of any suitable geometric pattern. In one embodiment, conductors
106 and
108 are implemented as terminals or pads on the substantially
planar upper surface of IC package substrate
102.
"Suitable", as used herein, means having characteristics that are sufficient
to produce the desired result(s). Suitability for the intended purpose can be determined
by one of ordinary skill in the art using only routine experimentation.
Each conductor
106 or
108 is to be electrically coupled to a respective
terminal of an IC (such as IC
122, FIG.
4). Each conductor
106
or
108 is also physically and electrically coupled to a respective terminal
of at least one capacitor
110. Capacitor
110 can be of the same type
as capacitor
710 shown in FIG.
15 and described further below. In
one embodiment, capacitor
110 is an "0201", i.e. 20 mils (0.508 mm) by 10
mils (0.254 mm).
Capacitors
110 comprise a terminal
112 of a first polarity
type, and a terminal
114 of a second polarity type. Each terminal
112
of each capacitor
110 is physically and electrically coupled to a conductor
106 of a first polarity type. Likewise, each terminal
114 of each
capacitor
110 is physically and electrically coupled to a conductor
108
of a second polarity type.
It will be noted that there is additional space for another capacitor
110
in the upper-left hand corner of IC mounting region
104, and for several
additional capacitors
110 in the right-hand column of IC mounting region
104. Such capacitors
110 could be included, if desired, or not. The
number and placement of capacitors
110 to be positioned within IC mounting
region
104 can be varied as necessary to satisfy the particular requirements
of the overall IC package. In one embodiment, the plurality of capacitors
110
are distributed substantially throughout the IC mounting region
104, and
each capacitor
110 is in electrical contact with at least one of the conductors
106 or
108.
In the embodiment illustrated in FIG. 3, the plurality of capacitors
110
are arranged as a plurality of sets of capacitors
110. Each set of capacitors
110 comprises one or more capacitors that are aligned substantially end-to-end.
For example, the capacitors
110 of each row of capacitors
110 in
IC mounting region
104 can constitute a set of capacitors
110.
It will be noted that, in the embodiment illustrated in FIG. 3, capacitors
110
are mounted atop conductors
106 and
108. In other embodiments, such
as that illustrated in FIGS. 10 and 11 to be discussed further below, the capacitors
are located beside (e.g. between) the conductors of the IC package substrate.
FIG. 4 illustrates a cross-sectional representation of IC package
120,
including die
122, and a cross-sectional view of capacitors
110 and
IC package substrate
102 shown in FIG. 3 taken along line
101 of
FIG.
3.
Die
122 can be of any suitable type. In one embodiment, die
122
is a high performance processor. In other embodiments, die
122 could be
an ASIC, custom chip, wireless filter circuit, or any other type of circuit. The
present invention is not limited to any particular type of die.
Die
122 comprises a plurality of bumps or terminals
126 and
128
on its lower surface. Terminals
126 are of a first polarity type (e.g. Vcc),
and terminals
128 are of a second polarity type (e.g. ground). Terminals
126 and
128 can be of any suitable type, geometry, and composition.
Although terminals
126 and
128 can be bar-like in shape (referred
to in some embodiments as "Alternative Bump Metallurgy" (ABM)), they could alternatively
be ellipsoid, square, rectangular, or any other suitable shape. In some embodiment,
terminals
126 and
128 are metal bumps.
Terminals
126 and
128 can be formed of any suitable material,
including metals or metal alloys known to those of ordinary skill in the art, such
as lead, solder, copper, silver, aluminum, gold, etc.
Also, although terminals
126 and
128 are shown disposed over
substantially the entire lower surface of die
122, in other embodiments,
terminals
126 and
128 may be disposed primarily in a central or core
region of the lower surface of die
122, and other terminals, such as input/output
(I/O) terminals may be disposed around the periphery of the lower surface of die
122.
Still referring to FIG. 4, one of terminals
126 of die
122 is
coupled to terminals
112 of two adjacent capacitors
110, and one
of conductors
106 of IC package substrate
102 is coupled to the terminals
112 of the two adjacent capacitors
110. One of terminals
128
of die
122 is coupled to terminal
114 of capacitor
110, and
one of conductors
108 of IC package substrate
102 is coupled to the
terminal
114 of capacitor
110.
Die
122 is thus electrically coupled to IC package substrate
102
through terminals
126 and
128 of die
122, capacitors
110,
and conductors
106 and
108 of IC package substrate
102.
FIG. 5 illustrates a top view of an IC mounting region
204 of an IC package
substrate
202, and a plurality of relatively long capacitors
210
overlying the IC mounting region
204, in accordance with an embodiment of
the invention.
IC package substrate
202, IC mounting region
204, and conductors
206 and
208 can be similar to those previously illustrated in FIGS.
3 and 4.
Each conductor
206 or
208 is to be electrically coupled to a respective
terminal of an IC (such as IC
222, FIG.
6). At least one capacitor
210 lies atop conductors
206 and
208.
Each conductor
206 or
208 is physically and electrically coupled
to a respective terminal of at least one capacitor
210. Capacitor
210
can be of the same type as capacitor
720 shown in FIG.
16 and described
further below. For example, each capacitor
210 comprises a plurality of
terminals
212 of a first polarity type, and a plurality of terminals
214
of a second polarity type.
Each terminal
212 of each capacitor
210 is physically and electrically
coupled to a conductor
206 of a first polarity type. Likewise, each terminal
214 of each capacitor
210 is physically and electrically coupled
to a conductor
208 of a second polarity type.
More or fewer capacitors
210 could be utilized. The number and placement
of capacitors
210 to be positioned within IC mounting region
204
can be varied as necessary to satisfy the particular requirements of the overall
IC package. In one embodiment, the plurality of capacitors
210 are distributed
substantially throughout the IC mounting region
204, and each capacitor
210 is in electrical contact with at least one of the conductors
206
or
208.
FIG. 6 illustrates a cross-sectional representation of an IC package
220,
including a die
222, and a cross-sectional view of a capacitor
210
and IC package substrate
202 shown in FIG. 5 taken along line
201
of FIG.
5. In this view, the section is taken through terminals
206
and
208 that are disposed along one edge of the uppermost capacitor
210.
Die
222 comprises a plurality of bumps or terminals
226 and
228
on its lower surface. Terminals
226 and
228 can be similar to those
shown and described above regarding FIG.
4.
One of terminals
226 of die
222 is coupled to terminal
212
of capacitor
210, and one of conductors
206 of IC package substrate
202 is coupled to terminal
212 of capacitor
210. One of terminals
228 of die
222 is coupled to terminal
214 of capacitor
210,
and one of conductors
208 of IC package substrate
202 is coupled
to terminal
214 of capacitor
210.
Die
222 is thus electrically coupled to IC package substrate
202
through terminals
226 and
228 of die
222, capacitor
210,
and conductors
206 and
208 of IC package substrate
202.
FIG. 7 illustrates a top view of an IC mounting region
254 of an IC package
substrate
252, and a plurality of relatively long capacitors
260
overlying the IC mounting region
254, in accordance with an embodiment of
the invention.
IC package substrate
252 and IC mounting region
254 can be similar
to those previously illustrated in FIGS. 5 and 6. In this embodiment, conductors
256 and
258 are long parallel conductors, similar to those illustrated
in FIG. 5, except that conductors
256 and
258 are arranged on a diagonal
(i.e., non-orthogonally) rather than being orthogonal to capacitors
260.
Capacitors
260 lie atop conductors
256 and
258. In other embodiments,
conductors
256 and
258 could be arranged in other orthogonal or non-orthogonal
patterns, such as but not limited to concentric circles, concentric rectangles,
L's, zigzags, serpentine patterns, or combinations thereof.
Each conductor
256 or
258 is physically and electrically coupled
to a respective terminal of at least one capacitor
260. Capacitor
260
can be of the same type as capacitor
730 shown in FIG.
17 and described
further below. For example, each capacitor
260 comprises a plurality of
terminals
262 of a first polarity type, and a plurality of terminals
264
of a second polarity type. Each terminal
262 of each capacitor
260
is physically and electrically coupled to a conductor
256 of a first polarity
type. Likewise, each terminal
264 of each capacitor
260 is physically
and electrically coupled to a conductor
258 of a second polarity type.
More or fewer capacitors
260 could be utilized. The number and placement
of capacitors
260 to be positioned within IC mounting region
254
can be varied as necessary to satisfy the particular requirements of the overall
IC package. In one embodiment, the plurality of capacitors
260 are distributed
substantially throughout the IC mounting region
254, and each capacitor
260 is in electrical contact with at least one of the conductors
256
or
258.
FIG. 8 illustrates a top view of a capacitor array
310, in accordance
with an embodiment of the invention. Capacitor array
310 comprises a plurality
of terminals
312 of a first polarity type, and a plurality of terminals
314 of a second polarity type. Although capacitor array
310 is illustrated
as being substantially square, it could be implemented in any other suitable geometry.
Also, while terminals
312 and
314 are illustrated as being arranged
in a grid of alternating polarity types, and that they are disposed over substantially
the entire upper surface of capacitor array
310, they could be arranged
in many other different patterns and groupings. The invention is not intended to
be limited to any particular type of capacitor array
310.
In one embodiment, each terminal
312 on the upper surface of capacitor
array
310 has a corresponding terminal
342 of the same polarity type
on the lower surface. Likewise, each terminal
314 on the upper surface of
capacitor array
310 has a corresponding terminal
344 of the same
polarity type on the lower surface. In other embodiments, capacitor array
310
can have terminals arranged in a different manner on its upper and lower surfaces.
For example, the terminals can be bar-like terminals, or terminals of other geometrical
shapes, or they can be a combination of different shapes of terminals. In one embodiment,
capacitor array
310 can be a large-scale chip capacitor.
FIG. 9 illustrates a cross-sectional representation of an IC package
320,
including a die
322, and a cross-sectional view of the capacitor array
310
shown in FIG. 8 taken along line
311 of FIG.
8.
In this view, the section is taken through terminals
312 and
314
that are disposed closest to the lower edge of capacitor array
310. As mentioned
earlier, in this embodiment of capacitor array
310, each terminal
312
on the upper surface of capacitor array
310 has a corresponding terminal
342 of identical polarity type on the lower surface of capacitor array
310.
Likewise, each terminal
314 on the upper surface of capacitor array
310
has a corresponding terminal
344 of identical polarity type on the lower
surface of capacitor array
310. However, in other embodiments of capacitor
array
310, the arrangement of terminals on the upper and lower surfaces
of capacitor array
310 could be different.
Die
322 comprises a plurality of bumps or terminals
326 and
328
on its lower surface. Terminals
326 and
328 are of first and second
polarity types, respectively. Terminals
326 and
328 are arranged
on the lower surface of die
322 in a pitch and placement corresponding to
the pitch and placement of terminals
312 and
314, respectively, of
capacitor array
310.
One of terminals
326 of a first polarity type of die
322 is coupled
to terminal
312 of a first polarity type on the upper surface of capacitor
array
310, and one of terminals
342 of the first polarity type on
the lower surface of capacitor array
310 is coupled to a conductor
306
of a first polarity type of IC package substrate
302.
Similarly, one of terminals
328 of a second polarity type of die
322 is coupled to terminal
314 of a second polarity type on the upper
surface of capacitor array
310, and one of terminals
344 of the second
polarity type on the lower surface of capacitor array
310 is coupled to
a conductor
308 of the second polarity type of IC package substrate
302.
Die
322 is thus electrically and physically coupled to IC package substrate
302 through terminals
326 and
328 of die
322, capacitor
array
310, and conductors
306 and
308 of IC package substrate
302.
In FIG. 9, capacitor array
310 is illustrated as having a relatively large
footprint in the core area of die
322; however, in other embodiments it
can have a relatively smaller footprint, leaving relatively more area on the lower
surface of die
322 for I/O terminals.
IC package
320 can form part of an
