Electronic control unit Number:7,178,069 from the United States Patent and Trademark Office (PTO) owispatent An electronic control unit includes a serial communication circuit capable of easily confirming presence or absence of communication error while regular transmission/regular report between master station and sub station are performed timely. First and second control circuit sections 200a (master station) and 200b (substation) communicate mutually via series-parallel converters 117, 127. The master station includes regular transmission device 201 and irregular transmission device 211. The substation includes regular report device 221, confirmation reply device 205 and report reply device 215 relative to transmission data from the master station, and unprocessed data table 204. The confirmation reply device 205 and report reply device 215 confirm whether or not downstream communication from the master station to sub station is normal. When any error is present in regular report data through upstream communication, the error is confirmed on the fact the irregular transmission device 211 makes retransmission readout request.<H Electronic, control, Electronic, cont, 7178069.html, Patent, pto, 7178069

Title: Electronic control unit

Abstract: An electronic control unit includes a serial communication circuit capable of easily confirming presence or absence of communication error while regular transmission/regular report between master station and sub station are performed timely. First and second control circuit sections 200a (master station) and 200b (substation) communicate mutually via series-parallel converters 117, 127. The master station includes regular transmission device 201 and irregular transmission device 211. The substation includes regular report device 221, confirmation reply device 205 and report reply device 215 relative to transmission data from the master station, and unprocessed data table 204. The confirmation reply device 205 and report reply device 215 confirm whether or not downstream communication from the master station to sub station is normal. When any error is present in regular report data through upstream communication, the error is confirmed on the fact the irregular transmission device 211 makes retransmission readout request.

Patent Number: 7,178,069 Issued on 02/13/2007 to Hashimoto, et al.

Inventors: Hashimoto; Kohji (Tokyo, JP), Nakamoto; Katsuya (Tokyo, JP), Iwagami; Yuki (Tokyo, JP), Ishii; Akihiro (Tokyo, JP)
Assignee: Mitsubishi Denki Kabushiki Kasiha (Tokyo, JP)

Appl. No.: 10/788,439

Filed: March 1, 2004

Foreign Application Priority Data


Aug 08, 2003 [JP]			P2003-290006

Current U.S. Class: 714/47 ; 701/1; 701/36; 714/11; 714/18; 714/48; 714/49

Current International Class: G06F 11/00 (20060101)

Field of Search: 714/11,18,48,49,47 701/1,36

References Cited [Referenced By]

U.S. Patent Documents


5812880	September 1998	Goto et al.
5966305	October 1999	Watari et al.
6678586	January 2004	Nakamoto et al.
2002/0035650	March 2002	Nakamoto et al.
2002/0040261	April 2002	Nakamoto et al.

Foreign Patent Documents


09-162814	Jun., 1997	JP
2000-267948	Sep., 2000	JP
2002-108835	Apr., 2002	JP
2002-235598	Aug., 2002	JP
2002-333901	Nov., 2002	JP

Primary Examiner: Beausoliel, Jr.; Robert W.
Assistant Examiner: Ehne; Charles
Attorney, Agent or Firm: Sughrue Mion, PLLC

Claims

What is claimed is:

1. An electronic control unit comprising: a first control circuit section containing a program memory, an operation processing RAM memory, a microprocessor, and a first series-parallel converter; and a second control circuit section containing a communication control circuit section at least for carrying out communication of monitoring and control signals, a data memory, and a second series-parallel converter, wherein serial communication of monitoring and control signals is carried out mutually between said first and second control circuit sections via said first and second series-parallel converters, wherein said first control circuit section includes regular transmission means and irregular transmission means, and said second control circuit section includes regular report means and an unprocessed data table, wherein said regular transmission means acts as write setting means that regularly transmits control output data or constant set data from said first control circuit section with respect to said second control circuit section, and executes a retransmission processing from the first control circuit section to the second control circuit section if any communication error in a confirmation reply of whether or not the second control circuit section has received said regular transmission data, is present, wherein said regular report means acts as one-way input readout means which regularly reports monitoring input data and status information from said second control circuit section to said first control circuit section, whereby no confirmation reply of whether or not the first control circuit section has received said regular report data is carried out, wherein said irregular transmission means operates as transmission means that is applicable when any error is present in a report communication provided by said regular report means, and is applied if a readout request for monitoring input data of a specified address from said first control circuit section to said second control circuit section is required, and if a readout request for reading out and checking a write save data having been written and set by said regular transmission means is required; wherein said irregular transmission means further operates as readout request means that makes a readout request from the first control circuit section to the second control circuit section if any communication error in a report reply of a monitoring input data of a specified address or a write save data is present, said report reply being carried out as a confirmation reply related said second control circuit section having received said irregular transmission data, wherein said unprocessed data table operates as a receiving-side command memory arranged so as to sequentially save command data for executing a confirmation reply when said second control circuit section receives any transmission data from said first control circuit section, and to sequentially erase said saved data when said second control circuit section transmits the confirmation reply data to said first control circuit section; and the transmission of a regular report data is carried out while preventing upstream communication jam-up from said second control circuit section to said first control circuit section with said unprocessed data table.

2. The electronic control unit according to claim 1, wherein said first control circuit section comprises a reply-waiting data table and retransmission means, wherein said reply-waiting data table operates as a transmission-side command memory arranged so as to sequentially save a transmission command that said first control circuit section has transmitted to said second control circuit section with regular transmission means and irregular transmission means, and to sequentially erase said saved command when receiving a confirmation reply data or a report reply data from the second control circuit section, wherein said retransmission means operates when there is any communication error in a confirmation reply or a report reply to said regular transmission means or irregular transmission means, or when a leading transmission command having been stored in said transmission-side command memory is not erased even after a predetermined time period has passed, and transmits transmission data based on said error transmission command; and wherein a transmission command having been transmitted again is deleted from and re-stored in said transmission-side command memory, and a first-in first-out processing is carried out.

3. The electronic control unit according to claim 1, wherein said second control circuit section comprises readout request setting means, wherein said readout request setting means operates as means for making the request for the readout of a selected data memory of a specified address that is provided in said second control circuit section by adding a readout request flag to status information contained in said regular report means, and wherein said first control circuit section is arranged so as to operate when there is a communication error in said regular report data, or when said readout request is present, and is operable to make a readout request for a regular report content or a selected data memory with said irregular transmission means.

4. The electronic control unit according to claim 1, wherein at least one of said regular transmission means or regular report means comprises division circulating means, and wherein said division circulating means operates as means that divides a large number of control output data intended to be regularly transmitted or a large number of monitoring input data intended to be regularly reported, and sequentially divides and transmits or sequentially divides and reports in a cycle corresponding to a required emergency degree, whereby a data amount to be transmitted or reported at a single communication is suppressed.

5. The electronic control unit according to claim 1, wherein said first control circuit section comprises regular report permission means; and said regular report permission means operates as means for storing command data that is transmitted by said regular transmission means to a memory of a predetermined address provided in said second control circuit section, and operates to permit the second control circuit section to transmit said regular report.

6. An electronic control unit comprising: a first control circuit section containing a program memory, an operation processing RAM memory, a microprocessor, and a first series-parallel converter; and a second control circuit section containing a communication control circuit section at least for carrying out communication of monitoring and control signals, a data memory, and a second series-parallel converter, wherein serial communication of monitoring and control signals is carried out mutually between said first and second control circuit sections via said first and second series-parallel converters, wherein said first control circuit section includes regular transmission means and irregular transmission means, and said second control circuit section includes regular report means; said first and second control circuits section include first and second communication error determination means, first and second adding-subtracting means, and first and second error occurrence definition means respectively, and said first control circuit section includes retransmission means, wherein said regular transmission means operates as write setting means that regularly transmits control output data or constant set data from said first control circuit section to said second control circuit section, and executes retransmission processing from the first control circuit section to the second control circuit section if any communication error in confirmation reply of whether or not the second control circuit section has received said regular transmission data is present, wherein said regular report means operates as one-way input readout means which regularly reports monitoring input data and status information from said second control circuit section to said first control circuit section, whereby no confirmation reply of whether or not the first control circuit section has received said regular report data is carried out, wherein said irregular transmission means operates as transmission means that is applicable when any error is present in a report communication provided by said regular report means, and is applied if a readout request for monitoring input data of a specified address from said first control circuit section to said second control circuit section is required, and if a readout request for reading out and checking a write save data having been written and set by the mentioned regular transmission means is required, wherein said irregular transmission means operates as readout request means that makes a readout request from the first control circuit section to the second control circuit section if any communication error in a report reply of a monitoring input data of a specified address or a write save data is present, said report reply being carried out as a confirmation reply to said second control circuit section having received said irregular transmission data, wherein said first and second communication error determination means operate as plural types of receiving error determination means that determine presence or absence of any error regarding various regular and irregular communication packets that a control circuit section on the side where the mentioned determination means is provided has received from the other control circuit section, or that determine a state that any communication packet to be received cannot be received, wherein said first and second adding-subtracting means operate as operation means that adds or subtracts a second variation value when any of said plural types of receiving error determination means determines the presence of error, and subtracts or adds a first variation value when all the receiving error determination means determine the absence of any error to perform an addition-subtraction compensation with respect to a current value memory so as to offset each other, and stops an addition-subtraction compensation with said first variation value at a predetermined normal-side limit value when the determination of the absence of error continues, wherein said first and second error occurrence definition means operate as comparison means that generate first and second error detection signals when a current value of said adding-subtracting means gets out of a scope of a predetermined abnormal-side limit value as a result of accumulation of said first and second variation values, wherein said retransmission means operate when any error is present in a transmission data provided from said first control circuit section to the mentioned second control circuit section, or when error is present in a confirmation reply data in response to said transmission data, and with which the first control circuit section transmits a communication packet corresponding to the old transmission command, and adds or subtracts a second variation value with respect said first adding-subtracting means, and wherein said second variation value is set to a value smaller than a permitted accumulation value, being a difference between said abnormal-side limit value and normal-side limit value, and stopping the operation, or initialization and restart of said first or second control circuit section is carried out responsive to the occurrence of said error detection signal.

7. The electronic control unit according to claim 6, wherein said first and second control circuit sections comprise first and second initialization means, wherein said first initialization means operates as means that operates when said-first error occurrence definition means generates an error detection signal, resets a current value of said first adding-subtracting means at a predetermined initialization value at the start of operation, and initializes and restarts a communication control circuit section provided in said second control circuit section, wherein said second initialization means operates as means that operates when said second error occurrence definition means generates an error detection signal, resets a current value of said second adding-subtracting means at a predetermined initialization value at the start of operation, and initializes to restart or stop the operation of a microprocessor provided in said first control circuit section, and wherein an initialization value of the first and second adding-subtracting means to be reset by said first and second initialization means is a value close to said abnormal-side limit value from said normal-side limit value.

8. The electronic control unit according to claim 6, wherein said first and second communication error determination means comprise at least one of bit information monitoring means and reply delay monitoring means or receiving interval monitoring means, wherein said bit information monitoring means operates as bit error determination means for determining presence or absence of any lack or mix in bit information such as parity check or sum check relative to a serial data communicated between said first and second control circuit sections, wherein said reply delay monitoring means operates as reply response error determination means for making an error determination at the first control circuit section, being a source side when a reply data from said second control circuit section in response to any data, which said first control circuit section has transmitted, cannot be received even when a predetermined reply response time period has passed, wherein said receiving interval monitoring means operates as receiving interval error determination means for making an error determination when a receiving interval time period of the other-side control circuit section with respect to a regular transmission data that said first control circuit section transmits or a regular report data that said second control circuit section transmits exceeds a predetermined value, and wherein said adding-subtracting means performs an addition-subtraction compensation with a first variation value when none of said bit information monitoring means, reply delay monitoring means, and receiving interval monitoring means makes an error determination.

9. The electronic control unit according to claim 8, wherein said second variation value, which said adding-subtracting means adds or subtracts when the determination of said bit information monitoring means is a communication error, is a value larger than said first variation value; and wherein a variation value, which said adding-subtracting means adds or subtracts when the determination of said reply delay monitoring means or receiving interval monitoring means is a communication error, is a third variation value, being a value different from said second variation value; and further said third variation value is a value smaller than a permitted accumulation value, being a difference between said abnormal-side limit value and normal-side limit value.

10. The electronic control unit according to claim 8, wherein said first control circuit section comprises a reply-waiting data table, wherein said reply-waiting data table operates as a transmission-side command memory arranged so as to sequentially save a transmission command, which said first control circuit section has transmitted to said second control circuit section, and to erase said saved command when said first control circuit section has received a confirmation reply data from said second control circuit section, and wherein said reply delay monitoring means operates as reply error determination means for making an error determination when a save time period of leading data remained in said transmission-side command memory exceeds a predetermined value, and a command determined as a reply error and wherein a command having a confirmation reply of any receiving failure are sequentially deleted from said transmission-side command memory, and stored anew in the transmission-side command memory at the time of being transmitted again.

11. The electronic control unit according to claim 8, wherein said first control circuit section comprises a first set data memory; wherein said first set data memory acts as a data memory in which stored is a part or all of various control constants such as first variation value, second variation value, normal-side limit value, abnormal-side limit value, or initial value to be processed in said first adding-subtracting means; or a part or all of various control constants such as permitted values of a reply response time period or a receiving interval time period to be used in said first communication error determination means; and wherein a part or all of said various control constants are transferred and written from a non-volatile program memory cooperating with said microprocessor.

12. The electronic control unit according to claim 8, wherein said second control circuit section comprises a second set data memory, wherein said second set data memory operates as a data memory in which a part or all of various control constants such as first variation value, second variation value, normal-side limit value, abnormal-side limit value, or initial value to be processed in said second adding-subtracting means are stored; or wherein a part or all of various control constants such as permitted value of a receiving interval time period to be used in said second communication error determination means are stored, and wherein a part or all of said various control constants are transmitted and written from a non-volatile program memory cooperating with said microprocessor via said first and second series-parallel converters.

13. The electronic control unit according to claim 6, wherein said second control circuit section comprises current value report means, wherein said current value report means operates as means for adding a current value of said second adding-subtracting means to said status information, and regularly reporting result information to said first control circuit section.

14. The electronic control unit according to claim 6, wherein said first control circuit section comprises a direct input/output signal interface circuit, and either said first or second control circuit section comprises a watchdog timer and error occurrence storage means, wherein said direct input/output signal interface circuit is bus-connected to said microprocessor, wherein said microprocessor is arranged so as to generate an output signal in response to a direct input signal having been inputted via said direct input signal interface, an indirect input signal having been received by serial communication from a second series-parallel converter provided in said second control circuit section, and a content of said program memory to drive an electrical load group, which is connected to said direct output signal interface circuit, and to transmit an indirect output signal via said first and second series-parallel converters to the second control circuit section, wherein said watchdog timer operates as a run-away monitoring timer circuit that monitors a watchdog clear signal, being a pulse train, which said microprocessor generates, and generates a reset pulse signal when a pulse width of said watchdog clear signal exceeds a predetermined value, wherein error occurrence storage means operates as an error storage circuit that stores said first and second error detection signals or a reset pulse signal to bring annunciation means such as alarm, display, printing, and history save in operation when said error detection signals are generated, and when the reset pulse signal provided by said watchdog timer is generated, and wherein said microprocessor is initialized and restarted when said watchdog timer generates a reset pulse signal and when said second error detection signal is generated, and a communication control circuit section of said second control circuit section is initialized and restarted when said watchdog timer generates a reset pulse signal and when said first error detection signal is generated.

15. The electronic control unit according to claim 14, wherein said second control circuit section comprises an auxiliary CPU, and said first control circuit section comprises run-away monitoring means with respect to said auxiliary CPU, wherein said auxiliary CPU operates as a microprocessor that is contained in said second control circuit section along with an auxiliary program memory cooperating with said auxiliary CPU, an operation processing auxiliary RAM memory, an indirect input/output signal interface circuit and a second series-parallel converter, transmits an indirect input signal associated with a signal having been inputted via said indirect input signal interface circuit to the first control circuit section via said first and second series-parallel converters, and drives an electrical load group that are connected to said indirect output signal interface circuit with an output associated with an indirect output signal having been received from said first control circuit section via said first and second series-parallel converters, wherein said run-away monitoring means operates as means for monitoring with said microprocessor a watchdog clear signal, being a pulse train that said auxiliary CPU generates, and generating a reset pulse signal when a pulse width of said watchdog clear signal exceeds a predetermined value, and wherein when said run-away monitoring means generates a reset pulse signal, when said watchdog timer generates a reset pulse signal and when said first error detection signal is generated, said auxiliary CPU is initialized and restarted, and said error storage circuit is arranged to store the occurrence of error.

16. The electronic control unit according to claim 14, wherein said error occurrence storage means is constituted of a count storage circuit, wherein said count storage circuit counts an OR output with respect to said first and second error detection signals and a reset pulse signal provided by the watchdog timer or the run-away monitoring means, and brings said annunciation means in operation when said count value reaches a predetermined value.

17. The electronic control unit according to claim 14, wherein at least one of said first and second control circuit sections comprises driving stop means and clear means, wherein said driving stop means operates as a gate circuit that operates when said error occurrence storage means stores an error occurrence to inhibit driving of specified electrical loads, being a part of said electrical load group, and wherein said clear means operates as means for initializing an error storage signal provided by said error occurrence storage means by manual operation such as turning on a power supply switch again.

18. The electronic control unit according to claim 16, wherein at least one of said first and second control circuit sections comprises driving stop means and clear means, wherein said driving stop means operates as a gate circuit that operates when a count value of said count storage circuit is not less than a predetermined value to inhibit driving of specified electrical loads, being a part of said electrical load group, and wherein said clear means operates as means for initializing a current value of said count storage circuit by manual operation such as turning on a power supply switch.

Description

This application is related to application Ser. No. 10/788,370, filed on Mar. 1, 2004 commonly assigned with the present invention.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an on-vehicle electronic control unit having a microprocessor built-in for use in, for example, a fuel supply control of an automobile engine and, more particularly, to an improvement of an electronic control unit that includes a plurality of control circuit sections electrically divided so as to carry out a mutual communication of serial signals.

2. Description of the Related Art

Electronic control unit in which information exchange by a method of serial communication is carried out among a plurality of microprocessors sharing functions, and communication error is detected to carry out error processing, has been practically and widely used in various fields.

For example, according to the Japanese Patent Publication (unexamined) No. 108835/2002, the following "On-Vehicle Electronic Control Unit" is proposed. This on-vehicle electronic control unit comprises serial communication means that is constituted of a main CPU and a sub CPU, and is capable of transferring a control constant at the time of start of operation and mutually communicating a variety of data during the operation freely. Further disclosed in this on-vehicle electronic control unit are means for sum check error and retransmission processing relative to serial communication data, means for timeout check error and reset processing of microprocessor, or means for inhibition processing of control output.

According to the Japanese Patent Publication (unexamined) No. 333901/2002, another "On-Vehicle Electronic Control Unit" is proposed. This on-vehicle electronic control unit comprises serial communication means that is constituted of an integrated circuit section having a microprocessor and a communication control circuit, and is capable of transferring a control constant at the time of start of operation and mutually communicating a variety of data during the operation. In this on-vehicle electronic control unit, an example of a communication packet arrangement is described in detail.

On the other hand, according to the Japanese Patent Publication (unexamined) No. 162814/1997, the following "Communication Monitoring Unit" has been proposed. This communication monitoring unit comprises a communication control section that controls data communication and outputs an error notification signal upon detecting any communication error, an error counter that counts up in response to the input of the above-mentioned error notification signal, and an annunciation section that announces a communication error in response to the fact that a count value of this error counter has reached a plus predetermined value (threshold). In this communication-monitoring unit, there is provided counter subtraction means that counts down a count value of the above-mentioned error counter upon the fact that the control of data communication is normally carried out in the above-mentioned communication control section. Further it is arranged so as to prevent an alarm generation in vain with respect to a sporadic and chronic error in which an error state automatically recovers, while immediately making an annunciation with respect to a fatal and continuous failure.

Further, according to the Japanese Patent Publication (unexamined) No. 267948/2000, the following "Electronic Apparatus and Control Method of the Electronic Apparatus, and Recording Medium Recording a Controlling Software of the Electronic Apparatus" is proposed. This electronic apparatus comprises a first unit having a first computer and a second unit that includes a second computer, and is constructed detachably with respect to the above-mentioned first unit. In this electronic apparatus, the above-mentioned first computer comprises means for transmitting an operation confirmation signal in order to confirm the operation of the above-mentioned second computer to the above-mentioned second computer at intervals of a predetermined time period; and the above-mentioned second computer comprises means for replying an in-operation signal indicating a normal operation in response to the above-mentioned confirmation signal at the time of normal operation. Further, the above-mentioned first computer comprises means for resetting the above-mentioned second computer in the case where the above-mentioned in-operation signal is not replied within a predetermined standby time period to the transmission of the above-mentioned operation confirmation signal, and reliably resets the second computer when the second unit is mounted.

As for the rest, in association with this invention, according to the Japanese Patent Publication (unexamined) No. 235598/2002, the following "Vehicle Control Unit" is proposed. This vehicle control unit includes error occurrence storage means for restarting a microprocessor after having assured safety when the microprocessor such as main CPU or sub CPU, which is contained in any on-vehicle electronic device, runs away. However, the one that is described in this publication does not relate to a communication control.

According to the Japanese Patent Publication (unexamined) No. 108835/2002, five types of packets of A.cndot.control constant transmission, B.cndot.transmission of regular data, C.cndot.transmission of irregular data, D.cndot.transmission of readout request command, E.cndot.transmission of required data, are applied as downstream communication from a main CPU to a sub CPU.

Likewise, as upstream communication, all the communication packets of B E, except for A.cndot.control constant transmission, are applied on an equal basis.

Furthermore, a receiving confirmation reply or a retransmission request can be made with respect to each of the upstream and downstream communications, so that an extremely high degree of freedom is achieved. A problem, however, exists in that a communication jam-up takes place at the time of occurrence of some sort of communication error making it incapable to carry out transmitting and receiving an essentially required data.

According to the Japanese Patent Publication (unexamined) No. 333901/2002, types of a communication packet is enormously reduced. In this control unit, 5 types of communication packets of A.cndot.control constant transmission, B.cndot.whole input readout request, C.cndot.whole output transmission, D.cndot.specific input readout request specifying an address, E.cndot.specific output transmission specifying an address as a downstream communication, are applied from a master station to a sub station; while no spontaneous upstream communication packet from the sub station to the master station is prepared.

Accordingly, reporting from the sub station cannot be carried out without request from the master station, and therefore a regular request comes to be necessary in the case of presence of any regular report data, eventually resulting in a problem that unnecessary downstream communication takes place.

According to the Japanese Patent Publication (unexamined) No. 162814/1997, there remain the following problems. That is, a problem exists in that in case of setting a threshold for determining an error to a large value, any response delay is generated in detection of error occurrence subsequent to a normal communication. On the other hand, in case of setting a threshold for determining an error to a small value, too-sensitive error detection is carried out even when any slight and sporadic error occurs.

Moreover, response to a variety of numerous communication errors and processing of timeout error or retransmission are not described from a comprehensive viewpoint.

According to the Japanese Patent Publication (unexamined) No. 267948/2000, a problem exists in that a computer is reset only with a single timeout. A further problem exists in that processing of sum check error or retransmission is not described from a comprehensive viewpoint.

According to the Japanese Patent Publication (unexamined) No.235598/2002, a problem exists in that although timeout of communication can be detected by monitoring the run-away of microprocessor, communication error in terms of lack or mix in bit such as sum check error is not monitored.

SUMMARY OF THE INVENTION

Accordingly, a first object of the present invention is to provide an electronic control unit that includes first and second control circuit sections electrically divided so as to perform mutual communication of serial signals, the electronic control unit being arranged such that a regular transmission from the first control circuit section acting as a master station to the second control circuit section acting as a sub station, and a regular report from the sub station to the master station can be carried out as required; and furthermore confirmation of presence or absence of any communication error relative to various communication packets, and a retransmission processing can be easily carried out while preventing communication jam-up.

A second object of this invention is to provide an electronic control unit that is capable of preventing too sensitive error determination with respect to a sporadic and chronic error in which communication error state automatically recovers; and is capable of comprehensively determining number of times of retransmission processing and an error definition timing with respect to a variety of communication errors such as sum check error or timeout error relative to various communication packets.

To accomplish the foregoing objects, according to the first aspect of the invention, an electronic control unit includes:

a first control circuit section containing a program memory, an operation processing RAM memory, a microprocessor, and a first series-parallel converter; and a second control circuit section containing a communication control circuit section at least for carrying out communication of monitoring and control signals, a data memory, and a second series-parallel converter; and in which serial communication of monitoring and control signals is carried out mutually between the mentioned first and second control circuit sections via the mentioned first and second series-parallel converters.

In this electronic control unit, the mentioned first control circuit section includes regular transmission means and irregular transmission means, and the mentioned second control circuit section includes regular report means and an unprocessed data table.

The mentioned regular transmission means acts as write setting means that regularly transmits a control output data or a constant set data from the mentioned first control circuit section to the mentioned second control circuit section, and executes a retransmission processing from the first control circuit section to the second control circuit section in the case of presence of any communication error in confirmation reply of whether or not the second control circuit section has received the mentioned regular transmission data. The mentioned regular report means acts as one-way input readout means which regularly reports a monitoring input data and status information from the mentioned second control circuit section to the mentioned first control circuit section, whereby no confirmation reply of whether or not the first control circuit section has received the mentioned regular report data is carried out.

The mentioned irregular transmission means acts as transmission means that is applicable when any error is present in a report communication provided by the mentioned regular report means, and is also applied when required as to a readout request for a monitoring input data of a specified address from the mentioned first control circuit section to the mentioned second control circuit section, and a readout request for reading out and checking a write save data having been written and set by the mentioned regular transmission means.

Furthermore, the mentioned irregular transmission means acts as readout request means that makes a readout request again from the first control circuit section to the second control circuit section in the case of presence of any communication error in a report reply of a monitoring input data of a specified address or a write save data, the mentioned report reply being carried out as a confirmation reply to the fact that the mentioned second control circuit section has received the mentioned irregular transmission data.

The mentioned unprocessed data table acts as a receiving-side command memory arranged so as to sequentially save a command data for executing a confirmation reply when the mentioned second control circuit section receives any transmission data from the mentioned first control circuit section, and to sequentially erase the mentioned saved data when the mentioned second control circuit section transmits the confirmation reply data to the mentioned first control circuit section.

The transmission of a regular report data can be carried out while preventing upstream communication jam-up from the mentioned second control circuit section to the mentioned first control circuit section with the mentioned unprocessed data table.

According to the second aspect of the invention, an electronic control unit includes:

a first control circuit section containing a program memory, an operation processing RAM memory, a microprocessor, and a first series-parallel converter; and a second control circuit section containing a communication control circuit section at least for carrying out communication of monitoring and control signals, a data memory, and a second series-parallel converter; and in which serial communication of monitoring and control signals is carried out mutually between the mentioned first and second control circuit sections via the mentioned first and second series-parallel converters.

In this electronic control unit, the mentioned first control circuit section includes regular transmission means and irregular transmission means, and the mentioned second control circuit section includes regular report means and an unprocessed data table.

Further, the mentioned first and second control circuit sections include first and second communication error determination means, first and second adding-subtracting means, and first and second error occurrence definition means respectively, and the mentioned first control circuit section includes retransmission means.

The mentioned regular transmission means acts as write setting means that regularly transmits a control output data or a constant set data from the mentioned first control circuit section to the mentioned second control circuit section, and executes retransmission processing from the first control circuit section to the second control circuit section in the case of presence of any communication error in confirmation reply of whether or not the second control circuit section has received the mentioned regular transmission data.

The mentioned regular report means acts as one-way input readout means which regularly reports a monitoring input data and status information from the mentioned second control circuit section to the mentioned first control circuit section, whereby no confirmation reply of whether or not the first control circuit section has received the mentioned regular report data is carried out.

The mentioned irregular transmission means acts as transmission means that is applicable when any error is present in a report communication provided by the mentioned regular report means, and is also applied when required as to a readout request for a monitoring input data of a specified address from the mentioned first control circuit section to the mentioned second control circuit section, and a readout request for reading out and checking a write save data having been written and set by the mentioned regular transmission means.

The mentioned irregular transmission means acts as readout request means that makes a readout request again from the first control circuit section to the second control circuit section in the case of presence of any communication error in a report reply of a monitoring input data of a specified address or a write save data, the mentioned report reply being carried out as a confirmation reply to the fact that the mentioned second control circuit section has received the mentioned irregular transmission data.

The mentioned first and second communication error determination means act as plural types of receiving error determination means that determine presence of absence of any error regarding various regular and irregular communication packets that a control circuit section on the side where the mentioned determination means is provided has received from the other control circuit section, or that discriminate a state that any communication packet to be received cannot be received.

The mentioned first and second adding-subtracting means act as operation means that adds or subtracts a second variation value when any of the mentioned plural types of receiving error determination means determines the presence of error, and subtracts or adds a first variation value when all the receiving error determination means determine the absence of any error to perform an addition-subtraction compensation with respect to a current value memory so as to offset each other, and stops an addition-subtraction compensation with the mentioned first variation value at a predetermined normal-side limit value when the determination of the absence of error continues.

The mentioned first and second error occurrence definition means act as comparison means that generates an error detection signal when a current value of the mentioned adding-subtracting means gets out of a scope of a predetermined abnormal-side limit value as a result of accumulation of the mentioned first and second variation values.

The mentioned retransmission means is means, which operates when any error is present in a transmission data provided from the mentioned first control circuit section to the mentioned second control circuit section, or when error is present in a confirmation reply data in response to the mentioned transmission data, and with which the first control circuit section transmits again a communication packet corresponding to the old transmission command, and adds or subtracts a second variation value with respect to mentioned first adding-subtracting means.

The mentioned second variation value is set to a value smaller than a permitted accumulation value, being a difference between the mentioned abnormal-side limit value and normal-side limit value, and stopping the operation, or initialization and restart of the mentioned first or second control circuit section is carried out responsive to the occurrence of the mentioned error detection signal.

In the electronic control unit of the invention of above arrangement, although the confirmation reply to a regular report provided by regular report means is not carried out, it is possible to reconfirm a regular report content with irregular transmission means at the time of detecting a communication error relative to a regular report data, and it is possible to make a readout request as needed with the irregular transmission means as to a write save data having been written and set by the regular transmission means to confirm a content thereof.

As a result, an advantage is exhibited in that it is possible to omit any report direction or confirmation reply to a regular report each time, and it is possible to reduce an amount of a downstream communication thereby diminishing a burden of communication control.

A further advantage is exhibited in that the regular transmission or the regular report can be carried out on a timely basis while preventing jam-up of an upstream communication from the second control circuit section to the first control circuit section with the unprocessed data table.

In the electronic control unit according to claim 2 of the invention, as defined in claim 1, the first control circuit section includes a reply-waiting data table and retransmission means. As a result, an advantage is exhibited in that it is easy to discriminate whether or not the confirmation reply is present, and it is possible to easily decide a command to be retransmitted and processed at the time of occurrence of any communication error.

In the electronic control unit according to claim 3 of the invention, as defined in claim 1 or 2, the second control circuit section includes readout request setting means. As a result, the second control circuit section not merely carries out the regular report, but a content of a selected data memory can be immediately read out as the need arises. In consequence, an advantage is exhibited in that it is possible to immediately report error information other than a communication error to the first control circuit section while reducing an amount of a regular report data.

In the electronic control unit according to claim 4 of the invention, as defined in claim 1, at least one of regular transmission means of regular report means includes division circulating means. As a result, data are sequentially divided and transmitted, or divided and reported in a cycle corresponding to a required emergency degree, thereby enabling to suppress a data amount to be transmitted or reported at a single communication to prevent jam-up of communication.

In the electronic control unit according to claim 5 of the invention, as defined in claim 1, the first control circuit section includes regular report permission means. As a result, when a large number of initialization set data and the like are transmitted from the first control circuit section to the second control circuit section at the time of start of operation, the regular report from the second control circuit section is inhibited thereby resulting in an advantage that jam-up of communication is prevented.

An electronic control unit according to claim 6 of the invention is constituted of first and second control circuit sections mutually carrying out a serial communication of monitoring and control signals via first and second series-parallel converters. In this electronic control unit, the first and second control circuit sections include first and second communication error determination means, first and second adding-subtracting means, and first and second error occurrence definition means respectively; and in which the first control circuit section includes retransmission means; and a variety of communication errors are collected and counted at the first or second adding-subtracting means, and a retransmission processing can be executed until a current value of the adding-subtracting means reaches an abnormal-side limit value.

As a result, an advantage is exhibited in that a too sensitive error determination is not carried out in the case of a sporadic and chronic error; and the error determination is made based on the fact that a current value of the first adding-subtracting means gets out of the scope of an abnormal-side limit value, and the initialization and restart are carried out in the case where a communication error still occurs even if the retransmission processing continues. Consequently, an advantage is exhibited in that it is possible to rationally regulate the permitted number of times of retransmission processing depending on a past history of whether or not the normal communication has continued.

In the electronic control unit according to claim 7 of the invention, as defined in claim 6, the first and second control circuit sections include first and second initialization means.

As a result, it is possible to initialize a control circuit section on the other side without depending on a communication line where any error occurs. Since a current value of the adding-subtracting means is made closer to an abnormal-side limit value at the time of restart, an advantage is exhibited in that safety shortly after the start can be improved.

In the electronic control unit according to claim 8 of the invention, as defined in claim 6 or 7, the mentioned first and second communication error determination means include at least one of bit information monitoring means and reply delay monitoring means or receiving interval monitoring means; and in which adding-subtracting means performs an addition-subtraction compensation with a first variation value when none of the bit information monitoring means, reply delay monitoring means, and receiving interval monitoring means makes any error determination.

As a result, an advantage exists in that a variety of determinations of a communication error enable improvement in detection accuracy and an early detection of the communication error; and that a highly accurate error determination can be carried out due to the fact that definition of any error occurrence is carried out with data collected at a pair of adding-subtracting means.

In the electronic control unit according to claim 9 of the invention, as defined in claim 8, a second variation value, which an adding-subtracting means adds or subtracts when the determination of bit information monitoring means is any communication error, is a value larger than a first variation value; and a variation value, which the adding-subtracting means adds or subtracts when the determination of reply delay monitoring means or receiving interval monitoring means is any communication error, is a third variation value, being a value different from a second variation value; and further, the mentioned third variation value is also a value smaller than a permitted accumulation value, being a difference between an abnormal-side limit value and normal-side limit value.

As a result, it is possible to make an error determination with weighting a variety of determinations of a communication error. Furthermore, it is unnecessary to set an excessive float as a determination threshold value for a timeout error such as reply delay or receiving interval excess, and it is possible to set a determination time period appropriate for a raw power. Consequently, an advantage is exhibited in that a highly accurate timeout determination can be carried out.

In the electronic control unit according to claim 10 of the invention, as defined in claim 8 or 9, the first control circuit section includes a reply-waiting data table; and in which the mentioned reply-waiting data table acts as reply error determination means for making an error determination when a save time period of a leading data remained in a transmission-side command memory, being mentioned reply-waiting data table exceeds a predetermined value, and a command data determined to be a reply error and a command data having a confirmation reply of a receiving failure are sequentially deleted from the mentioned transmission-side command memory, and stored anew in the transmission-side command memory at the time of being transmitted again.

As a result, an advantage is exhibited in that the determination of whether the reply delay or the receiving failure is present or absent is easily made, and that a command to be retransmitted and processed when the error determination is made can be easily decided.

In the electronic control unit according to claim 11 of the invention, as defined in any one of claims 6 through 10, the first control circuit section includes a first set data memory; and in which a part or all of various control constants are transferred and written from a non-volatile program memory cooperating with a microprocessor.

As a result, an advantage is exhibited in that it is possible to change a variety of control constants in accordance with an operation environment, and easily optimize the conditions for deciding the error occurrence.

In the electronic control unit according to claim 12 of the invention, as defined in any one of claims 6 through 11, the second control circuit section includes a second set data memory; and in which a part or all of various control constants are transmitted and written from a non-volatile program memory cooperating with a microprocessor via the first and second series-parallel converters.

As a result, an advantage is exhibited in that it is possible to change a variety of control constants in accordance with an operation environment, and easily optimize conditions for deciding the error occurrence. A further advantage is exhibited in that it is possible to set conditions for deciding the error occurrence in the first and second control circuit sections as different conditions, thereby enabling to carry out various error determinations.

In the electronic control unit according to claim 13 of the invention, as defined in any one of claims 6 through 12, the second control circuit section includes regular report means and current value report means.

As a result, an advantage is exhibited in that it is possible for the first control circuit section to monitor in a comprehensive manner a current value of the first and second adding-subtracting means. A further advantage is exhibited in that it is possible for the first control circuit section to immediately detect error with status information in the case of occurring any receiving interval error of the second control circuit section responsive to the regular transmission.

In the electronic control unit according to claim 14 of the invention, as defined in any one of claims 6 through 13, there are provided a direct input/output signal interface circuit, a watchdog timer, and error occurrence storage means. The error occurrence storage means acts as error storage circuit that stores first and second error detection signals or a reset pulse signal to bring annunciation means such as alarm, display, printing, and history save when the mentioned error detection signals are generated and when the reset pulse signal provided by the watchdog timer is generated; and the main CPU is initialized and restarted when the watchdog timer generates a reset pulse signal and when the second error detection signal is generated. A communication control circuit section of the second control circuit section is initialized and restarted when the watchdog timer generates a reset pulse signal and when the first error detection signal is generated.

As a result, an advantage is exhibited in that it is possible to restart the main CPU without depending on a communication line where the error occurs. Furthermore, while an error detection signal regarding communication is generated due to plural times of communication errors, the occurrence of any watchdog timer error immediately causes the error storage or restart to be carried out. In consequence, a further advantage is exhibited in that it is possible to change weighting with respect to the error processing, and announce the error.

Furthermore, even in the case where the error is a temporary noise malfunction of the main CPU, and the main CPU is immediately restarted in a normal way, the fact that the error occurs is well marked. In consequence, a further advantage is exhibited in that it is possible to induce a maintenance inspection.

In the electronic control unit according to claim 15 of the invention, as defined in claim 14, there are provided an auxiliary CPU, and run-away monitoring means with respect to this auxiliary CPU; and the auxiliary CPU is initialized and restarted, and an error storage circuit stores an error occurrence when the mentioned run-away monitoring means generates a reset pulse signal, when the watchdog timer generates a reset pulse signal, and when a first error detection signal is generated.

As a result, an advantage is exhibited in that it is possible to restart the auxiliary CPU without depending on a communication line where any error occurs. A further advantage is exhibited in that it is possible to change the weighting of the error processing in response to the occurrence of a communication error and the occurrence of a run-away error provided by the run-away monitoring means, and announce the errors.

Furthermore, even in the case where the error is a temporary noise malfunction of the auxiliary CPU, and the auxiliary CPU is immediately restarted in a normal way, the fact that the error occurs is well marked. In consequence, advantageously it is possible to induce a maintenance inspection.

In the electronic control unit according to claim 16 of the invention, as defined in claim 14 or 15, error occurrence storage means is constituted of a count storage circuit; and the mentioned count storage circuit counts an OR output with respect to first and second error detection signals and a reset pulse signal provided by the watchdog timer or the run-away monitoring means, and brings the mentioned annunciation means in operation when the mentioned count value reaches a predetermined value.

As a result, an advantage is exhibited in that it is possible to set a determination threshold value of the watchdog timer at a strict value matching a raw power cycle of a watchdog timer clear signal, and make an accurate run-away determination; and it is possible to prevent the error alarm from being carried out in vain.

Further, since there is provided the OR means, there is an advantage that communication errors attributed to the run-away error are not counted redundantly.

In the electronic control unit according to claim 17 of the invention, as defined in claim 14 or 15, at least one of the first and second control circuit sections includes driving stop means and clear means.

As a result, an advantage is exhibited in that even in the case where an error is a temporary noise malfunction and the electronic control unit is immediately restarted in a normal way, driving the specified electrical loads having a negative affect on safety is stopped thereby improving the safety. A further advantage is exhibited in that it is possible to cause the electronic control unit to return to the normal operation state by manual operation.

In the electronic control unit according to claim 18 of the invention, as defined in claim 16, at least one of the first and second control circuit sections includes driving stop means and clear means. As a result, even in the case where an error is a temporary noise malfunction and the electronic control unit is immediately restarted in a normal way, driving the specified electrical loads having a negative affect on safety is stopped thereby improving the safety. A further advantage is exhibited in that it is possibl