Gain control methods and systems in an amplifier assembly Number:7,183,845 from the United States Patent and Trademark Office (PTO) owispatent A Variable Gain Amplifier (VGA) amplifies an input signal according to a gain, to produce an amplified signal. A detector module detects a power indicative of a power of the amplified signal. A comparator module compares the detected power to a high threshold, a low threshold and a target threshold intermediate the high and low thresholds. A controller module changes the gain of the VGA so as to drive the detected power in a direction toward the middle threshold when the comparator module indicates the detected power is not between the high and low thresholds.<H amplifier, assembly, Gain, control, me, 7183845.html, Patent, pto, 7183845

Title: Gain control methods and systems in an amplifier assembly

Abstract: A Variable Gain Amplifier (VGA) amplifies an input signal according to a gain, to produce an amplified signal. A detector module detects a power indicative of a power of the amplified signal. A comparator module compares the detected power to a high threshold, a low threshold and a target threshold intermediate the high and low thresholds. A controller module changes the gain of the VGA so as to drive the detected power in a direction toward the middle threshold when the comparator module indicates the detected power is not between the high and low thresholds.

Patent Number: 7,183,845 Issued on 02/27/2007 to Dauphinee, et al.

Inventors: Dauphinee; Leonard (Irvine, CA), Burns; Lawrence M. (Laguna Hills, CA)
Assignee: Broadcom Corporation (Irvine, CA)

Appl. No.: 11/118,336

Filed: May 2, 2005

Related U.S. Patent Documents


Application Number	Filing Date	Patent Number	Issue Date
10822729	Apr., 2004
10353939	Jan., 2003	6798286
60430061	Dec., 2002

Current U.S. Class: 330/129 ; 330/279

Current International Class: H03G 3/20 (20060101)

Field of Search: 330/129,279,136,282 455/240.1

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Primary Examiner: Choe; Henry
Attorney, Agent or Firm: Sterne, Kessler, Goldstein & Fox P.L.L.C.

Parent Case Text

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 10/822,729 filed Apr. 13, 2004, entitled "Gain Control Methods and Systems in an Amplifier Assembly," now allowed, which is a continuation of U.S. patent application Ser. No. 10/353,939, filed Jan. 30, 2003 now U.S. Pat. No. 6,798,286, entitled "Gain Control Methods and Systems in an Amplifier Assembly," now issued, which claims priority to U.S. Provisional Application No. 60/430,061, filed Dec. 2, 2002, entitled "Amplifier Assembly with AGC for a Tuner," which are all incorporated herein by reference in their entirety;

This application is related to U.S. Non-Provisional application Ser. No. 10/353,940, filed Jan. 30, 2003, entitled "Amplifier Assembly Including Variable Gain Amplifier, Parallel Programmable Amplifiers, and AGC," which is incorporated herein by reference in its entirety.

Claims

What is claimed is:

1. A method of amplification, comprising: (a) amplifying an input signal using one or more activated gain stages of a plurality of parallel gain stages to produce a first output signal, a gain of the amplification being a sum of respective fixed gains of the one or more activated gain stages of the plurality of gain stages; (b) providing the first output signal to N individually programmable amplifier(s) to produce N second output signal(s), respectively, wherein N is a natural number; and (c) detecting a power of one or more of the N second output signals, and changing the gain of the amplification so as to drive the power between a high threshold and a low threshold when the power is not between the high and low thresholds.

2. The method of claim 1, wherein step (c) comprises changing the gain of the amplification until the power crosses a target threshold, wherein the target threshold is between the high and low thresholds.

3. The method of claim 1, further comprising not changing the gain of the amplification when the power is between the high and low thresholds.

4. The method of claim 1, further comprising repeating step (c) at predetermined time intervals.

5. The method of claim 1, wherein step (c) comprises changing the gain of the amplification according to a ramp function.

6. The method of claim 1, wherein step (c) comprises: decreasing the gain of the amplification when the power is above the high threshold; and increasing the gain of the amplification when the power is below the low threshold.

7. An amplification apparatus, comprising: a plurality of parallel gain stages to amplify an input signal and having a combined gain that is a sum of respective fixed gains of one or more activated gain stages of the plurality of gain stages, so as to produce a first amplified output signal; N individually programmable amplifier(s) to produce N second amplified output signal(s), respectively, from the first output signal, wherein N is a natural number; a detector module to detect a power of one or more of the N second amplified output signals; and a controller module to change the combined gain, so as to drive the power between a high threshold and a low threshold.

8. The apparatus of claim 7, further comprising: a comparator module to compare the power of the amplified signal to the high and low thresholds.

9. The apparatus of claim 8, wherein the controller module: decreases the combined gain when the comparator module indicates the power is above the high threshold; and increases the combined gain when the comparator module indicates the power is below the low threshold.

10. The apparatus of claim 8, wherein the controller module does not change the combined gain when the comparator module indicates the power is between the high and low thresholds.

11. The apparatus of claim 7, wherein at least some of the parallel gain stages are non-attenuated gain stages having substantially equal maximum gains.

12. The apparatus of claim 7, wherein at least some of the parallel gain stages are attenuated gain stages having progressively decreasing maximum gain.

13. The apparatus of claim 12, wherein the individual attenuated gain stages further comprise: an amplifier; and an attenuator, wherein the individual attenuated gain stages are cascaded in parallel such that the individual attenuated gain stages share attenuators.

14. The apparatus of claim 13, wherein the attenuators of the individual attenuated gain stages have a fixed attenuation.

15. The apparatus of claim 13, wherein the attenuators of the individual attenuated gain stages have a programmable attenuation.

16. The apparatus of claim 12, further comprising a resistor ladder, wherein the individual attenuated gain stages are coupled to successive taps of the resistor ladder.

17. The apparatus of claim 12, wherein each individual attenuated gain stage further comprises an amplifier, wherein the amplifiers of the individual attenuated gain stages have progressively decreasing size.

18. The apparatus of claim 7, wherein at least some of the parallel gain stages are fixed-attenuated gain stages having substantially equal constant attenuation.

19. The apparatus of claim 18, wherein each individual fixed-attenuated gain stages further comprises an amplifier, wherein the individual fixed-attenuated gain stages share a single attenuator.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to variable gain amplifier (VGA) assemblies and components thereof, gain control in such assemblies, and applications of the same.

2. Related Art

VGA assemblies are known in the art. What is needed is a more linear, lower noise, less costly amplifier assembly for providing variable amplifier gain in a variety of applications, such as those including multiple tuners for cable television and data signal applications.

SUMMARY OF THE INVENTION

Embodiments of the present invention are directed to an amplifier assembly and components/modules used therein, gain control in the amplifier assembly, and associated methods. An embodiment of the present invention is directed to an Automatic Gain Control (AGC) system of the amplifier assembly, comprising: a Variable Gain Amplifier (VGA) configured to amplify an input signal according to a gain, to produce an amplified signal; a detector configured to detect a power indicative of a power of the amplified signal; a comparator module configured to compare the detected power to a high threshold, a low threshold and a target threshold between the high and low thresholds; and a controller module configured to change the gain of the VGA so as to drive the detected power in a direction toward the middle threshold when the comparator module indicates the detected power is not between the high and low thresholds.

Other embodiments of the present invention are apparent from the ensuing description.

BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES

In the drawings, like reference numbers indicate identical or functionally similar elements.

FIG. 1 is a block diagram of an example VGA assembly for use in a tuner.

FIG. 2 is a block diagram of an example arrangement of the VGA assembly of FIG. 1.

FIG. 3 is a block diagram of an example arrangement of a VGA, including an array of parallel gain stages, for use in the VGA assembly of FIG. 2.

FIG. 4 is a block diagram of an example arrangement of an attenuated gain stage of the VGA of FIG. 3.

FIG. 4A is a block diagram of another example arrangement of a portion of an attenuated gain stage of the VGA of FIG. 2.

FIG. 4B is a block diagram of an arrangement of multiple attenuated gain stages, which is based on the gain stage arrangement of FIG. 4A.

FIG. 4C is a block diagram of another example arrangement of the VGA of FIG. 2, using the attenuated gain stage arrangements of FIGS. 4A and 4B, and including differential components.

FIG. 5 is a block diagram of still another example arrangement of the VGA of FIG. 2, including single-ended components.

FIG. 6 is a block diagram of another example arrangement of an attenuated gain stage.

FIG. 7 is a circuit diagram of an example differential amplifier used in a differential gain stage of the VGA of FIG. 2.

FIG. 8 is a gain response curve or transfer function for a gain stage of the VGA of FIG. 2.

FIG. 9 is an illustration of an exemplary smooth and continuous ramp-shaped gain change (increase) over time for a gain stage of the VGA of FIG. 2.

FIG. 10 is an illustration of an exemplary smooth and continuous ramp-shaped gain change (decrease) over time for a gain stage of the VGA of FIG. 2.

FIG. 10A is an illustrative example of how the aggregate gain of the VGA of FIG. 2 may be changed in steps in the present invention.

FIG. 10B is an example plot of an AGC power control signal versus time for the amplifier assembly of FIG. 2, corresponding to an example receive signal scenario.

FIG. 11 is a block diagram expanding on a controller module and a tri-level AGC window comparator of the amplifier assembly of FIG. 2, according to an embodiment of the present invention.

FIG. 12 is a block diagram of an example switch within a decoder and switch matrix of the amplifier assembly of FIG. 2.

FIG. 13 is a block diagram of an example arrangement of a power detector of the amplifier assembly of FIG. 2.

FIG. 14 is a circuit diagram of an example arrangement of the tri-level AGC window comparator of the amplifier assembly of FIG. 2.

FIG. 15 is a circuit diagram of an example arrangement of a ramp generator portion of a signal generator of the amplifier assembly of FIG. 2.

FIG. 16 is a circuit diagram of an example arrangement of a reference signal generator portion, and an associated ramp window comparator, of the signal generator of the amplifier assembly of FIG. 2.

FIG. 16A is a circuit/block diagram of an example process monitor of the amplifier assembly of FIG. 1.

FIG. 16B is a circuit diagram of an example sense circuit module of the processor monitor of FIG. 16B.

FIG. 17 is a flowchart of an example method of controlling gain that may be performed in the amplifier assembly of FIG. 2.

FIG. 18 is a flow chart expanding on an initial gain setting step of the method of FIG. 17, according to an embodiment of the present invention.

FIG. 19 is a flow chart expanding on a gain change step of the method of FIG. 17, according to an embodiment of the present invention.

FIG. 20 is a flow chart of a low-level example method expanding on the gain change step of the method of FIG. 17, which focuses on operations performed by elements of a controller module of the amplifier assembly of FIG. 2 during the gain change.

FIG. 21 is a flow chart of another example method of controlling VGA gain performed in the amplifier assembly of FIG. 2.

FIG. 22 is an example system in which the amplifier assembly of FIG. 1 may be used.

DETAILED DESCRIPTION OF THE INVENTION

Glossary

AGC--automatic gain control.

CATV--Community Antenna Television.

CI--Control Interface.

CMOS--Complementary Metal Oxide Semiconductor.

FET--Field Effect Transistor.

IC--Integrated Circuit.

VGA--Variable Gain Amplifier.

QAM: Quadrature Amplitude Modulated.

QPSK: Quadrature Phase Shift Keyed.

Television (TV) Standards: NTSC--National Television System Committee. PAL--Phase Alternating Line. SECAM--Sequential Color with Memory (French). I. Overview

In a Community Antenna Television (CATV) system (also referred to as cable TV), a plurality of signals are frequency division multiplexed onto one or more coaxial cables. The CATV system has a downstream band or aggregate signal (headend-to-user) and an upstream band or aggregate signal (user-to-headend). In the downstream band, there can be approximately 135 channels having frequencies that range from 50 MHz to 860 MHz. The individual downstream channels represent different television signals that can be a mixture of analog television signals or digital signals. The analog television signals are preferably NTSC or PAL compliant television signals. The digital television signals carry digital video or cable modem data (e.g. internet traffic), and are typically modulated using 64 QAM or 256 QAM. Other outputs include a buffered version of an input (bypass function) and out-of-band (OOB) control signals.

While the amplitude of each signal varies as a function of the information being transmitted on that channel, the amplitude of the combined signal on the cable will vary not only as a function of the amplitude of each of the individual signals, but also as a function of the phase and amplitude relationship of each channel with respect to the others. Thus, the overall amplitude of the signal will be time varying as the phase and amplitude of each of the individual signals line up. As an example, an amplifier used in a tuner that receives the downstream signal has to have good distortion performance when 135 channels, each at 0 Decibel-milliVolts (dBmV), are fed to the amplifier input. When the input level is increased to +15 dBmV on each channel, the amplifier must attenuate the input level back down to the same output level as in the case when all channels were at 0 dBmV, while maintaining good distortion performance.

FIG. 1 is a block diagram of an exemplary amplifier assembly 102 for use in a tuner for CATV, for example. Amplifier assembly 102 includes a VGA amplifier module 104, AGC control circuitry or module 106 for controlling a gain of the VGA amplifier module, a process monitor 108. Amplifier assembly 102 also includes a control interface (CI) 109 for controlling and monitoring amplifier module 104, AGC module 106, and process monitor 108, over a control bus 110. An external controller 112 controls and receives status information from amplifier assembly 102, over an external control bus 114 coupled to CI 109. External control bus 114 may be a digital control bus including serial data lines and a clock line, for example. CI 109 may be an analog or digital controller, and control bus 110 may be an analog or digital control bus.

Amplifier module 104 receives a signal 114 including downstream channels spanning 54 860 MHz, for example. Signal 114 may include TV channels formatted according to NTSC, PAL, or SECAM standards, for example. Signal 114 may also include channels carrying digital data. Amplifier module 104 amplifies receive signal 114 in accordance with a gain of the amplifier module and divides or power-splits the resulting amplified receive signal, to produce a plurality of individual, separate amplified receive signals 118(1) 118(n). Amplifier assembly 102 produces signals 118(1) 118(n) in parallel with one another. Each signal 118(i) represents an amplified version of receive signal 114. Each of amplified signals 118 is associated with its own gain, and thus, may have a different power level than the other of amplified signals 118. The interchangeable terms "gain" and "gain value" as used herein are general, and are intended to include positive, negative or zero gain. Thus, an amplifier having a gain may amplify a signal at a first power level, to produce an amplified signal at a second power level. The second power level may be greater than, less than, or equal to the first power level, depending on whether the gain is positive, negative, or zero, respectively.

In response to a power level of one of amplified signals 118 (e.g., signal 118(2)), AGC module 106 generates one or more gain control signals 120 that collectively control the gain of amplifier module 104, and thus the power levels of output signals 118. As a power level of receive signal 114 varies, AGC module 106 adjusts the gain of amplifier module 104 so as to maintain the individual power levels of amplified signals 118 at substantially constant respective power levels.

FIG. 2 is a block diagram of an example arrangement of amplifier assembly 102, expanding on FIG. 1. Amplifier assembly 102 includes various circuit elements constructed on an integrated circuit (IC) substrate or chip 202, depicted in dashed-line. Such on-chip circuit elements are depicted within the dashed-line 202. Amplifier assembly 102 also includes various circuit elements external to IC substrate 202, depicted outside of the dashed-line 202.

Amplifier module 104 includes a first stage amplifier 204 followed by a plurality of, for example, five, parallel second stage amplifiers 206 for generating corresponding, separate parallel amplified signals 118. In an exemplary arrangement, first stage amplifier 204 is a VGA including an array of variable gain stages arranged in parallel with each other, each having an individual gain controlled responsive to a corresponding one of gain control signals 120.

In the arrangement of FIG. 2, VGA 204 is a differential amplifier, including differential inputs and differential outputs. A pair of differential signal lines 208 carry receive signal 114 to the differential inputs of VGA 204. Amplifier assembly 102 includes a resistor 204a coupled between input lines 208, external to IC chip 202. Together, resistor 204a and input attenuation of VGA 204 (not shown in FIG. 2, but discussed below), set an input impedance of amplifier assembly 102. VGA 204 includes one or more gain control inputs 205 for receiving corresponding gain control signals 120. In an arrangement, gain control signals 120 include bias or control currents. In an alternative arrangement, gain control signals include bias or control voltages.

VGA 204 amplifies receive signal 114 according to a gain of the VGA set by gain control signals 120, and produces an intermediate amplified receive signal 210. A pair of differential signal lines 212, coupled between the differential output of VGA 204 and respective differential inputs of each of second stage amplifiers 206, carry amplified signal 210 to the second stage amplifiers. Thus, each of parallel amplifiers 206 is fed with signal energy from a common input, e.g., the output of VGA 204/lines 212. Also, a termination circuit or output load 207 (described below in connection with FIG. 7) couples output lines 212 to a power supply rail of amplifier assembly 102.

Each of second stage amplifiers 206 has a gain that is programmable through CI 109. Thus, each of second stage amplifiers 206 is also a VGA. Programmable gain registers 214, coupled to CI 109 and respective gain control inputs of second stage amplifiers 206, hold respective gain values that program the gains of the corresponding amplifiers 206. Each amplifier 206(i) further amplifies amplified receive signal 210 in accordance with its respective gain set by the programmable gain in corresponding gain register 214(i), to produce respective amplified signal 118(i). As depicted in FIG. 2, each amplifier 118(i) is a differential amplifier, and each amplified signal 118(i) is a differential signal. Termination circuits or output loads 207'(1) 207'(n) (where each of the loads 207' is similar to load 207) couple respective outputs of amplifiers 206(1) 206(n) to a power supply rail of amplifier assembly 102. The output of each second stage amplifiers 206(i) is configured for driving its own load, for example, an individual tuner coupled to the output. Thus, amplifier assembly 102 is configured to drive multiple loads (such as tuners) in parallel.

In an arrangement, a first sub-plurality of second stage amplifiers 206 (for example, outside amplifiers 206(1) and 206(n)) have a common gain, that is, a programmed first gain, and a second sub-plurality of second stage amplifiers 206 (for example, inner amplifiers 206(2) through 206(n-1)) have a common second gain, that is, a programmed second gain. In this arrangement, the second gain is less than the first gain. For example, a ratio of the programmed first gain to the program second gain may be in a range of ratios of between 1:1 to 2:1.

Amplifier assembly 102 also includes AGC control circuitry or module 106 coupled between the output of second stage amplifier 206(2) and gain control inputs 205 of VGA 204. In an alternative arrangement, ACG module 106 is coupled between the output of VGA 204 (e.g., to lines 212) and gain control inputs 205. AGC control circuitry 106 includes, in series, a power detector 216, a comparator module 218, and an AGC controller module 220.

Power detector 216 detects a power level of output signal 206(2), and provides a detected power indicator 230, that is, a power level signal 230, to comparator module 218. Power detector 216 detects the combined power of all of the frequency channels in output signal 206(2) (which are the frequency channels in input signal 114). Therefore, power level signal 230 is representative of this combined power. Comparator module 218 includes a tri-level AGC window comparator 222, an upper threshold register 224, a lower threshold register 226, and a middle or target threshold register 228. Threshold registers 224, 226 and 228 provide respective upper (high), lower (low) and target power thresholds 224a, 226a and 228a to respective comparison inputs of comparator 222. Thresholds 224a 228a may be programmed through CI 109. Target threshold 228a may be half-way between thresholds 224a and 226a, closer to threshold 226a, or closer to threshold 224a, as desired.

Comparator 222 receives power level signal 230 at a comparison input of the comparator. Comparator 222 compares power level signal 230 to thresholds 224a, 226a and 228a, to produce a comparison result signal 232. Comparison result signal 232 indicates where the detected power of signal 118(2) (that is, power level signal 230) is in relation to thresholds 224a 228a. Together, upper threshold 224a and lower threshold 226a define an AGC window.

Controller module 220 includes a controller 233 that receives comparison result signal 232 and a clock 234 generated by a clock generator 236. Controller 233 generates a set of control signals 238 responsive to comparison result 232, and provides the control signals to a decoder and switch matrix 240 (also referred to as switch matrix 240). A signal generator 242, including an off-chip capacitor 244, generates a set of ramp and reference signals 246, and provides the ramp and reference signals to decoder and switch matrix 240. Decoder and switch matrix 240 generates gain control signals 120 in response to signals 246 and control signals 238.

CI 109 can assert control over, and collect status information from, controller module 220, through control interface registers 249. For example, CI 109 can command clock generator 236 to either start or stop generating clock 234. CI 109 can access status information in controller 233 indicative of a present gain setting of VGA 204. CI 109 can command controller 233 to set the gain of VGA 204 to any desired gain value. In normal AGC operation, controller module 220 adjusts the gain of VGA 204 responsive to comparison result 232. However, CI 109 can command controller 233 to hold the gain of VGA 204 fixed at a desired gain value, that is, controller 233 can be commanded to be non-responsive to comparison result signal 232. Essentially, this disables AGC operation in amplifier assembly 102. Since the gains of VGA 204 and second-stage parallel amplifiers 206 may be controlled through CI 109, an alternative arrangement of the amplifier assembly omits AGC module 106. In such an arrangement, the gain of the VGA module is controlled exclusively by CI 109.

In yet another mode of gain control operation, the output of power detector 216 can be turned off, and an external control voltage 250 can be substituted for the output of power detector 216. In other words, external control voltage 250 replaces signal 230.

In an arrangement, clock generator 236 is a relaxation oscillator based on alternately charging an on-chip capacitor (not shown in FIG. 2) with a reference current Iref and discharging the capacitor with a current 2Iref. This action produces a 50% duty-cycle triangle wave on a terminal of the capacitor. The control signals for the charge/discharge action are actually the clock output square wave.

The frequency of clock 234 can be tuned by changing the charge/discharge current to the capacitor. An example frequency tuning range is approximately 1.25 kHz to 80 kHz. An additional frequency tuning factor of 2.times. can be obtained by either reducing the on-chip capacitor in half, or making the capacitor 2.times. larger.

Oscillator 236 also includes a synchronous reset capability which does not produce glitches (i.e., undesired narrow pulse width outputs) on clock 234 when a RESET signal from CI 109 is asserted (e.g., set to a logic "1"). Likewise, when the RESET signal is set to logic "0, " no glitch occurs. This is performed by logic circuitry within oscillator 236. This no-glitch action insures that the last-held-state of controller 233, when controller 233 is implemented as a stage machine, is maintained at reset and seamlessly restarted when reset is finished. The purpose of this feature is to allow for clock-free operation of the state machine (e.g., controller 233), except when checking for gain corrections via an external controller (e.g., controller 112). This was done in case relaxation oscillator 236 produces spurious signals on its output 234.

Amplifier assembly 102 also includes process monitor 108. In response to commands issued over CI bus 110, process monitor 108 selectively couples various ones of its process monitor outputs to the CI bus 110.

Amplifier assembly 102 also includes a bandgap voltage reference circuit 260. The bandgap voltage reference circuit 260 produces multiple voltages, including a first fixed voltage that does not vary with temperature, power supply voltage VDD or process variations. An example fixed voltage is approximately 1.2 Volts (V). Circuit 260 also produces a second voltage that increases proportional to absolute temperature (PTAT), but does not change with VDD or process variations.

Circuit 260 may produce bias currents based on the fixed and PTAT voltages. For example, the fixed voltage is applied across various resistors (both on- and off-chip 202) to create correspondingly fixed bias currents used by various sub-circuits within the IC chip. In general, the bias currents on the order of 200 .mu.A are sent to each sub-circuit. Each sub-circuit then mirrors the currents, sometimes at fixed ratios (either up or down) to get the current(s) needed in each sub-circuit.

Likewise, the PTAT voltage is applied across various resistors (both on- and off-chip 202) to create PTAT bias currents used by various sub-circuits within the chip. The PTAT currents would increase at temperature increases.

A substantial portion of the circuits of amplifier assembly 102 are constructed on IC chip 202. However, input load resistor 204a, capacitor 244, and output load circuit 207 are external to IC chip 202. A general advantage of using such external or off-chip components is that relatively cheaper off-chip components have relatively more accurate parameter values (e.g., resistance, capacitance, inductance, and so on) as compared to corresponding internal or on-chip components. For example, low-cost off-chip components typically have 5% tolerances for resistors and 10% tolerances for capacitors and inductors. Even tighter tolerances can be achieved for slightly more expensive off-chip components.

In alternative arrangements of the present invention, input resistor 204a is on-chip. In yet another arrangement, output load circuit 207 is on-chip. Similarly, capacitor 244 may be provided on-chip. The parameter accuracy of the on-chip components in such arrangements may be achieved in a variety of ways. For example, switched resistor banks with calibration routines may be used to select a best-valued on-chip resistor among multiple resistors, and so on. In the case of an on-chip version of external capacitor 244, which is a large capacitance capacitor, capacitor multipliers may be used.

In another alternative arrangement of amplifier assembly 102, parallel second-stage amplifiers 206 are omitted whereby the output of VGA 204 drives subsequent processing stages.

II. VGA

FIG. 3 is a block diagram of an example arrangement 300 of VGA 204. In the example arrangement depicted in FIG. 3, VGA 204 includes a plurality of individual gain stages 302 arranged in parallel with each other. Each gain stage 302(i) receives a corresponding gain control signal 120(i). Each gain stage 302(i) includes a variable gain amplifier 304(i) having a gain controlled responsive to the corresponding gain control signal 120(i). In the example arrangement of FIG. 3, VGA 204 includes an array of seventy (70) variable gain stages 302, however, any number of gain stages from 1-to-n may be used. If only one gain stage is used, then AGC module 106 generates only one corresponding gain control signal 120(i).

VGA 204 includes an input node 310 coupled to differential signal lines 208. Gain stages 302 have their respective inputs 312 coupled to input node 310. Similarly, their respective outputs 314 are coupled to an output summing node 316 that combines together the respective gain stage outputs. Summing node 316 may be a wire-OR, for example, or any other circuit that combines together the gain stage outputs. Summing node 316 may include multiple sub-combining nodes for combining subsets of the outputs of gain stages 302. In an arrangement, input node 310, each of the inputs 312 and outputs 314, each gain stage 302(i), and summing node 316 are differential. However, these elements are depicted as being single-ended in FIG. 3. In VGA 204, gain stages 302 are considered to be arranged in parallel for at least the reason that their respective inputs are coupled to common input node 310, and thus, all of the gain stages are fed, with signal energy, from the common input node. Furthermore, the respective outputs of the gain stages are combined together at summing node 316.

In operation, each gain stage 302(i) amplifies receive signal 114 in accordance with its individual gain (g(i)) set by corresponding gain control signal 120(i) to produce a corresponding amplified receive signal presented at its output 314(i). Summing node 316 combines together all of these individual amplified signals to produce composite or aggregate amplified signal 210. Together, the array of parallel gain stages 302 establishes an aggregate gain of VGA 204 that is equal to a sum of all of the individual gains of gain stages 302. The aggregate gain is controlled in accordance with gain control signals 120.

In the arrangement depicted in FIG. 3, VGA 204 includes a first subset 316 of non-attenuated gain stages, including gain stages 302(1) 302(20). First subset gain stages 316 have substantially equal respective maximum gains. Amplifier array 204 also includes a second subset 320 of attenuated gain stages, including gain stages 302(21) 302(70). In an example arrangement, second subset gain stages 320 have progressively decreasing maximum gains in the direction 302(21) 302(70). In another example arrangement, VGA 204 includes a third subset of constant-attenuated gain stages (not sown in FIG. 3) added to the bottom of the structure depicted in FIG. 3. All of the third subset of gain stages have fixed, constant attenuation.

FIG. 4 is a block diagram of an example arrangement of an attenuated gain stage in the second subset or group of attenuated gains stages 320. Attenuated gain stage 302(i) includes an attenuator 402(i) followed by amplifier 304(i). Attenuator 402(i) may provide fixed or, alternatively, programmable attenuation.

FIG. 4A is a block diagram of another example arrangement of an attenuated gain stage. In the arrangement of FIG. 4A, a tap-point or junction 404(i) between attenuator 402'(i) and amplifier 304(i) of attenuated gain stage 302(i) is coupled to a next attenuated gain stage 302(i+1), and so on. The attenuator reference numeral 402' includes the prime suffix (') to indicate that the attenuator is shared between gain stages. The use of the attenuated gain stage of FIG. 4A in VGA 204 leads to a another parallel arrangement of attenuated gain stages, as depicted in FIG. 4B.

FIG. 4B is a block diagram of such a parallel arrangement 410 of attenuated gain stages. In arrangement 410, the attenuated gain stages are cascaded in parallel with each other such that the attenuated gain stages share attenuators. Arrangement 410 includes an attenuation ladder 412 coupled between input node 310 (not shown in FIG. 4B) and the inputs of the amplifiers of the attenuated gain stages. Attenuation ladder 412 includes a string of series connected attenuators 402'. Successive amplifiers 304(i), 304(i+1), and so on, have their respective inputs fed from corresponding successive taps 404(i), 404(i+1), and so on, of attenuation ladder 412. That is, each attenuator 402'(i) feeds both the input to amplifier 304(i) and also the input to attenuator 402'(i+1) of next gain stage 302(i+1), and so on. Thus, the successive taps are associated with increasing attenuation. In this arrangement, attenuated gain stage 302(i+1) includes attenuator 402'(i), attenuator 402'(i+1), and amplifier 304(i+1) connected in series with one another. Similarly, attenuated gain stage 302(i+2) includes attenuator 402'(i), attenuator 402'(i+1), attenuator 402'(i+2), and amplifier 304(i+2) connected in series with each other, and so on.

FIG. 4C is a block diagram of a differential arrangement 420 of VGA 204, using the attenuation ladder configuration described above in connection with FIG. 4B. In arrangement 420, input node 310, amplifiers 304, attenuators 402', and output combining node 316 are all differential. Attenuation ladder 412 includes cascaded attenuators 402'. Each attenuator 402'(i) includes resistors 422(i), 424(i) and 426(i) connected together as depicted in FIG. 4C. Together, external input resistor 204a and internal attenuators, 402' (for example, attenuation ladder 412) set or control the input impedance of amplifier assembly 102, that is, the impedance seen looking into the amplifier assembly along input lines 208.

FIG. 5 is a block diagram of a single-ended (that is, non-differential) arrangement 500 of VGA 204. The amplifier arrangement of FIG. 5 includes a resistor ladder 502, including resistors 504, coupled between input node 310, specifically between node 506 and ground. Amplifiers 304(21) 304(70) in the attenuated gain stages have their respective inputs tied to corresponding successive taps of resistor ladder 502. In an alternative arrangement, the individual taps of resistor ladder 502 are coupled to outputs of amplifiers 320, instead of to the inputs of the amplifiers.

FIG. 6 is a block diagram of another example arrangement of attenuated gain stage 302(i). As depicted in FIG. 6, attenuated gain stage 302(i) includes amplifier 304(i) followed by attenuator 402(i).

In still another arrangement of VGA 204, attenuators are omitted, so that the parallel attenuated gain stages are simply amplifiers (e.g., FETs) sized smaller than the amplifiers of the parallel non-attenuated gain stages. Since the gain of an amplifier is proportional to its size, the smaller amplifiers provide less gain. The attenuated gain stage amplifiers have progressively decreasing sizes, and therefore, progressively decreasing maximum gains.

In each of the arrangements of VGA 204 depicted in FIGS. 3, 4B, 4C and 5, all of the gain stages are considered to be arranged in parallel with each other for at least the reason that they are fed from a common input node. Also, their individual outputs are combined together to produce an aggregate output, e.g., amplified signal 210.

In still another arrangement of the VGA, the attenuated gain stages may be omitted. In such an arrangement, all of the parallel gain stages have substantially the same maximum gain.

FIG. 7 is a circuit diagram of an example differential gain stage amplifier 304(i) used in the present invention, for example, in amplifier array 204. As depicted in FIG. 7, a pair of differentially configured amplifier transistors 708a and 708b have their respective gate terminals connected to complimentary differential nodes of input 312(i). The drains of transistors 708a and 708b are coupled to respective complimentary sides of output 314(i). Termination circuit 207 (also referred to as an output load circuit, and mentioned above in connection with FIG. 2) couples the drains of transistors 708a and 708b (and sources of corresponding differential transistors in all of the other amplifiers 304) to a power supply rail P.sub.S, at power supply voltage VDD, for example. Specifically, in termination circuit 207, the drain of transistor 708a is connected to power supply rail P.sub.S through series connected resistor 709a and inductor 710a, and a ferrite bead 711a connected in parallel with the series resistor and inductor. Ferrite bead 711a has the effect of a large value inductor in parallel with a large resistor. Also, the drain of transistor 708b is similarly coupled to rail P.sub.S through resistor 709b, inductor 710b, and ferrite bead 711b.

The respective source-drain paths of transistors 708a and 708b are connected together and to a current mirror 712, at a common terminal 713. Current mirror 712 includes a diode configured transistor 714 coupled to a gain control input terminal 715 (part of gain inputs 205) of amplifier 304(i), and also to a gate of a transistor 716, which has its source-drain path connected between terminal 713 and ground. Thus, transistor 716 operates as the tail current transistor, and thus as a current source, for differential transistors 708. In operation, gain control signal 120(i), applied to current mirror 712, controls a current 720 flowing through the source-drain path of tail transistor 716. The differential gain (g(i)) of amplifier 304(i) is controlled responsive to a magnitude of current 720. Thus, gain control signal 120(i) controls the gain (g(i)) of amplifier 304(i) and corresponding gain stage 302(i). In a typical arrangement, transistor 714 is a fraction, for example, one-eighth, the size of transistor 716. Thus, tail current 720 is a multiple, for example, eight times as large as, of control current 120(i).

Referring again to FIG. 2, each second stage amplifier 206(i) may include a differential amplifier that is similar to the amplifier depicted in FIG. 7. As mentioned above, each second stage amplifier 206(i) has its differential output coupled to respective termination circuit 207'(i). Also, each termination circuit 207'(i) is substantially the same as termination circuit 207 depicted in FIG. 7. However, the component values used in each circuit 207'(i) may differ from the component values used in the other circuits 207', and from the component values used in circuit 207.

FIG. 8 is a gain response curve for gain stage 302(i) and gain stage 304(i). That is, FIG. 8 is a plot of gain stage gain (g(i)) versus the amplitude of corresponding gain control signal 120(i). In the present invention, gain control signal 120(i) is a current signal I(i). A given gain control signal 120(i) can set the gain of corresponding gain stage 302(i) to a minimum gain (e.g., zero gain), a maximum respective gain for that gain stage, or may cause the gain to change between its minimum value (e.g., zero) and the maximum value.

In the present invention, a gain change between the minimum and maximum gain levels for a given gain stage 302(i) is achieved according to (that is, follows) a ramp function. That is, the gain changes (e.g., increases or decreases) gradually over a time interval. In accordance with the ramp function, the gain changes smoothly and continuously to avoid abrupt, discontinuous gain changes.

III. VGA Gain Change Operation--Overview

FIG. 9 is an illustration of such a smooth and continuous ramp-shaped gain change for a given gain stage 302(i). Specifically, FIG. 9 is an example combined plot for (i) gain versus time, and correspondingly, (ii) gain control current I(i) versus time, for gain stage 302(i). In the plot of FIG. 9, gain stage 302(i) undergoes a gain change (i.e., increase) from zero gain at time t.sub.1 to its respective maximum gain at time t.sub.2 in response to gain control current I(i). The gain change is continuous, that is, does not have discrete gain level. steps or jumps. Also, the gain change is smooth. For example, the slope of the gain change is continuous, and thus, does not exhibit discontinuities. The gain may increase monotonically over time, such as linearly or exponentially. However, the gain change may also include non-monotonic portions, as long as they are smooth and continuous.

FIG. 10 is combined plot similar to FIG. 9, but for a decrease in gain. That is, FIG. 10 is an illustration of an exemplary smooth and continuous ramp-shaped gain change (decrease) over time for a gain stage 302(i) of the VGA of FIG. 3.

FIG. 10A is an illustrative example of how the aggregate gain of first stage amplifier 204, e.g., amplifier array 204, may be changed in the present invention. In this illustrative example, the aggregate gain of amplifier array 204 is decreased from a maximum aggregate gain to an intermediate aggregate gain. In FIG. 10A, each gain stage 302(i) is depicted as a triangle. Dark-shaded triangles depict gain stages that are fully ON, that is, operated at their respective maximum gains. In contrast, triangles that are not shaded (that is, un-shaded triangles) depict gain stages that are fully OFF, that is, gain stages set to zero gain. Triangles filled with cross-hatches indicate gain stages that are in the process of having their respective gains changed, for example, either increased or decreased. Also, the process of changing aggregate gain depicted in FIG. 10A proceeds from a first step "Step 1" depicted at the top of FIG. 10A, to a final step "Step 5" depicted at the bottom of the FIG. 10A.

Initially, in Step 1, the aggregate gain of amplifier array 204 is at a maximum aggregate gain level. In this state, all of non-attenuated gain stages 316 (i.e., gain stages 302(1) 302(20)) are set to or operating at their respective maximum gains. Concurrently, all of the attenuated gain stages 320 (i.e., gain stages 302(21) 302(70)) are set to or operated at zero gain. Thus, in Step 1, gain stages 302(1) through 302(20) represent first gain stages among the set of gain stages 302 that are set to their respective maximum gains. Similarly, gain stages 302(21) through 302(70) represent second gain stages of the gain stages 302 that are set to zero gain. Note here that the terms "first gain stages" and "second gain stages" refer to gain stages of VGA 204 only, and are not to be confused with "first stage amplifier 204" and "second stage amplifiers 206" discussed above in connection with FIG. 2, for example.

In Step 2, the gain of one of the first gain stages is decreased to zero gain according to a ramp function and the gain of one of the second gain stages is increased to its respective maximum gain according to the ramp function. More specifically, the gain of gain stage 302(1) is decreased to zero gain according to the ramp function and the gain of gain stage 302(21) is increased to its respective maximum gain according to the ramp function. The gain increase operation and the gain decrease operation may be performed concurrently, or alternatively, sequentially, that is one after the other.

After the gain changes of Step 2, the amplifier array 204 is configured as depicted in Step 3 of FIG. 10A. Namely, gain stages 302(2) through 302(21) are set to the respective maximum gains (and thus, represent a new set of first gain stages that are fully ON), while gain stages 302(1) and 302(22) 302(70) are set to zero gain (and thus, represent a new set of second gain stages that are fully OFF).

In step 4, a further decrease in aggregate gain is achieved by decreasing the gain of gain stage 302(2) to zero and increasing the gain of gain stage 302(22) to its respective maximum. These gain changes may be performed concurrently or sequentially.

After the gain change of Step 4, amplifier array 204 is configured as depicted in Step 5. The aggregate gain of amplifier array 204 in Step 5 is less than the aggregate gain of amplifier array 204 in Step 1. This is because the sum of the maximum gains of the gain stages turned ON in Step 5 (i.e., gain stages 302(3) 302(22)) is less than the sum of the maximum gains of the gain stages turned ON in Step 1 (i.e., gain stages 302(1) 302(20)). State otherwise, the sum of the maximum gains of gain stages 302(20) 302(21) is less than the sum of the maximum gains of gain stages 302(1) 302(2).

During the gain change process depicted in FIG. 10A, a contiguous set of gain stages (e.g., twenty gain stages) are maintained in their fully ON states. This contiguous set of ON gain stages is dynamic, and "slides" to the right across the full set of gain stages 302 depicted in FIG. 10A. If the aggregate gain is further decreased to a point where the lower twenty attenuated gain stages, e.g., gain stages 302(51) 302(70)), are ON, then any further decrease in gain is achieved by sequentially turning OFF gain stage 302(51), then gain stage 302(52), and so on until none of the gain stages remain ON.

The process for increasing aggregate gain is essentially opposite from the process for decreasing aggregate gain. That is, higher numbered gain stages are sequentially turned fully ON, while lower numbered gain stages are sequentially turned fully OFF. In this case, the contiguous set of ON gain stages would slide to the left in FIG. 10A as the aggregate gain is increased.

FIG. 10B is an example plot of power control signal 230 versus time corresponding to an example receive signal scenario. The example plot of FIG. 10B serves as a useful illustration of the operation of VGA 204 and AGC module 106 with respect to power level signal 230 and thresholds 224a 228a. An initial assumption is that at a time to, the power of receive signal 114, the aggregate gain of VGA 204, and the resulting power of amplified receive signal 118(2) are such that power level signal 230 is between upper threshold 224a and lower threshold 226a, as depicted in FIG. 10B. It is also assumed that at periodic time intervals t.sub.sample, controller module 220 (more specifically, controller 233) polls or "samples" comparison result signal 232.

Beginning at a time t.sub.0, a slow increase in the power of receive signal 114 causes a correspondingly slow increase in amplified signals 210 and 118(2), and power detector level signal 230. AGC module 106 maintains the gain of amplifier 204 at a fixed level as power signal 230 rises. Eventually, power signal 230 rises to a level that is greater than upper threshold 224a, as indicated at 1050 in FIG. 10B. At a next sample time 1052, controller module 220 polls comparison result signal 232, which indicates the over-threshold condition at 1050. In response to this over-threshold condition, controller module 220 generates gain control signals 120 to decrease the gain of VGA 204 continuously and smoothly, and correspondingly, power level signal 230, until the power level signal passes below target threshold 228a.

At a sample time 1054, controller module 220 becomes informed that power level signal 230 has crossed, e.g., dropped below, target threshold 228a. In response to this condition, controller module 220 generates gain control signals 120 such that the gain of amplifier 204 remains fixed. That is, controller module 220 stops changing the gain amplifier 204 because power signal 230 is at or near the target threshold 228a. Controller module 220 will cause the gain of amplifier 204 to remain at this fixed level until power level signal 230 again becomes either too high (i.e., above upper threshold 224a) or too low (i.e., below lower threshold 226a). Controller module 220 causes the gain of VGA 204 to decrease in a smooth and continuous manner between points 1050 and 1054. This results in the smooth and continuous downward slope of power level signal 230 depicted in FIG. 10B. In an example arrangement, controller module 220 causes the gain of VGA 204 to decrease according to the process discussed above in connection with FIG. 10A, that is, by sequentially turning OFF and ON gain stages in the amplifier array 204. The smooth and continuous gain change arrangement produces a correspondingly smooth and continuous change in the power levels of signals 210 and 118.

The smooth and continuous change of power level signal 230 depicted in FIG. 10B includes small stair-steps or "wiggles" having sloped falling edges. This results from smooth and continuous gain changes having corresponding stair-steps. These stair-steps result from pauses between incremental gain changes. For example, with reference again to FIG. 10A, gain is changed in the following manner. In Step 2, the gain of VGA 204 is decreased an incremental amount, smoothly and continuously according to a ramp function. Then, in step 3, the gain of VGA 204 remains constant for a short period of time, that is, the gain remains level. Then, in Step 4, the gain of VGA 204 is decreased again an incremental amount, smoothly and continuously according to a ramp function. Steps 2, 3 and 4 repeat until power level signal 230 crosses target threshold 228a. The pause between successive incremental gain changes is discussed below in connection with FIG. 20.

IV. Controller Module, Detector Module, and Comparator

FIG. 11 is a block diagram expanding on controller module 220 and portions of comparator module 218, discussed above in connection with FIG. 2. Depicted in FIG. 11 are various low-level control signals not specifically depicted in FIG. 2. As mentioned above, controller module 220 generates gain control signals 120 responsive to comparison result signal 232. Controller 233 of controller module 220 provides a comparator control signal 1102 to comparator 222. At periodic time intervals, controller 233 asserts comparator control signal 1102, thus causing comparator 222 to produce comparison result signal 232 at these time intervals. Thereafter, controller 233 polls comparison result signal 232 to determine whether the gain of VGA 204 should be either changed or maintained at a current or present level, as mentioned above in connection with FIG. 10B. In the present invention, the periodic time intervals (e.g., the time between successive polling operations) are programmable in duration, and should correspond to the rate at which the power level of input signal 114 is expected to vary. Exemplary time intervals may be between 1 millisecond and 1 minute, or even longer. More typical time intervals are in the range of 1 10 milliseconds. In an arrangement, controller 233 is a state-machine based controller clocked by clock 234. However, controller 233 may be any digital or analog controller.