Title: High linearity passive mixer and associated LO buffer
Abstract: An RF communications system includes a transmit node for transmitting an RF information signal and a receive node for receiving the transmitted RF information signal. The receive node includes a passive mixer coupled to an amplifier for producing an IF or baseband differential mixer output signal as a function of a LO drive signal. The passive mixer having a first plurality of transistors of a first polarity type arranged in a ring configuration and a second plurality of transistors of a second polarity type, wherein each of second plurality of transistors is coupled to one of the first plurality of transistors.
Patent Number: 6,989,705 Issued on 01/24/2006 to Behzad
| Inventors:
|
Behzad; Arya Reza (Poway, CA)
|
| Assignee:
|
Broadcom Corporation (Irvine, CA)
|
| Appl. No.:
|
973705 |
| Filed:
|
October 26, 2004 |
| Current U.S. Class: |
327/359; 327/355; 455/326; 455/333 |
| Current Intern'l Class: |
G06F 7/44 (20060101); G06G 7/10 (20060101) |
| Field of Search: |
327/355-361,362,560-563
455/326,333
|
References Cited [Referenced By]
U.S. Patent Documents
| 4947062 | Aug., 1990 | Weiner et al.
| |
| 5361409 | Nov., 1994 | Vice.
| |
| 5513390 | Apr., 1996 | Vice.
| |
| 6057714 | May., 2000 | Andrys et al.
| |
| 6133793 | Oct., 2000 | Lau et al.
| |
| 6194947 | Feb., 2001 | Lee et al.
| |
| 6380777 | Apr., 2002 | Degardin et al.
| |
| 6608527 | Aug., 2003 | Moloudi et al.
| |
| 6781445 | Aug., 2004 | Feldman.
| |
| 2004/0174202 | Sep., 2004 | Behzad.
| |
| 2004/0259519 | Dec., 2004 | Su.
| |
| 2005/0073352 | Apr., 2005 | Behzad.
| |
| Foreign Patent Documents |
| 0 726 646 | Aug., 1996 | EP.
| |
Other References
Flaviis et al., X-Band Doubly Balanced Resistive FET Mixer with Very Low Intermodulation,
Short Papers, IEEE Transactions on Microwave Theory and Techniques, Feb. 1995,
pp. 457-460, vol. 43, No. 2.
Cho Y et al., "A New CMOS Passive Mixer with High Linearity," Extended Abstracts
of the International Conference on Solid State Devices and Materials, Japan Society
of Applied Physics, Tokyo, JA, vol. 2001, Sep. 26, 2001, pp. 400-401, XP 001074832.
Muraguchi M et al., "A 1.9 GHz-band Ultra Low Power Consumption Amplifier Chip
Set for Personal Communications," Microwave and Millimeter-Wave Monolithic Curcuits
Symposium, 1995. Digest of Papers., IEEE 1995 Orlando, FL May 15-16, 1995, New
York, NY May 15, 1995, pp. 145-158, XP 010148470, ISBN: 0-7803-2590-7.
Keng Leong Fong et al, "A 2.4 GHz Monolithic Mixer for Wireless LAN Applications,"
Custom Integrated Circuits Conference, 1997, Proceedings of the IEEE 1997 Santa
Clara, CA, May 5-8, 1997, New York, NY, IEEE, US, May 5, 1997, pp. 185-188, XP
010235288, ISBN: 0-7803-3669-0.
Jenshan Lin et al., "3V GSM base station RE Receivers Using 0.25/spl mu/m BiCMOS,"
IEEE International Solid-State Circuit Conference, Feb. 5, 2001, pp. 416, 417 and
471, XP 010536327.
EP Search Report, European Patent Application No. 04004414.1, Sep. 27, 2004.
|
Primary Examiner: Le; Dinh T.
Attorney, Agent or Firm: Christie, Parker & Hale, LLP
Parent Case Text
CROSS-REFERENCE TO RELATED APPLICATION(S)
This application is a divisional of U.S. patent application Ser. No. 10/382,811,
filed on Mar. 6, 2003, and entitled "HIGH LINEARITY PASSIVE MIXER AND ASSOCIATED
LO BUFFER," the entire contents of which are incorporated herein by reference.
Claims
What is claimed is:
1. An RF circuit comprising:
a differential pair of inductively loaded LO buffer transistors, each coupled
between a positive voltage source and a ground through an inductive load for producing
a differential LO drive signal for driving a mixer responsive to a different input signal;
a limiter coupled to LO buffer outputs to limit a common mode voltage of the
differential LO drive signal; and
a bias circuit coupled to the gate electrodes of said LO buffer transistors to
provide biasing voltage at the gate electrodes of the LO buffer transistors,
wherein the mixer comprises a passive mixer, and wherein the passive mixer comprises:
a first plurality of transistors of a first type arranged in a ring configuration; and
a second plurality of transistors of a second type,
wherein each of the second plurality of transistors is coupled to a corresponding
one of the first plurality of transistors, and
wherein the passive mixer produces a differential mixer output signal.
2. The RF circuit of claim 1, wherein the differential mixer output signal comprises
an IF signal and wherein the IF signal is produced by the passive mixer as a function
of the differential LO drive signal and an RF information signal received by the
passive mixer.
3. The RF circuit of claim 1, wherein the differential pair of inductively loaded
LO buffer transistors comprise NMOS FETS.
4. An RF circuit comprising:
a differential pair of inductively loaded LO buffer transistors, each coupled
between a positive voltage source and a ground through an inductive load for producing
a differential LO drive signal for driving a mixer responsive to a different input signal;
an LO buffer voltage limiter coupled to first and second buffer outputs of the
differential pair of inductively loaded LO buffer transistors to limit a common
mode voltage of the differential LO drive; and
an LO buffer bias circuit coupled to gate electrodes of the differential pair
of inductively loaded LO butter transistors.
5. The RF circuit of claim 4, wherein the voltage limiter comprises first and
second shunt capacitors, and wherein the first shunt capacitor is coupled to the
first buffer output of the differential pair of inductively loaded LO buffer transistors
and the second shunt capacitor is coupled to the second buffer output of the differential
pair of inductively loaded LO buffer transistors.
6. The RF circuit of claim 4, wherein the voltage limiter comprises first and
second resistors, and wherein the first resistor is coupled between a node of the
common mode voltage and the first buffer output of the differential pair of inductively
loaded LO buffer transistors and the second resistor is coupled between the node
of the common mode voltage and the second buffer output of the differential pair
of inductively loaded LO buffer transistors.
7. The RF circuit of claim 6, wherein the voltage limiter comprises first and
second capacitors, and wherein the first capacitor is commonly coupled to the first
buffer output of the differential pair of inductively loaded LO buffer transistors
with the first resistor and the second capacitor is commonly coupled to the second
buffer output of the differential pair of inductively loaded LO buffer transistors
with the second resistor.
8. An RF circuit for producing a differential LO drive signal for driving a mixer,
the mixer receiving an input signal and producing a differential mixer output signal
using the input signal and the differential LO drive signal, the RF circuit comprising:
a positive voltage source;
a ground;
a differential pair of inductively loaded LO buffer transistors, each coupled
between the positive voltage source and the ground through an inductive load, each
of the pair of inductively loaded LO buffer transistors comprising a gate electrode;
a limiter coupled to LO buffer outputs to limit a common mode voltage of the
differential LO drive signal;
a node coupled between the gate electrodes of the differential pair of inductively
loaded LO buffer transistors; and
an LO buffer bias circuit coupled to the node,
wherein, when one of the differential pair of inductively loaded LO buffer transistors
is powered off by a first buffer drive signal, the other differential pair of inductively
loaded LO buffer transistors is powered on by a second buffer drive signal.
9. The RF circuit of claim 8, wherein the LO buffer bias circuit comprises a
pair of LO buffer bias resistors and an LO buffer biasing source and wherein the
LO buffer biasing source is coupled to the gate electrodes of the differential
pair of inductively loaded LO buffer transistors via the pair of LO buffer bias resistors.
10. The RF circuit of claim 9, wherein the LO buffer biasing source comprises
a current source and a MOS transistor having a gate and a source, wherein the gate
of the MOS transistor is coupled to the gate electrodes of the differential pair
of inductively loaded LO buffer transistors via the pair of LO buffer bias resistors,
and wherein the current source is electrically coupled to both the gate and the
source of the MOS transistor.
11. The RF circuit of claim 10, wherein an aspect ratio of each of the differential
pair of inductively loaded LO buffer transistors is about K times larger than an
aspect ratio of the MOS transistor.
12. The RF circuit of claim 8, wherein the differential pair of inductively loaded
LO buffer transistors comprise NMOS FETS.
13. The RF circuit of claim 8, wherein each of the differential pair of LO buffer
transistors further comprises a drain and a source, wherein the drain of each of
the differential pair of LO butter transistors is coupled to a transistor, and
wherein the source of each of the differential pair of LO buffer transistors is
coupled together and to the ground.
14. The RF circuit of claim 8, further comprising an impedance coupled between
the positive voltage source and the inductively loaded LO buffer transistors to
limit a common mode voltage of the differential LO drive signal.
15. An RF communication system, comprising:
a transmit node for transmitting an RF information signal; and
a receive node for receiving the transmitted RF information signal, and for producing
an IF differential mixer output signal using the received RF information signal,
the receive node including a passive mixer coupled to an amplifier and an LO buffer
for producing a differential LO drive signal for driving the mixer responsive to
a differential input signal, the LO buffer comprising:
a positive voltage source;
a ground;
a differential pair of inductively loaded LO buffer transistors, each coupled
between the positive voltage source and the ground through an inductive load; and
a limiter coupled to LO buffer outputs to limit a common mode voltage of the
differential LO drive signal; and
a bias circuit coupled to the gate electrodes of said LO buffer transistors to
provide biasing voltage at the gate electrodes of the LO buffer transistors,
wherein the passive mixer produces the IF differential mixer output signal as
a function of the drive signal and the received RF information signal, and wherein
the passive mixer comprises:
a first plurality of transistors of a first type arranged in a ring configuration; and
a second plurality of transistors of a second type;
wherein each of the second plurality of transistors is coupled to a corresponding
one of the first plurality of transistors.
16. The RF communication system of claim 15, wherein each of the differential
pair of inductively loaded LO buffer transistors and the first plurality of transistors
comprises an n-type transistor and wherein each of the second plurality of transistors
comprises a p-type transistor.
Description
BACKGROUND
This invention generally relates to communication systems and more particularly
relates to high linearity intermediate frequency stages for RF communication systems.
Communication networks such as wireless networks for transmitting data
and audio information are increasingly in use. Typically, transceivers for wireless
nodes are superheterodyne radio frequency (RF) receivers that mix the received
signal with a local oscillator (LO) signal to down-convert the received signal
(e.g., the RF signal) to one or more intermediate frequency (IF) signals. The IF
signals have fixed, or at least restricted, frequencies which allow the IF signals
to be more easily filtered, amplified, and otherwise processed.
Mixers are typically used to translate the received RF signal in frequency
by combining the received signal with a Local Oscillator (LO) signal to create
an output signal at either the sum (f
RF+f
LO) or the difference
(f
RF-f
LO or f
LO-f
RF) of the input signals.
Mixers may be either passive or active. Passive mixers are based on un-biased semiconductors.
Passive mixer circuits generally exhibit a low noise figure and are highly linear
over a relatively wide dynamic range.
However, passive mixer circuits generally require a relatively high power
local oscillator drive signal as well as low noise IF amplification to compensate
for relatively high insertion loss. For example, most passive mixers have a conversion
loss on the order of 6 dB, a noise figure on the order of 6 dB, and an intercept
point dependant on the amount of LO drive provided which is typically between 0
to +17 dBm for a passive mixer.
SUMMARY OF THE INVENTION
In one aspect of the present invention an RF communications circuit includes a
first plurality of transistors of a first polarity type arranged in a ring configuration
and a second plurality of transistors of a second polarity type. In this embodiment,
a source electrode of each of the second plurality of transistors is coupled to
a drain electrode of a different one of the first plurality of transistors and
a drain electrode of each of the second plurality of transistors is coupled to
a source electrode of a different one of the first plurality of transistors. The
first and second plurality of transistors produce a mixer output signal and a complementary
mixer output signal having a frequency which is a function of the frequency of
an input signal and the frequency of the drive signal.
In another aspect of the present invention a RF communication circuit includes
a first plurality of transistors of a first polarity type arranged in a ring configuration
and a second plurality of transistors of a second polarity type. Each of the second
plurality of transistors is coupled to a unique one of the first plurality of transistors.
In addition an inductively loaded LO buffer for producing differential LO drive
signals drives the first and second plurality of transistors In operation the first
and second plurality of transistors produces an IF differential mixer output signal
and a complementary mixer output signal.
In a further aspect of the present invention a RF communication circuit includes
a differential pair of inductively loaded LO buffer transistors coupled between
a positive voltage source and ground for producing a differential LO drive signal
for driving a mixer.
In a still further aspect of the present invention an RF communications system
includes a transmit node for transmitting an RF information signal and a receive
node for receiving the transmitted RF information signal. The receive node includes
a passive mixer coupled to an amplifier for producing an IF differential mixer
output signal as a function of a LO drive signal. The passive mixer includes a
first plurality of transistors of a first polarity type arranged in a ring configuration
and a second plurality of transistors of a second polarity type, wherein each of
the second plurality of transistors is coupled to a unique one of the first plurality
of transistors.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will become better understood with regard to the following
description, appended claims, and accompanying drawings, in which:
FIG. 1 is a simplified schematic diagram of a conventional passive mixer;
FIG. 2 is a graphical illustration of the on resistance of a Metal-Oxide-Semiconductor
(MOS) Field Effect Transistor (FET) as a function of the gate source voltage;
FIG. 3 is a simplified schematic diagram of a passive mixer having complementary
PMOS transistors coupled to NMOS transistors in accordance with an exemplary embodiment
of the present invention;
FIG. 4 is a graphical illustration of the on resistance of an NMOS transistor,
a PMOS transistor and the parallel resistance of the NMOS and PMOS transistors
as a function of the absolute value of the gate source voltage;
FIG. 5 is a simplified block diagram of the passive mixer of FIG. 3 coupled
to an inductively loaded high swing LO buffer in accordance with an exemplary embodiment
of the present invention;
FIG. 6 is a simplified schematic diagram of the inductively loaded high swing
LO buffer of FIG. 5 in accordance with an exemplary embodiment of the present invention;
FIG. 7 is a simplified schematic diagram of the inductively loaded high swing
LO buffer of FIG. 6 having a bias circuit coupled to inputs of the LO buffer in
accordance with an exemplary embodiment of the present invention;
FIG. 8 is a simplified schematic diagram of the inductively loaded high swing
LO buffer of FIG. 5 wherein the outputs of the LO buffer are AC coupled in accordance
with an exemplary embodiment of the present invention;
FIG. 9 is a simplified schematic diagram of the inductively loaded high swing
LO buffer of FIG. 5 having a resistor coupled between a positive voltage source
and the inductive loads to limit the common mode voltage of the outputs of the
LO buffer in accordance with an exemplary embodiment of the present invention;
FIG. 10 is a simplified block diagram of an RF communications system having
a transmit node and a receive node; and
FIG. 11 is a simplified block diagram of the receiver in the receiver node of
the RF communication system of FIG. 10 in accordance with an exemplary embodiment
of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
An exemplary embodiment of the present invention includes a passive mixer in a
high linearity IF stage for an RF communication system. FIG. 1 illustrates a simplified
circuit diagram of a doubly balanced passive mixer having four FETs M
1-M
4,
arranged in a ring configuration. During passive mixing the drain source bias V
DS
of FETs M
1-m
4 is approximately equal to zero so that each of the
devices operate in the linear region and the channel resistance (i.e. the resistance
between the source and drain) is of the devices is modulated with a large LO drive signal.
In this embodiment the sources of M
3 and M
4 are coupled to the
sources
of M
1 and M
2 respectively to form an IF mixer output
20 and
a complementary IF mixer output
30. In addition, the drains of M
1
and M
2 are coupled to the RF input while the drains of M
3 and M
4
are coupled to the complement of the RF input (i.e. RF input shifted by 180 degrees).
In this embodiment the resistance of the drain-source channels of FETs M
1-M
4
are controlled by the instantaneous voltage applied to their gate electrodes by
the LO drive signal and its complement (i.e. LO
bar).
For example, during the first (positive) half of a sinusoidal LO cycle, the voltage
applied to the gate electrodes of FETs M
1 and M
4 is increased, causing
the drain-to-source resistances of FETs M
1 and M
4 to become very
low. Therefore, the IF mixer output
20 is coupled to the RF input via FET
M
1 and the complement of the RF input is coupled to the complement of the
IF mixer output
30 via M
4 during the positive half of a LO drive
signal cycle.
At the same time, the voltage applied to the gate electrodes of the other pair
of FETS, M
2 and M
3, is decreased (due to the 180 degree phase shift
of the LO signal component applied to those gate electrodes), driving FETs M
2
and M
3 into pinch-off. This causes the source-to-drain channels of FETs
M
2 and M
3 to appear substantially as open-circuits during the positive
half of a LO drive signal cycle.
The opposite occurs during the second or negative half of the sinusoidal LO drive
signal cycle. That is, the gate voltage of FETs M
2 and M
3 is increased
by the complement of the LO signal to produce low drain-to-source resistances for
FETs M
2 and M
3, while the drain-to-source resistances of FETs M
1
and M
4 are driven very high by the instantaneous decrease in the gate voltage
of FETs M
1 and M
4. Thus, the RF signal is coupled through FET M
2
to the complementary IF mixer output
30 and the complement of the RF signal
is coupled through FET M
3 to the IF mixer output
20 during the second
or negative half of the sinusoidal LO drive signal cycle.
In operation, therefore, the outputs
20 and
30 of the passive mixer
switch between the RF input and the complement of the RF input (i.e. essentially
between +/-1) at the LO frequency. The switching action of FETs M
1-M
4
in the time domain provides the desired frequency translation in the frequency
domain. Therefore, the mixer converts the differential RF signal into a baseband
signal or an intermediate frequency (IF) signal having a pair of components 180
degrees out of phase with each other.
However, FETs have a non-linear switch-on resistance as a function of gate-source
voltage (V
GS) as illustrated in FIG. 2. In addition, the sinusoidal
LO drive signal and its complement have relatively small drive voltages for a significant
part of their period. As a result the RF input signal may vary the switch-on resistance
of FETs M
1-M
4 during the periods when the amplitude of the LO drive
voltage is at a low level, thereby introducing distortion and insertion loss into
the mixer output signals.
Therefore, an exemplary passive mixer
100, in accordance with the
present invention, illustrated in FIG. 3, comprises complementary PMOS FETs M
5-M
8
coupled to the NMOS FETS M
1-M
4 respectively to reduce the resistance
and loss associated with the switching transistors M
1-M
4. In the
described exemplary embodiment the source electrode of each of the PMOS FETs M
5-M
8
is coupled to a drain electrode of a corresponding NMOS FET, M
1-M
4
respectively, and a drain electrode of each of the PMOS FETs M
5-M
8
is coupled to a source electrode of a corresponding NMOS FET, M
1-M
4 respectively.
In the described exemplary mixer
100 PMOS FETs M
5 and M
8
are driven by the complement of the LO drive signal and PMOS FETs M
6 and
M
7 are driven by the LO drive signal. Therefore, during the first (positive)
half of a sinusoidal LO drive signal cycle, the voltage applied to the gate electrodes
of NMOS FETs M
1 and M
4 is increased, as is the negative voltage applied
to the gate electrodes of PMOS FETs M
5 and M
8, reducing the drain-to-source
resistances of FETs M
1, M
4, M
5 and M
8. The described
exemplary embodiment therefore provides low impedance switches with on resistances
equal to the parallel resistance of M
1 and M
5 and M
4 and M
8
during the positive half of a LO drive signal cycle. In this instance MOSFETs M
1
and M
5 couple the RF signal to the IF mixer output
20 and MOSFETs
M
4 and M
8 couple the complement of the RF signal to the complement
of the IF mixer output
30.
At the same time, the voltage applied to the gate electrodes of the other pair
of NMOS FETs M
2 and M
3 and PMOS FETs M
6 and M
7 is decreased
(due to the 180 degree phase shift of the LO drive signal component applied to
those gate electrodes), driving. FETs M
2, M
3, M
6 and M
7
into pinch-off. This causes the source-to-drain channels of NMOS FETs M
2
and M
3 and PMOS FETs M
6 and M
7 to appear substantially as
open-circuits during the positive half of a LO drive signal cycle.
The opposite again occurs during the second or negative half of the sinusoidal
LO drive signal cycle. That is, the gate voltages of NMOS FETs M
2 and M
3
are increased by the complement of the LO drive signal to produce a low drain-to-source
resistance for FETs M
2 and M
3, while the drain-to-source resistances
of FETs M
1 and M
4 are driven very high by the instantaneous decrease
in the gate voltage of FETs M
1 and M
4. Similarly, the gate voltage
of PMOS FETs M
6 and M
7 are negative producing a low drain-to-source
resistance for PMOS FETs M
6 and M
7, while the drain-to-source resistances
of PMOS FETs M
5 and M
8 are driven very high by the instantaneous
decrease in the gate voltage of PMOS FETs M
5 and M
8.
Therefore, the described exemplary embodiment provides low impedance switches
whose on resistances are equal to the parallel impedance of M
2 and M
6
and M
3 and M
7 during the second or negative half of the sinusoidal
LO drive signal cycle. In this embodiment the low impedance MOSFETs M
2 and
M
6 couple the RF signal input to the complementary IF mixer output
30
and MOSFETs M
3 and M
7 couple the complement of the RF signal to the
IF mixer output
20 respectively during the second or negative half of the
sinusoidal LO signal cycle.
Thus the outputs
20 and
30 of the described exemplary passive
mixer are again switched between the RF input and the complement of the RF input
(i.e. essentially between +/-1) at the LO frequency. The switching action of FETs
M
1-M
8 in the time domain provides the desired frequency translation
in the frequency domain. Therefore, the described exemplary passive mixer converts
the differential RF signal into a baseband signal or an intermediate frequency
(IF) signal having a pair of components 180 degrees out of phase with each other.
In practice the complementary PMOS devices, M
5-M
8, reduce the average
on resistance and associated loss of the NMOS devices, M
1--M
4, for
a sinusoidal LO drive signal. For example, FIG. 4 graphically illustrates the general
dependence of the on resistance of an NMOS FET
120 and a PMOS FET
130
as a function of the absolute value of the gate-source voltage. The opposite polarity
of the devices is such that the on resistance of a PMOS FET is relatively low when
the on resistance of an NMOS FET is relatively high and vice versa. Therefore,
the parallel combination
140 of the on resistance of a PMOS FET and NMOS
FET, on average, is significantly lower and more linear over a cycle of a sinusoidal
drive signal than the on resistance of the NMOS or PMOS devices alone.
However, the mobility of PMOS FETs tends to be significantly less than the
mobility of a comparably sized NMOS device. Therefore, the aspect ratio of the
PMOS devices M
5-M
8 of the described exemplary mixer are about 3-5
times larger than the aspect ratio of the corresponding NMOS devices M
1-M
4
to provide an optimum match between the on resistance of the PMOS and NMOS devices.
The capacitance of the complementary PMOS devices therefore tends to be relatively
high requiring a relatively high power LO drive signal for distortion free mixing.
Therefore, referring to FIG. 5, an exemplary embodiment of the present invention
further comprises a high swing, inductively loaded LO buffer
200 that provides
high power drive signals
205 and
210 for optimum performance of the
described exemplary passive mixer
100.
For example, FIG. 6 is a simplified schematic diagram of an exemplary LO buffer
200 for driving the described exemplary passive mixer. In this embodiment,
a differential pair of inductively loaded NMOS FETs M
11 and M
12 are
coupled between a positive voltage source V
DD and ground. In operation,
NMOS FETs M
11 and M
12 are driven by a complementary differential
buffer drive signal such that when the drive signal for FET M
11 is high
the drive signal for FET M
12 is low. In operation, if the buffer drive signal
is high, NMOS transistor M
11 is on and LO buffer output
220 is low.
In addition, when the buffer drive signal is high the complement of the buffer
drive signal is low and complementary LO buffer output
230 switches high
(i.e. coupled to the positive voltage source V
DD) through inductive
load L
2.
Similarly, if the buffer drive signal is low, NMOS transistor M
11
is off, and the LO buffer output
220 switches high (i.e. coupled to the
positive voltage source V
DD) through the inductive load L
1. In
addition, in this instance the complement of the buffer drive signal is high switching
on NMOS FET m
12 thereby coupling the complementary LO buffer output
230
to ground (i.e. switching to low).
Advantageously, the use of inductive loads L
1 and L
2
tunes out the capacitance of the buffer and reduces the required power consumption
of the buffers. However, in the described exemplary embodiment, the LO buffer is
coupled between a positive voltage source and ground and does not include a tail
end bias current coupled to the sources of the NMOS FETs M
11 and M
12.
Therefore, in the described exemplary embodiment the driver for the LO buffer may
include an LO buffer bias circuit to apply a predetermined bias voltage to the
gates of NMOS FETS M
11 and M
12. In an exemplary embodiment the LO
buffer bias circuit comprises AC coupling capacitors C
1 and C
2, drive
resistors R
1 and R
2 and an LO buffer biasing source
250 adapted
to provide the desired voltage at nodes N
1 and N
2.
For example referring to FIG. 7, the LO buffer biasing source
250 may
comprise a MOS transistor M
14 having a gate coupled to R
1 and R
2,
the gate and source coupled to a current source I
1 and the drain coupled
to ground. In one embodiment the aspect ratio of NMOS FETs M
11 and M
12
may be substantially equal. In addition, in the described exemplary embodiment
the aspect ratio of NMOS FETs M
11 and M
12 is K times larger than
the aspect ratio of MOS transistor M
14, where K is a constant greater than
unity. The described exemplary biasing circuit therefore performs as a current
mirror where the bias current that drives FETs M
11 and M
12 is approximately
K times larger than the level of current source I
1.
In the described exemplary Lo buffer the inductive loads L
1 and L
2
on the output side of the NMOS FETs M
11 and M
12 may be used to tune
out the capacitance associated with the PMOS FETs M
5--M
8 of the passive
mixer (see FIG. 3). Therefore, the power consumption of the described exemplary
buffer may also be reduced.
In the described exemplary embodiment, the differential LO waveforms output by
the LO buffer
200 are, by way of example, sine waves delivered from a relatively
low output impedance buffer. The described exemplary inductively loaded differential
transistor pair M
11 and M
12 output a very high swing LO buffer signal
220 and complementary LO buffer output signal
230. In an exemplary
embodiment the LO sine waves output by the LO buffer have nearly rail-rail excursions
with the minimum sine wave amplitude limited only by the drain source voltage of
NMOS transistors M
11 and M
12 (i.e. ground+V
DS).
However, the maximum excursion of the differential LO sine waves output
by the inductively loaded transistors may exceed V
DD and may therefore
breakdown the FET devices M
1-M
8 of the passive mixer (see FIG. 3).
In addition, the common mode voltage of the LO buffer output signals, LO and the
complement of LO
220 and
230, is approximately equal to V
DD
which is higher than the optimum drive level for the PMOS FETs M
5-M
8
of the passive mixer.
Therefore, referring to the simplified circuit diagram of FIG. 8, an exemplary
LO buffer
200 may further comprise an LO buffer voltage limiter
225
coupled to the LO buffer outputs
220 and
230 to limit the common
mode voltage of the buffer output signals. In an exemplary embodiment, the voltage
limiter may comprise AC coupling capacitors C
3 and C
4 on the LO buffer
220 and complementary LO buffer
230 outputs along with biasing resistors
R
1 and R
2 which are biased to a predetermined voltage, i.e. V
Common Mode.
In this embodiment, the LO buffer
220 and complementary LO buffer
230
outputs are sinusoidal signals with a common mode voltage that may be set to a
desired level. For example, in one embodiment the common mode output of the LO
buffers may be set at approximately V
DD/2 to provide the optimum gate-source
drive levels for both the NMOS M
1-M
4 and PMOS M
5-M
8
devices of the passive mixer
100 (see FIG. 3).
In operation, however nodes N
3 and N
4 of the LO buffer may still
experience inductive load swings above V
DD. These relatively high voltage
levels may stress the gate to drain junction of NMOS FETs, M
11 and M
12,
compromising the reliability of these devices. In addition, shunt capacitors C
3
and C
4 on the outputs of the LO buffer create a capacitive voltage divider
with the capacitive FETs M
1-M
8 of the passive mixer. The capacitive
voltage divider may significantly reduce the amplitude of the mixer drive signals
for small ratios of the shunt capacitors C
3 and C
4 to the load capacitance
of the FETs of the passive mixer.
Therefore, referring to FIG. 9, an exemplary LO buffer may include a load,
such as for example, a limiting resistor R
5, coupled between the positive
voltage source V
DD and the inductive loads L
1 and L
2 to
limit the common mode voltage of the LO buffer output singals. In this embodiment,
the resistor R
5 creates a voltage drop across the resistor equal to the
product of the current I
3 flowing through R
5 and the resistive value
of R
5 (i.e. an IR drop). Therefore, assuming that inductors L
1 and
L
2 are ideal, the common mode voltage at nodes N
3 and N
4 is
approximately equal to V
DD-I
3R
5. Accordingly, the
reliability of NMOS device M
11 and M
12 may be improved by adjusting
the value of R
5 as can the common mode drive level of FETs M
1-M
8
of the described exemplary passive mixer.
In addition, R
5 will consume less on chip die space than shunt capacitors
C
3 and C
4 (see FIG. 8) and eliminate the signal loss resulting from
the capacitive voltage divider created by the shunt capacitors. One of skill in
the art will appreciate that a capacitor may be coupled in parallel with resistor
R
5 between the positive voltage source and load
FIG. 10 illustrates the integration of the described exemplary passive mixer
100 into an exemplary communication system. The illustrated communications
system
500 comprises a transmit node
502 for transmitting a radio
frequency information signal
505 and a receive node
510 for receiving
and processing the transmitted RF information signal.
Referring to FIG. 11, an exemplary receive node
510 includes, by
way of example, a radio receiver
520, a communications control system or
controller
530, and an antenna
540. In an exemplary embodiment the
antenna may be incorporated directly into the receiver
520. In one embodiment
the communications controller
530 is, by way of example, a media access
controller (MAC) operating in accordance with one or more standards, including
but not limited to, IEEE 802.11, Bluetooth, advanced mobile phone services (AMPS),
global systems for mobile communications (GSM), code division multiple access (CDMA),
local multi-point distribution systems (LMDS), multi-channel-multi-point distribution
systems (MMDS), and or variations thereof. In an exemplary embodiment the communications
controller
530 is coupled to the radio receiver and is, by way of example,
an integrated digital controller with a plurality of inputs and outputs, such as
a transmit data output and a receive data input.
In the illustrated receiver node
510, the receiver
520 is coupled
to the antennae
540 and includes a low noise amplifier
550, one or
more intermediate frequency stages
560 and a filtering stage
570.
In an exemplary embodiment, at least one of the one or more intermediate frequency
stages includes the described exemplary passive mixer.
In the illustrated embodiment, the low noise amplifier
550 receives an
inbound RF signal from the antennae and outputs an amplified received signal to
the described exemplary passive mixer. The passive mixer mixes the amplified received
RF signal with one or more local oscillator signals to convert the amplified received
RF signal into a baseband signal or an intermediate frequency (IF) signal.
The filtering stage
570 then filters the IF or baseband signal to attenuate
unwanted out of band signals to produce a filtered IF signal. The communications
controller recovers raw data from the filtered IF signal in accordance with the
particular communications standard in use.
The invention described herein will itself suggest to those skilled in the various
arts, alternative embodiments and solutions to other tasks and adaptations for
other applications. It is the applicant's intention to cover by claims all such
uses of the invention and those changes and modifications that could be made to
the embodiments of the invention herein chosen for the purpose of disclosure without
departing from the spirit and scope of the invention.
*
