Title: High-speed silicon-based electro-optic modulator
Abstract: A silicon-based electro-optic modulator is based on forming a gate region of a first conductivity to partially overly a body region of a second conductivity type, with a relatively thin dielectric layer interposed between the contiguous portions of the gate and body regions. The modulator may be formed on an SOI platform, with the body region formed in the relatively thin silicon surface layer of the SOI structure and the gate region formed of a relatively thin silicon layer overlying the SOI structure. The doping in the gate and body regions is controlled to form lightly doped regions above and below the dielectric, thus defining the active region of the device. Advantageously, the optical electric field essentially coincides with the free carrier concentration area in this active device region. The application of a modulation signal thus causes the simultaneous accumulation, depletion or inversion of free carriers on both sides of the dielectric at the same time, resulting in high speed operation.
Patent Number: 6,845,198 Issued on 01/18/2005 to Montgomery, et al.
| Inventors:
|
Montgomery; Robert Keith (Easton, PA);
Ghiron; Margaret (Allentown, PA);
Gothoskar; Prakash (Allentown, PA);
Patel; Vipulkumar (Monmouth Junction, NJ);
Shastri; Kalpendu (Orefield, PA);
Pathak; Soham (Allentown, PA);
Yanushefski; Katherine A. (Zionsville, PA)
|
| Assignee:
|
SiOptical, Inc. (Allentown, PA)
|
| Appl. No.:
|
795748 |
| Filed:
|
March 8, 2004 |
| Current U.S. Class: |
385/50; 359/245; 385/14; 385/39; 385/40 |
| Intern'l Class: |
G02B 006/26 |
| Field of Search: |
385/14,39,40,50
359/245
|
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|
Primary Examiner: Kim; Ellen E.
Parent Case Text
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the benefit of Provisional Application No.
60/457,242, filed Mar. 25, 2003.
Claims
What is claimed is:
1. A silicon-based electro-optic device comprising:
a relatively thin silicon body region doped to exhibit a first conductivity
type;
a relatively thin silicon gate region doped to exhibit a second
conductivity type, the silicon gate region disposed at least in part over
the silicon body region to define a contiguous area between said silicon
body and gate regions;
a relatively thin dielectric layer disposed in the contiguous area between
said silicon body and gate regions, the combination of said silicon body
and gate regions with the interposed relatively thin dielectric layer
defining the active region of the electro-optic device;
a first electrical contact coupled to said silicon gate region; and
a second electrical contact coupled to said silicon body region, wherein
upon application of an electrical signal to the first and second
electrical contacts, free carriers accumulate, deplete or invert within
the silicon body and gate regions on both sides of the relatively thin
dielectric layer at the same time, such that the optical electric field of
said optical signal substantially overlaps with the free carrier
concentration modulation area in the active region of said electro-optic
device.
2. A silicon-based electro-optic device as defined in claim 1 wherein the
relative placement of the silicon gate region with respect to the silicon
body region is controlled, in combination with the doping concentrations
and thickness of said silicon gate and body regions and the thickness of
the dielectric layer, such that upon the application of an electrical
signal to the first and second electrical contacts, the position of the
free carrier concentration modulation peak near the dielectric layer
substantially coincides with the position of the peak of the optical
electric field.
3. A silicon-based electro-optic device as defined in claim 1 wherein the
peak of the optical electric field is within one fourth of the total
thickness of the silicon gate region as defined from the relatively thin
dielectric layer and within one fourth of the total thickness of the
silicon body region as defined from said relatively thin dielectric layer.
4. A silicon-based electro-optic device as defined in claim 3 wherein the
peak of the optical electric field is within one eighth of the total
thickness of the silicon gate region as defined from the relatively thin
dielectric layer and within one eighth of the total thickness of the
silicon body region as defined from said relatively thin dielectric layer.
5. A silicon-based electro-optic device as defined in claim 1 wherein the
percentage of the optical electric field in the silicon gate region is
substantially equal to the percentage of the optical electric field in the
silicon body region.
6. A silicon-based electro-optic device as defined in claim 1 wherein
the relatively thin silicon gate region is defined as comprising a first
portion associated with the active region and a second portion associated
with the location of a first electrical contact region.
7. A silicon-based electro-optic device as defined in claim 6 wherein the
second portion of the silicon gate region includes first and second
separated areas disposed on either side of the first portion, with the
first electrical contact region disposed in the first separated area and a
third electrical contact region disposed in the second separated area.
8. A silicon-based electro-optic device as defined in claim 7 wherein the
first and third electrical contact regions each comprise a silicide formed
within the first and second areas of the second portion of the silicon
gate region.
9. A silicon-based electro-optic device as defined in claim 8 wherein the
silicide is chosen from the group consisting of tantalum silicide, cobalt
silicide, titanium silicide, molybdenum silicide, tungsten silicide and
nickel silicide.
10. A silicon-based electro-optic device as defined in claim 9 wherein the
silicide is titanium silicide.
11. A silicon-based electro-optic device as defined in claim 7 wherein the
first and third electrical contact regions each comprise a plurality of
separate contact areas disposed at different locations along the first and
second areas, respectively, of the second portion of the silicon gate
region to reduce optical loss while providing low series resistance.
12. A silicon-based electro-optic device as defined in claim 7 wherein the
silicon gate region is patterned to include a central longitudinal extent
disposed to essentially cover the active device region, and at least two
contact arms disposed orthogonal to said central longitudinal extent, each
contact arm providing electric contact to the first and third electrical
contact regions in the first and second areas of the second gate portion.
13. A silicon-based electro-optic device as defined in claim 7 wherein the
silicon gate region is patterned to include a relatively wide longitudinal
extent disposed to cover an extended central portion of the device
extending beyond the active device region, the silicon gate region further
patterned to form a plurality of contacts to the first and third
electrical contact regions in the first and second areas of the second
gate portion, and a plurality of openings to expose a plurality of
contacts to the second and fourth electrical contact regions of the first
and second areas of the second body portion.
14. A silicon-based electro-optic device as defined in claim 6 wherein the
first portion of the silicon gate region is more lightly doped than the
second portion of the silicon gate region to reduce optical loss in the
first portion, the second portion being more heavily doped to provide a
relatively low series resistance between the active region and the first
electrical contact region.
15. A silicon-based electro-optic device as defined in claim 14 wherein the
relatively low series resistance allows for high speed operation when
driven by an electrical signal source having a relatively low output drive
impedance.
16. A silicon-based electro-optic device as defined in claim 14 wherein the
silicon gate region exhibits a graded dopant concentration increasing from
the first portion to the second portion.
17. A silicon-based electro-optic device as defined in claim 6 wherein the
silicon gate region exhibits a third portion disposed above the first
portion, the third portion being more lightly doped than the first portion
to reduce optical loss within the active portion.
18. A silicon-based electro-optic device as defined in claim 17 wherein the
silicon gate region exhibits a graded dopant concentration decreasing from
the first portion to the third portion.
19. A silicon-based electro-optic device as defined in claim 6 wherein the
first portion of the silicon gate region exhibits a dopant concentration
on the order of 10.sup.17 cm.sup.-3 and the second portion of the silicon
gate region exhibits a dopant concentration on the order of 10.sup.19
cm.sup.-3.
20. A silicon-based electro-optic device as defined in claim 6 wherein the
first electrical contact region comprises a silicide formed within the
second portion of the silicon gate region.
21. A silicon-based electro-optic device as defined in claim 20 wherein the
silicide is chosen from the group consisting of tantalum silicide, cobalt
silicide, titanium silicide, molybdenum silicide, tungsten silicide and
nickel silicide.
22. A silicon-based electro-optic device as defined in claim 6 wherein the
first electrical contact region comprises a plurality of separate contact
areas disposed at different locations along the second portion of the
silicon gate region to reduce optical signal loss while providing low
series resistance.
23. A silicon-based electro-optic device as defined in claim 1 wherein the
thickness of the relatively thin silicon gate region is controlled to
maintain the peak of the optical electric field at substantially the
location of the relatively thin dielectric layer.
24. A silicon-based electro-optic device as defined in claim 1 wherein the
relatively thin silicon gate region comprises a thickness less than
one-half micron.
25. A silicon-based electro-optic device as defined in claim 24 wherein the
relatively thin silicon gate region comprises a thickness less than 0.2
.mu.m.
26. A silicon-based electro-optic device as defined in claim 1 wherein the
relatively thin silicon gate region comprises one or more forms of silicon
chosen from the group consisting of: polysilicon, amorphous silicon,
grain-size-enhanced polysilicon, grain-boundary-passivated polysilicon,
grain-aligned polysilicon, strained silicon, substantially single crystal
silicon, Si.sub.x Ge.sub.1-x and single crystal silicon.
27. A silicon-based electro-optic device as defined in claim 26 wherein the
relatively thin silicon gate region comprises a single layer of one form
of silicon selected from the identified group.
28. A silicon-based electro-optic device as defined in claim 26 wherein the
relatively thin silicon gate region comprises multiple layers of silicon,
selected from one or more of the forms of silicon in the identified group.
29. A silicon-based electro-optic device as defined in claim 26 wherein the
relatively thin silicon gate region comprises polysilicon.
30. A silicon-based electro-optic device as defined in claim 29 wherein the
polysilicon comprises grain-size-enhanced polysilicon.
31. A silicon-based electro-optic device as defined in claim 30 wherein the
grain-size-enhanced polysilicon is formed using a seed catalyst technique.
32. A silicon-based electro-optic device as defined in claim 30 wherein the
grain-size-enhanced polysilicon is formed using a silicon implantation and
anneal process.
33. A silicon-based electro-optic device as defined in claim 29 wherein the
polysilicon comprises grain-boundary-passivated polysilicon.
34. A silicon-based electro-optic device as defined in claim 33 wherein the
grain-boundary-passivated polysilicon is formed using a hydrogen anneal
process.
35. A silicon-based electro-optic device as defined in claim 29 wherein the
polysilicon comprises grain-aligned polysilicon.
36. A silicon-based electro-optic device as defined in claim 26 wherein the
relatively thin silicon gate region comprises amorphous silicon.
37. A silicon-based electro-optic device as defined in claim 26 wherein the
relatively thin silicon gate region comprises strained silicon.
38. A silicon-based electro-optic device as defined in claim 26 wherein the
relatively thin silicon gate region comprises substantially single crystal
silicon.
39. A silicon-based electro-optic device as defined in claim 26 wherein the
relatively thin silicon gate region comprises Si.sub.x Ge.sub.1-x.
40. A silicon-based electro-optic device as defined in claim 26 wherein the
relatively thin silicon gate region comprises single crystal silicon.
41. A silicon-based electro-optic device as defined in claim 1 wherein the
silicon gate region exhibits one or more rounded corner edges in the
active device region to reduce optical signal loss.
42. A silicon-based electro-optic device as defined in claim 1 wherein the
relatively thin silicon body region is defined as comprising a first
portion associated with the active region and a second portion associated
with the location of a second electrical contact region.
43. A silicon-based electro-optic device as defined in claim 42 wherein the
second portion of the silicon body region includes first and second
separated areas disposed on either side of the first portion, with the
second electrical contact region disposed in the first separated area and
a fourth electrical contact region disposed in the second separated area.
44. A silicon-based electro-optic device as defined in claim 43 wherein the
second and fourth electrical contact regions each comprise a silicide
formed within the first and second areas of the second portion of the
silicon body region.
45. A silicon-based electro-optic device as defined in claim 44 wherein the
silicide is chosen from the group consisting of tantalum silicide, cobalt
silicide, titanium silicide, molybdenum silicide, tungsten silicide and
nickel silicide.
46. A silicon-based electro-optic device as defined in claim 43 wherein the
second and fourth electrical contact regions each comprise a plurality of
separate contact areas disposed at different locations along the first and
second areas, respectively, of the second portion of the silicon body
region to reduce optical loss while providing low series resistance.
47. A silicon-based electro-optic device as defined in claim 42 wherein the
first portion of the silicon body region is more lightly doped than the
second portion of the silicon body region to reduce optical signal loss in
the first portion, the second portion being more heavily doped to provide
a relatively low series resistance between the active region and the
second electrical contact region.
48. A silicon-based electro-optic device as defined in claim 47 wherein the
relatively low series resistance allows for higher speed operation when
driven by an electrical signal source having a relatively low output drive
impedance.
49. A silicon-based electro-optic device as defined in claim 47 wherein the
silicon body region exhibits a graded dopant concentration increasing from
the first portion to the second portion.
50. A silicon-based electro-optic device as defined in claim 42 wherein the
silicon body region exhibits a third portion disposed below the first
portion, the third portion being more lightly doped than the first portion
to reduce optical loss within the active region.
51. A silicon-based electro-optic device as defined in claim 50 wherein the
silicon body region exhibits a graded dopant concentration decreasing from
the first portion to the third portion.
52. A silicon-based electro-optic device as defined in claim 42 wherein the
first portion of the silicon body region exhibits a dopant concentration
on the order of 10.sup.17 cm.sup.-3 and the second portion of the silicon
body region exhibits a dopant concentration on the order of 10.sup.19
cm.sup.-3.
53. A silicon-based electro-optic device as defined in claim 42 wherein the
second electrical contact region comprises a silicide formed within the
second portion of the silicon body region.
54. A silicon-based electro-optic device as defined in claim 42 wherein the
silicide is chosen from the group consisting of tantalum silicide, cobalt
silicide, titanium silicide, molybdenum silicide, tungsten silicide and
nickel silicide.
55. A silicon-based electro-optic device as defined in claim 42 wherein the
second electrical contact region comprises a plurality of separate contact
areas disposed at different locations along the second portion of the
silicon body region to reduce optical signal loss while providing low
series resistance.
56. A silicon-based electro-optic device as defined in claim 1 wherein the
thickness of the relatively thin silicon body region is controlled to
maintain the peak of the optical electric field at substantially the
location of the relatively thin dielectric layer.
57. A silicon-based electro-optic device as defined in claim 1 wherein the
relatively thin silicon body region comprises a thickness of less than
one-half micron.
58. A silicon-based electro-optic device as defined in claim 57 wherein the
relatively thin silicon body region comprises a thickness of less than 0.2
.mu.m.
59. A silicon-based electro-optic device as defined in claim 1 wherein the
relatively thin silicon body region comprises one or more forms of silicon
chosen from the group consisting of: partially-depleted silicon,
fully-depleted silicon, strained silicon, substantially single crystal
silicon, Si.sub.x Ge.sub.1-x and single crystal silicon.
60. A silicon-based electro-optic device as defined in claim 59 wherein the
relatively thin silicon body region comprises a single layer of one form
of silicon selected from the identified group.
61. A silicon-based electro-optic device as defined in claim 59 wherein the
relatively thin silicon body region comprises multiple layers of silicon,
selected from one or more of the forms of silicon in the identified group.
62. A silicon-based electro-optic device as defined in claim 59 wherein the
relatively thin silicon body region comprises partially-depleted silicon.
63. A silicon-based electro-optic device as defined in claim 59 wherein the
relatively thin silicon body region comprises fully-depleted silicon.
64. A silicon-based electro-optic device as defined in claim 59 wherein the
relatively thin silicon body region comprises strained silicon.
65. A silicon-based electro-optic device as defined in claim 59 wherein the
relatively thin silicon body region comprises substantially single crystal
silicon.
66. A silicon-based electro-optic device as defined in claim 59 wherein the
relatively thin silicon body region comprises Si.sub.x Ge.sub.1-x.
67. A silicon-based electro-optic device as defined in claim 59 wherein the
relatively thin silicon body region comprises single crystal silicon.
68. A silicon-based electro-optic device as defined in claim 1 wherein the
silicon body region exhibits one or more rounded corner edges in the
active device region to reduce optical signal loss.
69. A silicon-based electro-optic device as defined in claim 1 wherein the
silicon body region exhibits p-type conductivity and the silicon gate
region exhibits n-type conductivity.
70. A silicon-based electro-optic device as defined in claim 1 wherein the
silicon body region exhibits n-type conductivity and the silicon gate
region exhibits p-type conductivity.
71. A silicon-based electro-optic device as defined in claim 1 wherein the
silicon body region exhibits both n-type and p-type conductivity, with the
concentration of the electrons being greater than the concentration of the
holes, and the silicon gate region exhibits both n-type and p-type
conductivity, with the concentration of the holes being greater than the
concentration of electrons, the differences in concentration sufficient to
provide for free carrier movement upon application of an electrical
signal.
72. A silicon-based electro-optic device as defined in claim 1 wherein the
silicon body region exhibits both n-type and p-type conductivity, with the
concentration of the holes being greater than the concentration of the
electrons, and the silicon gate region exhibits both n-type and p-type
conductivity, with the concentration of electrons being greater than the
concentration of holes, the differences in concentration sufficient to
provide for free carrier movement upon application of an electrical
signal.
73. A silicon-based electro-optic device as defined in claim 1 wherein the
relatively thin dielectric layer comprises a material exhibiting rapid
charge and discharge of free carriers within the silicon gate and body
regions on both sides of said relatively thin dielectric layer.
74. A silicon-based electro-optic device as defined in claim 73 wherein the
relatively thin dielectric layer comprises a single layer formed of one
material.
75. A silicon-based electro-optic device as defined in claim 73 wherein the
relatively thin dielectric layer comprises a plurality of sub-layers
comprising at least one material.
76. A silicon-based electro-optic device as defined in claim 73 wherein the
dielectric is chosen from the group consisting of: silicon dioxide,
silicon nitride, oxynitride, bismuth oxide, hafnium oxide, and any
combination thereof.
77. A silicon-based electro-optic device as defined in claim 1 wherein the
relatively thin dielectric layer comprises a thickness of no more than
1000 .ANG..
78. A silicon-based electro-optic device as defined in claim 77 wherein the
relatively thin dielectric layer comprises a thickness of no more than 200
.ANG..
79. A silicon-based electro-optic device as defined in claim 1 wherein the
device further comprises a surrounding region exhibiting a lower effective
refractive index than the active region, the surrounding region disposed
such that the effective refractive index decreases away from the active
region to provide substantial vertical and horizontal optical signal
confinement within the electro-optic device.
80. A silicon-based electro-optic device as defined in claim 79 wherein the
surrounding region comprises one or more materials chosen from the group
consisting of silicon dioxide, silicon nitride or silicon.
81. A silicon-based electro-optic device as defined in claim 1 wherein the
device comprises an electro-optic phase modulator, with an electrical
modulating signal applied to the first and second electrical contacts, the
modulator drawing substantially zero DC power during operation.
82. A silicon-based electro-optic device as defined in claim 81 wherein the
device is a low power device, drawing substantially zero DC power during
operation and drawing AC power essentially only during the transitions
between optical "1" and optical "0" phase conditions.
83. A silicon-based electro-optic device as defined in claim 81 wherein the
device is a defined as a low voltage device, operating with an electrical
modulating signal input voltage of a value less than or equal to a supply
voltage consistent with the integral CMOS transistor technology.
84. A silicon-based electro-optic device as defined in claim 81 wherein the
device is a defined as a low voltage device, operating with an electrical
modulating signal input voltage of a value less than 2V.
85. A silicon-based electro-optic device as defined in claim 81 wherein the
device comprises an active length along the optical propagation direction
of no more than 2 millimeters.
86. A silicon-based electro-optic device as defined in claim 1 wherein the
device comprises a plurality of electro-optic phase modulators, with at
least one electrical modulating signal applied as an input to at least one
of the first and second electrical contacts.
87. A silicon-based electro-optic device as defined in claim 86 wherein the
plurality of electro-optic phase modulators comprises a parallel array of
electro-optic phase modulators.
88. A silicon-based electro-optic device as defined in claim 86 wherein the
plurality of electro-optic phase modulators comprises a serial connection
of electro-optic phase modulators.
89. A silicon-based electro-optic device as defined in claim 1 wherein the
electro-optic device is formed as part of a silicon-on-insulator (SOI)
arrangement including a silicon substrate, a buried dielectric layer and a
relatively thin surface silicon layer, with the silicon body region of
said electro-optic device formed within the relatively thin surface
silicon layer.
90. A silicon-based electro-optic device as defined in claim 89 wherein the
buried dielectric layer comprises a material with a lower refractive index
than silicon and provides for optical confinement within the relatively
thin silicon body region formed in the SOI surface silicon layer.
91. A silicon-based electro-optic device as defined in claim 89 wherein the
buried dielectric layer comprises a thickness associated with achieving
substantially low optical loss.
92. A silicon-based electro-optic device as defined in claim 91 wherein the
buried dielectric layer comprises a thickness of at least 0.2 microns.
93. A silicon-based electro-optic device as defined in claim 89 wherein the
relatively thin surface silicon layer comprises a thickness no greater
than one-half micron.
94. A silicon-based electro-optic device as defined in claim 93 wherein the
relatively thin surface silicon layer comprises a thickness no greater
than 0.2 .mu.m.
95. A silicon-based electro-optic device as defined in claim 1 wherein the
silicon gate region comprises a shape including an input, increasing taper
along a portion of the device where an optical signal is coupled into the
active region, the input taper to minimize optical signal reflections at
the input of the electro-optic device.
96. A silicon-based electro-optic device as defined in claim 95 wherein the
input, increasing taper is essentially undoped.
97. A silicon-based electro-optic device as defined in claim 95 wherein the
input taper is a one-dimensional taper in same direction as the optical
signal propagation direction.
98. A silicon-based electro-optic device as defined in claim 95 wherein the
input taper is a two-dimensional taper including a first dimension taper
in the same direction as the optical signal propagation and a second
dimension taper in a direction perpendicular to the optical signal
propagation direction.
99. A silicon-based electro-optic device as defined in claim 95 wherein the
device further comprises an angled silicon body region, the angled silicon
body region having a shape such that an overlap between the angled silicon
body region and the tapered silicon gate region reduces corner reflections
and provides optical mode matching at the input of the electro-optic
device.
100. A silicon-based electro-optic device as defined in claim 99 wherein
the angled silicon body region is patterned to angle in opposition to the
input and output tapers of the silicon gate region such that the overlap
between the opposing directions of the body and gate regions is used to
control and define the width of the active device region.
101. A silicon-based electro-optic device as defined in claim 1 wherein the
silicon gate region comprises a shape including an output, decreasing
taper along a portion of the device where an optical signal is coupled out
of the active region, the output taper to minimize optical signal
reflections at the output of the electro-optic device.
102. A silicon-based electro-optic device as defined in claim 101 wherein
the output, decreasing taper is essentially undoped.
103. A silicon-based electro-optic device as defined in claim 101 wherein
the output taper is a one-dimensional taper in same direction as the
optical signal propagation direction.
104. A silicon-based electro-optic device as defined in claim 101 wherein
the output taper is a two-dimensional taper including a first dimension
taper in the same direction as the optical signal propagation and a second
dimension taper in a direction perpendicular to the optical signal
propagation direction.
105. A silicon-based electro-optic device as defined in claim 101 wherein
the device further comprises an angled silicon body region, the angled
silicon body region having a shape such that an overlap between the angled
silicon body region and the tapered silicon gate region reduces corner
reflections and provides optical mode matching at the output of the
electro-optic device.
106. A silicon-based electro-optic device as defined in claim 105 wherein
the angled silicon body region is patterned to angle in opposition to the
input and output tapers of the silicon gate region such that the overlap
between the opposing directions of the body and gate regions is used to
control and define the width of the active device region.
107. A silicon-based electro-optic device as defined in claim 106 wherein
the overlap may be defined to comprise a width less than the individual
layer minimum design width rules used to form the electro-optic device.
108. A silicon-based electro-optic device as defined in claim 1 wherein the
silicon body region comprises a shape including an input, decreasing taper
along a portion of the device where an optical signal is coupled into the
active region to provide optical mode matching into the electro-optic
device.
109. A silicon-based electro-optic device as defined in claim 108 wherein
the input, decreasing taper is essentially undoped.
110. A silicon-based electro-optic device as defined in claim 108 wherein
the input taper is a one-dimensional taper in the same direction as the
optical signal propagation direction.
111. A silicon-based electro-optic device as defined in claim 1 wherein the
silicon body region comprises a shape including an output, increasing
taper along a portion of the device where an optical signal is coupled out
of the active region to provide optical mode matching out of the
electro-optic device.
112. A silicon-based electro-optic device as defined in claim 111 wherein
the output, increase taper is essentially undoped.
113. A silicon-based electro-optic device as defined in claim 111 wherein
the output taper of the silicon body region is a one-dimensional taper in
the same direction as the optical signal propagation direction.
114. A Mach-Zehnder interferometer comprising
an input optical waveguide splitter, defined as comprising an input
waveguide section optically coupled to both a first arm and a second arm,
said first and second arms disposed in parallel; and
an output optical waveguide combiner, defined as comprising an output
waveguide section optically coupled to the input optical waveguide
splitter first and second arms, wherein the first arm includes a first
electro-optic phase modulator comprising:
a relatively thin silicon body region doped to exhibit a first conductivity
type;
a relatively thin silicon gate region doped to exhibit a second
conductivity type, the silicon gate region disposed at least in part over
the silicon body region to define a contiguous area between said silicon
body and gate regions;
a relatively thin dielectric layer disposed in the contiguous area between
said silicon body and gate regions, the combination of said silicon body
and gate regions with the interposed relatively thin dielectric layer
defining the active region of the electro-optic device;
a first electrical contact coupled to said silicon gate region; and
a second electrical contact coupled to said silicon body region, wherein
upon application of an electrical signal to the first and second
electrical contacts, free carriers accumulate, deplete or invert within
the silicon body and gate regions on both sides of the relatively thin
dielectric layer at the same time, such that the optical electric field of
said optical signal substantially overlaps with the free carrier
concentration modulation area in the active region of said first
electro-optic phase modulator device.
115. A Mach-Zehnder interferometer as defined in claim 114 wherein the
interferometer further comprises a second electro-optic modulator disposed
along the second arm, said second electro-optic modulator comprising
a relatively thin silicon body region doped to exhibit a first conductivity
type;
a relatively thin silicon gate region doped to exhibit a second
conductivity type, the silicon gate region disposed at least in part over
the silicon body region to define a contiguous area between said silicon
body and gate regions;
a relatively thin dielectric layer disposed in the contiguous area between
said silicon body and gate regions, the combination of said silicon body
and gate regions with the interposed relatively thin dielectric layer
defining the active region of the electro-optic device;
a first electrical contact coupled to said silicon gate region; and
a second electrical contact coupled to said silicon body region, wherein
upon application of an electrical signal to the first and second
electrical contacts, free carriers accumulate, deplete or invert within
the silicon body and gate regions on both sides of the relatively thin
dielectric layer at the same time, such that the optical electric field of
said optical signal substantially overlaps with the free carrier
concentration modulation area in the active region of said second
electro-optic modulator.
116. A Mach-Zehnder interferometer as defined in claim 115 wherein the
first arm operates in depletion mode and the second arm operates in
accumulation mode.
117. A Mach-Zehnder interferometer as defined in claim 115 wherein the
first arm operates in accumulation mode and the second arm operates in
depletion mode.
118. A Mach-Zehnder interferometer as defined in claim 115 wherein both the
first and second arms operate in depletion mode.
119. A Mach-Zehnder interferometer as defined in claim 115 wherein both the
first and second arms operate in accumulation mode.
120. A Mach-Zehnder interferometer as defined in claim 115 wherein both the
first and second arms operate in inversion mode.
121. A Mach-Zehnder interferometer as defined in claim 115 wherein the
Mach-Zehnder interferometer is balanced and symmetric such that the active
length along the optical propagation direction of the first arm is
essentially equal to the active length along the optical propagation
direction of the second arm.
122. A Mach-Zehnder interferometer as defined in claim 115 wherein the
Mach-Zehnder interferometer comprises an asymmetric construction between
the first and second arms.
123. A Mach-Zehnder interferometer as defined in claim 122 wherein the
active length along the optical propagation direction of the first arm is
unequal to the active length along the optical propagation direction of
the second arm.
124. A Mach-Zehnder interferometer as defined in claim 122 wherein the
first arm comprises a plurality of N separate electro-optic modulators and
the second arm comprises a plurality of M separate electro-optic
modulators, where N.noteq.M.
125. A Mach-Zehnder interferometer as defined in claim 122 wherein the
first arm comprises a plurality of N separate electro-optic modulators and
the second arm comprises a plurality of M separate electro-optic
modulators, where N=M.
126. A Mach-Zehnder interferometer as defined in claim 122 wherein the
dopant concentration in the first arm is different than the dopant
concentration in the second arm.
127. A Mach-Zehnder interferometer as defined in claim 122 wherein the
input optical waveguide splitter presents a ratio of input optical signal
power other than 50:50 to the first and second arms.
128. A Mach-Zehnder interferometer as defined in claim 115 wherein
the first electro-optic modulator disposed along the first arm is formed
such that the silicon gate region is located on the exterior of the first
arm optical waveguide and the silicon body region is located on the
interior of said first arm optical waveguide; and
the second electro-optic modulator disposed along the second arm is formed
such that the silicon body region is located on the exterior of the first
arm optical waveguide and the silicon gate region is located on the
interior of said second arm optical waveguide.
129. A Mach-Zehnder interferometer as defined in claim 114 wherein the
input and output optical waveguides are formed in the relatively thin
silicon layer used to form the body region.
130. A Mach-Zehnder interferometer as defined in claim 114 wherein the
relatively thin silicon gate region comprises a form of silicon capable of
supporting optical transmission and the input and output optical
waveguides are formed at least in part in said relatively thin silicon
gate region.
131. A Mach-Zehnder interferometer as defined in claim 114 wherein the
input and output optical waveguides are formed by a combination of the
silicon gate region, the relatively thin gate dielectric layer and the
silicon body region, the combination as defined by the active device
region.
132. A Mach-Zehnder interferometer as defined in claim 114 wherein the
Mach-Zehnder interferometer comprises a plurality of separate
interferometers disposed in a predetermined combination.
133. A Mach-Zehnder interferometer as defined in claim 132 wherein the
plurality of Mach-Zehnder interferometers are disposed in a parallel
configuration.
134. A Mach-Zehnder interferometer as defined in claim 132 wherein the
plurality of Mach-Zehnder interferometers are disposed in a serial
configuration.
Description
TECHNICAL FIELD
The present invention relates to a silicon-based electro-optic modulator
and, more particularly, to an electro-optic modulator based on SOI
technology and utilizing a Silicon-Insulator-Silicon CAPacitor (SISCAP)
guide geometry to provide efficient, high-speed operation.
BACKGROUND OF THE INVENTION
Silicon-based photonic components working at 1330 and 1500 nm fiber-optic
communication wavelengths for various systems such as fiber-to-the-home
and local area networks (LANs) are a subject of intensive research as a
result of the possibility of integrating optical elements and advanced
electronics together on a silicon substrate using the well-known
techniques of CMOS technology.
Passive silicon structures, such as waveguides, couplers and filters have
been extensively studied. Less work has been reported on active silicon
devices (i.e., tunable devices), such as modulators and switches, despite
their importance as a means of manipulating light beams for such
communication systems. Some silicon-based thermo-optic active devices have
been designed, where the refractive index of the silicon is modulated by
varying the silicon temperature, thereby inducing a phase modulation and
absorption which in turn is used to produce an intensity modulation at the
output of the device. Nevertheless, the thermo-optic effect is rather slow
and can only be used for device speeds up to 1 Mb/s modulation frequency.
Therefore, for higher modulation frequencies (which are of more interest
in most systems, including communication systems), electro-optic active
devices are required.
Most of the proposed electro-optic devices exploit the free carrier
dispersion effect to change both the real and imaginary parts of the
refractive index. This exploitation is used since the unstrained pure
crystalline silicon does not exhibit a linear electro-optic (Pockels)
effect, and the refractive index changes due to the Franz-Keldysh effect
and Kerr effect are very weak. In free carrier absorption modulators, as
will be discussed in detail below, changes in the optical absorption of
the structures are directly transformed into an output intensity
modulation. Phase modulation in a specific region of optical devices, such
as Mach-Zehnder modulators, total-internal-reflection (TIR)-based
structures, cross switches, Y-switches, ring resonators and Fabry-Perot
resonators, is also used to modulate the output intensity.
Free carrier concentration in electro-optic devices can be varied by
injection, accumulation, depletion or inversion of carriers. Most of such
devices investigated to date present some common features: they require
long interaction lengths (for example, 5-10 mm) and injection current
densities higher than 1 kA/cm.sup.3 in order to obtain a significant
modulation depth. Long interaction lengths are undesirable in order to
achieve high levels of integration and miniaturization for fabricating
low-cost compact device arrangements. High current densities may induce
unwanted thermo-optic effects as a result of heating the structure and
will, indeed, cause an opposite effect on the real refractive index change
relative to that associated with free carrier movement, thus reducing its
effectiveness.
FIG. 1 illustrates an exemplary prior art, silicon-based electro-optic
phase modulator 1 formed using a raised rib waveguide on an SOI structure.
Electro-optic phase modulator 1 includes a layer of intrinsic (single
crystal) silicon 2 that has been processed to include a rib structure 3
that extends transversely (as shown in the insert) to form the optical
waveguide of modulator 1, where the direction of optical signal
propagation is also shown in the insert. Intrinsic silicon layer 2 is
illustrated as the top layer of a conventional silicon-on-insulator (SOI)
wafer structure, which further comprises a buried oxide (BOX) layer 4 and
silicon substrate 5. The structure as shown forms a PIN diode modulator
and is arranged to vary the refractive index in silicon rib waveguide 3 by
using the free carrier dispersion effect, as mentioned above. In this
particular example, silicon layer 2 is formed to include a heavily-doped
p-type region 6 in contact with a first electrical contact 7. Layer 2
further includes, as shown, a heavily-doped n-type region 8 and associated
second electrical contact 9. In one example, regions 6 and 8 may be doped
to exhibit a dopant concentration on the order of 10.sup.20 carriers per
cm.sup.3. In this PIN structure, p-type region 6 and n-type region 8 are
spaced apart on opposite sides of rib 3 so that intrinsic silicon lies
between the heavily doped regions both in rib 3 and silicon layer 2.
In operation, first and second electrical contacts are connected to a
voltage supply so as to forward bias the diode and thereby inject free
carriers into waveguide 3. The increase in free carriers changes the
refractive index of the silicon (as discussed using the Drude model,
below) and can therefore be used to achieve phase modulation of light
transmitted through the waveguide. However, to act as an optical
modulator, the speed of operation of electro-optic modulator 1 is limited
by the lifetime of free carriers in rib 3, as well as the carrier
diffusion rates when the forward bias is removed. Such prior art PIN diode
phase modulators typically have a speed of operation in the range of 10-50
Mb/s for forward biased operation. By introducing impurities into the
silicon, which act as carrier lifetime "killers", the switching speed can
be increased, but the introduced impurities detrimentally affect the
optical transmission. However, the primary impact on speed is due to the
RC time constant product, where the capacitance (C) in forward bias
becomes very large due to the reduction in the depletion layer width of
the PN junction in forward bias. Theoretically, high speed operation of a
PN junction could be achieved in reverse bias, although this would require
large drive voltages and long device lengths, which are incompatible with
the CMOS process.
There remains, therefore, an urgent need for optical modulator structures
based on the electro-optic effect that can be implemented in a sub-micron
region while offering low cost, low current density, low power
consumption, high modulation depth, low voltage requirements and high
speed modulation.
SUMMARY OF THE INVENTION
The need remaining in the prior art is addressed by the present invention,
which relates to a silicon-based electro-optic modulator and, more
particularly, to the formation of an electro-optic modulator on an SOI
wafer utilizing novel SISCAP designs with optical guide confinement
geometries to provide low optical loss, high-speed operation.
In accordance with the present invention, complementary-doped silicon
regions (defined hereinafter as a "body" region and "gate" region) are
formed to partially overly one another with a relatively thin "gate"
dielectric layer disposed therebetween (thus forming the SISCAP
structure), where the area associated with the layered arrangement of a
doped gate region/dielectric/doped body region then defines the location
of free carrier movement into and out of each doped region during
modulation. The term "relatively thin", when used in the context of
describing the body and/or gate regions, is intended to define a thickness
of less than one-half micron. A first doped region is formed in the thin
(i.e., sub-micron) surface silicon layer of an SOI structure and
conventional CMOS processing is used to form an overlying dielectric and
complementary-doped silicon layer, CMOS processing being capable of
providing the desired doping concentration profiles within each region.
The underlying body (or surface) silicon layer may comprise a
partially-depleted or fully-depleted CMOS element, strained silicon,
Si.sub.x Ge.sub.1-x, single crystal silicon or any combination thereof.
The dielectric layer is formed of a material (or ultra-thin layers of more
than one material) that provides for efficient transport of carriers into
and out of the body and gate regions when the device is biased functioning
as a barrier to carrier transport between the body and gate regions. For
example, hafnium oxide, oxynitride, bismuth oxide, silicon nitride,
silicon dioxide, or any multi-layer combinations of these materials may be
used. The overlying silicon gate layer may comprise, for example,
polysilicon; amorphous silicon; grain-size-enhanced,
grain-boundary-passivated or grain-aligned silicon; strained silicon;
Si.sub.x Ge.sub.1-x, substantially single crystal or single crystal
silicon, or combinations of these forms of silicon (various ones of these
forms of silicon being associated with improved carrier mobility and/or
reduced optical loss, as will be discussed below). Electrical connections
in the form of contacts to silicide regions are then made to each of the
doped gate and body regions. An optical signal to be modulated is coupled
into the relatively thin (doped) surface optical waveguide layer, and an
electrical modulating signal is applied to the electrical connections,
resulting in phase modulation of the optical signal as it exits the
waveguide layer.
It is an advantage of the present invention that the doping of the silicon
layers can be controlled to provide for lightly doped regions in the
active free carrier movement region and more heavily doped re
