Hybrid configurable circuit for a configurable IC Number:7,521,958 from the United States Patent and Trademark Office (PTO) owispatent

Title: Hybrid configurable circuit for a configurable IC

Abstract: Some embodiments of the invention provide a configurable integrated circuit ("IC"). This IC includes several configurable logic circuits for receiving configuration data and configurably performing a set of operations based on the configuration data. It also includes several hybrid circuits. Each particular hybrid circuit has: (1) a set of inputs, (2) a set of outputs for selectively connecting to the set of inputs, and (3) a set of select lines for receiving select signals that direct the hybrid circuit to connect the input set to the output set in a particular manner. At least one select signal is for controllably receiving configuration data and at least one select line is for controllably receiving signals generated by the configurable logic circuits.

Patent Number: 7,521,958 Issued on 04/21/2009 to Hutchings,   et al.

---

Inventors:	Hutchings; Brad (Fremont, CA), Schmit; Herman (Palo Alto, CA), Teig; Steven (Menlo Park, CA)
Assignee:	Tabula, Inc. (Santa Clara, CA)
Appl. No.:	11/739,095
Filed:	April 23, 2007

---

Related U.S. Patent Documents

---

	Application Number	Filing Date	Patent Number	Issue Date
	11082221	Mar., 2005	7224182

---

Current U.S. Class:	326/38 ; 326/41; 326/47
Current International Class:	G06F 7/38 (20060101); H03K 19/173 (20060101)
Field of Search:	326/37-41,47

---

References Cited [Referenced By]

---

U.S. Patent Documents

4873459	October 1989	El Gamal et al.
5245575	September 1993	Sasaki et al.
5349250	September 1994	New
5357153	October 1994	Chiang et al.
5365125	November 1994	Goetting et al.
5369622	November 1994	McLaury
5426378	June 1995	Ong
5521835	May 1996	Trimberger
5532958	July 1996	Jiang et al.
5552721	September 1996	Gould
5600263	February 1997	Trimberger et al.
5610829	March 1997	Trimberger
5629637	May 1997	Trimberger et al.
5631578	May 1997	Clinton et al.
5646544	July 1997	Iadanza
5646545	July 1997	Trimberger et al.
5659484	August 1997	Bennett et al.
5682107	October 1997	Tavana et al.
5692147	November 1997	Larsen et al.
5694057	December 1997	Gould
5701441	December 1997	Trimberger
5719889	February 1998	Iadanza
5732246	March 1998	Gould et al.
5737235	April 1998	Kean et al.
5745422	April 1998	Iadanza
5745734	April 1998	Craft et al.
5761483	June 1998	Trimberger
5764954	June 1998	Fuller et al.
5768178	June 1998	McLaury
5777360	July 1998	Rostoker et al.
5802003	September 1998	Iadanza et al.
5815726	September 1998	Cliff
5825662	October 1998	Trimberger
5889411	March 1999	Chaudhary
5914616	June 1999	Young et al.
5914906	June 1999	Iadanza et al.
5944813	August 1999	Trimberger
5973340	October 1999	Mohsen
5982655	November 1999	Doyle
6002991	December 1999	Conn, Jr. et al.
6023421	February 2000	Clinton et al.
6038192	March 2000	Clinton et al.
6044031	March 2000	Iadanza et al.
6054873	April 2000	Laramie
6069490	May 2000	Ochotta et al.
6075745	June 2000	Gould et al.
6078191	June 2000	Chan et al.
6084429	July 2000	Trimberger
6086631	July 2000	Chaudhary et al.
6091263	July 2000	New et al.
6091645	July 2000	Iadanza
6107821	August 2000	Kelem et al.
6110223	August 2000	Southgate et al.
6118707	September 2000	Gould et al.
6130854	October 2000	Gould et al.
6134154	October 2000	Iwaki et al.
6140839	October 2000	Kaviani et al.
6150838	November 2000	Wittig et al.
6163168	December 2000	Nguyen et al.
6173379	January 2001	Poplingher et al.
6175247	January 2001	Scalera et al.
6184707	February 2001	Norman et al.
6205076	March 2001	Wakayama
6233191	May 2001	Gould et al.
6255849	July 2001	Mohan
6275064	August 2001	Agrawal et al.
6292019	September 2001	New et al.
6326807	December 2001	Veenstra et al.
6346824	February 2002	New
6348813	February 2002	Agrawal et al.
6381732	April 2002	Burnham et al.
6462577	October 2002	Lee et al.
6469540	October 2002	Nakaya
6476634	November 2002	Bilski
6480954	November 2002	Trimberger
6487709	November 2002	Keller et al.
6490707	December 2002	Baxter
6496918	December 2002	Dehon et al.
6515509	February 2003	Baxter
6526559	February 2003	Schiefele et al.
6529040	March 2003	Carberry et al.
6545501	April 2003	Bailis et al.
6593771	July 2003	Bailis et al.
6601227	July 2003	Trimberger
6603330	August 2003	Snyder
6629308	September 2003	Baxter
6636070	October 2003	Altaf
6642744	November 2003	Or-Bach et al.
6667635	December 2003	Pi et al.
6668361	December 2003	Bailis et al.
6675309	January 2004	Baxter
6703861	March 2004	Ting
6714041	March 2004	Darling et al.
6732068	May 2004	Sample et al.
6806730	October 2004	Bailis et al.
6809979	October 2004	Tang
6829756	December 2004	Trimberger
6831479	December 2004	Lo
6838902	January 2005	Elftmann et al.
6870395	March 2005	Schadt et al.
6924663	August 2005	Masui et al.
6937535	August 2005	Ahn et al.
6956399	October 2005	Bauer
6991947	January 2006	Gheewala
6992505	January 2006	Zhou
6998872	February 2006	Chirania et al.
7028281	April 2006	Agrawal et al.
7038490	May 2006	Singh et al.
7075333	July 2006	Chaudhary et al.
7109752	September 2006	Schmit et al.
7126372	October 2006	Vadi et al.
7126856	October 2006	Sun et al.
7129746	October 2006	Balasubramanian et al.
7135886	November 2006	Schlacter
7138827	November 2006	Trimberger
7145361	December 2006	Rohe et al.
7212448	May 2007	Trimberger
7224182	May 2007	Hutchings et al.
7253660	August 2007	Leventis et al.
7298169	November 2007	Hutchings et al.
7307449	December 2007	Redgrave et al.
7310003	December 2007	Hutchings et al.
7358765	April 2008	Verma et al.
2001/0007428	July 2001	Young et al.
2002/0008541	January 2002	Young et al.
2002/0010853	January 2002	Trimberger et al.
2002/0113619	August 2002	Wong
2002/0125910	September 2002	New et al.
2002/0125914	September 2002	Kim
2002/0161568	October 2002	Sample et al.
2002/0163357	November 2002	Ting
2003/0009731	January 2003	Wallace
2003/0042931	March 2003	Ting
2003/0080777	May 2003	Baxter
2003/0110430	June 2003	Bailis et al.
2004/0010767	January 2004	Agrawal et al.
2004/0103265	May 2004	Smith
2004/0196066	October 2004	Ting
2004/0233758	November 2004	Kim et al.
2005/0146352	July 2005	Madurawe
2007/0075737	April 2007	Schmit et al.
2007/0143577	June 2007	Smith
2007/0241781	October 2007	Hutchings
2007/0257700	November 2007	Caldwell et al.
2008/0100336	May 2008	Hutchings et al.
2008/0129335	June 2008	Hutchings et al.
2008/0129337	June 2008	Redgrave, et al.

Other References

Trimberger, S., "Effects of FPGA Architecture on FPGA Routing," 32.sup.nd ACM/IEEE Design Automation Conference. Jun. 1995, ACM. cited by other . ".sctn.3 Programmable Logic Devices," Digital System Design, 2001 Month N/A, slides 3.1-3.28. cited by other . "Design for Low Power in Actel Antifuse FPGAs", Actel Application Note, 2000 Actel Corporation, Sep. 2000, pp. 1-8. cited by other . "The Effect of SRAM Table Sharing and Cluster Size on FPGA Area", NPL Date Unknown, pp. 1-10. cited by other . "The Xilinx Virtex Series FPGA," Jan. 22, 2001, slides 1-22. cited by other . "Unifying Sequential and Spatial Computing with a Single Instruction Set Architecture," ISCA '04, Jun. 19-23, 2004, ACM, Munchen, Oberbayern, Germany. cited by other . Agrawal, O., et al., "An Innovative, Segmented High Performance FPGA Family with Variable-Grain-Architecture and Wide-gating Functions," FPGA 99, Feb. 1999, pp. 17-26, ACM, Monterey, California, USA. cited by other . Ahmed, E., et al., "The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density," FPGA 2000, Feb. 2000, ACM, Monterey, California, USA. cited by other . Altera Corp., "6. DSP Blocks in Stratix II Devices," SII52006-1.0, Feb. 2004, pp. 1-32. cited by other . Altera, "Stratix II DSP Performance," White Paper, Feb. 2004, pp. 1-9, ver. 1.0, Altera Corporation, San Jose, California, USA. cited by other . Backus, J., "Can Programming be Liberated from the Von Neumann Style? A Functional Style and its Algebra of Programs," Communications of the ACM, Aug. 1978, pp. 613-641, vol. 21, No. 8, ACM. cited by other . Barker, R., "QuickSilver ACM SilverStream Design Methodology with the Inspire SDK Tool Set," A Technology Application Whitepaper, Jan. 26, 2004, pp. 1-8, QuickSilver Technology, Inc., San Jose, California, USA. cited by other . Brand, D., et al., "Minimization of AND-EXOR Expressions Using Rewrite Rules," IEEE Transactions on Computers, May 1993, pp. 568-576, IEEE. cited by other . Butts, M., "Future Directions of Dynamically Reprogrammable Systems," IEEE 1995 Custom Integrated Circuits Conference, May 1995, pp. 487-494, IEEE. cited by other . Camposano, R., "The Growing Semiconductor Zoo: ASICs, CSSP, ASSP, ASIP, Structured Arrays, FPGAs, Processor Arrays, Platforms . . . and Other Animalia," Aug. 29, 2003, pp. 1-74, Synopsys, Inc. cited by other . Caspi, E., et al., "A Streaming Multi-Threaded Model," MSP-3, Dec. 2, 2001, pp. 1-23. cited by other . Caspi, E., et al., "Stream Computations Organized for Reconfigurable Execution (SCORE): Introduction and Tutorial," Aug. 25, 2000, pp. 1-31, Version 1.0. cited by other . Ciemat, J.V., et al., "Annealing Placement by Thermodynamic Combinatorial Optimization," ACM Transcations on Design Automation of Electronic Systems, Jul. 2004, pp. 310-332, vol. 9, No. 3, ACM, New York, NY. cited by other . Compton, K., et al., "An Introduction to Reconfigurable Computing", IEEE Computer, Apr. 2000. cited by other . Compton, K., et al., "Reconfigurable Computing: A Survey of Systems and Software," ACM Computing Surveys, Jun. 2002, pp. 171-210, vol. 34, No. 2, ACM, New York, New York, USA. cited by other . Cong, J., et al., "A Theory on Partially-Dependent Functional Decomposition with Application in LUT-based FPGA," pp. 1-22. cited by other . Cong, J., et al., "Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays," ACM Transactions on Design Automation of Electronic Systems, Apr. 1996, pp. 145-204, vol. 1, No. 2, ACM, Inc. cited by other . Coudert, O., "Chapter 13: Doing Two-Level Logic Minimization 100 Times Faster," Proceedings of the 6.sup.th annual ACM-SIAM symposium on Discrete algorithms, Jan. 1995, pp. 112-121. cited by other . Damiani, M., et al., "The Disjunctive Decomposition of Logic Functions," Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, Nov. 1997, pp. 78-82, San Jose, California, USA. cited by other . Davare, A., et al., "The Best of Both Worlds: The Efficient Asynchronous Implementation of Synchronous Specifications," DAC '04, Jun. 7-11, 2004, ACM, San Diego, California, USA. cited by other . Dehon, A., "Balancing Interconnect and Computation in a Reconfigurable Computing Array (or, why don't you really want 100% LUT utilization)," Proceedings of the International Symposium on Field Programmable Gate Arrays, Feb. 1999, pp. 125-134. cited by other . Dehon, A., "DPGA Utilization and Application," Proceedings of the 1996 ACM Fourth International Symposium on Field-Programmable Gate Arrays FPGA, Feb. 11-13, 1996, Monterey, California, USA. cited by other . Dehon, A., "Dynamically Programmable Gate Arrays: A Step Toward Increased Computational Density," Proceedings of the Fourth Canadian Workshop on Field-Programmable Devices, May 1996, pp. 47-54. cited by other . Dehon, A., "Reconfigurable Architectures for General-Purpose Computing," A.I. Technical Report No. 1586, Oct. 1996, pp. i-353. cited by other . Dehon, A., "The Density Advantage of Configurable Computing," Apr. 2000, pp. 41-49, IEEE. cited by other . Dehon, A., "Transit Note #121: Notes on Programmable Interconnect," M.I.T. Transit Project, Feb. 1995, pp. 1-13. cited by other . Dehon, A., et al., "Design Patterns for Reconfigurable Computing," Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, Apr. 2004. cited by other . Dehon, A., et al., "DPGA-Coupled Microprocessors: Commodity ICs for the Early 21.sup.st Century," FCCM '94-IEEE Workshop on FPGAs for Custom Computing Machines, Apr. 1994, Napa Valley, California, USA. cited by other . Dehon, A., et al., "Reconfigurable Computing: What, Why, and Implications for Design Automation," DAC 1999, Jun. 1999, ACM, New Orleans, Louisiana. cited by other . Enzler, R., et al., "Virtualizing Hardware with Multi-Context Reconfigurable Arrays," Lecture Notes in Computer Science, Sep. 2003, pp. 151-160. cited by other . Gayasen, A., et al., "Reducing Leakage Energy in FPGAs Using Region-Constrained Placement," FPGA '04, Feb. 22-24, 2004, pp. 51-58, ACM, Monterey, California, USA. cited by other . George, V., "Low Energy Field-Programmable Gate Array," A Dissertation Submitted in Partial Satisfaction o the Requirements for the Degree of Doctor of Philosophy in Engineering-Electrical Engineering and Computer Sciences in the Graduate Division of the University of California, Berkeley, Fall 2000 Month N/A, pp. 1-190. cited by other . Giraud-Carrier, C., "A Reconfigurable Data Flow Machine for Implementing Functional Programming Languages," SIGPLAN Notices, Sep. 1994, vol. 29 (9): 22-28. cited by other . Goldstein, S.C., et al., "PipeRench: A Coprocessor for Streaming Multimedia Acceleration," International Symposium on Computer Architecture (ISCA), May 1999, pp. 28-39. cited by other . Goldstein, S.C., et al., "PipeRench: A Reconfigurable Architecture and Compiler," Apr. 2000, pp. 70-77, IEEE. cited by other . Hauck, S., et al., "Montage: An FPGA for Synchronous and Asynchronous Circuits," Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping, 1993 Month N/A, Springer-Verlag, Berlin. cited by other . Hauck, S., et al., "Totem: Domain-Specific Reconfigurable Logic," IEEE Transactions on VLSI Systems, 2006 Month N/A, pp. 1-25. cited by other . Heidari, G., et al., "Introducing a Paradigm Shift in the Design and Implementation of Wireless Devices," A Wireless Devices Whitepaper, Apr. 28, 2004 but .COPYRGT. 2003, pp. 1-10, QuickSilver Technology, Inc., San Jose, California, USA. cited by other . Hofstee, H.P., "Cell Broadband Engine Architecture from 20,000 Feet," Aug. 24, 2005, pp. 1-6. cited by other . Huang, A.S., "Tao: An Architecturally Balanced Reconfigurable Hardware Processor," Submitted to the Dept. of Electrical Engineering and Computer Science in Partial Fulfillment of the Requirements for the Degrees of Bachelor of Science in Electrical Science and Engineering and Master of Engineering in Electrical Engineering and Computer Science at the Massachusetts Institute of Technology, May 23, 1997, pp. 1-86, 107-109. cited by other . IBM, "Cell Broadband Engine Architecture, Version 1.0," Aug. 8, 2005, pp. 1-319, USA. cited by other . IBM, "SPU Application Binary Interface Specification, Version 1.3," CBEA JSRE Series, Aug. 1, 2005, pp. iv-26, USA. cited by other . IBM, "SPU Assembly Language Specification, Version 1.2," CBEA JSRE Series, Aug. 1, 2005, pp. iii-22, USA. cited by other . IBM, "SPU C/C++ Language Extensions, Version 2.0" CBEA JSRE Series, Aug. 1, 2005, pp. iv-84, USA. cited by other . IBM, "Synergistic Processor Unit Instruction Set Architecture, Version 1.0," Aug. 1, 2005, pp. 1-257, USA. cited by other . Kaviani, A., et al., "Computational Field Programmable Architecture," Custom Integrated Circuits Conference, Proceedings of the IEEE 1998, May 11-14, 1998. cited by other . Kaviani, A., et al., "Hybrid FPGA Architecture," Proceedings of the 1996 ACM Fourth International Symposium on Field-Programmable Gate Arrays, Feb. 11-13, 1996, pp. 3-9, Monterey, California, USA. cited by other . Keutzer, K., "Overview of *configurable* architectures," Feb. 28, 2002, slides 1-29. cited by other . Kocan, F., et al., "Logic Modules with Shared SRAM Tables for Field-Programmable Gate Arrays," FPL 2004, Aug./Sep. 2004, pp. 289-300, Springer-Verlag, Berlin Heidelberg. cited by other . Kravets, V.N, et al., "Generalized Symmetries in Boolean Functions," Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, Nov. 2000, San Jose, California, USA. cited by other . Lehn, D.I., et al., "Evaluation of Rapid Context Switching on a CSRC Device," Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, Jun. 24-27, 2002. cited by other . Lemieux, G., et al., "Generating Highly-Routable Sparse Crossbars for PLDs," FPGA 2000, Feb. 2000, ACM, Monterey, California, USA. cited by other . Lemieux, G., et al., "Using Sparse Crossbars within LUT Clusters," FPGA 2001, Feb. 11-13, 2001, ACM, Monterey, California, USA. cited by other . Lertora, F., et al., "Handling Different Computational Granularity by a Reconfigurable IC Featuring Embedded FPGAs and a Network-On-Chip," 13.sup.th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005) 2005, Apr. 18-20, 2005. cited by other . Lewis, D., et al., "The Stratix-II Routing and Logic Architecture," Proceedings of the 2005 ACM/SIGDA 13.sup.th International Symposium on Field-Programmable Gate Arrays, Feb. 20-22, 2005, pp. 1-22, Monterey, California, USA. cited by other . Ling, A., "The Search for the Optimal FPGA Logic Block," 2001 Month N/A, ACM. cited by other . M2000, "FlexEOS Embedded FPGA Cores," 2003 Month N/A, M2000. cited by other . Markovskiy, Y., et al., "Analysis of Quasi-Static Scheduling Techniques in a Virtualized Reconfigurable Machine," FPGA '02, Feb. 24-26, 2002, ACM, Monterey, California, USA. cited by other . Master, P., "The Next Big Leap in Reconfigurable Systems," A Technology Vision Whitepaper, Apr. 28, 2004 but .COPYRGT. 2003, pp. 1-8, QuickSilver Technology, Inc., San Jose, California, USA. cited by other . Mathstar, Inc., "MathStar FPOA Architecture: A New Approach to High Throughput, Scalable, and Reprogrammable Design," Technology Overview, 2003 Month N/A, MathStar, Inc. cited by other . Mirsky, E., et al., "Matrix: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources," Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, Apr. 1996. cited by other . Mirsky, E., et al., "Matrix: A Reconfigurable Computing Device with Configurable Instruction Distribution (Extended Abstract)," Hot Chips Symposium 1997, Aug. 1997. cited by other . Mishchenko, A., "Fast Computation of Symmetries in Boolean Functions," Computer-Aided Design of Integrated Circuits and Systems, Nov. 2003. cited by other . Mishchenko, A., et al., "A New Enhanced Constructive Decomposition and Mapping Algorithm," DAC 2003, Jun. 2-6, 2003, pp. 143-148, ACM, Anaheim, California, USA. cited by other . Morris, K., "Lattice Launches XP: Non-Volatility at the Forefront of FPGA," FPGA and Programmable Logic Journal, Mar. 1, 2005, pp. 1-5, Techfocus Media, Inc. cited by other . Morris, K., "Rationalizing Reconfigurability: The Importance of Being Programmable," FPGA and Structured ASIC Journal, Sep. 27, 2005. cited by other . Nelson, B.E., "Reconfigurable Computing: An Introduction and Overview," Sep. 23, 1998, pp. 1-43. cited by other . Niedzielski, D., "An Overview of Reconfigurable Computing," NPL Date Unknown. cited by other . Ochotta, E.S., et al., "A Novel Predictable Segmented FPGA Routing Architecture," FPGA 98, Feb. 1998, pp. 3-11, ACM, Monterey, California, USA. cited by other . Ohkura, J., et al., "Dataflow in the Adaptive Computing Machine (ACM)," A Technology Application Whiepaper, Apr. 28, 2004 but .COPYRGT. 2003, pp. 1-9, QuickSilver Technology, Inc., San Jose, California, USA. cited by other . Parhami, B., "Part IV: Low-Diameter Architectures," ECE 254B: Advanced Computer Architecture: Parallel Processing, UCSB, Spring 2005 Month N/A, slides 1-93, Behrooz Parhami, Santa Barbara, California, USA. cited by other . Pedram, M., "IEEE Circuits and Systems Society Distinguished Lecturer Program," NPL Date Unknown. cited by other . Perissakis, S., et al., "Embedded DRAM for a Reconfigurable Array," Proceedings of the 1999 Symposium on VLSI Circuits, Jun. 1999, slides 1-24. cited by other . Perissakis, S., et al., "Embedded DRAM for a Reconfigurable Array," Proceedings of the 1999 Symposium on VLSI Circuits, Jun. 1999. cited by other . Perkowski, M.A., "A New Representation of Strongly Unspecified Switching Functions and its Application to Multi-Level AND/OR/EXOR Synthesis," Proc. Of the 2.sup.nd Workshop on Applications of Reed-Muller Expansion in Circuit Design, Aug. 27-29, 1995, pp. 143-151, Chiba City, Japan. cited by other . Plunkett, B., "In Search of the SDR Holy Grail," A Technology Application Whitepaper, Apr. 28, 2004 but .COPYRGT. 2003, pp. 1-7, QuickSilver Technology, Inc., San Jose, California, USA. cited by other . Plunkett, B., et al., "Adapt2400 ACM Architecture Overview," A Technology Whitepaper, 2004 Month N/A, pp. 1-9, QuickSilver Technology, Inc. cited by other . Quicklogic Corp., "Ultra-Low Power FPGA Combining Performance, Density, and Embedded RAM," Eclipse II Family Data Sheet, Nov. 2005, pp. 1-92, QuickLogic Corporation, USA. cited by other . Quicksilver Technology, Inc., "Adapt2000 ACM System Platform,"0 Apr. 2004, pp. 1-39, QuickSilver Technology, Inc., San Jose, California, USA. cited by other . Quicksilver Technology, Inc., "InSpire SDK Tool Set," Product Brief, 2004 Month N/A, QuickSilver Technology, Inc., San Jose, California, USA. cited by other . Quicksilver Technology, Inc., "QS2412 Adaptive Computing Machine," Product Brief, 2004 Month N/A, QuickSilver Technology, Inc., San Jose, California, USA. cited by other . Rahman, A., et al., "Wiring Requirement and Three-Dimensional Integration Technology for Field Programmable Gate Arrays," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Feb. 2003, pp. 44-54, vol. 11, No. 1, IEEE. cited by other . Rose, J., "Hard vs. Soft: The Central Question of Pre-Fabricated Silicon," 34.sup.th International Symposium on Multiple-Valued Logic (ISMVL '04), May 2004, pp. 2-5. cited by other . Sambhwani, S., et al., "Implementing W-CDMA Transceiver Structure on an Adaptive Computing Platform," A Technology Application Whitepaper, Apr. 28, 2004 but .COPYRGT. 2003, pp. 1-12, QuickSilver Technology, Inc., San Jose, California, USA. cited by other . Scalera, S.M., et al., "A Mathematical Benefit Analysis of Context Switching Reconfigurable Computing," Proceedings of the 5.sup.th Reconfigurable Architectures Workshop (RAW), Mar. 30, 1998, vol. 1388 of Lecture Notes in Computer Science, pp. 73-78. cited by other . Schaumont,P., et al., "A Quick Safari Through the Reconfiguration Jungle," 38.sup.th Design Automation Conference, Jun. 2001, pp. 172-177, Las Vegas, Nevada, USA. cited by other . Schmit, H., "Extra-Dimensional Island-Style FPGAs," Field Programmable Logic and Application (FPL 2003), Sep. 2003, pp. 406-415. cited by other . Schmit, H., "Extra-dimensional Island-Style FPGAs," Field Programmable Logic and Application (FPL 2003), Sep. 2003, slides 1-26. cited by other . Schmit, H., "Incremental Reconfiguration for Pipelined Applications," Proceedings of the 5.sup.th IEEE Symposium on FPGA-Based Custom Computing Machines, Apr. 16-18, 1997. cited by other . Schmit, H., et al., "FPGA Switch Block Layout and Evaluation," FPGA '02, Feb. 24-26, 2002, ACM, Monterey, California, USA. cited by other . Schmit, H., et al., "PipRench: A Virtualized Programmable Datapath in 0.18 Micron Technology," Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, May 12-15, 2002, pp. 63-66. cited by other . Schmit, H., et al., "Queue Machines: Hardware Compilation in Hardware," Proceedings of the 10.sup.th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, Apr. 22-24, 2002. cited by other . Scholl, C., "Multi-output Functional Decomposition with Exploitation of Don't Cares," May 19-21, 1997. cited by other . Sharma, A., et al., "Accelerating FPGA Routing Using Architecture-Adaptive A* Techniques," Proceedings of the IEEE Conference on Field-Programmable Technology 2005, Dec. 11-14, 2005. cited by other . Singh, A., et al., "Interconnect Pipelining in a Throughput-Intensive FPGA Architecture," FPGA 2001, Feb. 11-13, 2001, pp. 153-160, ACM, Monterey, California, USA. cited by other . Singh, A., et al., "PITIA: An FPGA for Throughput-Intensive Applications," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Jun. 2003, pp. 354-363, vol. 11, No. 3, IEEE. cited by other . Slade, A.L., et al., "Reconfigurable Computing Application Frameworks," 11.sup.th Annual IEEE Symposium on Field-Programmable Custom Computer Machines, Apr. 9-11, 2003. cited by other . Snider, G., "Performance-Constrained Pipelining of Software Loops onto Reconfigurable Hardware," FPGA '02, Feb. 24-26, 2002, pp. 177-186, ACM, Monterey, California, USA. cited by other . Stankovic, R.S., et al., "Remarks on the Number of Logic Networks with Same Complexity Derived from Spectral Transform Decision Diagrams," Proceedings Int. TICS Workshop on Spectral Methods and Multi-Rate Signal Processing, SMMSP '02, Sep. 7-8, 2002, pp. 163-170, Toulouse, France. cited by other . Tau, E., et al., "A First Generation DPGA Implementation," Proceedings of the Third Canadian Workshop on Field-Programmable Devices, May 1995, pp. 138-143. cited by other . Tau, E., et al., "Transit Note #114: A First Generation DPGA Implementation," M.I.T. Transit Project, Jan. 1995, pp. 1-8. cited by other . Teifel, J., et al., "Highly Pipelined Asynchronous FPGAs," Proceedings of the 2004 ACM/SIGDA 12.sup.th International Symposium on Field Programmable Gate Arrays, Feb. 22-24, 2004, ACM, Monterey, California, USA. cited by other . Tessier, R., et al., "Balancing Logic Utilization and Area Efficiency in FPGAs," Proceedings of the Roadmap to Reconfigurable Computing, 10.sup.th International Workshop on Field Programmable Logic and Applications, Aug. 27-30, 2000, pp. 535-544. cited by other . Tom, M., et al., "Clustering of Large Designs for Channel-Width Constrained FPGAs," Univsersity of British Columbia, Department of Electrical and Computer Engineering, Jun. 2005, slides 1-39, Vancouver, British Columbia, Canada. cited by other . Tom, M., et al., "Logic Block Clustering of Large Designs for Channel-Width Constrained FPGAs," DAC 2005, Jun. 13-17, 2005, pp. 726-731, ACM, Anaheim, California, USA. cited by other . Tsu, W., et al., "HSRA: High-Speed, Hierarchical Synchronous Reconfigurable Array," Proceedings of the International Symposium on Field Programmable Gate Arrays, Feb. 1999, pp. 69-78. cited by other . Wawrzynek, J., "EECS150-Digital Design: Lecture 5--Field Programmable Gate Arrays (FPGAs)," Feb. 4, 2002, slides 1-20. cited by other . Weaver, N., et al., "The SFRA: A Corner-Turn FPGA Architecture," FPGA '04, Feb. 22-24, 2004, ACM, Monterey, California, USA. cited by other . Wegener, I., "The Complexity of Boolean Functions," Wiley-Teubner Series in Computer Science, 1987, John Wiley & Sons Ltd. and B.G. Teubner, Stuttgart, New York. (Month N/A). cited by other . Wilton, S.J.E., "Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays," FPGA 97, Feb. 1997, pp. 10-16, ACM, Monterey, California, USA. cited by other . Xilinx, Inc., "Virtex-4 Family Overview," Advance Product Specification, Sep. 10, 2004, pp. 21-30, v1.1, Xilinx, Inc. cited by other . Zilic, Z. et al., "Using BDDs to Design ULMs for FPGAs," Proceedings of the 1996 ACM Fourth International Symposium on Field-Programmable Gate Arrays (FPGA '96), Feb. 11-13, 1996, pp. 1-10, Monterey, California, USA. cited by other . Zuchowski, P.S., "A Hybrid ASIC and FPGA Architecture," 2002 Month N/A, IEEE. cited by other . Final Office Action of U.S. Appl. No. 11/269,141, mailed Jul. 14, 2008, Caldwell, Andrew, et al. cited by other . U.S. Appl. No. 12/058,662, filed Mar. 28, 2008, Caldwell, Andrew, et al. cited by other . Final Office Action of U.S. Appl. No. 11/081,850, mailed May 28, 2008, Hutchings, Brad, et al. cited by other . Non-Final Office Action of U.S. Appl. No. 11/933,311, mailed Jul. 1, 2008, Redgrave, Jason, et al. cited by other . U.S. Appl. No. 11/371,198, filed Mar. 8, 2006, Schmit, Herman, et al. cited by other . Final Office Action of U.S. Appl. No. 11/371,198, mailed Apr. 29, 2008, Schmit, Herman, et al. cited by other . Non-Final Office Action of U.S. Appl. No. 11/371,198, mailed Jul. 18, 2007, Schmit, Herman, et al. cited by other . U.S. Appl. No. 11/926,100, filed Oct. 28, 2007, Hutchings, et al. cited by other . U.S. Appl. No. 11/933,311, filed Oct. 31, 2007, Redgrave, et al. cited by other . U.S. Appl. No. 11/942,691, filed Nov. 19, 2007, Hutchings, et al. cited by other . Notice of Allowance of U.S. Appl. No. 11/269,168, mailed Aug. 2, 2007, Redgrave, et al. cited by other . Non-Final Office Action of U.S. Appl. No. 11/269,168, mailed Mar. 30, 2007, Redgrave, et al. cited by other . Non-Final Office Action of U.S. Appl. No. 11/081,850, mailed Sep. 10, 2007, Hutchings. cited by other . Notice of Allowance of U.S. Appl. No. 11/082,199, mailed Jul. 31, 2007, Hutchings, et al. cited by other . Non-Final Office Action of U.S. Appl. No. 11/082,199, mailed Mar. 21, 2007, Hutchings, et al. cited by other . Non-Final Office Action of U.S. Appl. No. 11/082,199, mailed Nov. 21, 2006, Hutchings, et al. cited by other . Non-Final Office Action of U.S. Appl. No. 11/269,141, mailed Nov. 20, 2007, Caldwell, et al. cited by other . Notice of Allowance of U.S. Appl. No. 11/081,883, mailed Jul. 9, 2007, Hutchings, et al. cited by other . Non-Final Office Action of U.S. Appl. No. 11/081,883, mailed Mar. 13, 2007, Hutchings, et al. cited by other . Non-Final Office Action of U.S. Appl. No. 11/081,883, mailed Nov. 3, 2006, Hutchings, et al. cited by other . Notice of Allowance of U.S. Appl. No. 11/082,221, mailed Jan. 16, 2007, Hutchi

Free Web Sudoku Puzzles. Solve with your browser.       3     8         6   9     2   5       7   3       9       7   3     4   8 5 6   1     2   9       7       3   6       1   7     1   4         4     3       What is it?