Title: Hybrid electrical circuit method with mated substrate carrier method
Abstract: A hybrid integrated circuit fabrication method in which an insulating substrate member and its metallic substrate carrier are made to be mating with precision through use of computer controlled machining performed on each member. A combination of disclosed specifically tailored software and commercially available software are used in the method to generate code for controlling a precision milling machine during the fabrication of substrate and substrate carrier members. The method for precision mating of substrate and substrate carrier enable disposition of a precision recess in the substrate carrier and the location of recess pillars and pedestals (the latter being for integrated circuit die mounting use) at any carrier recess location desirable for electrical, thermal or physical strength reasons. Enhanced electrical thermal and physical properties are achieved in hybrid devices fabricated according to the method especially when compared with devices and methods having the limited availability of comparable elements afforded by previous hybrid fabrication arrangements.
Patent Number: 6,971,160 Issued on 12/06/2005 to Welch, et al.
| Inventors:
|
Welch; Ryan J. (Bellbrook, OH);
Quach; Tony K. (Lebanon, OH)
|
| Assignee:
|
The United States of America as represented by the Secretary of the Air Force (Washington, DC)
|
| Appl. No.:
|
034769 |
| Filed:
|
January 3, 2002 |
| Current U.S. Class: |
29/832; 29/846; 29/847; 29/852; 29/833; 29/834; 29/740; 257/315; 257/316; 438/201 |
| Intern'l Class: |
H01K 003/30 |
| Field of Search: |
29/840-842,832,825,827,592,854
174/524
228/107
257/676,666,315
361/811
700/2,97
438/201,211
|
References Cited [Referenced By]
U.S. Patent Documents
| 3848078 | Nov., 1974 | Guillot, Jr.
| |
| 4547755 | Oct., 1985 | Roberts.
| |
| 4951014 | Aug., 1990 | Wohlert et al.
| |
| 5023994 | Jun., 1991 | Bujatti et al.
| |
| 5291372 | Mar., 1994 | Matsumoto.
| |
| 5638599 | Jun., 1997 | Beratan et al.
| |
| 5783857 | Jul., 1998 | Ziegner et al.
| |
| 6049977 | Apr., 2000 | Atkins et al.
| |
| 6131277 | Oct., 2000 | Cadenhead et al.
| |
| 6137163 | Oct., 2000 | Kim et al.
| |
| 6807727 | Oct., 2004 | Bolotin.
| |
| 2002/0050611 | May., 2002 | Yitzchaik et al.
| |
Primary Examiner: Trinh; Minh
Attorney, Agent or Firm: AFMCLO/JAZ, Hollins; Gerald B.
Goverment Interests
RIGHTS OF THE GOVERNMENT
The invention described herein may be manufactured and used by or for the Government
of the United States for all governmental purposes without the payment of any royalty.
Claims
1. Computer aided, low grounding impedance and efficient-cooling method of disposing
a substrate-received hybrid electronic circuit device on a device-supporting metallic
carrier member, said method comprising the steps of:
segregating a selected length of metallic carrier member stock from an extended
length of said stock;
defining in computer code an array of milling machine cutter paths extending
across an upper surface of said selected length of metallic carrier member stock,
from an open end of a carrier recess well to be milled in said metallic carrier
member upper surface;
said defining in computer code the array of milling machine cutter paths including
a plurality of milling machine cutter operation-free upstanding metallic carrier
member pillar regions selectively disposed across a bottom surface of said recess
well in response to pillar region-defining coding in said computer code;
machining said recess well, with recess well remainder areas comprising said
upstanding pillar regions, into said metallic carrier member stock using lateral
movements of said milling machine cutter controlled by said computer code;
fabricating a carrier recess well-conforming, conductor-clad, electrically insulating,
hybrid electrical circuit device substrate member from a blank of said substrate
member stock using a milling machine also controlled by the computer code;
said fabricated hybrid electrical circuit device substrate member including substrate-piercing
hole members disposed therein in clad conductor locations registered with said
metallic carrier member pillar regions; and
attaching said hybrid electrical circuit device substrate member to said metallic
carrier member within said carrier recess well using heat responsive electrically
conductive attachment material;
said attaching step including forming attachment material bonds between said
clad conductor and said upstanding metallic carrier member pillar regions at said
substrate-piercing hole members.
2. The computer aided, low grounding impedance and efficient-cooling method of
disposing a substrate-received hybrid electronic circuit device on a device-supporting
metallic carrier member of claim 1 wherein said step of machining said recess well
includes milling machine cutter lateral cutting engagement with said metallic carrier
member stock.
3. The computer aided, low grounding impedance and efficient-cooling method of
disposing a substrate-received hybrid electronic circuit device on a device-supporting
metallic carrier member of claim 1 wherein said milling machine cutter control
computer code includes a special case algorithm supporting cutter machining in
pillar separation spaces smaller than a nominal cutter diameter.
4. The computer aided, low grounding impedance and efficient-cooling method of
disposing a substrate-received hybrid electronic circuit device on a device-supporting
metallic carrier member of claim 1 wherein said step of fabricating a carrier recess
well-conforming, conductor-clad, electrically insulating, hybrid electrical circuit
device substrate member from a blank of said substrate member stock includes milling
machine cutter operation on a substrate member upper surface conductor comprising
a microwave electronic circuit and milling machine cutter operation through a lower
ground plane conductor.
5. The computer aided, low grounding impedance and efficient-cooling method of
disposing a substrate-received hybrid electronic circuit device on a device-supporting
metallic carrier member of claim 1 wherein said fabricated hybrid electrical circuit
device substrate member further includes additional substrate-piercing hole members
disposed in clad conductor locations non registered with said metallic carrier
member pillar regions.
6. The computer aided, low grounding impedance and efficient-cooling method of
disposing a substrate-received hybrid electronic circuit device on a device-supporting
metallic carrier member of claim 1 wherein said step of defining in computer code
an array of milling machine cutter paths extending across an upper surface of said
selected length of metallic carrier member stock, from an open end of a carrier
recess well to be milled in said metallic carrier member upper surface includes
defining a sequence of orthogonally disposed milling machine cutter movement paths.
7. The computer aided, low grounding impedance and efficient-cooling method of
disposing a substrate-received hybrid electronic circuit device on a device-supporting
metallic carrier member of claim 1 wherein said step of defining in computer code
an array of milling machine cutter paths extending across an upper surface of said
selected length of metallic carrier member stock, from an open end of a carrier
recess well to be milled in said metallic carrier member upper surface, includes
defining in computer code a pedestal member region larger in physical size than
said carrier member pillar regions.
8. The computer aided, low grounding impedance and efficient-cooling method of
disposing a substrate-received hybrid electronic circuit device on a device-supporting
metallic carrier member of claim 1 wherein said step of machining includes cutting
a substrate-receiving recess in said supporting metallic carrier member using a
computer algorithm guided milling machine cutter bit.
9. The computer aided, low grounding impedance and efficient-cooling method of
disposing a substrate-received hybrid electronic circuit device on a device-supporting
metallic carrier member of claim 1 wherein:
said step of fabricating a hybrid electrical circuit device substrate member
includes disposing a plurality of thickness-traversing apertures in precisely defined,
lateral locations of said substrate member and disposing a shaped additional larger
aperture in a precisely defined, lateral location of said substrate member; and
said machining step also includes leaving an upstanding carrier metal-comprised
pillar member, disposed in registration with said shaped additional larger substrate
member aperture, on a floor portion of said metallic carrier member; and further
including the step of
locating an electronic circuit die member on an upper surface of said upstanding
carrier member metal-comprised pillar member within said substrate shaped additional
larger aperture.
10. The computer aided, low grounding impedance and efficient-cooling method
of disposing a substrate-received hybrid electronic circuit device on a device-supporting
metallic carrier member of claim 1 further including the step of connecting circuit
nodes of said pillar-mounted electronic circuit die member with circuit nodes of
said substrate-received hybrid electrical circuit device substrate member using
bond wire jumper conductors.
11. The computer aided, low grounding impedance and efficient-cooling method
of disposing a substrate-received hybrid electronic circuit device on a device-supporting
metallic carrier member of claim 1 wherein said attaching step forming of attachment
material bonds between said clad conductor and said upstanding metallic carrier
member pillar regions at said substrate-piercing hole members includes use of one
of a conductive epoxy adhesive material, indium solder material and tin-lead solder material.
12. The computer aided, low grounding impedance and efficient-cooling method
of disposing a substrate-received hybrid electronic circuit device on a device-supporting
metallic carrier member of claim 1 wherein said pillar region-defining coding in
said computer code and said defining step computer code are located in a same computer
code file.
13. The computer aided, low grounding impedance and efficient-cooling method
of disposing a substrate-received hybrid electronic circuit device on a device-supporting
metallic carrier member of claim 1 wherein said fabricating step conductor-cladding
includes a ground plane element conductor having a computer code determined metallic
carrier member pillar region receiving aperture disposed therein.
Description
BACKGROUND OF THE INVENTION
In the development of radio frequency circuits and especially microwave radio
frequency circuits two different approaches to experimental or work in progress
circuit implementation are often used. These approaches are the monolithic microwave
integrated circuit (MMIC) and the hybrid integrated circuit. The MMIC process consists
here of an entire circuit including active and passive elements being fabricated
on a part of a wafer of semiconductor material. In the hybrid approach, the active
element(s) is/are fabricated on a semiconductor material wafer and the remaining
portions of the circuit are fabricated on a dielectric substrate. The individual
parts are then assembled on a solid metal carrier that holds the circuit together
mechanically. The carrier also provides a common ground plane and acts as a thermal
heat sink.
The MMIC has the advantage of being very small, accurate, and repeatable and
is indeed the ultimate goal of many circuit development efforts. Some disadvantages
of the MMIC technique are however the large investment in time and other resources
needed for each new iteration of a design, the imposed small circuit size (which
limits the electrical size of the passive elements and types of circuit elements
that are realizable), a minimum tuning capability, and a wasting of active semiconductor
material to make passive components. The hybrid circuit offers advantages with
respect to design flexibility as a result of its larger size, increased range of
tuning to meet specifications, and the avoidance of costly device material waste
on passive component realization. Hybrid circuits suffer from being considerably
larger in physical size, and more importantly have limited accuracy and repeatability
characteristics. These inaccuracies stem from an assembly process not having the
tight tolerances of semiconductor fabrication technology. Notwithstanding these
difficulties however the hybrid integrated circuit remains a necessary part of
the development cycle for many circuits and indeed the final configuration of many
circuit designs particularly in the radio frequency and microwave integrated circuit arts.
It is perhaps worth mention in this background discussion that a radio frequency
signal processing circuit and particularly a transmitter circuit intended for use
in the microwave range of radio frequencies is, in one of its most technically
challenging portions, (i.e., the signal output stage) a power handling circuit,
i.e., a circuit capable of generating a specified number of watts of output signal
power from a lesser number of watts of input signal power while functioning at
an elevated operating frequency. The need for significant output power levels and
the absence of high power handling efficiency in such circuits, especially when
some form of linear or "class A" circuit operation rather than the more energy
efficient "class C" operation is dictated, results in a need for such circuits
to have significant power dissipating capability, dissipation without exceeding
the operating temperatures acceptable for semiconductor device operation. This
power dissipating need usually precludes the mounting of a radio frequency circuit
die directly on a ceramic substrate member in a hybrid integrated circuit arrangement
for example and requires that an efficient and direct thermal energy circuit be
established between the dissipating semiconductor device and some metallic heat
sink such as the substrate carrier of the present invention. It is this needed
heat dissipating capability which dictates disposition of the radio frequency circuit
die in the present invention within an aperture of the substrate member and into
direct metallic connection with a chip carrier recess-received pedestal member.
In this disposition of the radio frequency circuit die, bond wires may be used
to advantage in making connections between the substrate conductor nodes and the
circuit die connection pads.
Considering now a related but somewhat different aspect of a hybrid integrated
circuit device, circuit designers typically attempt to minimize the length of the
bond wires used within an integrated circuit package to for example connect a circuit
die to external package pins. This minimizing limits a frequent source of circuit
variability and is usually accomplished through use of one or more of three techniques.
A first of these techniques involves use of a very thin dielectric material substrate
to fabricate the circuit pattern. A typical active device measures four mils in
thickness for example and the dielectric materials typically range from 8 mils
to 30 mils in thickness for microwave operation. If the designer uses a thin dielectric
material (of say 10 mils thickness), the active device can be mounted on a flat
carrier and the bond wires will stretch 6 mils from the top of the active device
up to the surface of the dielectric material. This arrangement is shown in FIG.
26A and FIG. 26B of the drawings herein where cross sectional and top views appear.
FIG. 26A is enlarged and FIG. 26B is of approximately real device size in these
drawings. The layer of for example tin/lead solder used to attach the substrate
to the substrate carrier in the FIG. 26A drawing and also in the present invention
hybrid devices is identified at 2600 in FIG. 26.
In the FIG. 26A and FIG. 26B drawings the carrier is simple to design and fabricate.
However, the thinner dielectric material in the substrate limits the networks a
designer can realize on the dielectric material surface. With such thin dielectric
material for example the fabrication rules usually impose a fixed minimum line
width. Thinner dielectric materials in a substrate require smaller line widths
to get the same characteristic impedance as is usually achieved with thicker dielectrics.
Thus, a thinner dielectric will not realize the high impedance characteristics
of a thicker dielectric material.
Thin substrates have additional drawbacks in a hole milling process. In addition
to inherent fragility the milling bit must extend some distance into the dielectric
material during a substrate milling operation in order to ensure all the surface
metal is removed and obtain a clean cut for via hole or other use. With a thin
dielectric material, the amount of removed dielectric material becomes a significant
percent of the total thickness and can thereby cause objectionable inaccuracies
in the circuit modeling. Modeling assumes a constant substrate thickness however
machining removes some substrate and thereby can reduce the modeling accuracy.
This effect is minimized when thicker substrates are used.
The second bond wire limiting technique is to build a ridge of metal called a
"pedestal" on the carrier. Typically the pedestal is made to place the top surface
of the active device at the level of the dielectric material top surface so the
bond wire length for the device connection is minimized. The pedestal height may
be varied to allow thicker device or substrate materials thus eliminating the drawbacks
of thin dielectric materials. This technique is shown in the drawings of FIG. 27A
and FIG. 27B where the pedestal resides between two substrate members that are
joined by bond wires comprising for example active device connections. This technique
however poses severe limitations on a device designer since the FIG. 27A and FIG.
27B configuration has the effect of physically separating circuit blocks in the
lateral direction by the presence of an active device. As a result of this separation
any feedback arrangement in the circuit will necessarily include a bond wire connection
between circuit blocks and this is not desirable from both circuit characteristics
tolerance and fabrication cost viewpoints. Having pedestal-separated hybrid device
pieces also makes the packaging more difficult and less repeatable. The pedestal
disposition arrangement therefore minimizes the length of the bond wires to the
active device but can introduce longer bond wires in other locations such as feedback
paths. Moreover if the circuit needs a short circuit between a surface conductor
and the carrier at any location, a bond wire is still needed and its length is
the height of the substrate dielectric material.
The third bond wire limiting technique uses filled via-holes for connecting both
active and passive components. Various methods have been reported for the filled
via-hole process depending on the substrate being used. If an alumina substrate
is used, the filled via-hole process may employ the technique of Bujatti and Sechii
as disclosed in U.S. Pat. No. 5,023,994. This technique however requires fabrication
temperatures in excess of 250 degree Celsius and is therefore limiting with respect
to substrate materials and device materials for examples. The filled via-hole arrangement
is shown in FIG. 28A and FIG. 28B of the drawings. Conventional methodologies for
both of these types of substrates therefore require added processing steps along
with chemical usage to fill the via-holes. These added steps dramatically increase
the cost and cycle time to build a hybrid microwave circuit and are therefore believed
to be less desirable than the bond wire limiting achieved with the present invention.
To summarize these paragraphs of background it may be appreciated that heretofore
there has not been available to the hybrid circuit designer an arrangement in which
combined electrical grounding, heat sinking capability and substrate physical support
can be made available at randomly selected locations over the extent of the substrate
in a hybrid integrated circuit device. The filled via hole process has been considered
for this role but has been less than desirable in that it is difficult to fabricate
satisfactorily and has other disadvantages. Additionally the etching processes
which may be applied to a substrate and its mating carrier do not result in interfitted
elements of desirably precise geometry and small tolerance relationships. It has
moreover been difficult to provide part-machining capability of both the accuracy
and human interface convenience needed for integrated circuit-compatible hybrid
circuit fabrications seeking to avoid the filled via hole and the etching accomplished
hybrid device fabrication techniques. The present invention is believed to answer
these needs.
SUMMARY OF THE INVENTION
The present invention provides a combined hybrid integrated circuit and mating
substrate carrier in which desirable low ground plane electrical impedance, favorable
structural integrity and effective thermal energy conduction are achieved. The
invention is seen as an improvement to the filled via hole technique often used
in radio frequency integrated circuit devices.
It is therefore an object of the present invention to provide a hybrid integrated
circuit and carrier combination of improved electrical, physical and thermal characteristics.
It is another object of the invention to provide a hybrid electronic circuit
and
mating substrate carrier combination that is useful for radio frequency, digital,
audio and other classes of electronic circuits.
It is another object of the invention to provide a hybrid integrated circuit
and
carrier combination that is improved in characteristics and manufacturability with
respect to the filled via hole hybrid integrated circuit arrangement.
It is another object of the invention to provide a hybrid integrated circuit
and
carrier combination in which the benefits of a custom fabricated substrate carrier
are realized.
It is another object of the invention to provide a hybrid integrated circuit
and
carrier combination in which the benefits of a machined custom substrate carrier
are realized.
It is another object of the invention to provide a hybrid integrated circuit
and
carrier combination in which the benefits of an automated numerically controlled
machined custom substrate carrier are realized.
It is another object of the invention to provide a hybrid integrated circuit
and
carrier combination in which the benefits of a multiple point electrical, structural
and thermal supplementing of a substrate ground plane element by a substrate carrier
element are achieved.
It is another object of the invention to provide a hybrid integrated circuit
and
carrier combination in which need for chemically etched via holes is reduced or avoided.
It is another object of the invention to provide a hybrid integrated circuit
and
carrier combination in which a substrate electrical ground plane disposed in multiple
physical planes can be accommodated by the mating substrate carrier element.
It is another object of the invention to provide a hybrid integrated circuit
and
carrier combination in which the need for bonding wires is reduced or eliminated.
It is another object of the invention to provide a hybrid integrated circuit
and
carrier combination in which the benefits of a plurality of metallic mechanical
connections between a hybrid integrated circuit substrate and its mated substrate
carrier element are achieved.
It is another object of the invention to provide a hybrid integrated circuit
and
carrier combination capable of providing both the small pillar and the larger pedestal
type of grounded element connections with a substrate element and with an integrated
circuit element.
It is another object of the invention to combine the capabilities of commercially
available precision machining software with the characteristics of custom software
to achieve an improved microwave hybrid circuit device while circumventing a number
of fabrication limitations.
These and other objects of the invention will become apparent as the description
of the representative embodiments proceeds.
These and other objects of the invention are achieved by the low electrical
impedance thermally efficient method of mounting a substrate-received hybrid electronic
circuit device in a device-supporting metallic carrier member, said method comprising
the steps of:
- disposing a plurality of thickness-traversing apertures in precisely
defined, circuit trace and ground plane conductor-inclusive, lateral locations
of said hybrid circuit device substrate;
- forming a substrate-receiving recess in said device-supporting metallic
carrier member;
- said forming step including leaving a plurality of upstanding chip carrier
metal-comprised pillar members disposed in selected precise lateral locations across
a floor portion of said metallic carrier member substrate-receiving recess;
- each said upstanding device carrier metal-comprised pillar member being
disposed in a recess location laterally registered with one of said substrate thickness-traversing apertures;
- each said upstanding device carrier metal-comprised pillar member including
an upstanding portion entering one of said substrate thickness-traversing apertures
and extending through said ground plane conductor elements and said substrate circuit
trace in an assembled-device condition;
- joining each said upstanding device carrier metal-comprised pillar member
with surrounding portions of said substrate circuit trace and said ground plane
conductor elements using a thermally responsive conductive media.
BRIEF DESCRIPTION OF THE DRAWING
The accompanying drawings incorporated in and forming a part of the specification,
illustrate several aspects of the present invention and together with the description
serve to explain the principles of the invention. In the drawings:
FIG. 1A represents a top view of a milling machine usable in fabricating a substrate
carrier according to the present invention.
FIG. 1B represents a front, motor-up, view of a milling machine usable in fabricating
a substrate carrier according to the present invention.
FIG. 1C shows a side, motor-up, view of a milling machine usable in fabricating
a substrate carrier according to the present invention.
FIG. 1D shows a side, motor-down, view of a milling machine usable in fabricating
a substrate carrier according to the present invention.
FIG. 2A shows a bottom view of a milling machine and depth limiter usable in
fabricating a substrate carrier according to the present invention.
FIG. 2B shows a side view of an in-position milling machine and depth limiter
usable in fabricating a substrate carrier according to the present invention.
FIG. 3 shows a top view of starting chip carrier stock and a directional convention
used in the present document.
FIG. 4 shows an exemplary substrate carrier with removable and remaining metal areas.
FIG. 5 shows the FIG. 4 exemplary substrate carrier with smaller milling areas defined.
FIG. 6A shows a box used to define insulation paths (i.e., milling machine cutter
paths) and path orientation to a substrate carrier.
FIG. 6B shows an overall movement path for a milling machine cutter or bit in
the box of FIG. 6A.
FIG. 6C shows a first movement path for a milling machine cutter or bit and
a representative cutter bit width.
FIG. 6D shows a second movement path for the FIG. 6C milling machine bit.
FIG. 6E shows a third movement path for the FIG. 6C milling machine bit.
FIG. 6F shows the total milled area once the FIG. 6B milling is completed.
FIG. 7 shows a substrate carrier with a first set of boxes defined.
FIG. 8A shows a substrate carrier with a second set of boxes defined.
FIG. 8B shows a substrate carrier with total boxes defined thus far.
FIG. 9A shows a substrate carrier with a third set of boxes defined.
FIG. 9B shows a substrate carrier with horizontal boxes on y edges.
FIG. 10A shows an original substrate carrier having no pillars or pedestals.
FIG. 10B shows the FIG. 10A carrier with outline boxes defined.
FIG. 10C shows the FIG. 10A carrier with final boxes defined.
FIG. 10D shows the FIG. 10A carrier with all boxes defined.
FIG. 11 shows carrier boxes and data structures at a sweep beginning along with
important feature locations.
FIG. 12A shows carrier and data structures at a first stop along a carrier sweep.
FIG. 12B shows the completed one box and two in progress at this point in the processing.
FIG. 13A shows carrier and data structures at a second stop of the FIG. 12A structure.
FIG. 13B shows the three boxes completed and one in process at this point in
the FIG. 12A processing.
FIG. 14A shows carrier and data structures at the end of carrier sweep of the
FIG. 12A structure.
FIG. 14B shows four boxes completed and none in process at the end of the FIG.
12A processing.
FIG. 15 shows a special spacing case when creating boxes.
FIG. 16A shows a special spacing situation original layout.
FIG. 16B shows a special spacing situation error situation.
FIG. 17 shows a sweep beginning for a special spacing case.
FIG. 18A shows new box carrier and data structures stopped at a first pillar
starting edge in a special situation case.
FIG. 18B shows all completed box structures in the FIG. 18A case.
FIG. 19A shows carrier and data structures stopped at a first pillar stopping
edge after closure of a box above the pillar.
FIG. 19B shows a thus-far completed representation of the FIG. 12A through FIG.
19B special spacing situation.
FIG. 20A shows carrier and data structures stopped at a first pillar stopping
edge after closure of a box below the pillar.
FIG. 20B shows a thus-far completed representation of the FIG. 12A through FIG.
20B special spacing situation.
FIG. 21A shows carrier and data structures stopped at a first pillar stopping
edge after this edge has been fully processed.
FIG. 21B shows a thus-far completed representation of the FIG. 12A through FIG.
21B special spacing situation; four boxes completed and none open.
FIG. 22A shows carrier and data structures stopped at a second pillar starting
edge after this edge has been fully processed.
FIG. 22B shows a thus-far completed representation of the FIG. 12A through FIG.
22B special spacing situation; four boxes completed and two open.
FIG. 23A shows carrier and data structures when stopped at a second pillar stopping
edge after one box has been closed.
FIG. 23B shows a thus-far completed representation of the FIG. 12A through FIG.
23B special spacing situation; five boxes completed and one open.
FIG. 24A shows carrier and data structures when stopped at a second pillar stopping
edge after the second box has been closed.
FIG. 24B shows a thus-far completed representation of the FIG. 12A through FIG.
24B special spacing situation; six boxes completed and none open.
FIG. 25A shows carrier and data structures stopped at a second pillar stopping
edge after the entire edge has been processed.
FIG. 25B shows a thus-far completed representation of the FIG. 12A through FIG.
25B special spacing situation; all boxes are completed.
FIG. 26A shows an enlarged cross sectional view of a prior art thin substrate
hybrid device comprised of substrate, carrier, and die.
FIG. 26B shows an approximately real size top view representation of the FIG.
26A hybrid circuit device.
FIG. 27A shows an enlarged cross sectional view of a prior art pedestal-inclusive
hybrid device comprised of substrate, carrier, and die.
FIG. 27B shows an approximately real size top view representation of the FIG.
27A hybrid circuit device.
FIG. 28A shows an enlarged cross sectional view of a prior art filled via hybrid
device comprised of substrate, carrier, and die.
FIG. 28B shows an approximately real size top view representation of the FIG.
28A hybrid circuit device.
FIG. 29 shows an exploded view of a hybrid circuit device made in accordance
with the present invention.
FIG. 30A shows a top view of a substrate having pillar holes according to the
present invention.
FIG. 30B shows a top view of a mating substrate carrier for the FIG. 30A substrate.
FIG. 30C shows the substrate of FIG. 30A and the substrate carrier of FIG. 30B
in a mated, assembled state.
FIG. 31A shows a prior art grounding arrangement for a representative hybrid
component in cross section.
FIG. 31B shows a grounding arrangement for a representative hybrid component
according to the present invention in cross section.
FIG. 32 shows a software flow diagram in block form.
DETAILED DESCRIPTION OF THE INVENTION
A practicing of the present invention involves fabrication of a substrate member
of specific physical dimensions with a precise pattern of apertures or via holes
disposed in selected locations across the surface of this substrate and with an
additional opening in the substrate for receiving an integrated circuit die, a
die which mounts directly on a metallic pedestal of the chip carrier. The invention
further involves fabrication of a mating substrate carrier member, from a material
such as brass, in which there is disposed a recess or receptacle closely conforming
with the substrate overall dimensions and containing an array of upstanding pedestal
members and pillars or mesa members. The pedestal members are located in registration
with integrated circuit die-receiving apertures located in the substrate and the
pillar members are located in registration with the apertures or via holes of the
substrate precise pattern.
Fabrication of two mating parts of this nature is believed within the
capabilities of a person of ordinary skill in the machining or mechanical apparatus
or the etching arts—especially since the relevant technology is mechanical
rather than chemical or biological in nature. Applicants nevertheless disclose
herein a computer-aided process usable in performing these fabrications with a
minimum of human input and supervision and with desirable repeatability and accuracy.
This process includes the performance of substrate carrier machining under the
control of a suitably programmed personal computer. In the descriptive material
following and in the folders of files disclosed on the compact disc appendix of
this application there are numerous references to the invention using the expression
"UCCAS"; this expression is an abbreviation for the name "Unified Custom Carrier
and Substrate", the name used by the inventors and colleagues in their laboratory
in referring to the invention.
The Compact Disc appendix included in the U.S. Patent and Trademark Office file
of the present patent document is submitted in the form of two identical disc copies
each including two file folders. One of these file folders, the folder "uccas
—code"
is of 99.1 Kilobytes (101,559 bytes) size, contains 42 individual files and is
dated Sep. 24, 2001; this file folder discloses software code used in embodiment
of the invention. The second of these file folders, the folder "uccas
—examples"
is of 898 bytes size, contains 3 individual files and is dated Sep. 24, 2001; this
file folder discloses sample data usable to verify operation of the invention.
The contents of these compact disc file folder materials are hereby incorporated
by reference herein.
The uccas
—code and uccas
—examples folders of
the compact disc appendix contain individual files of the following semicolon-separated names:
Folder: uccas
—code
CIRCLE.M; draw—box.m; draw—box2.m;
draw—box3.m; dtype1.m; dtype2.m; dtype3.m; dtype4.m; dtype5.m;
dtype6.m; find—box.m; find—extremes.m; find—xmaxa.m;
find—xmaxb.m; find—xmina.m; find—xminb.m;
find—ymax.m; find—ymax—range.m;
find—ymax—st.m; find—ymin.m;
find—ymin—range.m; find—ymin—st.m;
get—pillars.m; hole—check.m; insulate.m; insulate—box—polish.m;
insulate—box—rough.m; layout.m; layout—serp.m;
my—error—uccas.m; parse—gds.m;
parse—techfile.m; remove—box.m; sort—check.m;
uccas.m; writedxf.m; writegerber.m; write—carrier—files.m;
zoom—full—view.m; zoom—start.m;
zoom—stop.m; zoom—uccas.m.
Folder: uccas
—examples
techfile.utf; test1.gds; test2.gds.
The following material explains the operation of the milling machine algorithm
by way of focus on the steps used to mill an exemplary substrate carrier.
UCCAS Algorithm
Summary of Algorithm Steps:
1) Read in GDSII file
2) Read in technology file
3) Write DXF files for the top metal layer and circuit boundary layer for
the substrate
4) Process GDSII data to get information about the carrier
- a) Physical dimensions of carrier
- b) Location and size of each pillar
5) Draw what carrier will look like
6) Create tool paths to mill the carrier
7) Write Gerber files for the carrier milling, carrier cutting, and the
substrate holes
For the UCCAS process, step 6 in this sequence is a key to making this entire
process operational. The remainder of these steps support step 6. Therefore the
following disclosure focuses on a word and picture description of how step 6 functions
and the limitations that are circumvented.
Milling Machine Description
A miniature milling machine such as the LPKF Laser and Electronics model 91S/VS
machine made in Garbsen Germany and sold by the manufacturer's branch at 2820 SW
Bobery Road Wilsonville, Oreg. 97070 or an equivalent machine made by another manufacturer
may be used in the following fabrication of parts for the present invention. FIG.
1A through FIG. 1D in the drawings shows a basic top, front, and side representations
of the milling machine 101 used. In these drawings the surface the material
to be machined appears at 100 and a raised arm 102 is attached to
the base of the machine 101 by supports 106 on the side. This arm
102 can move from the left edge of the machine to the right edge. The raised
arm 102 supports the motor housing 104. The motor housing 104
can move from the bottom edge of the machine to the top edge as shown in FIG. 1A.
The milling bit 108 can be placed at any location over the material to be
machined by the combination of the raised arm 102 moving horizontally and
the motor housing 104 moving vertically. The motor housing 104 has
two settings, up or down. When the motor is up, FIG. 1C, the milling bit 108
can be moved around without the bit touching the material to be machined. When
the motor is down, FIG. 1D, the milling bit can be moved around with the bit milling
the material.
In the FIG. 1 drawings when the bit 108 is down, a part of the motor housing
104, the depth limiter 200, actually rides along the top surface
of the material to be machined, at 200. FIG. 2B shows the configuration.
The milling bit 108 attaches to the center of the motor and is surrounded
by the depth limiter 200 as shown in FIG. 2A. When the motor housing 104
is down, the depth limiter 200 rides along the surface of the material 202
and the bit is spinning in the center of the depth limiter opening. The depth of
the cut is controlled by adjusting the bottom of the bit 108 relative to
the bottom of the depth limiter 200.
Set-up Considerations
The milling machine 101 is not specifically made to machine metal. Machining
metals with the FIG. 1 apparatus therefore is most successful if the bit is used
only to mill and not drill the material to be machined. Milling is a process where
the bit moves horizontally and removes material with the side of the bit. Drilling
is a process where the bit moves vertically into the material and removes material
with the bottom of the bit. Therefore, in the present apparatus the motor head
can be lowered in only two different locations on the material to be machined 202.
The first location is beside the material 202 such that the bit 108
does not drill but the depth limiter 200 rests on the material 202.
This situation is shown in the side view of FIG. 2B. The second location in which
the motor head can be lowered is over an area that has already been milled under
the bit 108 but not milled under some part of the depth limiter 200.
For instance if a cut parallel to the y axis were made on the material to be machined
202 in FIG. 3, the bit could be lowered anywhere directly above that cut
and not have the bit drill into the material since the material was already milled
by the vertical cut. In order to make present invention substrate carriers, the
stock metal must be shaped (sheared or cut) prior to milling. The metal is shaped
such that one dimension of the final carrier (typically the width) is finalized
from the dimension of the starting material. Therefore, the starting metal is typically
a strip of some width and usually about 8 inches long. The width of the strip is
chosen to be approximately 0.5 inches wider than the substrate that will fit on
the carrier. Several carriers can be machined out of the strip of starting material.
FIG. 3 shows a typical starting material blank; FIG. 3 also shows the convention
adopted herein for x and y coordinate directions. Individual carriers are segregated
from the remaining FIG. 3 material by making a cut along the material in the y
direction all the way through the metal.
The second setup consideration is that the depth limiter 200 should always
have contact with the un-machined top of the stock metal 202. This is to
ensure the same milling depth over the entire region. If a recess region larger
than the depth limiter were machined and the depth limiter got into that recess
region, the milling depth would change and the depth limiter 200 would not
be able to escape from this recess. Therefore, the carrier must be processed in
the positive x direction i.e., left to right, as shown in FIG. 3. This insures
that the depth limiter 200 always rides on top of the stock material 202.
UCASS Algorithm Step 6
Step 6 in the above summary of the UCASS algorithm represents the heart of the
present process. The process of making substrate carriers that match substrates
in essence amounts to a question of how to machine the carriers within given constraints.
Again, the first constraint is that the motor head must be lowered at a location
such that the bit will not drill into the material. The second constraint is that
the processing must move from one side of the carrier to the other such that the
depth limiter is always resting on un-machined material. The left side of the milling
machine bit will always be the areas already milled, and the right side of the
bit will be the areas to be milled. A significant goal of the milling machine control
program is therefore to specify how the milling bit must move to create the carrier
while staying within these constraints.
The process of creating the milling machine bit patterns (also called "insulation
paths" herein) is accomplished by breaking the substrate carrier work piece into
smaller regions called boxes. When all the individual box regions are machined,
the carrier is complete with the substrate-mating pillars and pedestals left where
they need to be ("pedestals" are herein considered to be larger upstanding non
machined areas suitable for integrated circuit die mounting, "pillars" are considered
to be smaller upstanding non machined areas suitable for individual substrate via
hole mating; pedestals and pillars are therefore somewhat equivalent for present
purposes). FIG. 4 in the drawings shows an example of a very simple carrier. The
areas 400, 402 and 404 are where the carrier metal will not
be machined and the area 406 is where the carrier metal will be machined.
In this case, there is only one pillar 408 in the center of the carrier.
FIG. 5 shows all the boxes that are defined when working with the FIG. 4 carrier.
Milling occurs in the boxes 500, 502, 504 and so on. Although
the individual boxes are difficult to see in FIG. 5, the important point is that
all of the area to be machined 406 is covered with boxes and the areas 400,
402 and 404 are not. Each box used in FIG. 5 is shown separately
and discussed in more detail below herein.
Once the FIG. 5 boxes have been defined, the process for making the insulation
paths is not difficult. One insulation path is defined as the path the milling
bit 108 will take from the time it is lowered to the time it is raised again.
Each box receives one insulation path. FIG. 6B in the drawings shows the appearance
of insulation paths in a box. The starting point is always the top left of the
box. The path then moves to the bottom of the box. The second movement is one-half
of the milling bit diameter in the x direction as shown at 600 in FIG. 6B.
The third movement is back to the top of the box as shown at 602 in FIG.
6B and so-on. The general pattern is to make one move in the y direction (from
one extreme of the box to the other) and then move one half of the milling bit
diameter in the positive x direction. This is continued until the move in x would
put the edge of the milling bit outside of the box. The last movement in x is adjusted
so the edge of the milling bit will be at the edge of the box. This adjustment
can be easily seen at 604 in FIG. 6B where the right-most vertical line
has a much smaller spacing than the other vertical lines. FIGS. 6C through 6F show
the same path as FIG. 6B but now showing the width of the milling bit. The only
exception to this milling bit progression occurs if a horizontal cut is needed.
These cuts will only be allowed to be one bit width and are used only in limited
situations. In the horizontal cut case the insulation path starts at the left edge
and goes to the right edge. It is notable that the horizontal movement each time
is one-half of the milling bit diameter; this degree of overlap is however a matter
of user election. This means that each new vertical cut will only remove one half
of the width of the milling tool. This arrangement reduces the load on the milling
machine motor and helps preserve milling bit lifetime.
Since creation of the insulation paths within a box is therefore somewhat standardized,
the more complex part of the present process lies in defining the boxes that break
up the carrier area. The different boxes described below will be shown in the order
created in the program and not in the order that their corresponding insulation
paths are to be machined. In fact once all the insulation paths are created, they
are sorted in the x direction. This sorting procedure causes the milling to start
at the left edge of the carrier and move to the right edge. More importantly, this
sorting enforces the second constraint that the depth limiter always rests on un-machined metal.
The first set of FIG. 4 and FIG. 5-defined boxes that are created are shown in
FIG. 7. The areas 700 and 702 in FIG. 7 are the boxes. These boxes
define the horizontal edges of the carrier. When the carrier is cut out, the cut
will go through this box. The first box at 700 is made to be longer than
the width of the carrier. This way the milling bit is lowered such that it does
not touch the material being cut but the depth limiter does. This box 700
goes the entire width of the carrier. These first boxes are critical to adhering
to the constraint of not using the milling bit to drill. The left box at 700
defines the initial cut into the carrier. Following the FIG. 7 cuts the milling
bit can be set down over the initial cut at 700 without the bit drilling
into the material.
The second set of FIG. 4 and FIG. 5-defined boxes that are created are shown
in FIG. 8A. The FIG. 8 drawings in fact show the new boxes created in FIG. 8A and
all of the thus-far created boxes in FIG. 8B. This showing will be the standard
from this point forward in this discussion. The FIG. 8A new boxes 800 and
802 define the upper most and lower most areas to be milled. As a result
of the above-described milling path sorting and the milling path sorting in the
x direction, the first area to be milled is the left most box in FIG. 7. The next
two boxes to be milled are the new boxes shown in FIG. 8A. When these areas are
milled, the bit will not drill into the substrate carrier material being milled
because the motor head comes down directly over a box that was defined in the first
set of boxes. By milling the carrier from left to right, the depth limiter will
always rest on un-machined metal, thus ensuring the proper milling depth. Thus
far, the boundaries of the carrier have been milled out. Note that the necessity
of the cut along the upper and lower edge of the carrier force a design rule of
no pillars being allowed within one tool diameter of the y boundaries of the carrier.
The third set of boxes that are created are shown in FIG. 9A. Each pillar receives
horizontal cuts as the cuts 900 and 902 along the top and the bottom
of each pillar. These cuts are made so that the edges of each pillar are clean
and are needed to keep the bit from drilling. The boxes that will be created over
and under the pillar in later steps will be aligned with the edge of the pillar.
If these horizontal boxes were not cut first, the milling bit would have to drill
into metal when milling above or below the pillar. All of the boxes milled thus-far
are shown in the FIG. 9B drawing. (FIG. 9B shows the order of box definition not
the order of machining as is explained above—therefore the cut 902
for example does not imply the use of drilling.)
For all carriers, the first three sets of boxes are easily defined and are used
to outline the carrier and any pillars as has been shown in the FIG. 5 through
FIG. 9 process steps. These initial boxes are called outline boxes. The only exception
is if there are no pillars. In this case, the first two sets of boxes are defined
and then one final box is defined that covers the remainder of the carrier metal.
FIG. 10 shows this case. This carrier is the same as the one shown in the previous
examples but the center pillar is removed. FIG. 10 shows outline boxes, final box
and all boxes in the views of FIG. 10A, FIG. 10B, FIG. 10C and FIG. 10D.
Once the outline boxes have been defined, a next set of boxes is created to
remove the remainder of the carrier metal to form the desired recess and leave
the pedestal/pillar areas standing in the recess. This arrangement is satisfactory
so long as the standing areas are square and they are separated in the x or y direction
by at least one milling tool diameter. The general algorithm functions by starting
from the left edge of the carrier and moving right. The program manages two data
structures as it moves in the x direction. The first is a list of all the completed
boxes and the second is a list of all the processing boxes. A processing box means
that some of the values for the box have been entered but not all of them. A processing
box is moved to the completed box data structure once all the values have been
determined. The values for the box are the minimum and maximum x and y locations
(values stored as xmin, ymin, xmax, and ymax). As the program moves across the
carrier the two data structures are processed at each edge of each pillar. If the
edge of the pillar is a starting edge (left edge of the pillar), then one box is
moved from the processing boxes to the completed boxes and two new entries are
made into the processing boxes structure. If the edge of the pillar is an ending
edge (right edge of the pillar), then two boxes are moved from the processing boxes
to the completed boxes and one new entry is made into the processing boxes structure.
There are some special cases to consider but these are discussed later. To demonstrate
how this processing functions, the process will be demonstrated on the carrier
shown in the previous examples. For each step, the entries for both data structures
are listed. The drawings used have a diagram of all the completed boxes to that
point and a diagram of only the new completed boxes. New processing boxes can not
be drawn since all their information is not known. The outline boxes are already
stored in the completed box data structure. Those entries are ignored during this
explanation in the interest of simplicity.
FIG. 11 in the drawings shows the starting point of the sweep in the x direction
i.e., the x=0 point along the x axis. Initial boxes as shown in FIG. 5 through
FIG. 9 are however not shown in FIG. 1 in the interest of simplicity. The number
of completed boxes are the same in FIG. 11 as those in FIG. 8. FIG. 11 shows the
initial entries into the data structures with dimensions being in mills or thousandths
of an inch. FIG. 11 also shows the locations of important features in the carrier.
The xmin, ymin and ymax values of the initial processing box are set by the boundary
of the carrier. The xmax value will be set later. The original carrier had a minumum
y of -400 and a maximum y of 400. All the data stored in the boxes data structures
are at the location of the center of the milling machine bit. This makes the processing
of insulation paths easier. The milling bit for this example is a 79 mil diameter
end mill. This explains why ymax is 360.5 and ymin is -360.5. These values are
adjusted by the radius (39.5) of the milling bit. For the remainder of this example,
radius is always 39.5 with all values being expressed in mils or thousandths of
an inch.
When the program comes to a pillar feature (either a start or a stop edge),
it has to do some processing at this x location. The processing depends on the
type of pillar location and whether the feature was a start or stop edge on the
pillar. In every case, the first pillar feature is a start edge. In order to close
a box (move from processing boxes to completed boxes), the program needs information
to find the correct box in the processing box structure. The program searches for
features above and below the pillar having the current edge the program is processing.
The value that it finds above is called ymaxs (maximum y for searching) and the
value that it finds below is called ymins (minimum y for searching). The proper
box to close is identified when ymaxs is equal to the ymax of the box and ymins
is equal to the ymin of the box. This example is a very simple case where there
is only one box being processed however the described process is needed for more
complicated carriers where there may many entries in the processing box data structure.
To find the ymaxs value the program looks for any pillars above the current x location
i.e., pillars above the pillar that spans the current edge being processed. There
are three possible cases. The first is if there are no pillars above the current
pillar's starting edge. The ymaxs value in this case is set to the maximum y value
of the carrier. The second case is if there is one pillar above the current pillar's
starting edge. The ymaxs value in this case is set to the minimum y of the pillar
that is above the current pillar. The third case is if there are multiple pillars
above the current pillar's starting edge. The ymaxs value in this case is the minimum
y value of the pillar that is closest to the current pillar. To find the ymins
value, the program does the same as for the ymaxs value but it now searches below
the current pillar. Once the ymaxs and ymins values are found, they are used to
search the processing box data structure. Ymaxs and ymins are shifted by the radius
of the milling tool since this is how the values are stored in the processing box
data structure. When the proper entry in the processing box is found, the xmax
of that box is set to the x location of the pillar edge being processed minus the
radius. The box is then removed from the processing box data structure and added
to the completed box data structure. Now one box is closed. Two new boxes must
now be opened.
For a start edge of a pillar, the program also opens two new entries into the
processing box structure. The xmin, ymax, and ymin for both boxes are already known.
The xmin is the current location of the starting edge of the pillar. For the box
above the pillar, the ymin of the box is set to the maximum y value of the pillar
and the ymax value of the box is set to ymaxs, which was found in the searching
done for closing out a box. For the box below the pillar, the ymax of the box is
set to the minmum y value of the pillar and the ymin value of the box is set to
ymin
