Title: Image suppression filter circuit
Abstract: An image suppression filter circuit comprises a first phase shifter outputting a first output signal and a second output signal substantially orthogonal thereto, a second phase shifter outputting a third output signal and a fourth output signal orthogonal to the third output signal, a first subtracter subtracting the fourth output signal from the first output signal, a first adder adding the second and third output signals, a third phase shifter outputting a fifth output signal and a sixth output signal orthogonal to the fifth output signal, a fourth phase shifter outputting a seventh output signal and an eighth output signal orthogonal thereto, a second subtracter subtracting the eighth output signal from the fifth output signal, and a second adder adding the sixth and the seventh output signals.
Patent Number: 6,990,326 Issued on 01/24/2006 to Otaka
| Inventors:
|
Otaka; Shoji (Yokohama, JP)
|
| Assignee:
|
Kabushiki Kaisha Toshiba (Kawasaki, JP)
|
| Appl. No.:
|
897911 |
| Filed:
|
July 5, 2001 |
Foreign Application Priority Data
| Jul 05, 2000[JP] | 2000-203655 |
| Current U.S. Class: |
455/302; 455/114.2; 455/323 |
| Current Intern'l Class: |
H04B 1/10 (20060101) |
| Field of Search: |
455/105,118,114.2,285,302,313,314,323
|
References Cited [Referenced By]
U.S. Patent Documents
Other References
Jan Crols, et al., "A Single-Chip 900 MHz CMOS Receiver Front-End with a High
Performance Low-IF Topology", IEEE Journal of Solid-State Circuits, vol. 30, No.
12, pp. 1483-1492, Dec. 1995.
|
Primary Examiner: Hong; Harry S.
Attorney, Agent or Firm: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
Claims
What is claimed is:
1. An image suppression filter circuit comprising:
a first phase shifter which receives an inphase input signal, and outputs a first
output signal and a second output signal having a phase component substantially
orthogonal to the first output signal;
a second phase shifter which receives a quadrature input signal having a phase
component substantially orthogonal to the inphase input signal, and outputs a third
output signal and a fourth output signal having a phase component orthogonal to
the third output signal;
a first subtracter which subtracts the fourth output signal from the first output
signal, and outputs a subtraction signal;
a first adder which adds the second output signal and the third output signal,
and outputs an addition signal;
a third phase shifter which receives the subtraction signal, and outputs a fifth
output signal and a sixth output signal having a phase component orthogonal to
the fifth output signal;
a fourth phase shifter which receives the addition signal, and outputs a seventh
output signal and an eighth output signal having a phase component orthogonal to
the seventh output signal;
a second subtracter which subtracts the eighth output signal from the fifth output
signal, and outputs a subtraction result as an inphase output signal; and
a second adder which adds the sixth output signal and the seventh output signal,
and outputs an addition result as a quadrature output signal.
2. An image suppression filter circuit according to claim 1, comprising first
buffer device which outputs the first output signal and the fourth output signal
respectively to the first subtracter, and second buffer device which outputs the
second output signal and the third output signal respectively to the first adder.
3. An image suppression filter circuit according to claim 2, wherein the first
buffer device comprises a voltage-to-current converter having a differential circuit
structure, the first subtracter subtracts in a current mode.
4. An image suppression filter circuit according to claim 2, wherein the second
buffer device comprises a voltage-to-current converter having a differential circuit
structure, the first adder adds in a current mode.
5. An image suppression filter circuit according to claim 2, comprising third
buffer device which outputs the fifth output signal and the eighth output signal
to the second subtracter, and fourth buffer device which outputs the sixth output
signal and the seventh output signal to the second adder.
6. An image suppression filter circuit according to claim 5, wherein the third
buffer device comprises a voltage-to-current converter having a differential circuit
structure, the second subtracter subtracts in a current mode.
7. An image suppression filter circuit according to clam
5, wherein the
fourth buffer device comprises a voltage-to-current converter having a differential
circuit structure, the second adder adds in a current mode.
8. An image suppression filter circuit according to claim 1, wherein the first
phase shifter and the second phase shifter have an identical circuit structure.
9. An image suppression filter circuit according to claim 1, wherein the third
phase shifter and the fourth phase shifter have an identical circuit structure.
10. An image suppression filter circuit according to claim 1, wherein each of
the first phase shifter, the second phase shifter, the third phase shifter and
the fourth phase shifter comprises a bridge circuit including a first resistor,
a first end connected to one end of the first resistor, a first capacitor having
one end connected to the first end, a second end connected to the other end of
the first capacitor, a second resistor having one end connected to the second end,
a third end connected to the other end of the second resistor, a second capacitor
having one end connected to the third end, and a fourth end connected to the other
end of the second capacitor and the fourth end being connected with the other end
of the first resistor;
the first phase shifter receiving the inphase input signal as potential difference
between the fourth end and the second end of the bridge circuit, and outputting
the first output signal as potential of the third end of the bridge circuit and
the second output signal as potential of the first end of the bridge circuit;
the second phase shifter receiving the quadrature input signal as a potential
difference between the fourth end and the second end of the bridge circuit, and
outputting the third output signal as potential of the third end of the bridge
circuit and the fourth output signal as potential of the first end of the bridge
circuit;
the third phase shifter receiving the subtraction signal as potential difference
between the fourth end and the second end of the bridge circuit, and outputting
the fifth output signal as potential of the third end of the bridge circuit and
the sixth output signal as potential of the first end of the bridge circuit; and
the fourth phase shifter receiving the addition signal as potential difference
between the fourth end and the second end of the bridge circuit, and outputting
the seventh output signal as potential of the third end of the bridge circuit and
the eighth output signal as potential of the first end of the bridge circuit.
11. An image suppression filter circuit according to claim 1, wherein each of
the first phase shifter, the second phase shifter, the third phase shifter and
the fourth phase shifter comprises a bridge circuit including a first resistor,
a first end connected to one end of the first resistor, a first capacitor having
one end connected to the first end, a second end connected to the other end of
the first capacitor, a second resistor having one end to be connected to the second
end, a third end connected to the other end of the second resistor, a second capacitor
having one end connected to the third end, and a fourth end connected to the other
end of the second capacitor and the fourth end being connected with the other end
of the first resistor;
the first phase shifter receiving the inphase input signal as potential difference
between the fourth end and the second end of the bridge circuit, and outputting
the first output signal as potential of the third end of the bridge circuit and
the second output signal as potential of the first end of the bridge circuit;
the second phase shifter receiving the quadrature input signal as potential difference
between the fourth end and the second end of the bridge circuit, and outputting
the third output signal as potential of the third end of the bridge circuit and
the fourth output signal as potential of the first end of the bridge circuit;
the third phase shifter receiving the subtraction signal as potential difference
between the fourth end and the second end of the bridge circuit, and outputting
the fifth output signal as potential difference between the third end and the first
end of the bridge circuit and the sixth output signal as potential difference between
the fourth end and the second end of the bridge circuit; and
the fourth phase shifter receiving the addition signal as potential difference
between the fourth end and the second end of the bridge circuit and outputting
the seventh output signal as potential difference between the third end and the
first end of the bridge circuit and the eighth output signal as potential difference
between the fourth end and the second end of the bridge circuit.
12. An image suppression filter circuit according to claim 1, wherein each of
the first phase shifter, the second phase shifter, the third phase shifter and
the fourth phase shifter comprises a bridge circuit including a first resistor,
a first end connected to one end of the first resistor, a first capacitor having
one end connected to the first end, a second end connected to the other end of
the first capacitor, a second resistor having one end connected to the second end,
a third end connected to the other end of the second resistor, a second capacitor
having one end connected to the third end, and a fourth end connected to the other
end of the second capacitor and the fourth end being connected with the other end
of the first resistor;
the first phase shifter receiving the inphase input signal as potential difference
between the fourth end and the second end of the bridge circuit, and outputting
the first output signal as potential difference between the third end and the first
end of the bridge circuit and the second output signal as potential difference
between the fourth end and the second end of the bridge circuit;
the second phase shifter receiving the quadrature input signal as potential difference
between the fourth end and the second end of the bridge circuit, and outputting
the third output signal as potential difference between the third end and the first
end of the bridge circuit and the fourth output signal as potential difference
between the fourth end and the second end of the bridge circuit;
the third phase shifter receiving the subtraction signal as potential difference
between the fourth end and the second end of the bridge circuit, and outputting
the fifth output signal as potential of the third end of the bridge circuit and
the sixth output signal as potential of the first end of the bridge circuit; and
the fourth phase shifter; receiving the addition signal as potential difference
between the fourth end and the second end of the bridge circuit, and outputting
the seventh output signal as potential of the third end of the bridge circuit and
the eighth output signal as potential of the first end of the bridge circuit.
13. An image suppression filter circuit according to claim 1, wherein the first
phase shifter, the second phase shifter, the third phase shifter and the fourth
phase shifter are respectively constituted of a bridge circuit including a first
resistor, a first end connected to one end of the first resistor, a first capacitor
having one end connected to the first end, a second end connected to the other
end of the first capacitor, a second resistor having one end connected to the second
end, a third end connected to the other end of the second resistor, a second capacitor
having one end connected to the third end, and a fourth end connected to the other
end of the second capacitor and the fourth end being connected with the other end
of the first resistor;
the first phase shifter receiving the inphase input signal as potential difference
between the fourth end and the second end of the bridge circuit, and outputting
the first output signal as potential difference between the third end and the first
end of the bridge circuit and the second output signal as potential difference
between the fourth end and the second end of the bridge circuit;
the second phase shifter receiving the quadrature input signal as potential difference
between the fourth end and the second end of the bridge circuit, and outputting
the third output signal as potential difference between the third end and the first
end of the bridge circuit and the fourth output signal is output as potential difference
between the fourth end and the second end of the bridge circuit;
the third phase shifter receiving the subtraction signal as potential difference
between the fourth end and the second end of the bridge circuit, outputting the
fifth output signal as potential difference between the third end and the first
end of the bridge circuit and the sixth output signal is output as potential difference
between the fourth end and the second end of the bridge circuit; and
the fourth phase shifter receiving the addition signal as potential difference
between the fourth end and the second end of the bridge circuit, and outputting
the seventh output signal as potential difference between the third end and the
first end of the bridge circuit and the eighth output signal is output as potential
difference between the fourth end and the second end of the bridge circuit.
14. An image suppression filter circuit comprising:
a pre-stage phase shifter; and a plurality of rear-stage phase shifters:
the pre-stage phase shifter including:
a first phase shifter which receives an inphase input signal, and outputs a first
output signal and a second output signal having a phase component substantially
orthogonal to the first output signal;
a second phase shifter which receives a quadrature input signal having a phase
component substantially orthogonal to the inphase input signal, and outputs a third
output signal and a fourth output signal having a phase component orthogonal to
the third output signal;
a first subtracter which subtracts the fourth output signal from the first output
signal, and outputs a subtraction signal; and
a first adder which adds the second output signal and the third output signal,
and outputs an addition signal; and
each of the rear-stage phase shifter including:
a third phase shifter which receives the subtraction signal, and outputs a fifth
output signal having a second phase component as for the subtraction signal and
a sixth output signal having a phase component orthogonal to the fifth output signal;
a fourth phase shifter which receives the addition signal, and outputs a seventh
output signal having the second phase component as for the addition signal and
an eighth output signal having a phase component orthogonal to the seventh output
signal;
a second subtracter which subtracts the eighth output signal from the fifth output
signal, and outputs a subtraction result as an inphase output signal; and
a second adder which adds the sixth output signal and the seventh output signal,
and outputs an addition result as a quadrature output signal.
15. An image suppression filter circuit according to claim 14, comprising a buffer
device which receives the first output signal and the fourth output signal respectively
to the first subtracter, and the second output signal and the third output signal
respectively to the first adder.
16. An image suppression filter circuit according to claim 14, comprising a buffer
device which inputs the fifth output signal and the eighth output signal to the
second subtracter, and the sixth output signal and the seventh output signal to
the second adder.
17. An image suppression filter circuit according to claim 14, wherein the first
phase shifter and the second phase shifter have an identical circuit structure.
18. An image suppression filter circuit according to claim 14, wherein the third
phase shifter and the fourth phase shifter have an identical circuit structure.
19. A receiver apparatus comprising:
an amplifier which amplifies an input signal to output an amplified signal;
an input side mixer which receives the amplified signal and outputs an inphase
signal and a quadrature signal having a phase component orthogonal to the inphase
signal;
an image suppression filter circuit according to claim 1 and configured to receive
a first signal corresponding to the inphase signal and a second signal corresponding
to the quadrature signal and output an inphase output signal;
an output side mixer which converts the inphase output signal from the image
suppression filter circuit into an inphase reception signal and a quadrature reception
signal.
20. A transmitter apparatus comprising:
a first quadrature modulator which converts a transmission inphase signal and
a transmission quadrature signal into an intermediate frequency signal;
an image suppression filter circuit according to claim 1 and configured to generate
an inphase output signal and a quadrature output signal having a phase component
orthogonal to the inphase signal based on the intermediate frequency signal; and
a second quadrature modulator which converts the inphase output signal and the
quadrature output signal into a radio frequency signal.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior
Japanese Patent Application No. 2000-203655, filed Jul. 5, 2000, the entire contents
of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an image suppression filter circuit.
2. Description of the Related Art
Recently, a number of radio terminal systems such cellular phone, PHS,
and the like are becoming popular. One of these radio systems is a system for wire
communication between base stations, through radio communication between the radio
terminal and the base station.
A radio terminal for transmission/reception with the base station through radio
wave adopts in general a heterodyne scheme comprising an antenna, a low noise amplifier
(LNA), a frequency converter (or mixer), an intermediate frequency band pass filter
(IF-BPF), an intermediate frequency mixer (IF-MIX), a low pass filter (LPF), and
an analog-to-digital converter (ADC).
The radio terminal, having such a circuit configuration, receives a radio frequency
(RF) signal as a high frequency signal by the radio terminal antenna and amplifies
it with the low noise amplifier. This amplified high frequency signal is frequency
converted from high frequency RF to intermediate frequency by the frequency converter,
filtered by the IF-BPF and converted into a digital signal by the A/D converter
through the IF-MIX and the LPF.
As an integrated circuit necessary for the radio terminal, there is an image
suppression
filter circuit for suppressing image signal mixed into a desired frequency.
An image signal is a frequency signal converted into the same frequency band
as
the intermediate frequency band into which the wanted wave is converted, when the
received radio wave is converted from high frequency to intermediate frequency
by the frequency converter.
The frequency converter outputs intermediate frequency which is obtained by subtracting
a local frequency from a wanted frequency. However, this frequency converter also
converts a frequency component obtained by subtracting this intermediate frequency
band from the local signal into the same intermediate frequency band. This frequency
component is an image wave to become an unwanted wave.
In addition, various systems transmit and receive signals of various frequencies,
and a wanted wave of one system becomes an interference wave of another system,
and it further becomes an image signal.
Besides, the broadband noise emitted by the transistor itself provides an
image signal. Broad band noise includes thermal noise, shot noise or the like.
Such an image signal results in overlapping the same frequency band as the frequency
converted wanted band. The waves other than wanted wave are unwanted; however,
as the image signal is converted into the same frequency as the wanted wave, an
image suppression filter circuit for suppressing image signal is required.
In an image suppression filter circuit used for the frequency converter of the
aforementioned radio terminal reception system, first an RF signal is divided into
two. One RF signal is frequency converted into an inphase signal by a cosine wave
local signal generated in a first 90 degree phase shifter connected to a local
oscillator signal, while the other RF signal is frequency converted into a quadrature
signal by a sine wave local signal generated in the first 90 degree phase shifter.
Next, the quadrature signal frequency converted by the sine wave is further
phase shifted by 90 degrees by a second 90 degree phase shifter, added with the
inphase signal which is frequency converted by a cosine wave by an adder, thereby
suppressing the image wave.
Incidentally, if frequency conversion is performed simply by the local
signal without removing image signal, the signal is folded, and the wanted signal
and the image signal are converted into the same frequency. In short, the wanted
signal is spoiled by the image signal. Then, if image suppression is performed,
the image wave can be reduced while maintaining the wanted wave.
In other words, suppose the wanted wave signal conversion gain be 1, the image
wave conversion gain may be reduced to a small number not more than 1 (for instance,
0.01). This can prevent the wanted wave signal from being spoiled by the image wave.
This image suppression filter circuit allows a satisfactory filter function
to be achieved to some extent, even when the quality of an inductor or capacitor
is low due to integration.
Such an image suppression filter circuit uses a high phase accuracy phase shifter
wherein a phase is high and precisely constant for a wide range, or a high amplitude
accuracy phase shifter wherein the output amplitude accuracy is high and precisely
constant for a wide range image. Though satisfactory in phase accuracy according
to an applied frequency, the high phase accuracy phase shifter can not obtain sufficient
filter characteristics in a radio system used for broadband, as its output amplitude
is not constant.
The high amplitude phase shifter has a goof output amplitude accuracy corresponding
to the applied frequency. However, since the output phase accuracy is constant,
a sufficient filter characteristic is not obtained for a radio system used in a
broadband range.
As mentioned above, a high phase accuracy phase shifter and high amplitude accuracy
phase shifter can not obtain high phase accuracy and high amplitude accuracy in
the broadband simultaneously, and an image suppression filter circuit used for
broadband radio system can not be manufactured on the IC.
In addition, in a conventional portable radio system having a narrow wanted wave
band, it was enough that the 90 degree phase shifter had a high phase accuracy
and high amplitude accuracy only in a predetermined narrow band. However, in the
future, the amount of radio system information is expected to increase, making
the wanted wave band broader, and the 90 degree phase shifter will be required
to maintain a high accuracy also in the broadband.
However, in the high phase accuracy phase shifter and high amplitude accuracy
phase shifter, output amplitude and output phase vary respectively according to
the frequency, leading to a problem that the image suppression ratio can not be
increased in a broadband radio system.
It is an object of the present invention to provide an integrated image suppression
filter circuit that can also be used for a broadband radio system.
BRIEF SUMMARY OF THE INVENTION
According to a first aspect of the present invention, there is provided
image suppression filter circuit comprising a first phase shifter which receives
an inphase input signal, and outputs a first output signal and a second output
signal having a phase component substantially orthogonal to the first output signal,
a second phase shifter which receives a quadrature input signal having a phase
component substantially orthogonal to the inphase input signal, and outputs a third
output signal having a first phase component as for the quadrature input signal
and a fourth output signal having a phase component orthogonal to the third output
signal, a first subtracter which subtracts the fourth output signal from the first
output signal, and outputs a subtraction signal, a first adder which adds the second
output signal and the third output signal, and outputs an addition signal, a third
phase shifter which receives the subtraction signal, and outputs a fifth output
signal having a second phase component as for the subtraction signal and a sixth
output signal having a phase component orthogonal to the fifth output signal, a
fourth phase shifter which receives the addition signal, and outputs a seventh
output signal having the second phase component as for the addition signal and
an eighth output signal having a phase component orthogonal to the seventh output
signal, a second subtracter which subtracts the eighth output signal from the fifth
output signal, and outputs a subtraction result as an inphase output signal, and
a second adder which adds the sixth output signal and the seventh output signal,
and outputs an addition result as a quadrature output signal.
According to a second aspect of the present invention, there is provided
an image suppression filter circuit comprising a pre-stage phase shifter, and a
plurality of rear-stage phase shifters, the pre-stage phase shifter including a
first phase shifter which receives an inphase input signal, and outputs a first
output signal and a second output signal having a phase component substantially
orthogonal to the first output signal, second phase shifter which receives a quadrature
input signal having a phase component substantially orthogonal to the inphase input
signal, and outputs a third output signal having a first phase component as for
the quadrature input signal and a fourth output signal having a phase component
orthogonal to the third output signal, a first subtracter which subtracts the fourth
output signal from the first output signal, and outputs a subtraction signal, and
a first adder which adds the second output signal and the third output signal,
and outputs an addition signal, and each of the rear-stage phase shifter including
a third phase shifter which receives the subtraction signal, and outputs a fifth
output signal having a second phase component as for the subtraction signal and
a sixth output signal having a phase component orthogonal to the fifth output signal,
a fourth phase shifter which receives the addition signal, and outputs a seventh
output signal having the second phase component as for the addition signal and
an eighth output signal having a phase component orthogonal to the seventh output
signal, a second subtracter which subtracts the eighth output signal from the fifth
output signal, and outputs a subtraction result as an inphase output signal, and
a second adder which adds the sixth output signal and the seventh output signal,
and outputs an addition result as a quadrature output signal.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
FIGS. 1A, 1B and 1C show a circuit diagram, an input frequency—output
amplitude characteristic diagram, and an input frequency—output phase characteristic
diagram of a high phase accuracy phase shifter, respectively;
FIGS. 2A, 2B and 2C show a circuit diagram, an input frequency—output
amplitude characteristic diagram, and an input frequency—output phase characteristic
diagram of a high phase accuracy phase shifter, respectively;
FIG. 3 is a circuit diagram and block diagram of a high phase accuracy phase shifter;
FIG. 4 is a circuit diagram and block diagram of a high amplitude accuracy phase shifter;
FIG. 5 is a circuit diagram of a broadband and high accuracy image suppression
filter circuit according to a first embodiment of the present invention;
FIG. 6 is a circuit diagram of a broadband and high accuracy image suppression
filter circuit according to a second embodiment of the present invention;
FIG. 7 is a circuit diagram of a broadband and high accuracy image suppression
filter circuit according to a third embodiment of the present invention;
FIG. 8 is a circuit diagram of a broadband and high accuracy image suppression
filter circuit according to a fourth embodiment of the present invention;
FIG. 9 is a circuit diagram of a broadband and high accuracy image suppression
filter circuit according to a fifth embodiment of the present invention;
FIG. 10 is a buffer circuit diagram according to a linearized operation circuit;
FIG. 11 is a circuit diagram appropriate for the integration of a broadband
and high accuracy image suppression filter circuit according to the fifth embodiment
of the present invention;
FIG. 12 is a circuit diagram of a broadband and high accuracy image suppression
filter circuit according to a sixth embodiment of the present invention;
FIG. 13 is a circuit diagram appropriate for the integration of a broadband
and high accuracy image suppression filter circuit according to the sixth embodiment
of the present invention;
FIG. 14 is a circuit diagram of a broadband and high accuracy image suppression
filter circuit according to a seventh embodiment of the present invention;
FIG. 15 is a circuit diagram appropriate for the integration of a broadband
and high accuracy image suppression filter circuit according to the seventh embodiment
of the present invention;
FIGS. 16A and 16B are circuit diagrams of a gain enhanced high phase accuracy
phase shifter; and
FIG. 17 is a block diagram of a transceiver using an image suppression filter
circuit according to the present invention.
DETAILED DESCRIPTION OF THE INVENTION
Now, embodiments of the present invention will be described referring to the
drawings. First, a high phase accuracy phase shifter and high amplitude accuracy
phase shifter used for an image suppression filter circuit of the embodiments of
the present invention will be described referring to FIGS. 1 and 2.
FIG. 1A shows a high phase accuracy phase shifter. In this high phase accuracy
phase shifter, one end of a first resistor R
105 is connected to a first
end
101, and one end of a first capacitor C
106 is connected to this
first end
101. The other end of this first capacitor C
106 is connected
to a second end
102. This second end
102 is connected to one end
of a second resistor R
107. A third end
103 is connected to the other
end of this second resistor
107. One end of a second capacitor C
108
is connected to this third end
103. A fourth end
104 is connected
to the other end of this second capacitor C
108. This fourth end
104
and the other end of the first resistor R
105 are connected. In short, the
high phase accuracy phase shifter comprises a CR bridge circuit.
An input signal V
IN of this CR bridge circuit is input as the potential
difference between the fourth end
104 and the second end
102 and
outputs an input dependent output signal V
I and V
Q (signal
which is substantially orthogonal to V
I within a range of ±10%,
for example) respectively as the potential of the third end and the first end.
Here, R of the first and second resistors, C of the first and second capacitors
and the input signal V
IN and the output signals V
I and V
Q
represent respective symbols thereof, and at the same time, are used as values
of expressions described below. In this case, the resistance values of the first
resistor and the second resistor are made identical. In addition, in this case,
the first capacitor and the second capacitor are set to the same value.
In this high phase accuracy phase shifter, as shown in the input frequency—output
amplitude characteristics of FIG. 1B, the output amplitudes of V
I and
V
Q varies according to the input frequency value; however, as shown
in input frequency—output phase characteristics of FIG. 1C, the output phase
difference of V
I and V
Q is constant at π/2 (90 degrees)
independently of the input frequency, and it is characterized by a high accuracy
phase conversion. This characteristic is evident from the transmission function
of the high phase accuracy phase shifter shown below.
VI/VIN=R/(
R+(1
/jωC)) (1)
VQ/VIN=(1
/jωC)/(
R+(1
/jωC)) (2)
In this case, the amplitude ratio (amplitude accuracy) of V
I and V
Q
is R:1/jωC, the phase error is zero degrees (90 degree phased exactly).
In this high phase accuracy phase shifter, the phase accuracy is high and constant
in a broadband frequency range. However, the image signal for a radio system used
in the broadband can not sufficiently suppressed as described thereafter, since
the output amplitude is not constant.
FIG. 2A shows a high amplitude accuracy phase shifter. In this high amplitude
accuracy phase shifter, one end of a first resistor R
105 is connected to
a first end
101, and one end of a first capacitor C
106 is connected
to this first end
101. The other end of this first capacitor C
106
is connected to a second end
102. This second end
102 is connected
to one end of a second resistor R
107. A third end
103 is connected
to the other end of this second resistor
107. One end of a second capacitor
C
108 is connected to this third end
103. A fourth end
104
is connected to the other end of second capacitor C
108. This fourth end
104 and the other end of the first resistor R
105 are connected.
As the foregoing, the high amplitude accuracy phase shifter includes a CR bridge
circuit. An input signal V
IN of this CR bridge circuit is input as the
potential difference between the fourth end
104 and the second end
102,
an output signal V
I is output as the potential difference between the
third end
103 and the forth end
10, while V
Q (signal which
is orthogonal to V
I within a range of ±10%, for example) is output
as the potential difference signal between the fourth end
104 and the second
end
102. Here, R of the first and second resistors, C of the first and second
capacitors and the input signal V
IN and the output signals V
I and
V
Q represent respective symbols thereof, and at the same time, are used
as values of expressions described below. In this case, the resistance values of
the first resistor and the second resistor are made identical. In addition, in
this case, the first and second capacitors are set to the same value.
In this high amplitude accuracy phase shifter, as shown in the input frequency—output
amplitude characteristics of FIG. 2B, the output amplitude ratio (V
I/V
Q)
is precisely constant irrespective of the input frequency; however, as shown in
input frequency—output phase characteristics of FIG. 2C, the output phase
difference is characterized by varying according to the input frequency. This characteristic
is also evident from the transmission function of the high phase accuracy phase
shifter shown below.
VI/VIN=VI/VQ=(
R-(1
/jωC))/(
R+(1
/jω)
C)) (3)
In this case, the amplitude ratio (amplitude accuracy) of V
I and V
Q
is 1, the phase error is 2 tan
-1 (1/(ωCR)).
In this high amplitude accuracy phase shifter, the output amplitude accuracy
is
constant with a high accuracy over a broadband frequency, however, sufficient filter
characteristics for a radio system used in the broadband can not be obtained as
described thereafter, since the output phase accuracy is not high.
In order to simplify the description after drawings, the high phase accuracy
phase
shifter and the high amplitude accuracy phase shifter shown respectively in FIGS.
1A and 2A are shown by a block diagram in FIGS. 3 and 4. In the block diagram of
FIGS. 3 and 4, V
IN indicates an input signal, V
I indicates
a first output signal, V
Q indicates a second output signal converted
to a phase component orthogonal to the first input signal V
I. In the
block diagram, the value surrounded by a square represents the phase, and the value
noted under the square represent the amplitude.
The phase of the output signal V
I of the high phase accuracy phase
shifter shown in FIG. 3 is set to 0, and the output amplitude of the output signal
V
I to 1. Here, the output phase of the output signal V
Q is
set to -π/2 for the output signal V
I independently of the frequency,
and the output amplitude of the output signal V
Q is set to 1/ωCR
to be varied by the frequency ω.
The output phase of the output signal V
Q of the high amplitude accuracy
phase shifter shown in FIG. 4 is supposed to be 0, and the output amplitude of
the output signal V
Q is set to 1. The output signal V
I output
phase varies with the frequency ω as shown in the graphic of FIG. 2C, supposing
θ=2 tan -1(1/(ωCR)) with respect to the output phase of V
Q,
and the output amplitude of the output signal V
I is set to 1. Thus,
the output amplitude ratio is represented as V
I/V
Q=1.
Next, the image suppression filter circuit according to a first embodiment
of the present invention using the block diagram of FIGS. 3 and 4 will be described
referring to FIG.
5. This image suppression filter circuit according to
the first embodiment of the present invention comprises a first high phase accuracy
phase shifter
6, a second high phase accuracy phase shifter
7, a
third high phase accuracy phase shifter
8 and a fourth high phase accuracy
phase shifter
9, which are cascade-connected in two stages.
In this image suppression filter circuit, the first high phase accuracy phase
shifter
6 receives an inphase input signal I
IN, and outputs a
first output signal V
I, and a second output signal V
Q having
a phase component orthogonal to the first input signal V
I. The second
high phase accuracy phase shifter
7 receives a quadrature input signal Q
IN
having a phase component substantially orthogonal to the inphase input signal
I
IN, and outputs a third output signal V
I and a fourth output
signal V
Q converted into a phase component orthogonal to the third output
signal V
I.
The inphase input signal I
IN and quadrature input signal Q
IN
shown in FIG. 5 correspond, for instance, to inphase output and quadrature
output of a former stage quadrature mixer (not shown), and become respectively
the input signal V
IN of the first high phase accuracy phase shifter
6 and the input signal V
IN of the second high phase accuracy
phase shifter
7.
The fourth output V
Q output from the second high phase accuracy phase
shifter
7 is subtracted from the first output signal V
I output
from the first high phase accuracy phase shifter
6 by a first subtracter
10, and this subtraction result is output as subtraction signal X
1.
The second output signal V
Q output from the first high phase accuracy
phase shifter
6 and the third output signal V
I output from the
second high phase accuracy phase shifter
7 are added by a first adder
11
and this addition result is output as addition signal X
2.
The subtraction signal X
1 is input to the third high phase accuracy phase
shifter
8, which outputs a fifth output signal V
I, and a sixth
output signal V
Q whose phase is orthogonal to the fifth output signal V
I.
The addition signal X
2 is input to the fourth high phase accuracy phase
shifter
9, which outputs a seventh output signal V
I and an eighth
output signal V
Q whose phase is orthogonal to the seventh output signal V
I.
The eighth output signal V
Q output from the fourth high phase accuracy
phase shifter
9 is subtracted from the fifth output signal V
I output
from the third high phase accuracy phase shifter
8 by a second subtracter
12, and this subtraction result is an inphase output signal I
OUT.
The sixth output signal V
Q output from the third high phase accuracy
phase shifter
8 and the seventh output signal V
I output from
the fourth high phase accuracy phase shifter
9 are added by a second adder
13 and this addition result is a quadrature output signal Q
OUT.
The subtraction signal X
1, addition signal X
2, inphase output signal
I
OUT, and quadrature output signal Q
OUT of the thus constituted
image suppression filter circuit can be expressed by the following expressions.
X1=
ej(π/2)[IINe-j(π/2)+(
QIN/ωCR)] (4)
X2=(
IIN/ωCR)
e-j(π/2)+QIN (5)
##EQU1##
Nearer 0 degree is the phase error, more removed is the image signal, and
nearer 1 is the amplitude accuracy (amplitude ratio of inphase output signal and
quadrature output signal) more removed is the image signal.
From the aforementioned expressions (4) and (5), if, for instance, ωCR
is 1.2, the amplitude ratio (1/(1/ωCR)) of inphase output signal and quadrature
output signal remains 1.2, in a single stage image suppression filter circuit wherein
the phase shifter comprises such that the subtraction signal X
1 which is
the output result of a single stage of the first high phase accuracy phase shifter
6 and the second high phase accuracy phase shifter
7 is set to the
final inphase output signal. However, the phase difference of inphase output signal
and quadrature output signal is 90 degrees.
On the other hand, the amplitude ratio ({1+1/(ωCR)2}/{2/(ωCR)}) of
inphase input signal I
IN and quadrature input signal Q
IN,
becomes 1.017, at the inphase output signal I
OUT and the quadrature
output signal Q
OUT which are output results of two stages of first high
phase accuracy phase shifter
6, second high phase accuracy phase shifter
7 and third high amplitude accuracy phase shifter
8, fourth high
phase accuracy phase shifter
9, as the image suppression filter circuit
shown in FIG. 5, and the amplitude ratio is nearer to 1 (calculated from expressions
(5) and (6)).
While the inphase input signal I
IN phase is e
-j(π/2),
the quadrature input signal Q
IN phase is e
jo (=1), and inphase
output signal I
OUT and quadrature output signal Q
OUT perform
90 degree phase accurately. Consequently, by cascade connection of high phase accuracy
phase shifters, the amplitude ratio of inphase input signal I
IN and
quadrature input signal Q
IN is 1.017, and is sufficiently smaller than
1.2 of the single stage, and the phase accuracy is constant at 90 degrees. As a
result, an image suppression filter circuit high in amplitude accuracy and phase
accuracy over a broadband is realized.
A high precision of phase accuracy and amplitude accuracy can be realized for
a
still broadband, by increasing the number of connection stages to be cascade connected.
Also, the phase filters
6 and
7 are configured in the same circuit
structure so that a phase difference between the output signals V
I thereof
is 90°. Similarly, the phase filters
8 and
9 are configured
in the same circuit structure so that a phase difference between the output signals
V
I thereof is 90°.
The circuit configuration diagram of the image suppression filter circuit according
to a second embodiment of the present invention will be shown in FIG. 6 using the
block diagram shown in FIGS. 3 and 4. An image suppression filter circuit according
to this embodiment comprises a first high phase accuracy phase shifter
6,
a second high phase accuracy phase shifter
7, a third high amplitude accuracy
phase shifter
14 and a fourth high amplitude accuracy phase shifter
15,
which are cascade-connected in two stages.
In this image suppression filter circuit, the first high phase accuracy phase
shifter
6 receives an inphase input signal I
IN, and outputs a
first output signal V
I and a second output signal V
Q whose
phase is orthogonal to the first output signal V
I. The second high phase
accuracy phase shifter
7 receives a quadrature input signal Q
IN including
a phase component substantially orthogonal to the inphase input signal I
IN,
and outputs a third output signal V
I and a fourth output signal V
Q
whose phase is orthogonal to the third output signal V
I.
The inphase input signal I
IN and quadrature input signal Q
IN
shown in FIG. 6 correspond, for instance, to inphase output and quadrature
output of a not shown former stage quadrature mixer, and become respectively the
input signals V
IN of the first and second high phase accuracy phase
shifters
6 and
7.
The fourth output V
Q output from the second high phase accuracy phase
shifter
7 is subtracted from the first output signal V
I output
from the first high phase accuracy phase shifter
6 by a first subtracter
10, and this subtraction result is output as subtraction signal X
1.
The second output signal V
Q output from the first high phase accuracy
phase shifter
6 and the third output signal V
I output from the
second high phase accuracy phase shifter
7 are added by a first adder
11
and this addition result is output as addition signal X
2.
The subtraction signal X
1 is input to the third high amplitude accuracy
phase shifter
14, which outputs a fifth output signal V
I having
the substantially same component as the subtraction signal X
1 and a sixth
output signal V
Q converted into a phase component substantially orthogonal
to the fifth output signal V
I.
The addition signal X
2 is input to the fourth high amplitude accuracy
phase shifter
15, which outputs a seventh output signal V
I having
the substantially same phase component as the addition signal X
2 and an
eighth output signal V
Q converted into a phase component substantially
orthogonal to the seventh output signal V
I.
The eighth output signal V
Q output from the fourth high amplitude
accuracy phase shifter
15 is subtracted from the fifth output signal V
I
output from the third high amplitude accuracy phase shifter
8 by a
second subtracter
12, and this subtraction result is an inphase output signal I
OUT.
The sixth output signal V
Q output from the third high amplitude accuracy
phase shifter
8 and the seventh output signal V
I output from
the fourth high amplitude accuracy phase shifter
15 are added by a second
adder
13 and this addition result is a quadrature output signal.
The subtraction signal X
1, addition signal X
2, inphase output signal
I
OUT, and quadrature output signal Q
OUT of the image suppression
filter circuit can be expressed by the following expressions:
X1=
ej(π/2)[IINe-j(π/2)+(
QIN/ωCR)] (8)
X2=(
IIN/ωCR)
e-j(π/2)+QIN (9)
##EQU2##
Nearer 90 degree is the phase θ, more removed is the image signal, and
nearer 1 is the amplitude ratio of coefficient of inphase input signal I
IN
and quadrature input signal Q
IN, more removed is the image signal.
For instance, in case where ωCR is 1.2, from the expressions (8) and (9),
the amplitude ratio (1/(1/ωCR)) of inphase input signal and quadrature input
signal remains 1.2, with subtraction signal X
1 and addition signal X
2
which are output results of an image suppression filter circuit wherein the phase
shifter comprises a single stage of the first high phase accuracy phase shifter
6 and the second high phase accuracy phase shifter
7. However, the
phase difference of inphase input signal and quadrature input signal is 90 degrees.
On the other hand, the amplitude ratio in inphase output signal I
OUT
and quadrature output signal Q
OUT, which are output results of two stages
of first high phase accuracy phase shifter
6, second high phase accuracy
phase shifter
7 and third high amplitude accuracy phase shifter
14,
fourth high amplitude accuracy phase shifter
15, as the image suppression
filter circuit shown in FIG. 6, becomes 1.
While the phase difference Δφ in inphase output signal I
OUT
and quadrature output signal Q
OUT can be calculated as follows from
the expressions (10) and (11). Here, only inphase output signal I
OUT is
calculated using the expression (10), similarly, quadrature output signal Q
OUT
can also be calculated using the expression (11).
First, {e
j(θ-π/2)+1/(ωCR)} multiplied by the
inphase input signal I
IN can be expressed as follows.
##EQU3##
From this, this phase φ
1 can be expressed as follows:
φ
1=tan
-1(
B/A) (13)
In the expression (12), given θ=2 tan
-1(1/(ωCR)),=-5.6
is obtained by substituting values.
On the other hand, {e
j(θ-π/2)/(ωCR)+1} multiplied
by the quadrature output signal Q
IN can be expressed as follows.
##EQU4##
From this, this phase φ
2 can be expressed as follows:
φ
2=tan
-1(
D/C) (15)
In the expression (15), given θ=2 tan
-1(1/(ωCR)), φ
2=-4.7°
is obtained by substituting values.
Hence, the phase difference Δφ=-0.9° becomes extremely near
0. This is substantially improved as compared with the phase difference Δφ=π/2-θ=π/2-2
tan
-1(1/(ωCR))=-10.4° in case of using a single stage of
high amplitude accuracy phase shifter. The product of CR must be the same value
between the phase filters
6,
7 and
14,
15, but respective
values of C and R may be changed between the phase filters
6,
7 and
14,
15.
From the aforementioned results, the phase accuracy is -0.9° and the amplitude
accuracy is 1, by cascade connection of high phase accuracy phase shifter and high
amplitude accuracy phase shifter as in the image suppression filter circuit according
to the present invention, allowing to realize a high accuracy over a broadband.
A high precision of phase accuracy and amplitude accuracy for a still broader
band
can be realized, by increasing the number of connection stages to be cascade connected.
Next, the image suppression filter circuit according to a third embodiment
of the present invention will be shown in FIG. 7 using the block diagram shown
in FIGS. 3 and 4. An image suppression filter circuit according to this embodiment
comprises a first high amplitude accuracy phase shifter
16, a second high
amplitude accuracy phase shifter
17, a third high amplitude accuracy phase
shifter
8, and a fourth high phase accuracy phase shifter
9, which
are cascade-connected in two stages.
In this image suppression filter circuit, the first high amplitude accuracy phase
shifter
16 receives an inphase input signal I
IN, and outputs
a first output signal V
I and a second output signal V
Q having
a phase component substantially orthogonal to the first output signal V
I.
The second high amplitude accuracy phase shifter
17 receives a quadrature
input signal Q
IN, and outputs a third output signal V
I and
a fourth output signal V
Q converted into a phase component substantially
orthogonal to the third output signal V
I.
The inphase input signal I
IN and quadrature input signal Q
IN
shown in FIG. 7 correspond, for instance, to inphase output and quadrature
output of a former stage quadrature mixer (not shown), and become respectively
the input signal V
IN of the first high amplitude accuracy phase shifter
16 and the input signal V
IN of the second high phase accuracy
phase shifter
17.
The fourth output V
Q output from the second high amplitude accuracy
phase shifter
17 is subtracted from the first output signal V
I output
from the second high amplitude accuracy phase shifter
17 by a first subtracter
10, and this subtraction result is output as subtraction signal X
1.
The second output signal V
Q output from the first high amplitude accuracy
phase shifter
16 and the third output signal V
I output from the
second high amplitude accuracy phase shifter
17 are added by a first adder
11 and this addition result is output as addition signal X
2.
The subtraction signal X
1 is input to the third high phase accuracy phase
shifter
8, which outputs a fifth output signal V
I and a sixth
output signal V
Q having a phase component substantially orthogonal to
the fifth output signal V
I.
The addition signal X
2 is input to the fourth high phase accuracy phase
shifter
9, which outputs a seventh output signal V
I and an eighth
output signal V
Q having a phase component substantially orthogonal to
the seventh output signal V
I.
The eighth output signal V
Q output from the fourth high phase accuracy
phase shifter
9 is subtracted from the fifth output signal V
I output
from the third high phase accuracy phase shifter
8 by a second subtracter
12, and this subtraction result is an inphase output signal I
OUT.
The sixth output signal V
Q output from the third high phase accuracy
phase shifter
8 and the seventh output signal V
I output from
the fourth high phase accuracy phase shifter
9 are added by a second adder
13 and this addition result is a quadrature output signal Q
OUT.
The subtraction signal X
1, addition signal X
2, inphase output signal
I
OUT, and quadrature output signal Q
OUT of the thus constituted
image suppression filter circuit can be expressed by the following expressions:
X1=
IINejθ-QIN (16)
X2=
IIN+QINejθ (17)
##EQU5##
Here, θ=2 tan
-1 (1/(ωCR)) is represented.
Nearer 90 degree is the phase θ, more removed is the image signal, and
nearer 1 is the amplitude ratio of coefficient of inphase input signal I
IN
and quadrature input signal Q
IN, more removed is the image signal.
For instance, in case where ωCR is 1.2, from the expressions (16) and (17),
the phase error of inphase output signal and quadrature output signal is Δφ=π/2-θ=π/2-2
tan
-1(1/(ωCR))=-10.4°, with subtraction signal X
1
and addition signal X
2 which are output results of an image suppression
filter circuit wherein the phase shifter comprises a single stage of the first
high amplitude accuracy phase shifter
16 an
