Integrated circuit memory device and method Number:6,778,441 from the United States Patent and Trademark Office (PTO) owispatent

Title: Integrated circuit memory device and method

Abstract: Structures and methods for DEAPROM memory with low tunnel barrier intergate insulators are provided. The DEAPROM memory includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator having a tunnel barrier of less than 1.5 eV. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of NiO, Al.sub.2 O.sub.3, Ta.sub.2 O.sub.5, TiO.sub.2, ZrO.sub.2, Nb.sub.2 O.sub.5, Y.sub.2 O.sub.3, Gd.sub.2 O.sub.3, SrBi.sub.2 Ta.sub.2 O.sub.3, SrTiO.sub.3, PbTiO.sub.3, and PbZrO.sub.3. The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator. And, the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

Patent Number: 6,778,441 Issued on 08/17/2004 to Forbes,   et al.

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Inventors:	Forbes; Leonard (Corvallis, OR), Eldridge; Jerome M. (Los Gatos, CA), Ahn; Kie Y. (Chappaqua, NY)
Assignee:	Micron Technology, Inc. (Boise, ID)
Appl. No.:	09/945,498
Filed:	August 30, 2001

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Current U.S. Class:	365/185.26 ; 257/315; 257/316; 257/317; 257/E21.693; 257/E27.103; 257/E29.162; 257/E29.165; 438/257; 438/259; 438/262; 438/264; 438/268; 438/270
Current International Class:	H01L 27/115 (20060101); H01L 29/40 (20060101); H01L 21/70 (20060101); H01L 29/51 (20060101); H01L 21/8247 (20060101); G11C 16/04 (20060101)
Field of Search:	257/315,316,317 365/185.26 438/257,259,262,268,270,264

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References Cited [Referenced By]

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U.S. Patent Documents

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	5350738		September 1994		Hase et al.
	5508544		April 1996		Shah
	5801401		September 1998		Forbes
	5852306		December 1998		Forbes
	5981350		November 1999		Geusic et al.
	5991225		November 1999		Forbes et al.
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Primary Examiner: Nelms; David
Assistant Examiner: Pham; Ly Duy
Attorney, Agent or Firm: Schwegman, Lundberg, Woessner & Kluth, P.A.

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Parent Case Text

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CROSS REFERENCE TO RELATED APPLICATION

This application is related to the following co-pending, commonly assigned U.S. patent applications: "DRAM Cells with Repressed Memory Metal Oxide Tunnel Insulators," Ser. No. 09/945,395, "Programmable Array Logic or Memory Devices with Asymmetrical Tunnel Barriers," , Ser. No. 09/943,134, "Flash Memory with Low Tunnel Barrier Interpoly Insulators," Ser. No. 09/945,507, and "Field Programmable Logic Arrays with Metal Oxide and/or Low Tunnel Barrier Interpoly Insulators," Ser. No. 09/945,512, "SRAM Cells with Repressed Floating Gate Memory, Metal Oxide Tunnel Interpoly Insulators," Ser. No. 09/945,554, "Programmable Memory Address and Decode Devices with Low Tunnel Barrier Interpoly Insulators," Ser. No. 09/945,500, which are filed on even date herewith and each of which disclosure is herein incorporated by reference.

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Claims

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What is claimed is:

1. A DEAPROM memory array, comprising: a number of DEAPROM memory cells, wherein each DEAPROM memory cell includes: a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region and a second source/drain region separated by a channel region; a floating gate opposing the channel region in the number of pillars and separated therefrom by a gate oxide. a control gate opposing the floating gate; and wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator having a thickness of less than 20 Angstroms; a number of sourcelines coupled to the first source/drain regions along a first selected direction in the DEAPROM memory array; a number of control gate lines coupled to the control gates along a second selected direction in the DEAPROM memory array; a number of bitlines coupled to the second source/drain regions along a third selected direction in the DEAPROM memory array; and wherein each floating gate is a vertical floating gate formed in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.

2. The DEAPROM memory array of claim 1, wherein the low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of NiO, Al.sub.2 O.sub.3, Ta.sub.2 O.sub.5, TiO.sub.2, ZrO.sub.2, Nb.sub.2 O.sub.5, Y.sub.2 O.sub.3, Gd.sub.2 O.sub.3, SrBi.sub.2 Ta.sub.2 O.sub.3, SrTiO.sub.3, PbTiO.sub.3, and PbZrO.sub.3.

3. The DEAPROM memory array of claim 1, wherein the floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, wherein the metal layer is selected from the group consisting of platinum (Pt) and aluminum (Al).

4. The DEAPROM memory array of claim 1, wherein the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, wherein the metal layer is selected from the group consisting of platinum (Pt) and aluminum (Al).

5. The DEAPROM memory array of claim 1, wherein the second selected direction and the third selected direction are parallel to one another and orthogonal to the first selected direction, and wherein the number of control gate lines serve as address lines.

6. The DEAPROM memory array of claim 1, wherein the first selected direction and the third selected direction are parallel to one another and orthogonal to the second selected direction, and wherein the number of control gate lines serve as address lines.

7. The DEAPROM memory array of claim 1, wherein the first selected direction and the second selected direction are parallel to one another and orthogonal to the third selected direction, and wherein the number of bitlines serve as address lines.

8. An array of DEAPROM memory cells, comprising: a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; a number of control gates opposing the floating gates; a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells; a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of DEAPROM memory cells, wherein the number of control gates arc separated from the floating gates by a low tunnel barrier intergate insulator, and wherein the low tunnel barrier intergate insulator has a tunnel barrier of less than 1.5 eV; a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of DEAPROM cells ; and wherein each floating gate is a vertical floating gate formed in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.

9. The array of DEAPROM memory cells of claim 8, wherein the low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of NiO, Al.sub.2 O.sub.3, Ta.sub.2 O.sub.5, TiO.sub.2, ZrO.sub.2, Nb.sub.2 O.sub.5, Y.sub.2 O.sub.3, Gd.sub.2 O.sub.3, SrBi.sub.2 Ta.sub.2 O.sub.3, SrTiO.sub.3, PbTiO.sub.3, and PbZrO.sub.3.

10. The array of DEAPROM memory cells of claim 8, wherein each floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, wherein the metal layer is selected from the group consisting of platinum (Pt) and aluminum (Al).

11. The array of DEAPROM memory cells of claim 8, wherein each control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, wherein the metal layer is selected from the group consisting of platinum (Pt) and aluminum (Al).

12. The array of DEAPROM memory calls of claim 8, wherein the plurality of control gate lines are formed in the trench below the top surface of the pillar and between the pair of floating gates, wherein each pair of floating gates shares a single control gate line, and wherein each floating gate includes a vertically oriented floating gate having a vertical length of less than 100 nanometers.

13. The array of DEAPROM memory cells of claim 8, wherein the plurality of control gate lines are formed in the trench below the top surface of the pillar and between the pair of floating gates such that each trench houses a pair of control gate lines each addressing the floating gates one on opposing sides of the trench respectively, and wherein the pair of control gate lines are separated by an insulator layer.

14. The array of DEAPROM memory cells of claim 8, wherein the plurality of control gate lines are disposed vertically above the floating gates, and wherein each pair of floating gates shares a single control gate line.

15. The array of DEAPROM memory cells of claim 8, wherein the plurality of control gate lines are disposed vertically above the floating gates, and wherein each one of the pair of floating gates is addressed by an independent one of the plurality of control gate lines.

16. The array of DEAPROM memory cells of claim 8, wherein each floating gate is a horizontally oriented floating gate formed in a trench below a top surface of each pillar such that each trench houses a floating gate opposing the body regions in adjacent pillars on opposing sides of the trench, and wherein each horizontally oriented floating gate has a vertical length of less than 100 nanometers opposing the body region of the pillars.

17. The array of DEAPROM memory cells of claim 16, wherein the plurality of control gate lines are disposed vertically above the floating gates.

18. An electronic system, comprising: a processor; and a memory device coupled to the processor, wherein the memory device includes an array of DEAPROM memory cells, comprising: a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; a number of control gates opposing the floating gates; a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells, a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of DEAPROM memory cells, wherein the number of control gates fire separated from the floating gates by a low tunnel barrier intergate insulator having a thickness of less than 20 Angstroms; a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of DEAPROM cells; and wherein each floating gate is a vertical floating gate formed in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.

19. The electronic system of claim 18, wherein the low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of NiO, Al.sub.2 O.sub.3, Ta.sub.2 O.sub.5, TiO.sub.2, ZrO.sub.2, Nb.sub.2 O.sub.5, Y.sub.2 O.sub.3, Gd.sub.2 O.sub.3, SrBi.sub.2 Ta.sub.2 O.sub.3, SrTiO.sub.3, PbTiO.sub.3, and PbZrO.sub.3.

20. The electronic system of claim 18, wherein each floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, and wherein the low tunnel barrier includes a tunnel barrier of less than 1.5 eV.

21. The electronic system of claim 18, wherein each control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, and wherein the metal layer is selected from the group consisting of platinum (Pt) and aluminum (Al).

22. The electronic system of claim 18, wherein the plurality of control gate lines are formed in the trench below the top surface of the pillar and between the pair of floating gates, wherein each pair of floating gates shares a single control gate line, and wherein each floating gate includes a vertically oriented floating gate having a vertical length of less than 100 nanometers.

23. The electronic system of claim 18, wherein the plurality of control gate lines are formed in the trench below the top surface of the pillar and between the pair of floating gates such that each trench houses a pair of control gate lines each addressing the floating gates one on opposing sides of the trench respectively, and wherein the pair of control gate lines are separated by an insulator layer.

24. The electronic system of claim 18, wherein the plurality of control gate lines are disposed vertically above the floating gates, and wherein each pair of floating gates shares a single control gate line.

25. The electronic system of claim 18, wherein the plurality of control gate lines are disposed vertically above the floating gates, and wherein each one of the pair of floating gates is addressed by an independent one of the plurality of control lines.

26. The electronic system of claim 18, wherein each floating gate is a horizontally oriented floating gate formed in a trench below a top surface of each pillar such that each trench houses a floating gate opposing the body regions in adjacent pillars on opposing sides of the trench, and wherein each horizontally oriented floating gate has a vertical length of less than 100 nanometers opposing the body region of the pillars.

27. The electronic system of claim 26, wherein the plurality of control gate lines are disposed vertically above the floating gates.

28. A method for forming an array of DEAPROM memory cells, comprising: forming a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; forming a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; forming a number of control gates opposing the floating gates; forming a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells; forming a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of DEAPROM memory cells, wherein the number of control gates lines are separated from the floating gates by a low tunnel barrier intergate insulator having a thickness of less than 20 Angstroms; forming a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of DEAPROM cells; and wherein forming each floating gate includes forming a vertical floating gate in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.

29. The method of claim 28, wherein forming the low tunnel barrier intergate insulator includes forming a metal oxide insulator selected from the group consisting of NiO, Al.sub.2 O.sub.3, Ta.sub.2 O.sub.5, TiO.sub.2, ZrO.sub.2, Nb.sub.2 O.sub.5, Y.sub.2 O.sub.3, Gd.sub.2 O.sub.3, SrBi.sub.2 Ta.sub.2 O.sub.3, SrTiO.sub.3, PbTiO.sub.3, and PbZrO.sub.3.

30. The method of claim 28, wherein forming each floating gate includes forming a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier inter gate insulator, and wherein the metal layer is selected from the group consisting of platinum (Pt) and aluminum (Al).

31. The method of claim 28, wherein forming each control gate includes forming a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, and wherein forming the low tunnel barrier intergate insulator includes forming a low tunnel barrier intergate insulator having a tunnel barrier of less than 1.5 eV.

32. The method of claim 28, wherein forming the plurality of control gate lines includes forming each control gate line in the trench below the top surface of the pillar and between the pair of floating gates, wherein each pair of floating gates shares a single control gate line, and wherein each floating gate includes a vertically oriented floating gate having a vertical length of less than 100 nanometers.

33. The method of claim 28, wherein forming the plurality of control gate lines includes forming a pair of control gate lines in each trench below the top surface of the pillar and between the pair of floating gales such that each control gate line addresses a floating gate on opposing sides of the trench respectively, and wherein the pair of control gate lines are separated by an insulator layer.

34. The method of claim 28, wherein forming the plurality of control gate lines includes forming the control gate lines such that the control gate lines are disposed vertically above the floating gates such that each pair of floating gates shares a single control gate line.

35. The method of claim 28, wherein forming the plurality of control gate lines includes forming the control gate lines such that the control gate lines are disposed vertically above the floating gates, and forming the plurality of control lines such that each one of the pair of floating gates is addressed by an independent one of the plurality of control lines.

36. The method of claim 28, wherein forming each floating gate includes forming a horizontally oriented floating gate in a trench below a top surface of each pillar such that each trench houses a floating gate opposing the body regions in adjacent pillars on opposite sides of the trench, and wherein each horizontally oriented floating gate has a vertical length of less than 100 nanometers opposing the body region of the pillars.

37. The method of claim 36, wherein the forming the plurality of control gate lines includes forming the control gate lines such that the control gate lines are disposed vertically above the floating gates.

38. A memory array, comprising: a number of memory cells, wherein each memory cell includes: a first source/drain region and a second source/drain region separated by a channel region; a floating gate opposing the channel region and separated therefrom by a gate oxide; a control gate opposing the floating gate; and wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator having a thickness of less than 20 Angstroms; a number of sourcelines coupled to the first source/drain regions along a first selected direction in the memory array, a number of control gate lines coupled to the control gates along a second selected direction in the memory array; a number of bitlines coupled to the second source/drain regions along a third selected direction in the memory array; and wherein each floating gate is a vertical floating gate formed in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.

39. The memory array of claim 38, wherein the memory cells include electronically alterable programmable read-only memory.

40. An array of memory cells, comprising: a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; a number of control gates opposing the floating gates; a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells; a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of memory cells, wherein the number of control gates are separated from the floating gates by a low tunnel barrier intergate insulator, and wherein the low tunnel barrier intergate insulator has a tunnel barrier of less than 1.5 eV; a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of cells; and wherein each floating gate is a vertical floating gate formed in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.

41. The array of memory cells of claim 40, wherein the memory cells include electronically alterable programmable read-only memory.

42. A method for forming an array of memory cells, comprising: forming a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; forming a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; forming a number of control gates opposing the floating gates; forming a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells; forming a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of memory cells, wherein the number of control gates lines arc separated from the floating gates by a low tunnel barrier intergate insulator having a thickness of less than 20 Angstroms; forming a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of cells; and wherein forming each floating gate includes forming a vertical floating gate in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.

43. The array of memory cells of claim 42, wherein the memory cells include electronically alterable programmable read-only memory.

44. An electronic system, comprising: a processor; and a memory device coupled to the processor, wherein the memory device includes an array of memory cells, comprising: a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; a number of control gates opposing the floating gates; a number of buried source/lines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells; a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of memory cells, wherein the number of control gates are separated from the floating gates by a low tunnel barrier intergate insulator having a thickness of less than 20 Angstroms; a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of memory cells; and wherein each floating gate is a vertical floating gate formed in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.

45. The memory array of claim 38, wherein the low tunnel hairier intergate insulator includes a metal oxide insulator selected from the group consisting of NiO, Al.sub.2 O.sub.3, Ta.sub.2 O.sub.5, TiO.sub.2, ZrO.sub.2, Nb.sub.2 O.sub.5, Y.sub.2 O.sub.3, Gd.sub.2 O.sub.3, SrBi.sub.2 Ta.sub.2 O.sub.3, SrTiO.sub.3, PbTiO.sub.3, and PbZrO.sub.3.

46. The memory array of claim 38, wherein the floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, wherein the metal layer is selected from the group consisting of platinum (Pt) and aluminum (Al).

47. The memory array of claim 38, wherein the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, wherein the metal layer is selected from the group consisting of platinum (Pt) and aluminum (Al).

48. The memory array of claim 38, wherein the second selected direction and the third selected direction are parallel to one another and orthogonal to the first selected direction, and wherein the number of control gate lines serve as address lines.

49. The memory ray of claim 38, wherein the first selected direction and the third selected direction are parallel to one another and orthogonal to the second selected direction, and wherein the number of control gate lines serve as address lines.

50. The memory ray of claim 38, wherein the first selected direction and the second selected direction are parallel to one another and orthogonal to the third selected direction, and wherein the number of bitlines serve as address lines.

51. The array of memory cells of claim 40, wherein the low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of NiO, Al.sub.2 O.sub.3, Ta.sub.2 O.sub.5, TiO.sub.2, ZrO.sub.2, Nb.sub.2 O.sub.5, Y.sub.2 O.sub.3, Gd.sub.2 O.sub.3, SrBi.sub.2 Ta.sub.2 O.sub.3, SrTiO.sub.3, PbTiO.sub.3, and PbZrO.sub.3.

52. The array of memory cells of claim 40, wherein each floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, wherein the metal layer is selected from the group consisting of platinum (Pt) and aluminum (Al).

53. The array of memory cells of claim 40, wherein each control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, wherein the metal layer is selected from the group consisting of platinum (Pt) and aluminum (Al).

54. The array of memory cells of claim 40, wherein the plurality of control gate lines are formed in the trench below the top surface of the pillar and between the pair of floating gates, wherein each pair of floating gates shares a single control gate line, and wherein each floating gate includes a vertically oriented floating gate having a vertical length of less than 100 nanometers.

55. The array of memory cells of claim 40, wherein the plurality of control gate lines are formed in the trench below the top surface of the pillar and between the pair of floating gates such that each french houses a pair of control gate lines each addressing the floating gates one on opposing sides of the trench respectively, and wherein the pair of control gate lines are separated by an insulator layer.

56. The array of memory cells of claim 40, wherein the plurality of control gate lines are disposed vertically above the floating gates, and wherein each pair of floating gates shares a single control gate line.

57. The array of memory cells of claim 40, wherein the plurality of control gate lines are disposed vertically above the floating gates, and wherein each one of the pair of floating gates is addressed by an independent one of the plurality of control gate lines.

58. The array of memory cells of claim 40, wherein each floating gate is a horizontally oriented floating gate formed in a trench below a top surface of each pillar such that each trench houses a floating gate opposing the body regions in adjacent pillars on opposing sides of the trench, and wherein each horizontally oriented floating gate has a vertical length of less than 100 nanometers opposing the body region of the pillars.

59. The may of memory cells of claim 58, wherein the plurality of control gate lines are disposed vertically above the floating gates.

60. The electronic system of claim 44, wherein the low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of NiO, Al.sub.2 O.sub.3, Ta.sub.2 O.sub.5, TiO.sub.2, ZrO.sub.2, Nb.sub.2 O.sub.5, Y.sub.2 O.sub.3, Gd.sub.2 O.sub.3, SrBi.sub.2 Ta.sub.2 O.sub.3, SrTiO.sub.3, PbTiO.sub.3, and PbZrO.sub.3.

61. The electronic system of claim 44, wherein each floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, and wherein the low tunnel harrier includes a tunnel barrier of less than 1.5 eV.

62. The electronic system of claim 44, wherein each control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, and wherein the metal layer is selected from the group consisting of platinum (Pt) and aluminum (Al).

63. The electronic system of claim 44, wherein the plurality of control gate lines are formed in the trench below the top surface of the pillar and between the pair of floating gales, wherein each pair of floating gates shares a single control gate line, and wherein each floating gate includes a vertically oriented floating gate having a vertical length of less than 100 nanometers.

64. The electronic system of claim 44, wherein the plurality of control gate lines are formed in the trench below the top surface of the pillar and between the pair of floating gates such that each trench houses a pair of control gate lines each addressing the floating gates one On opposing sides of the french respectively, and wherein the pair of control gate lines are separated by an insulator layer.

65. The electronic system of claim 44, wherein the plurality of control gate lines are disposed vertically above the floating gates, and wherein each pair of floating gates shares a single control gate line.

66. The electronic system of claim 38, wherein the plurality of control gate lines are disposed vertically above the floating gates, and wherein each one of the pair of floating gates is addressed by an independent one of the plurality of control lines.

67. The electronic system of claim 38, wherein each floating gate is a horizontally oriented floating gate formed in a trench below a top surface of each pillar such that each trench houses a floating gate opposing the body regions in adjacent pillars on opposing sides of the trench, and wherein each horizontally oriented floating gate has a vertical length of less than 100 nanometers opposing the body region of the pillars.

68. The electronic system of claim 67, wherein the plurality of control gate lines arc disposed vertically above the floating gates.

69. The method of claim 42, wherein forming the low tunnel barrier intergate insulator includes forming a metal oxide insulator selected from the group consisting of NiO, Al.sub.2 O.sub.3, Ta.sub.2 O.sub.5, TiO.sub.2, ZrO.sub.2, Nb.sub.2 O.sub.5, Y.sub.2 O.sub.3, Gd.sub.2 O.sub.3, SrBi.sub.2 Ta.sub.2 O.sub.3, SrTiO.sub.3, PbTiO.sub.3, and PbZrO.sub.3.

70. The method of claim 42, wherein forming each floating gate includes forming a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, and wherein the metal layer is selected from the group consisting of platinum (Pt) and aluminum (Al).

71. The method of claim 42, wherein forming each control gate includes forming a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, and wherein forming the low tunnel barrier intergate insulator includes forming a low tunnel barrier intergate insulator having a tunnel barrier of less than 1.5 eV.

72. The method of claim 42, wherein forming the plurality of control gate lines includes forming each control gate line in the trench below the top surface of the pillar and between the pair of floating gates, wherein each pair of floating gates shares a single control gate line, and wherein each floating gate includes a vertically oriented floating gate having a vertical length of less than 100 nanometers.

73. The method of claim 42, wherein forming the plurality of control gate lines includes forming a pair of control gate lines in each trench below the top surface of the pillar and between the pair of floating gates such that each control gate line addresses a floating gate on opposing sides of the trench respectively and wherein the pair of control gate lines are separated by an insulator layer.

74. The method of claim 42, wherein forming the plurality of control gate lines includes forming the control gate lines such that the control gate lines are disposed vertically above the floating gates such that each pair of floating gates shares a single control gate line.

75. The method of claim 42, wherein forming the plurality of control gate lines includes forming the control gate lines such that the control gate lines arc disposed vertically above the floating gates, and forming the plurality of control lines such that each one of the pair of floating gates is addressed by an independent one of the plurality of control lines.

76. The method of claim 42, wherein forming each floating gate includes forming a horizontally oriented floating gate in a trench below a top surface of each pillar such that each trench houses a floating gate opposing the body regions in adjacent pillars on opposite sides of the trench, and wherein each horizontally oriented floating gate has a vertical length of less than 100 nanometers opposing the body region of the pillars.

77. The method of claim 42, wherein the forming the plurality of control gale lines includes forming the control gate lines such that the control gate lines are disposed vertically above the floating gates.

78. A method for forming an array of memory cells, comprising: forming a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; forming a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; forming a number of control gates opposing the floating gates; forming a number of busied sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells; forming a number of control gate lines formed integrally with the member of control gates along a second selected direction in the array of memory cells; separating the number of control gates lines from the floating gates by a low tunnel barrier intergate insulator having a tunnel barrier of less than 1.5 eV; forming a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of cells; and wherein forming each floating gate includes forming a vertical floating gate in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.

79. The array of memory cells of claim 77, wherein the memory cells include electronically alterable programmable read-only memory.

80. A method for forming an electronic system, comprising: providing a memory device including an array of memory cells formed by: forming a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; forming a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; forming a number of control gates opposing the floating gates; forming a number of buried sourcelines disposed below the number of pillars arid coupled to the first source/drain regions along a first selected direction in the array of memory cells; forming a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of memory cells separating the number of control gates lines from the floating gatos by a low tunnel barrier intergate insulator having a thickness of less than 20 Angstroms; forming a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of cells; and wherein forming each floating gate includes forming a vertical floating gate in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench; and connecting the memory device to a processor.

81. The method of claim 80, wherein separating the number of control gates lines from the floating gates by a low tunnel barrier intergate insulator includes separating the number of control gates lines from the floating gates by a low tunnel barrier intergate insulator having a tunnel barrier of less than 1.5 eV.

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Description

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FIELD OF THE INVENTION

The present invention relates generally to integrated circuits, and in particular to DEAPROM memory-with low tunnel barrier interpoly insulators which require refresh.

BACKGROUND OF THE INVENTION

Flash memories have become widely accepted in a variety of applications ranging from personal computers, to digital cameras and wireless phones. Both INTEL and AMD have separately each produced about one billion integrated circuit chips in this technology.

The original EEPROM or EARPROM and flash memory devices described by Toshiba in 1984 used the interpoly dielectric insulator for erase. (See generally, F. Masuoka et al. "A new flash EEPROM cell using triple polysilicon technology," IEEE Int. Electron Devices Meeting, San Francisco, pp. 464-67, 1984; F. Masuoka et al., "256 K flash EEPROM using triple polysilicon technology," IEEE Solid-State Circuits Conf., Philadelphia, pp. 168-169, 1985). Various combinations of silicon oxide and silicon nitride were tried. (See generally, S. Mori et al., "reliable CVD inter-poly dialectics for advanced E&EEPROM," Symp. On VLSI Technology, Kobe, Japan, pp. 16-17, 1985). However, the rough top surface of the polysilicon floating gate resulted in, poor quality interpoly oxides, sharp points, localized high electric fields, premature breakdown and reliability problems.

Widespread use of flash memories did not occur until the introduction of the ETOX cell by INTEL in 1988. (See generally, U.S. Pat. No. 4,780,424, "Process for fabricating electrically alterable floating gate memory devices," Oct. 25, 1988; B. Dipert and L. Hebert, "Flash memory goes mainstream," IEEE Spectrum, pp. 48-51, October, 1993; R. D. Pashley and S. K. Lai, "Flash memories, the best of two worlds," IEEE Spectrum, pp. 30-33, December 1989). This extremely simple cell and device structure resulted in high densities, high yield in production and low cost. This enabled the widespread use and application of flash memories anywhere a non-volatile memory function is required. However, in order to enable a reasonable write speed the ETOX cell uses channel hot electron injection, the erase operation which can be slower is achieved by Fowler-Nordhiem tunneling from the floating gate to the source. The large barriers to electron tunneling or hot electron injection presented by the silicon oxide-silicon interface, 3.2 eV, result in slow write and erase speeds even at very high electric fields. The combination of very high electric fields and damage by hot electron collisions in the oxide result in a number of operational problems like soft erase error, reliability problems of premature oxide breakdown and a limited number of cycles of write and erase.

Other approaches to resolve the above described problems include; the use of different floating gate materials, e.g. SiC, SiOC, GaN, and GaAIN, which exhibit a lower work function (see FIG. 1A), the use of structured surfaces which increase the localized electric fields (see FIG. 1B), and amorphous SiC gate insulators with larger electron affinity, .chi., to increase the tunneling probability and reduce erase time (see FIG. 1C).

One example of the use of different floating gate (FIG. 1A) materials is provided in U.S. Pat. No. 5,801,401 by L. Forbes, entitled "FLASH MEMORY WITH MICROCRYSTALLINE SILICON CARBIDE AS THE FLOATING GATE STRUCTURE." Another example is provided in U.S. Pat. No. 5,852,306 by L. Forbes, entitled "FLASH MEMORY WITH NANOCRYSTALLINE SILICON FILM AS THE FLOATING GATE." Still further examples of this approach are provided in pending applications by L. Forbes and K. Ahn, entitled "DYNAMIC RANDOM ACCESS MEMORY OPERATION OF A FLASH MEMORY DEVICE WITH CHARGE STORAGE ON A LOW ELECTRON AFFINITY GaN OR GaAIN FLOATING GATE," Ser. No. 08/908098, and "VARIABLE ELECTRON AFFINITY DIAMOND-LIKE COMPOUNDS FOR GATES IN SILICON CMOS MEMORIES AND IMAGING DEVICES," Ser. No. 08/903452.

An example of the use of the structured surface approach (FIG. 1B) is provided in U.S. Pat. No. 5,981,350 by J. Geusic, L. Forbes, and K. Y. Ahn, entitled "DRAM CELLS WITH A STRUCTURE SURFACE USING A SELF STRUCTURED MASK." Another example is provided in U.S. Pat. No. 6,025,627 by L. Forbes and J. Geusic, entitled "ATOMIC LAYER EXPITAXY GATE INSULATORS AND TEXTURED SURFACES FOR LOW VOLTAGE FLASH MEMORIES."

Finally, an example of the use of amorphous SiC gate insulators (FIG. 1C) is provided in U.S. patent application Ser. No. 08/903453 by L. Forbes and K. Ahn, entitled "GATE INSULATOR FOR SILICON INTEGRATED CIRCUIT TECHNOLOGY BY THE CARBURIZATION OF SILICON."

Additionally, graded composition insulators to increase the tunneling probability and reduce erase time have been described by the same inventors. (See, L. Forbes and J. M. Eldridge, "GRADED COMPOSITION GATE INSULATORS TO REDUCE TUNNELING BARRIERS IN FLASH MEMORY DEVICES," application Ser. No. 09/945514.

The authors of the present invention have also previously described the concept of a programmable read only memory which requires refresh or is volatile as a consequence of leakage currents though gate dielectrics with a low tunnel barrier between a floating gate and the silicon substrate/well, transistor source, drain, and body regions. (See generally, L. Forbes, J. Geusic and K. Ahn, "DEAPROM (Dynamic Electrically Alterable Programmable Read Only Memory) UTILIZING INSULATING AND AMORPHOUS SILICON CARBIDE GATE INSULATOR," application Ser. No. 08/902,843). An application relating to leakage currents through an ultrathin gate oxide has also been provided. (See generally, L. Forbes, E. H. Cloud, J. E. Geusic, P. A. Farrar, K. Y. Ahn, and A. R. Reinberg; and D. J. McElroy, and L. C. Tran, "DYNAMIC FLASH MEMORY CELLS WITH ULTRATHIN TUNNEL OXIDES," U.S. Pat. No. 6,249,460).

However, all of these approaches relate to increasing tunneling between the floating gate and the substrate such as is employed in a conventional ETOX device and do not involve tunneling between the control gate and floating gate through an inter-poly dielectric.

Therefore, there is a need in the art to provide improved DEAPROM cells which increase memory densities while avoiding the large barriers to electron tunneling or hot electron injection presented by the silicon oxide-silicon interface, 3.2 eV, which result in slow write and erase speeds even at very high electric fields. There is also a need to avoid the combination of very high electric fields and damage by hot electron collisions in the which oxide result in a number of operational problems like soft erase error, reliability problems of premature oxide breakdown and a limited number of cycles of write and erase. Further, when using an interpoly dielectric insulator erase approach, the above mentioned problems of having a rough top surface on the polysilicon floating gate which results in, poor quality interpoly oxides, sharp points, localized high electric fields, premature breakdown and reliability problems must be avoided.

SUMMARY OF THE INVENTION

The above mentioned problems with DEAPROM memories and other problems are addressed by the present invention and will be understood by reading and studying the following specification. Systems and methods are provided for DEAPROM memories with metal oxide and/or low tunnel barrier interpoly insulators which require refresh. That is, the present invention describes the use of an ultra-thin metal oxide inter-poly dielectric insulators between the control gate and the floating gate to create a memory cell which has a high current gain, and is easy to program by tunneling but which requires refresh. The low barrier tunnel insulator between the floating gate and control gates makes erase of the cell easy but results in the requirement for refresh. These devices act like DRAM's and can be utilized as DRAM replacements. A coincident address is achieved by addressing both the control gate address lines (y-address) and source address lines (x-address).

In one embodiment of the present invention, the DEAPROM memory includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator having a tunnel barrier of less than 1.5 eV. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of NiO, Al.sub.2 O.sub.3, Ta.sub.2 O.sub.5, TiO.sub.2, ZrO.sub.2, Nb.sub.2 O.sub.5, Y.sub.2 O.sub.3, Gd.sub.2 O.sub.3, SrBi.sub.2 Ta.sub.2 O.sub.3, SrTiO.sub.3, PbTiO.sub.3, and PbZrO.sub.3. The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator. And, the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1C illustrate a number of previous methods for reducing tunneling barriers in DEAPROM memory.

FIG. 2 illustrates one embodiment of a floating gate transistor, or DEAPROM memory cell, according to the teachings of the present invention.

FIG. 3 illustrates another embodiment of a floating gate transistor, or DEAPROM memory cell, according to the teachings of the present invention.

FIG. 4 is a perspective view illustrating an array of silicon pillars formed on a substrate as used in one embodiment according to the teachings of the present invention.

FIGS. 5A-5E are cross sectional views taken along cut line 5--5 from FIG. 4 illustrating a number of floating gate and control gate configurations which are included in the scope of the present invention.

FIGS. 6A-6D illustrate a number of address coincidence schemes can be used together with the present invention.

FIG. 7A is an energy band diagram illustrating the band structure at vacuum level with the low tunnel barrier interpoly insulator according to the teachings of the present invention.

FIG. 7B is an energy band diagram illustrating the band structure during an erase operation of electrons from the floating gate to the control gate across the low tunnel barrier interpoly insulator according to the teachings of the present invention.

FIG. 7C is a graph plotting tunneling currents versus the applied electric fields (reciprocal applied electric field shown) for an number of barrier heights.

FIG. 8 is an energy band diagram illustrating work function, tunnel barrier heights and electron affinities for a low tunnel barrier intergate insulator according to the teachings of the present invention.

FIG. 9 illustrates a block diagram of an embodiment of an electronic system according to the teachings of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. The embodiments are intended to describe aspects of the invention in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and changes may be made without departing from the scope of the present invention. In the following description, the terms wafer and substrate are interchangeably used to refer generally to any structure on which integrated circuits are formed, and also to such structures during various stages of integrated circuit fabrication. Both terms include doped and undoped semiconductors, epitaxial layers of a semiconductor on a supporting semiconductor or insulating material, combinations of such layers, as well as other such structures that are known in the art.

The term "horizontal" as used in this application is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term "vertical" refers to a direction perpendicular to the horizonal as defined above. Prepositions, such as "on", "side" (as in "sidewall"), "higher", "lower", "over" and "under" are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.

The present invention describes the use of an ultra-thin metal oxide inter-poly dielectric insulators having a tunnel barrier of less than 1.5 eV between the control gate and the floating gate. As shown in FIG. 2, the ultra-thin metal oxide inter-poly dielectric insulators having a tunnel barrier of less than 1.5 eV are used to create a memory cell which has a high current gain, and is easy to program by tunneling but which requires refresh. The low barrier tunnel insulator between the floating gate and control gates makes erase of the cell easy but results in the requirement for refresh. One possible array structure is shown in FIG. 6A, described in more detail below. These devices of the present invention act like DRAM's and can be utilized as DRAM replacements. In brief, FIG. 6A illustrates that a coincident address is achieved by addressing both the control gate address lines (y-address) and source address lines (x-address).

Also, as described in more detail below, FIG. 7A shows the conventional silicon oxide gate insulator with a high barrier and then the low tunnel barrier interpoly or intergate insulator between the floatin