Integrated circuit device and method of producing the same Number:7,084,507 from the United States Patent and Trademark Office (PTO) owispatent An integrated circuit device having vias having good resistance to migration causing the breaking of a wiring line, or an integrated circuit device having a wiring structure that is fined by breaking the limit of lithography technique is provided. The former device comprises a plurality of elements fabricated on a semiconductor substrate, wiring lines for making the elements and the integrated circuit device function, and vias for interconnecting wiring lines in separate layers, the via being formed of one or more cylindrical structures made up of carbon atoms. The latter device comprises a plurality of elements fabricated on a semiconductor substrate and wiring members for making the elements and the integrated circuit device function, at least part of the wiring members being formed of one or more cylindrical structures made up of carbon atoms. The latter device is preferably manufactured by a method comprising using a CVD process for the formation of the cylindrical structures, while applying a direct current electric field so as to grow the cylindrical structures in one direction, or applying an alternating current electric field so as to grow the cylindrical structures in two directions. A semiconductor device using a carbon nanotube and a method of forming a pattern using a carbon nanotube as a mask are also disclosed.<H Integrated, producing, Integrated, circ, 7084507.html, Patent, pto, 7084507

Title: Integrated circuit device and method of producing the same

Abstract: An integrated circuit device having vias having good resistance to migration causing the breaking of a wiring line, or an integrated circuit device having a wiring structure that is fined by breaking the limit of lithography technique is provided. The former device comprises a plurality of elements fabricated on a semiconductor substrate, wiring lines for making the elements and the integrated circuit device function, and vias for interconnecting wiring lines in separate layers, the via being formed of one or more cylindrical structures made up of carbon atoms. The latter device comprises a plurality of elements fabricated on a semiconductor substrate and wiring members for making the elements and the integrated circuit device function, at least part of the wiring members being formed of one or more cylindrical structures made up of carbon atoms. The latter device is preferably manufactured by a method comprising using a CVD process for the formation of the cylindrical structures, while applying a direct current electric field so as to grow the cylindrical structures in one direction, or applying an alternating current electric field so as to grow the cylindrical structures in two directions. A semiconductor device using a carbon nanotube and a method of forming a pattern using a carbon nanotube as a mask are also disclosed.

Patent Number: 7,084,507 Issued on 08/01/2006 to Awano

Inventors: Awano; Yuji (Kawasaki, JP)
Assignee: Fujitsu Limited (Kawasaki, JP)

Appl. No.: 10/107,480

Filed: March 28, 2002

Foreign Application Priority Data


May 02, 2001 [JP]			2001-135322
Sep 11, 2001 [JP]			2001-275089
Oct 01, 2001 [JP]			2001-305566

Current U.S. Class: 257/773 ; 257/734; 257/746; 977/762; 977/765; 977/766

Current International Class: H01L 23/48 (20060101)

Field of Search: 257/25,23,24,27,777,734,746,773 977/762,765,766

References Cited [Referenced By]

U.S. Patent Documents


6040248	March 2000	Chen et al.
6297063	October 2001	Brown et al.
6314019	November 2001	Kuekes et al.
6340822	January 2002	Brown et al.
6465813	October 2002	Ihm
6515339	February 2003	Shin et al.
6566704	May 2003	Choi et al.
2001/0023986	September 2001	Mancevski
2002/0158342	October 2002	Tuominen et al.
2002/0167375	November 2002	Hoppe et al.
2003/0179559	September 2003	Engelhardt et al.

Foreign Patent Documents


7-122198	May., 1995	JP
11-274470	Oct., 1999	JP
2002-1182468	Apr., 2002	JP
2003-17508	Jan., 2003	JP
2003-523608	Aug., 2003	JP

Other References

Kreupl et al., Carbon nanotubes in interconnect applications, Microelectronic Engineering, 64 (Oct. 2002) 399. cited by examiner .
Li et al., Bottom-up approach for carbon nanotube interconnects, Appl. Phys. Lett., 82 (Apr. 2003) 2491. cited by examiner .
Nihei et al., Simultaneous formation of multiwall carbon nanotubes and their end-bonded ohmic contacts to Ti electrodes for future ULSI interconnects, Japan. J. Appl. Phys., 43 (Apr. 2004) 1856. cited by exami- ner .
Japanese Office Action corresponding to Japanese Patent Application No. 2001-305566 dated Aug. 30, 2005. cited by other.

Primary Examiner: Smith; Bradley K.
Assistant Examiner: Menz; Douglas
Attorney, Agent or Firm: Staas & Halsey LLP

Claims

The invention claimed is:

1. An integrated circuit device comprising: a plurality of elements fabricated on a semiconductor substrate, wiring lines in separate layers of the integrated circuit device that enable the elements and the integrated circuit device to operate, an insulation layer formed between the layers of wiring lines, and vias interconnecting the wiring lines of different layers and the vias being located within openings in the insulation layer, each via being formed of one or more cylindrical structures made up of carbon atoms grown from one of the wiring lines, wherein the insulation layer surrounds the vias wherein each via is formed of a bundle of a plurality of cylindrical structures made up of carbon atoms, each cylindrical structure being constructed of a plurality of cylindrical bodies having different sizes and being arranged coaxially.

2. The integrated circuit device of claim 1, wherein each via is formed of a single cylindrical structure made up of carbon atoms.

3. The integrated circuit device of claim 1, wherein each via is formed of a plurality of cylindrical structures made up of carbon atoms.

4. The integrated circuit device of claim 1, wherein each of the one or more cylindrical structures is formed of a single cylindrical body.

5. The integrated circuit device of claim 1, wherein each of the one or more cylindrical structures is formed of a plurality of coaxially arranged cylindrical bodies.

6. The integrated circuit device of claim 2, wherein the single cylindrical structure is formed of a single cylindrical body.

7. The integrated circuit device of claim 2, wherein the single cylindrical structure is formed of a plurality of coaxially arranged cylindrical bodies.

8. The integrated circuit device of claim 3, wherein each of the cylindrical structures is formed of a single cylindrical body.

9. The integrated circuit device of claim 3, wherein each of the cylindrical structures is formed of a plurality of coaxially arranged cylindrical bodies.

10. The integrated circuit device of claim 3, wherein the plurality of cylindrical structures comprises, in combination, one or more cylindrical structures formed of a single cylindrical body and one or more cylindrical structures formed of a plurality of coaxially arranged cylindrical bodies.

11. The integrated circuit device of claim 1, wherein each bundle having the plurality of cylindrical structures comprises, in combination, one or more cylindrical structures formed of a single cylindrical body and one or more cylindrical structures formed of a plurality of coaxially arranged cylindrical bodies.

12. The integrated circuit device of claim 1, further comprising an insulation layer surrounding each via, the insulation layer being formed of a silicon-based insulation material or a porous material.

13. The integrated circuit device of claim 1, wherein a side of each via is exposed.

14. The integrated circuit device of claim 1, wherein some of the vias have a junction structure comprising a cylindrical structure with metallic properties and another cylindrical structure with semiconductor properties.

15. The integrated circuit device of claim 1, further comprising components exhibiting metallic properties that are located either in the one or more cylindrical structures or between neighboring ones of the one or more cylindrical structures, or are located both in the one or more cylindrical structures or between neighboring ones of the one or more cylindrical structures.

16. The integrated circuit device of claim 1, wherein each of the one or more cylindrical structures is a carbon nanotube.

17. The integrated circuit device of claim 1, wherein each wiring member is exposed.

18. An integrated circuit device comprising: a plurality of elements fabricated on a semiconductor substrate, wiring members enabling the elements and the integrated circuit device to operate, at least a part of the wiring members being formed of one or more cylindrical structures made up of carbon atoms, with some of the wiring members being horizontal to the semiconductor substrate, wherein each wiring member is formed of a bundle of a plurality of cylindrical structures made up of carbon atoms, each cylindrical structure being constructed of a plurality of cylindrical bodies having different sizes and being arranged coaxially; an insulation layer formed between the wiring members; and vias interconnecting the wiring members and formed in openings in the insulation layer, wherein the insulation layer surrounds the vias.

19. The integrated circuit device of claim 18, wherein each wiring member is formed of a single cylindrical structure made up of carbon atoms.

20. The integrated circuit device of claim 18, wherein each wiring member is formed of a plurality of cylindrical structures made up of carbon atoms.

21. The integrated circuit device of claim 18, wherein each of the one or more cylindrical structures is formed of a single cylindrical body.

22. The integrated circuit device of claim 18, wherein each of the one or more cylindrical structures is formed of a plurality of coaxially arranged cylindrical bodies.

23. The integrated circuit device of claim 19, wherein the single cylindrical structure is formed of a single cylindrical body.

24. The integrated circuit device of claim 19, wherein the single cylindrical structure is formed of a plurality of coaxially arranged cylindrical bodies.

25. The integrated circuit device of claim 20, wherein each of the cylindrical structures is formed of a single cylindrical body.

26. The integrated circuit device of claim 20, wherein each of the cylindrical structures is formed of a plurality of coaxially arranged cylindrical bodies.

27. The integrated circuit device of claim 20, wherein the plurality of cylindrical structures comprises, in combination, one or more cylindrical structures formed of a single cylindrical body and one or more cylindrical structures formed of a plurality of coaxially arranged cylindrical bodies.

28. The integrated circuit device of claim 18, wherein each bundle having the plurality of cylindrical structures comprises, in combination, one or more cylindrical structures formed of a single cylindrical body and one or more cylindrical structures formed of a plurality of coaxially arranged cylindrical bodies.

29. The integrated circuit device of claim 18, further comprising an insulation layer surrounding each wiring member, the insulation layer being formed of a porous material.

30. The integrated circuit device of claim 18, wherein part of the wiring members are exposed, and the remainder of the wiring members is embedded in an insulation material.

31. The integrated circuit device of claim 30, wherein the insulation material is porous.

32. The integrated circuit device of claim 18, wherein some of the wiring members have a junction structure comprising a cylindrical structure with metallic properties and another cylindrical structure with semiconductor properties.

33. The integrated circuit device of claim 18, wherein each of the one or more cylindrical structures is a carbon nanotube.

34. An integrated circuit device comprising: a plurality of elements fabricated on a semiconductor substrate, first and second layers of wiring lines enabling the elements and the integrated circuit device to operate; an insulation layer formed between the first and second layers of wiring lines, the insulation layer having an opening; and a via interconnecting the first and second layers of wiring lines and formed of one or more cylindrical structures made up of carbon atoms grown from one of the first and second layers of wiring lines, the via being located within the opening of the insulation layer, wherein the insulation layer surrounds the via, wherein the via is formed of a bundle of a plurality of cylindrical structures made up of carbon atoms, each cylindrical structure being constructed of a plurality of cylindrical bodies having different sizes and being arranged coaxially.

35. The integrated circuit device of claim 34, wherein the via is formed of a single cylindrical structure made up of carbon atoms.

36. The integrated circuit device of claim 34, wherein the via is formed of a plurality of cylindrical structures made up of carbon atoms.

37. The integrated circuit device of claim 34, wherein each of the one or more cylindrical structures is formed of a single cylindrical body.

38. The integrated circuit device of claim 34, wherein each of the one or more cylindrical structures is formed of a plurality of coaxially arranged cylindrical bodies.

39. The integrated circuit device of claim 35, wherein the single cylindrical structure is formed of a single cylindrical body.

40. The integrated circuit device of claim 35, wherein the single cylindrical structure is formed of a plurality of coaxially arranged cylindrical bodies.

41. The integrated circuit device of claim 36, wherein each of the cylindrical structures is formed of a single cylindrical body.

42. The integrated circuit device of claim 36, wherein each of the cylindrical structures is formed of a plurality of coaxially arranged cylindrical bodies.

43. The integrated circuit device of claim 36, wherein the plurality of cylindrical structures comprises, in combination, one or more cylindrical structures formed of a single cylindrical body and one or more cylindrical structures formed of a plurality of coaxially arranged cylindrical bodies.

44. The integrated circuit device of claim 34, wherein the bundle comprises, in combination, one or more cylindrical structures formed of a single cylindrical body and one or more cylindrical structures formed of a plurality of coaxially arranged cylindrical bodies.

45. The integrated circuit device of claim 34, wherein the insulation layer is formed of a silicon-based insulation material or a porous material.

46. The integrated circuit device of claim 34, wherein a side of the via is exposed.

47. The integrated circuit device of claim 34, wherein the via has a junction structure comprising a cylindrical structure with metallic properties and another cylindrical structure with semiconductor properties.

48. The integrated circuit device of claim 34, further comprising components exhibiting metallic properties that are located either in the one or more cylindrical structures or between neighboring ones of the one or more cylindrical structures, or are located both in the one or more cylindrical structures or between neighboring ones of the one or more cylindrical structures.

49. The integrated circuit device of claim 34, wherein each of the one or more cylindrical structures is a carbon nanotube.

50. An apparatus comprising: an integrated circuit including first and second layers of wiring lines, an insulation layer formed between the first and second layers of wiring lines, the insulation layer having an opening, and a via interconnecting the first and second layers of wiring lines and formed of one or more cylindrical structures made up of carbon atoms grown from one of the first and second layers of wiring lines, the via being located within the opening of the insulation layer, wherein the insulation layer surrounds the via wherein the via is formed of a bundle of a plurality of cylindrical structures made up of carbon atoms, each cylindrical structure being constructed of a plurality of cylindrical bodies having different sizes and being arranged coaxially.

51. The apparatus of claim 50, wherein the via is formed of a single cylindrical structure made up of carbon atoms.

52. The apparatus of claim 50, wherein the via is formed of a plurality of cylindrical structures made up of carbon atoms.

53. The apparatus of claim 50, wherein each of the one or more cylindrical structures is formed of a single cylindrical body.

54. The apparatus of claim 50, wherein each of the one or more cylindrical structures is formed of a plurality of coaxially arranged cylindrical bodies.

55. The apparatus of claim 51, wherein the single cylindrical structure is formed of a single cylindrical body.

56. The apparatus of claim 51, wherein the single cylindrical structure is formed of a plurality of coaxially arranged cylindrical bodies.

57. The apparatus of claim 52, wherein each of the cylindrical structures is formed of a single cylindrical body.

58. The apparatus of claim 52, wherein each of the cylindrical structures is formed of a plurality of coaxially arranged cylindrical bodies.

59. The apparatus of claim 52, wherein the plurality of cylindrical structures comprises, in combination, one or more cylindrical structures formed of a single cylindrical body and one or more cylindrical structures formed of a plurality of coaxially arranged cylindrical bodies.

60. The apparatus of claim 50, wherein the bundle comprises, in combination, one or more cylindrical structures formed of a single cylindrical body and one or more cylindrical structures formed of a plurality of coaxially arranged cylindrical bodies.

61. The apparatus of claim 50, wherein the insulation layer is formed of a silicon-based insulation material or a porous material.

62. The apparatus of claim 50, wherein a side of the via is exposed.

63. The apparatus of claim 50, wherein the via has a junction structure comprising a cylindrical structure with metallic properties and another cylindrical structure with semiconductor properties.

64. The apparatus of claim 50, further comprising components exhibiting metallic properties that are located either in the one or more cylindrical structures or between neighboring ones of the one or more cylindrical structures, or are located both in the one or more cylindrical structures or between neighboring ones of the one or more cylindrical structures.

65. The apparatus of claim 50, wherein each of the one or more cylindrical structures is a carbon nanotube.

66. An integrated circuit device comprising: a semiconductor substrate; a plurality of elements fabricated on the semiconductor substrate, wiring members enabling the elements and the integrated circuit device to operate, at least one of the wiring members being formed of one or more cylindrical structures made up of carbon atoms, with some of the wiring members being horizontal to the semiconductor substrate; an insulation layer formed between the wiring members; and a via interconnecting the wiring members and formed in an opening in the insulation layer, wherein the insulation layer surrounds the via, wherein each wiring member is formed of a bundle of a plurality of cylindrical structures made up of carbon atoms, each cylindrical structure being constructed of a plurality of cylindrical bodies having different sizes and being arranged coaxially.

67. The integrated circuit device of claim 66, wherein each wiring member is formed of a single cylindrical structure made up of carbon atoms.

68. The integrated circuit device of claim 66, wherein each wiring member is formed of a plurality of cylindrical structures made up of carbon atoms.

69. The integrated circuit device of claim 66, wherein each of the one or more cylindrical structures is formed of a single cylindrical body.

70. The integrated circuit device of claim 66, wherein each of the one or more cylindrical structures is formed of a plurality of coaxially arranged cylindrical bodies.

71. The integrated circuit device of claim 67, wherein the single cylindrical structure is formed of a single cylindrical body.

72. The integrated circuit device of claim 67, wherein the single cylindrical structure is formed of a plurality of coaxially arranged cylindrical bodies.

73. The integrated circuit device of claim 68, wherein each of the cylindrical structures is formed of a single cylindrical body.

74. The integrated circuit device of claim 68, wherein each of the cylindrical structures is formed of a plurality of coaxially arranged cylindrical bodies.

75. The integrated circuit device of claim 68, wherein the plurality of cylindrical structures comprises, in combination, one or more cylindrical structures formed of a single cylindrical body and one or more cylindrical structures formed of a plurality of coaxially arranged cylindrical bodies.

76. The integrated circuit device of claim 66, wherein each bundle comprises, in combination, one or more cylindrical structures formed of a single cylindrical body and one or more cylindrical structures formed of a plurality of coaxially arranged cylindrical bodies.

77. The integrated circuit device of claim 66, wherein the insulation layer is formed of a porous material.

78. The integrated circuit device of claim 66, wherein each wiring member is exposed.

79. The integrated circuit device of claim 66, wherein part of the wiring members are exposed, and the remainder of the wiring members is embedded in an insulation material.

80. The integrated circuit device of claim 79, wherein the insulation material is porous.

81. The integrated circuit device of claim 66, wherein some of the wiring members have a junction structure comprising a cylindrical structure with metallic properties and another cylindrical structure with semiconductor properties.

82. The integrated circuit device of claim 66, wherein each of the one or more cylindrical structures is a carbon nanotube.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to an integrated circuit device and, more particularly, to an integrated circuit device in which a cylindrical structure made up of carbon atoms is used as a material for a wiring member or a material for a via interconnecting wiring lines located in separate layers.

Also, the present invention relates to a semiconductor device, and in particular to a semiconductor device of a new type made up of a cylindrical multilayer structure or, typically, a new material called carbon nanotube.

Further, the present invention relates to a transistor, and in particular to a field effect transistor made of carbon nanotubes having metallic characteristics used as a gate material.

Furthermore, the present invention relates to a method of forming a micro pattern using carbon nanotubes as a masking material for dry etching.

2. Description of the Related Art

A half of a century has passed since the invention of the transistor, and remarkable progress has been made in semiconductor integrated circuits (semiconductor ICs) developed based on transistor technology, leading to large scale integrated circuits (LSIs) having ever greater integrity. With a current LSI, a phenomenon of movement of a metal atom of a wiring material, which is known as a migration phenomenon, is noted as a factor in loss of reliability of the LSI. This phenomenon can result in the breaking of a wiring line caused by stresses on the wiring metal material or electrons passing through the wiring line, and, in most cases, occurs particularly at a via for interconnecting wiring lines which must take a complex structure. The migration caused by stress is called stress migration, and that caused by electrons passing through a wiring is called electro-migration.

As a wiring material, copper (Cu) has recently started to be used in place of conventional aluminum (Al). Although the use of copper improves the migration resistance of a wiring to some extent, it is said that the migration resistance of a wiring line of copper, represented by a current density, is at most of the order of up to 10.sup.5 amperes per square centimeter. This critical value for the migration resistance has intimate relation to the capacity of heat dissipation of a wiring line, and it is known that the critical value is lowered in the case of poor heat dissipation or increased temperature.

On the other hand, providing semiconductor ICs having increased performance has been done according to the scaling rule of transistors. This approach would reach its limit sooner or later due to factors such as a limit of lithography technique. As a method for overcoming the limit of lithography technique, there is a technique of forming a fine structure using self-organizing. Currently, quantum dot devices and molecular devices using self-organizing, which are generally termed nano-devices, are energetically studied and, to enter an era in which such nano-devices are used as components in integrated circuits, wiring techniques for these devices must also be developed in parallel. Otherwise, the integrity of the nano-device is also forced to be determined by the limit of wiring technique.

On the other hand, since the invention of the transistor, it has progressed with various improvements. Taking as an example, the field effect transistor in which the channel region located between two regions including the source and the drain is formed as a current path of carriers and the electrical resistance of this channel is changed by the voltage of the gate electrode thereby to control the current flowing in the channel region, to meet the requirement of operation at higher speed and higher frequency, the gate length has been reduced and the carrier mobility of the channel material has increased greatly. The gate length has already been reduced to the order of 10 nm, which has posed many problems including the deteriorated matching accuracy due to fluctuations in lithography, an increased turn-off current of the transistor (short channel effect), a turn-on current saturation and an increased gate leakage current. Achieving a high dielectric constant of the gate insulating film has been studied as reliable means for solving some of these problems. On the other hand, an approach to improved current controlability of the gate has been conceived of by changing the gate structure of the transistor from the planar type currently employed to the three-dimensional type (e.g., what is called the surround gate structure).

In the surround gate structure, as shown in FIG. 9, a semiconductor channel layer (a p-type semiconductor layer in the case under consideration) 301 is surrounded by a gate electrode 302 like a coaxial cable. In this structure, the electric lines of force extending from the gate are prevented from escaping out of the channel, and therefore the current control efficiency is higher than that of the gate structure of planar type, thereby making a promising candidate for suppressing the short channel effect. In the semiconductor device shown in FIG. 9, reference numeral 303 designates a source electrode, numeral 304 a drain electrode, numeral 305 a high-concentration n-type semiconductor layer buried in a semiconductor substrate 309 for connecting the source electrode 303 and the channel 301, numeral 306 a high-concentration n-type semiconductor layer for connecting the drain electrode 304 and the channel 301, and numeral 307 an insulating material.

Nevertheless, the surround gate structure requires a cylindrical semiconductor layer extending upward of the substrate surface, which cannot be easily fabricated. For this reason, many problems still remain to be solved. For example, the threshold voltage (the gate voltage for turning off the current flowing in the transistor) is liable to vary from one transistor to another, and the control of impurities concentration by doping is difficult.

The various problems including the aforementioned ones are inherent to the conventional field effect transistors, or especially, those extremely micronized, and are a stumbling block to the development of a field effect transistor having superior characteristics which have yet to be realized.

Higher density of the semiconductor LSI has been promoted by the micro-fabrication technique of component semiconductor elements and wires. In the micro-fabrication of the semiconductor LSI, the first step is to etch a substrate using a resist patterned by lithography as a mask. A high resolution and a high etching durability are the characteristics required of the resist. In the conventional organic polymer resist, however, a pattern of the order of 10 nm, which is smaller than the polymer molecule, cannot be resolved. Also, insufficient resistance of the resist to dry etching makes it necessary to transfer the pattern to another film for etching.

The shortest gate length of the transistor so far reported is 8 nm for a transistor having a MOS structure fabricated by electron beam exposure. Since the resolution of the resist has almost reached a limit, however, the gate formed by this method has large gate size fluctuations and inferior linearity. This gate, therefore, is not suitable for practical applications. Generally, the reduction of gate length contributes most effectively to an improved high-speed and high-frequency performance of the transistor. Therefore, a technique for matching the gate to 10 nm or less with minimum fluctuations which replaces the use of resist is in great demand.

A HEMT (high electron mobility transistor) fabricated on an InP substrate is currently known as a high-frequency transistor of the highest performance. The HEMT of the highest performance reported by A. Endoh, et al. has a gate length of 25 nm with a cut-off frequency f.sub.T as high as about 400 GHz (A. Endoh et al., IPRM '01, pp.448 451 (2001)). with regard to the high-speed optical communication network, on the other hand, the TDM system having a communication speed of 40 Gbps is under development. As a future system, however, a communication speed of 160 Gbps is desired (FIG. 23). In such a case, the frequency f.sub.T four to five times as high as the communication speed is generally required as the characteristics of the electronic devices for communication of an optical modulation system. For the communication speed of 160 Gbps, for example, it is predicted that the frequency f.sub.T of 640 to 800 GHz is required. A certain correlationship is known between the frequency f.sub.T and the gate length of an electronic device, and is plotted as a graph in FIG. 24. In FIG. 24, the relation between the gate length so far realized and the corresponding frequency f.sub.T (the range indicated by solid line in FIG. 24) is extrapolated. It is thus seen that a gate length of less than 10 nm is required for obtaining the frequency f.sub.T of about 800 GHz. In this way, further reduction of the gate length is essential to meet the requirement of high-speed communication in the foreseeable future.

SUMMARY OF THE INVENTION

An object of the invention is to provide an integrated circuit device provided with vias having good resistance to migration causing the breaking of a wiring line, and having improved reliability.

Another object of the invention is to provide an integrated circuit device provided with a wiring structure that is fined by breaking the limit of lithography technique.

Still another object of the invention is to provide a semiconductor device of quite novel type, and in particular to a semiconductor device in which the short channel effect can be effectively suppressed, while making possible the high-speed and the high-frequency operation with a high current driving ability.

Yet another object of the invention is to provide a field effect transistor having a micro gate which is free of dimensional fluctuations to meet the demand for a gate reduced in size more than before.

A further object of the invention is to provide a method of forming a micro pattern whereby a micro structure including such a micro gate can be formed.

According to the invention, there is provided an integrated circuit device which is provided with vias having good migration resistance, the integrated circuit device comprising a plurality of elements fabricated on a semiconductor substrate, wiring lines for making the elements and the integrated circuit device function, and vias for interconnecting wiring lines in separate layers, wherein the via is formed of one or more cylindrical structures made up of carbon atoms.

There is also provided an integrated circuit device which is provided with a wiring structure that is fined by breaking the limit of lithography techniques, the integrated circuit device comprising a plurality of elements fabricated on a semiconductor substrate and wiring members for making the elements and the integrated circuit device function, wherein at least part of the wiring members are formed of one or more cylindrical structures made up of carbon atoms.

According to another aspect of the invention, there is provided a semiconductor device comprising a cylindrical multilayer structure configured of carbon elements, including an inner cylindrical member having semiconductor-like characteristics and an outer cylindrical member having metallic characteristics, in which the electric conductivity of the inner cylindrical member of the multilayer structure is controlled by the voltage applied to the outer cylindrical member.

More specifically, the semiconductor device according to the invention comprises a cylindrical multilayer structure configured of carbon elements including an inner cylindrical member having semiconductor-like characteristics and an outer cylindrical member having metallic characteristics, a pair of conductors arranged in opposed relation to each other with the outer cylindrical member in-between and connected to the opposed sides of the inner cylindrical member, respectively, and means for applying a voltage to the outer cylindrical member.

The basic configuration of the semiconductor device according to this invention is described above, and may take various forms as described in detail below.

According to still another aspect of the invention, there is provided a field effect transistor using a metallic carbon nanotube as a material for realizing a micro gate. Specifically, the field effect transistor according to the invention comprises a source for supplying carriers, i.e. electrons or holes contributing to electric conductivity in a semiconductor device such as a transistor, a drain for receiving the carriers, and a gate constituting a current control electrode for controlling the current flowing through a channel forming a current path between the source and the drain, by changing the conductivity of the channel, wherein the gate is formed of a metallic carbon nanotube.

According to yet another aspect of the invention, there is provided a method for forming a micro pattern free of dimensional variations by using the carbon nanotube as a mask for etching. Specifically, in the method of forming a micro pattern according to the invention, a carbon nanotube is arranged on a substrate, and using this carbon nanotube as a mask, the dry etching is carried out, so that the shape of the carbon nanotube is transferred to the substrate thereby to pattern the substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects and advantages of the invention will be well understood and appreciated by skilled persons in the art, from consideration of the following detailed description made by referring to the attached drawings, wherein:

FIG. 1 is an illustration showing an embodiment of the integrated circuit device of the invention provided with vias having good resistance to migration,

FIGS. 2A to 2D show the formation of the via in the integrated circuit device of FIG. 1,

FIG. 3 schematically shows a carbon nanotube containing fullerenes having a metal incorporated therein,

FIG. 4 schematically shows an integrated circuit device of the invention comprising wiring members formed of carbon nanotubes,

FIGS. 5A to 5D show the formation of carbon nanotube wiring members by a CVD process,

FIG. 6 is a schematic perspective view illustrating a three-dimensionally branched wiring structure,

FIGS. 7A to 7C illustrates different chiralities of carbon nanotubes,

FIG. 8 schematically shows a carbon nanotube having a metal-semiconductor junction,

FIG. 9 illustrates a semiconductor device having a surround gate structure,

FIG. 10 illustrates a basic configuration of a semiconductor device according to the invention,

FIGS. 11A and 11B illustrate an semiconductor device according to another embodiment of the invention,

FIG. 12 illustrates a semiconductor device according to still another embodiment of the invention,

FIGS. 13A and 13B illustrate a semiconductor device according to yet another embodiment of the invention,

FIGS. 14A to 14C illustrate the first half process of fabricating the semiconductor device shown in FIG. 11,

FIGS. 15A to 15C illustrate the second half process of fabricating the semiconductor device shown in FIG. 11,

FIGS. 16A to 16D illustrate the process of fabricating a semiconductor device having an insulating film interposed between the gate electrode and the carbon nanotube,

FIGS. 17A and 17B illustrate the process of fabricating a semiconductor device having a side wall of an insulating material on the side surface of the gate electrode shown in FIG. 12,

FIGS. 18A to 18C illustrate one part of the fabrication process of the semiconductor device shown in FIG. 13,

FIGS. 19A to 19C illustrate the next part of the fabrication process of the semiconductor device shown in FIG. 13,

FIGS. 20A and 20B illustrate the second next part of the fabrication process of the semiconductor device shown in FIG. 13,

FIGS. 21A and 21B illustrate the remaining part of the fabrication process of the semiconductor device shown in FIG. 13,

FIG. 22 is a plan view of a semiconductor device fabricated through the process shown in FIGS. 18 to 21,

FIG. 23 is a graph showing a prediction of the future speed of optical communication,

FIG. 24 is a graph showing the relation between the gate length and the cut-off frequency f.sub.T of an electronic device,

FIG. 25 illustrates a field effect transistor having the HEMT structure according to an embodiment of the invention,

FIG. 26 illustrates a conventional field effect transistor having the HEMT structure,

FIGS. 27A to 27C illustrate one part of the fabrication process of the conventional field effect transistor,

FIGS. 28A and 28B illustrate another part of the fabrication process of the conventional field effect transistor,

FIG. 29 illustrates the remaining part of the fabrication process of the conventional field effect transistor,

FIG. 30 is a top plan view schematically showing the conventional field effect transistor,

FIG. 31 is a perspective view illustrating the gate portion of a field effect transistor according to the invention,

FIGS. 32A and 32B illustrate a part of the method for fabricating the gate of a field effect transistor according to the invention,

FIG. 33 illustrates the remaining part of the method for fabricating the gate of the field effect transistor according to the invention,

FIGS. 34A and 34B illustrate another method of fabricating the gate of a field effect transistor according to the invention,

FIGS. 35A to 35C illustrate a part of the process for fabricating a field effect transistor having the HEMT structure according to another embodiment of the invention,

FIG. 36 illustrates the next part of the process for fabricating a field effect transistor having the HEMT structure according to the another embodiment of the invention,

FIG. 37 illustrates the second next part of the process for fabricating a field effect transistor having the HEMT structure according to the another embodiment of the invention,

FIG. 38 illustrates the remaining part of the process for fabricating a field effect transistor having the HEMT structure according to the another embodiment of the invention,

FIG. 39 is a graph showing the relation between the temperature and the width of the bottom surface of a V-groove observed in the case where the material is buried in the V-groove by MOCVD,

FIGS. 40A and 40B illustrate the first half of a method for forming a micro pattern according to the invention, and

FIGS. 41A and 41B illustrate the second half of a method for forming a micro pattern according to the invention.

DETAILED DESCRIPTION OF THE INVENTION

In the invention, a cylindrical structure made up of carbon atoms, which is a nano-structure based on self-organizing, is used as a material for wiring lines or vias in an integrated circuit device. Such nano-structures include a nano-structure generally known as a carbon nanotube.

Carbon nanotube is a new carbon-based material, to which attention has recently been paid because of its unique properties. Carbon nanotube has a structure of a cylindrically rolled graphite sheet in which carbon atoms are arranged in the form of united six-membered rings through the strongest bond of sp2, the end of the tube being closed by several six-membered rings accompanied with five-membered rings. Carbon nanotube can have a fined diameter of down to the order of sub-nanometer, with the minimum diameter being 0.4 nanometer. The physical properties of this material are only now being studied, and it is known that the material has a coefficient of thermal conductivity greater than that of diamond, a current density of approximately more than 10.sup.8 amperes per square centimeter, and a high Young's modulus.

For the formation of carbon nanotube, arc discharge or laser ablation are conventionally used. Recent study reports show that it is also possible to form carbon nanotube by a plasma or thermal CVD process. Although the method using arc discharge or laser ablation makes it possible to produce nanotubes having a high quality, it is not suitable for the production of integrated circuits. On the other hand, the method using a CVD process has feasibility for application to the production of integrated circuits.

The integrated circuit device according to the invention, which is provided with vias having good migration resistance, is characterized by using carbon nanotube as a via material. The carbon nanotube is preferably formed by a CVD process.

An embodiment of the integrated circuit device of the invention provided with vias having good migration resistance will now be illustrated making reference to FIG. 1, which shows the portion including a via in an integrated circuit device. In the device of this drawing, an underlying layer 11 is surmounted successively with a lower wiring layer 12, an insulation layer 13, and an upper wiring layer 14, the lower wiring layer 12 and the upper wiring layer 14 being interconnected by a via 15 piercing through the insulation layer 13 interposed therebetween. The via 15 is formed of a set of individual carbon nanotubes 16. The underlying layer 11 is commonly an insulation layer, and is located on a semiconductor substrate (not shown) or another wiring layer (not shown). The lower and upper wiring layer 12, 14 may be formed of any electrically conductive material, for example, a metal material such as copper or aluminum, or a laminate material comprising a layer of such a metal. The insulation layer 13 (also called an interlayer insulation layer) may be formed of a film of a silicon-based insulation material, which is commonly used at present, or of a film of a porous material or the like having a lower dielectric constant. In some cases, a so-called aerial wiring structure, in which the insulation layer 13 is eliminated, may be used.

Referring to FIG. 2, a method of forming vias shown in FIG. 1 is illustrated. As shown in FIG. 2A, on the lower wiring layer 12 provided on the underlying layer 11, the insulation layer 13 provided with an opening 17 having a pattern corresponding to the shape of a via to be formed is formed. In the drawing, a resist pattern for the formation of the patterned opening 17 is indicated by 13b. Subsequently, as shown in FIG. 2B, a catalyst 18 is deposited on the top face of the lower wiring layer 12 exposed at the bottom of the opening 17. As the catalyst 18, cobalt, nickel, iron or the like can be used. The deposition of the catalyst 18 can be carried out by a technique such as sputtering or evaporation, followed by lift-off of the resist pattern 13b. As shown in FIG. 2C, a via 15 consisting of a bundle of carbon nanotubes is grown within the opening 17 using the catalyst 18 by a plasma CVD or thermal CVD process. It is known that plasma CVD and thermal CVD are different from each other in growth mechanism. After the growth of carbon nanotubes, the catalyst 18 is left at the grown end of the nanotubes in the case of the plasma CVD, and is left at the root of the nanotubes (i.e., is left as it was at the bottom of the opening 17 as shown in FIG. 17B) in the case of thermal CVD. The via 15 shown in FIG. 2C represents one grown by plasma CVD. The upper wiring line 14 is then formed, the layer 14 being connected to the lower wiring layer 12 through the via 15, as shown in FIG. 2D. The lower and upper wiring layers 12, 14 and the insulation layer 13 may be formed by any known method in the art.

The catalyst 18 at the grown end of the via 15 shown in FIG. 2C may be removed prior to the formation of the upper wiring layer 14, or may be left as it is without removal thereof. In practice, the catalyst 18 at the grown end of the via 15 is located within each nanotube closed at its end by several six-membered rings of carbon atoms accompanied with five-membered rings. When the catalyst 15 is to be removed, a method such as one in which the portion of the five-membered ring, which has a weaker bond compared to the six-membered ring, is broken by oxygen plasma ashing or the like can be used.

It is known that a carbon nanotube may have a single layer structure or a multilayer structure. A nanotube of a single layer structure type is formed of one cylinder (one cylindrically rolled graphite sheet), and a nanotube of a multilayer structure type is formed of a plurality of cylinders, which have different diameters and arranged sequentially from the outermost to the innermost of the nanotube structure.

Thus, the via in the integrated circuit device of the invention may be formed of one or more cylindrical structures made up of carbon atoms, such as carbon nanotubes, the cylindrical structure being constructed of a single cylindrical body, such as a tube-like body, or of a plurality of cylindrical bodies having different sizes and arranged coaxially. Such a cylindrical structure, typically a carbon nanotube, used for the via of the integrated circuit device of the invention may be constructed of either a single cylindrical body or a plurality of coaxially arranged cylindrical bodies. Also, the via may include only one type of cylindrical structure constructed of a single cylindrical body and a plurality of cylindrical bodies, or a combination of both types of cylindrical structures.

In addition, the via in the integrated circuit device of the invention may be formed of one carbon nanotube, or a set of a plurality of nanotubes as referred to above.

The via in the integrated circuit device of the invention may be formed using a nanotube having a so-called pea-pod structure, in which a carbon nanotube is filled with nano-structures different therefrom, which exhibits metallic properties as a whole, such as a fullerene having a metal incorporated therein. FIG. 3 schematically shows a carbon nanotube 21 containing metal-incorporating fullerenes 22. Although a fullerene has a polyhedron structure consisting of five- and six-membered rings of carbon atoms, it is depicted in the form of a sphere in the drawing, for simplification. A metal incorporated in the fullerene 22 is not shown also for simplification. In addition, a carbon nanotube filled with a rod of metal, such as copper may be used, in place of fullerenes.

By using such a nanotube of pea-pod structure containing nano-structures different from the nanotube, it is possible to enhance the electrically conductive properties and the mechanical strength of a via. For example, in the case of a carbon nanotube containing metal-incorporating fullerene, it is known, from a first principle calculation, that the electrical charge of the incorporated metal appears at the outside of the fullerene, and further appears at the outside of the nanotube. In this case, the via accordingly has improved electrically conductive properties.

A nano-structure different from a carbon nanotube and exhibiting metallic properties as a whole, such as a metal-incorporating fullerene, or a molecule or atom also having such properties, may not be present in a nanotube, but be present between neighboring nanotubes forming a via. Also, it is possible to position such a nano-structure different from a carbon nanotube, or a molecule or atom having metallic properties, between neighboring nanotubes containing metal-incorporating fullerenes.

As a method of positioning metal-incorporating fullerenes in a carbon nanotube or between neighboring nanotubes, a method in which carbon nanotubes are exposed to an atmosphere containing metal-incorporating fullerenes can be referred to. The metal-incorporating fullerenes are sucked by a strong suction force which the carbon nanotube exhibits, to be positioned in place. In the case where fullerenes are to be positioned in a nanotube, it is necessary to open the end of the nanotube in advance by oxygen plasma ashing or the like.

The via of the integrated circuit device of the invention, which is made up of one or more carbon nanotubes, is characterized in that, among other things, (1) it has a high resistance to stress migration because a carbon nanotube has greater strength as a structure than that of a material currently used for a via, (2) it also has high resistance to electro-migration because a carbon nanotube has a strong bond between carbon atoms and low mobility of the atoms, (3) it has high heat dissipation efficiency because a carbon nanotube has the highest coefficient of thermal conductivity among existent materials, which is also useful as a measure against migration, (4) it allows a high-density current to pass therethrough, and (5) it may have a reduced sectional area because a carbon nanotube has a structure determined in a self-organizing manner.

The integrated circuit device according to the invention, which is provided with a wiring structure that is fined by breaking the limit of lithography techniques, is characterized by using wiring members formed of one or more cylindrical structures made up of carbon atoms. In this integrated circuit device, the carbon nanotube can also be preferably formed by a CVD process. The "wiring member" in the integrated circuit device includes wiring lines in a wiring layer formed on an insulation layer, vias piercing through an insulation layer and interconnecting wiring lines in wiring layers located on both sides of the insulation layer, and contacts connecting to a wiring line for interconnecting elements in the integrated circuit device. Part of the wiring members included in the integrated circuit device, such as wiring lines for connecting the integrated circuit device to an external circuit, may be formed of a conductive material other than carbon nanotube, such as a metal.

FIG. 4 schematically shows an integrated circuit device comprising wiring members formed of carbon nanotubes of a cylindrical structure made up of carbon atoms. In the device, elements, such as transistors 32, are fabricated in a silicon substrate 31, and a plurality of insulation layers (interlayer insulation layers) 33a 33f are formed over the elements. Wiring layers are located on both sides of an insulation layer, and a wiring line 35 in a certain wiring layer is connected to a wiring line 35 in another wiring layer through a via 36 piercing through the insulation layer. A contact connecting a wiring line 35' for interconnecting elements in the integrated circuit device is indicated by numeral 37. In the integrated circuit device shown in the drawing, all of wiring lines 35, 35', vias 36, and contacts 37 are formed of carbon nanotube. The top wiring layer is covered by a protective layer 38.

Referring to FIG. 5, the formation of carbon nanotube wiring members by a CVD process is illustrated. As described above, plasma CVD and thermal CVD are different from each other in growth mechanism, and at the end of the growth of carbon nanotubes, a catalyst used for the growth of the nanotubes is left at the grown end of the nanotubes in the case of plasma CVD, and is left at the root of the nanotubes in the case of thermal CVD. In the case illustrated in FIG. 5, carbon nanotubes are grown by plasma CVD and, accordingly, a catalyst is located at the end of a grown nanotube throughout the course of growth. In FIG. 5, however, the catalyst is not shown, for simplification. Also, in FIG. 5, carbon nanotubes are depicted in the form of a cylinder or a column, for simplification.

As shown in FIG. 5A, carbon nanotubes 43a are grown vertically and upward from electrode pads 42 provided on the top face of a substrate 41, by a plasma CVD process. A metal catalyst needed for the growth of the nanotube is positioned in advance at a predetermined location on the electrode pad 42.

It is known that to grow a carbon nanotube vertically from the face of a substrate by a CVD process, it is important that an electric field is present in the direction perpendicular to the face of the substrate. Thus, when the carbon nanotubes 43a are grown vertically and upward from the electrode pads 42, as shown in FIG. 5a, an electric field Ez is applied in the vertical direction, as shown in the drawing.

The carbon nanotube 43a is then opened at its grown end containing and covering the metal catalyst by oxygen plasma ashing, to thereby expose the catalyst metal, after which plasma CVD is continued to growth carbon nanotubes 43b while applying an electric field Ex(t) in the horizontal direction, as shown in FIG. 5B. In contrast to the electric field Ez applied in the step at FIG. 5A, which is a direct current electric field since the nanotubes 43a are grown in one direction, i.e., vertically and upward, the electric filed Ex(t) applied in the step of FIG. 5B is a alternating current electric field. As a result, in the step of FIG. 5B, the carbon nanotubes 43b are grown horizontally in two opposed directions starting from the end of the vertically grown nanotube 43a, at which the metal catalyst is exposed by the oxygen plasma ashing. The metal catalyst exposed prior to the application of the AC electric field is divided into two after the application of the AC electric field, each of which moves together with the grown end of the nanotube 43b in one of the two opposed directions. Although the grown nanotube illustrated in FIG. 5B is in the shape of a T as a whole because of the AC electric field applied parallel to the substrate 41, the shape of the grown nanotube is not limited only to the shape of a T. For example, by appropriate control of an applied electric field, such as by use of direction of an applied AC electric field other than horizontal, or application of an offset DC electric field. any possible three-dimensional an shape of carbon nanotube, such as Y- or .uparw.-shape, may be formed. Also, by the application of a horizontal DC electric field, a carbon nanotube in the form of a reversed L-shape can be formed.

The wiring member in the integrated circuit device of the invention may be formed of a single carbon nanotube or a set of a plurality of nanotubes. The carbon nanotube may have a single-layer structure or a multilayer structure. When a wiring member is formed of a plurality of nanotubes, the wiring member may be comprised of a combination of nanotubes having a single-layer structure and a multilayer structure, or only nanotubes having either a single-layer structure or a multilayer structure.

When the growth of carbon nanotubes in the horizontally opposed two directions is continued, the ends of the carbon nanotubes 43b grown from the ends of neighboring vertically grown nanotubes 43a so as to go near to each other may come into contact, as shown in FIG. 5C. At this point, if an AC electric field Ey(t) having an application direction perpendicular to the applying direction of the AC electric field Ex(t), as shown in FIG. 5D, carbon nanotubes 43c then start growing in the direction perpendicular to the growing direction of the previously grown carbon nanotubes 43b, in the same plane.

By repeating the vertical and horizontal growing steps described above, a three-dimensionally branched wiring structure can be readily formed. FIG. 6 illustrates a three-dimensionally branched wiring structure 48 formed on a substrate 41 by so repeatedly changing the directions of the applied electric field.

Such a three-dimensionally branched wiring structure may be formed not only by the plasma CVD process as earlier described but also a thermal CVD process, or by the use of a combination of a plasma CVD process and a thermal CVD process. For example, the three-dimensionally branched wiring structure 48 shown in FIG. 6 can be obtained by first forming vertical carbon nanotubes 43a' on the substrate 41 by a plasma CVD process while applying a vertical electric field, and then switching from the plasma CVD process to a thermal CVD process and continuing the growth of nanotubes by the thermal CVD process while alternately applying a horizontal AC electric field and a vertical DC electric field. In this case, a metal catalyst (not shown) for the growth of nanotube is left at the grown end of the nanotube 41a' formed by the first plasma CVD process.

As described, in the invention, a plasma or thermal CVD process is used for both the formation of vias having good resistance to migration and the construction of a wiring structure that is fined beyond the limit of lithography techniques. Although such a CVD technique is well known, and no explanation thereof is needed herein, reference can be made to a plasma CVD process carried out by feeding methane (CH.sub.4) and hydrogen (H.sub.2) gases at about 400 to 650.degree. C. and under an applied electric field and vacuum, and a thermal CVD process carried out by feeding acetylene (C.sub.2H.sub.2) and hydrogen gases also at about 400 to 650.degree. C. under an applied electric field and vacuum, by way of example. In both cases, a metal, such as cobalt, iron, or nickel, is used as a catalyst.

In FIGS. 5 and 6, no insulation layers are shown. Such a wiring structure having no insulation layer, which represents a so-called aerial wiring structure, has been proposed as an ultimate means for lowering the dielectric constant of an interlayer insulation film. Carbon nanotube has very high mechanical strength, so that the integrated circuit device of the invention using carbon nanotube as a material for wiring members is suited to have an aerial wiring structure in which the wiring members are not surrounded with an insulation layer and are exposed. In the aerial wiring structure, it is preferred to use a multi-wall nanotube which is superior in mechanical strength. Nonetheless, the integrated circuit device of the invention using