Integrated circuit including programmable logic and external-device chip-enable override control Number:7,521,960 from the United States Patent and Trademark Office (PTO) owispatent

Title: Integrated circuit including programmable logic and external-device chip-enable override control

Abstract: An integrated circuit device includes a programmable logic block, a monitoring input, a condition-sensing circuit coupled to the monitoring input and configured to generate a condition-sensed signal at an output in response to sensing a condition at the monitoring input, a first digital input, a first digital output, and a gating circuit configured in the programmable logic block and coupled between the first digital input and the first digital output. The gating circuit has a gating input coupled to the condition-sensing circuit and generates an output. The output is related to an input state of the first digital input in the absence of the condition-sensed signal and assumes an override state in the presence of the condition-sensed signal.

Patent Number: 7,521,960 Issued on 04/21/2009 to Balasubramanian,   et al.

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Inventors:	Balasubramanian; Rabindranath (Dublin, CA), Kolkind; Kurt (Truckee, CA), Bakker; Gregory (San Jose, CA)
Assignee:	Actel Corporation (Mountain View, CA)
Appl. No.:	11/932,901
Filed:	October 31, 2007

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Related U.S. Patent Documents

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	Application Number	Filing Date	Patent Number	Issue Date
	11279046	Apr., 2006	7362131
	10877045	Jun., 2004	7030649
	60491788	Jul., 2003

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Current U.S. Class:	326/38 ; 326/32; 326/33; 326/39
Current International Class:	H03K 19/173 (20060101)
Field of Search:	326/38-41 710/100

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Primary Examiner: Tan; Vibol
Attorney, Agent or Firm: Lewis and Roca LLP

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Parent Case Text

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CLAIM FOR PRIORITY

This application is a Divisional of U.S. patent application Ser. No. 11/279,046, filed Apr. 7, 2006, which is a Continuation of U.S. patent application Ser. No. 10/877,045, filed Jun. 25, 2004 now issued as U.S. Pat. No. 7,030,649, which claims priority from U.S. Provisional Patent application Ser. No. 60/491,788, filed Jul. 31, 2003.

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Claims

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What is claimed is:

1. A method for using a programmable system-on-a-chip including digital and analog circuits to send signals to off-chip integrated circuits in an electronic system comprising: performing a power-up sequence in the system-on-a-chip including: sensing that power supply voltage is ramping up; determining that a band-gap circuit in the system-on-a-chip is outputting correct reference voltage; determining that a first voltage regulator circuit in the system-on-a-chip is outputting correct reference voltage; determining that an FPGA circuit in the system-on-a-chip is functioning; determining that a non-volatile memory circuit in the system-on-a-chip is functioning; determining that a second voltage regulator circuit in the system-on-a-chip is outputting correct reference voltage; determining that a reference voltage to an analog-to-digital converter circuit in the system-on-a-chip is outputting correct reference voltage; calibrating the analog-to-digital converter circuit; initializing and configuring a state machine in the system-on-a-chip; and monitoring at least one condition of the electronic system.

2. The method of claim 1 wherein determining that the FPGA circuit in the system-on-a-chip is functioning comprises: determining that the FPGA circuit has become active; and outputting a signal indicating that the FPGA circuit has become active.

3. The method of claim 1 wherein determining that the non-volatile memory circuit in the system-on-a-chip is functioning comprises: determining that the non-volatile memory circuit has become active; and outputting a signal indicating that the non-volatile memory circuit has become active.

4. The method of claim 1 wherein monitoring at least one condition of the electronic system comprises: sampling a condition of the electronic system to create a condition value; converting the condition value to a digital condition value; comparing the digital condition value to a predetermined threshold; and sending a signal to at least one off-chip integrated circuit if the digital condition value exceeds the predetermined threshold.

5. The method of claim 4 wherein sampling a condition of the electronic system to create a condition value comprises: sampling a voltage powering a circuit external to the system-on-a-chip; creating a first condition value if the voltage is within a predetermined specification; creating a second condition value if the voltage is not within the predetermined specification; enabling a drive signal to the circuit external to the system-on-a-chip in response to the first condition value; and disabling the drive signal to the circuit external to the system-on-a-chip in response to the second condition value.

6. The method of claim 5 further comprising: continuing to sample the voltage powering the circuit external to the system-on-a-chip after disabling the drive signal to the circuit external to the system-on-a-chip in response to the second condition value; enabling the drive signal to the circuit external to the system-on-a-chip in response to recurrence of the first condition value.

7. The method of claim 6 wherein enabling the drive signal to the circuit external to the system-on-a-chip in response to recurrence of the first condition value comprises enabling the drive signal only after the first condition value has recurred for a predetermined time.

8. The method of claim 5 wherein: sampling a voltage powering a circuit external to the system-on-a-chip comprises sampling a voltage supplied to an external MOSFET; enabling a drive signal to the circuit external to the system-on-a-chip in response to the first condition value comprises supplying a voltage to the gate of the external MOSFET sufficient to turn it on; and disabling the drive signal to the circuit external to the system-on-a-chip in response to the second condition value comprises supplying a voltage to the gate of the external MOSFET sufficient to turn it off.

9. The method of claim 5 further including disabling the drive signal to the circuit external to the system-on-a-chip in response to an external reset signal applied to the system-on-a-chip.

10. The method of claim 9 further including providing a reset-out signal from the system-on-a-chip in response to the external reset signal applied to the system-on-a-chip.

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Description

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BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to integrated circuits. More particularly, the present invention relates to a device including a gating circuit configured in a programmable logic block coupled between an input and an output, a monitoring circuit, a condition-sensing circuit coupled to the monitoring input and the gating circuit to produce an override state in the presence of a sensed condition.

2. Background

Field-programmable gate array (FPGA) integrated circuits are known in the art. An FPGA comprises any number of logic modules, an interconnect-routing architecture and programmable elements that may be programmed to selectively interconnect the logic modules to one another and to define the functions of the logic modules. To implement a particular circuit function, the circuit is mapped into the array and the appropriate programmable elements are programmed to implement the necessary wiring connections that form the user circuit.

An FPGA includes an array of general-purpose logic circuits, called cells or logic blocks, whose functions are programmable. Programmable buses link the cells to one another. The cell types may be small multifunction circuits (or configurable functional blocks or groups) capable of realizing Boolean functions of multiple variables. The cell types are not restricted to gates. For example, configurable functional groups typically include memory cells and connection transistors that may be used to configure logic functions such as addition, subtraction, etc., inside of the FPGA. A cell may also contain a plurality of flip-flops. Two types of logic cells found in FPGA devices are those based on multiplexers and those based on programmable read only memory (PROM) table-lookup memories. Erasable FPGAs can be reprogrammed many times. This technology is especially convenient when developing and debugging a prototype design for a new product and for small-scale manufacture.

An FPGA circuit can be programmed to implement virtually any set of digital functions. Input signals are processed by the programmed circuit to produce the desired set of outputs. Such inputs flow from the user's system, through input buffers and through the circuit, and finally back out the user's system via output buffers referred to as input/output ports (I/Os). Such buffers provide any or all of the following input/output (I/O) functions: voltage gain, current gain, level translation, delay, signal isolation or hysteresis. The input/output ports provide the access points for communication between chips. I/O ports vary in complexity depending on the FPGA.

Recent advances in user-programmable interconnect technology have resulted in the development of FPGAs which may be customized by a user to perform a wide variety of combinatorial and sequential logic functions. Numerous architectures for such integrated circuits are known. Examples of such architectures are found disclosed in U.S. Pat. No. 4,870,302 to Freeman, U.S. Pat. No. 4,758,745 to El Gamal et al., and U.S. Pat. No. 5,132,571 to McCollum et al. The architecture employed in a particular FPGA integrated circuit will determine the richness and density of the possible interconnections that can be made among the various circuit elements disposed on the integrated circuit and thus profoundly affect its usefulness.

Traditionally, FPGAs and other programmable logic devices (PLDs) have been limited to providing digital logic functions programmable by a user. Recently, however, FPGA manufacturers have experimented with adding application specific integrated circuit (ASIC) blocks onto their devices (See, e.g., U.S. Pat. No. 6,150,837). Such ASIC blocks have included analog circuits (see U.S. Pat. No. 5,821,776). In addition, ASIC manufacturers have embedded programmable logic blocks in their devices to add programmable functionality to otherwise hardwired devices (See, e.g., devices offered (or formerly offered) by Triscend Corporation, Adaptive Silicon Inc., and Chameleon Systems.

Integrated circuits that sense whether a power supply voltage output falls below a fixed threshold voltage and provide microprocessor-related control functions are known in the art. As an example, the MAX 6365 and 6368 integrated circuits available from Maxim Integrated Products of Sunnyvale, Calif., employ dedicated circuitry that senses when a power-supply voltage has fallen below a fixed threshold value and take control of the commonly-employed reset and chip-enable signals that an interfaced microprocessor uses to communicate with other devices to which it is connected.

SUMMARY OF THE INVENTION

An integrated circuit device includes a programmable logic block, a monitoring input, a condition-sensing circuit coupled to the monitoring input and configured to generate a condition-sensed signal at an output in response to sensing a condition at the monitoring input, a first digital input, a first digital output, and a gating circuit configured in the programmable logic block and coupled between the first digital input and the first digital output. The gating circuit has a gating input coupled to the condition-sensing circuit and generates an output. The output is related to an input state of the first digital input in the absence of the condition-sensed signal and assumes an override state in the presence of the condition-sensed signal.

The conditions that may be sensed, and the actions that are overridden by the present invention vary widely according to the needs of a particular system design. In one disclosed illustrative embodiment, the digital input and output may be coupled to a chip-enable signal used, for example, to drive at least one semiconductor memory device. The sensing of a condition, such as an unstable supply voltage, may be used to override the chip-enable signal to inhibit performing a write operation in the at least one semiconductor memory device while the supply voltage is unstable. This will prevent the writing of corrupted data in to the at least one semiconductor memory device. A second digital input and output set may be provided to pass through a system reset signal for a system containing, for example, a microprocessor.

A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description of the invention and accompanying drawings, which set forth an illustrative embodiment in which the principles of the invention are utilized.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of one illustrative embodiment of a system-on-a-chip according to one aspect of the present invention.

FIG. 2 is a simplified diagram of a portion of an illustrative interconnect architecture that may be used to interconnect the inputs and outputs of the various circuit elements of the system-on-a-chip of FIG. 1 to form user circuit systems.

FIG. 3 is a block diagram of another illustrative embodiment of a system-on-a-chip that includes a volatile memory block such as an SRAM block.

FIG. 4 is a block diagram of another illustrative embodiment of a system-on-a-chip based on use of a highly successful flash FPGA architecture, for the programmable logic block.

FIG. 5 is a block diagram of another illustrative embodiment of a system-on-a-chip based on use of a flash FPGA architecture for the programmable logic block.

FIG. 6 is a schematic diagram of an illustrative glitchless clock multiplexer that is suitable for use in the SOC of the present invention.

FIG. 7 is a block diagram of a portion of the SOC of FIG. 5 showing analog I/O function circuits grouped into sets according to one illustrative embodiment of the present invention.

FIG. 8 is a diagram of a pre-scaler circuit that can scale external voltages by one of eight factors.

FIG. 9 is a diagram of an illustrative configuration for the amplifier of FIG. 7.

FIG. 10 is a diagram of an illustrative temperature monitor circuit that may be usefully employed in the analog I/O function circuit of FIG. 7.

FIG. 11 is a diagram of an illustrative gate drive circuit that may be usefully employed in the analog I/O function circuit of FIG. 7.

FIG. 12 is a diagram of an illustrative embodiment of internal interface circuits from FIG. 5 that are particularly useful for the SOC of the present invention.

FIG. 13 is a schematic diagram of an illustrative bandgap reference that may be used in the SOC of the present invention.

FIG. 14 is a more detailed diagram of the analog-to-digital converter shown in FIG. 5.

FIG. 15A is a power-up sequence state-machine flow chart showing a typical SOC internal power up sequence.

FIG. 15B is a timing diagram showing a typical SOC internal power up sequence.

FIG. 16 is a more detailed block diagram of the system supervisor master block from FIG. 5.

FIG. 17 is a diagram illustrating a portion of the power-up control circuit for performing functions early in the power-up sequence.

FIG. 18 is a block diagram of an integrated circuit including a conditional chip-enable override feature according to one aspect of the present invention.

FIG. 19 is a block diagram illustrating an exemplary system including the present invention.

DETAILED DESCRIPTION

Those of ordinary skill in the art will realize that the following description of the present invention is illustrative only and not in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons.

The term "system-on-a-chip" or "SOC" generally refers to an integrated circuit device that includes multiple types of integrated circuits on a single die, where the circuits are of types that have traditionally been constructed on separate silicon wafers.

An SOC 10 according to the present invention design is shown generally in a block-diagram architectural level drawing in FIG. 1, which shows its main components. As shown in FIG. 1, an illustrative embodiment of the present invention is a system-on-a-chip integrated circuit 10 that includes a programmable logic block 12, at least one non-volatile memory block 14, analog ASIC circuit blocks 16a through 16f, digital ASIC circuit blocks 18a through 18f, digital input/output ("I/O") circuit blocks 20 and analog I/O circuit blocks 22. ASIC refers to "application specific integrated circuits" and is used to refer to circuit blocks that are largely hardwired, in contrast to those that are programmable, writeable, or otherwise able to be modified or configured after manufacturing of the device. System-on-a-chip integrated circuit 10 also includes a system controller circuit block 24 and a clock circuit 26.

Programmable logic block 12 may be an FPGA array. FPGA arrays are well known in the art, and it is contemplated for purposes of the present invention that any type of FPGA circuit block may be employed in the system-on-a-chip integrated circuit 10 of the present invention. The number of data inputs and outputs and the number of implementable combinatorial and sequential logic functions will depend on the particular design of FPGA circuit used in the FPGA array. Persons of ordinary skill in the art will appreciate that other programmable logic blocks such as complex programmable logic devices (CPLD) and other programmable logic blocks may be used in the present invention.

Non-volatile memory block 14 may be formed from an array of, as a non-limiting example, flash memory cells and a memory controller for the array. Flash memory cells are well known in the art and the present invention is not limited to use of any particular kind of flash memory cells or other non-volatile memory technology, such as nanocrystal, SONOS, solid-electrolyte switching devices, and other types as will be appreciated by persons of ordinary skill in the art. Persons of ordinary skill in the art will appreciate that, in some embodiments of the present invention, non-volatile memory block 14 may be segmented into a plurality of separately addressable arrays, each with its own memory controller. The number of data inputs and outputs and address inputs will depend on the size of the array used.

Analog ASIC circuit blocks 16a through 16f are illustrated in FIG. 1, although persons of ordinary skill in the art will observe that the provision of six analog ASIC circuit blocks 16a through 16f in FIG. 1 is merely illustrative and in no way limiting. Actual embodiments of system-on-a-chip integrated circuits according to the present invention may have an arbitrary number of analog ASIC circuit blocks. Analog ASIC circuit blocks 16a through 16f may alternatively be described as "hardwired," "mask programmable," or "ASIC" circuits or circuit blocks. These analog blocks are also referred to as "analog peripherals," and may include, as non-limiting examples, a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), an Analog Pulse Width Modulator (PWM), a MOSFET Controller, a Voltage Reference circuit, a Low-dropout (LDO) regulator, an Analog multiplexer (MUX), or an RF Transceiver. In addition to the more general-purpose types of analog blocks described above, stand alone analog circuit blocks for more specific functions may be provided, as described above. For example, a stand-alone hardwired current monitor, a stand-alone hardwired temperature monitor, or a stand-alone hardwired voltage monitor may be provided. Stand-alone hard analog blocks may include I/O circuits.

Embedded analog peripherals may also be used to enhance generic microcontroller ("MCU") functions with a programmable "soft" processor core programmed into the programmable logic block. As will be appreciated by persons of ordinary skill in the art, the numbers and kinds of inputs and outputs of the individual analog ASIC circuit blocks 16a through 16f will depend on the functional nature of the circuits employed.

Digital ASIC circuit blocks 18a through 18f are illustrated in FIG. 1, although persons of ordinary skill in the art will observe that the provision of six digital ASIC circuit blocks 18a through 18f in FIG. 1 is merely illustrative and in no way limiting. Actual embodiments of system-on-a-chip integrated circuits according to the present invention may have an arbitrary number of digital ASIC circuit blocks. Digital ASIC circuit blocks 18a through 18f may comprise circuit blocks such as, but not limited to, state machines, analog sequencers, microprocessors,digital signal processors DSP("s"). Hard digital blocks are especially useful to implement interfaces such as the interface between the programmable logic and the memory blocks on a device. The FPGA/Memory interface is described in more detail in the section describing the non-volatile memory controller. Hard digital blocks may also be used to implement interfaces between the programmable logic or the memory blocks and hard analog blocks. A hard digital block is used as a control block for the non-volatile memory block. The non-volatile memory controller is described in more detail herein.

Such digital blocks may be implemented in a similar manner to the way in which such digital blocks are implemented in current application-specific integrated circuits ("ASICs"). In addition to being implemented as hard digital circuit blocks, all, or a portion of each of these types of blocks may be implemented in programmable logic, sometimes referred to as "soft" implementations. As will be appreciated by persons of ordinary skill in the art, the numbers and kinds of inputs and outputs of the individual digital ASIC circuit blocks 18a through 18f will depend on the functional nature of the circuits employed.

System-on-a-chip integrated circuit 10 also includes digital I/O circuit blocks 20. Digital I/O circuit blocks 20 may comprise conventional digital I/O circuitry, such as that commonly employed in known FPGA and similar integrated circuits.

System-on-a-chip integrated circuit 10 also includes analog I/O circuit blocks 22. Analog I/O circuit blocks 22 may comprise any of the many analog buffer circuits that are well known in the art.

System-on-a-chip integrated circuit 10 also includes a system controller circuit block 24. A system controller circuit block 24 provides master control functionality for the other blocks in the SOC device, including managing power up sequencing and inter-operation of the various components of the system on a chip. In addition, the system controller 24 may control off-chip devices via signals output via the digital or analog I/Os of the device of the present invention such as reset and enable signals. The system controller 24 includes various circuits for managing the different functions of the SOC device. In some embodiments, these circuits may all be implemented in hardwired circuit blocks, while in other embodiments, some of the circuits may be implemented in a portion of the programmable logic of the programmable logic block 12. An advantage of implementing control functions in programmable logic is that the user is able to adapt the control functions to the user's application. This is especially useful if the user wishes to employ the programmable system on a chip device to control elements of the user's system that are outside the system on a chip device.

In the embodiment of a system controller shown in FIG. 1, a portion of the system controller's circuits are implemented in hardwired blocks, and a portion are implemented in programmable logic. The system controller 24 shown in FIG. 1 includes a power-up control circuit, an analog power supply circuit, a voltage reference circuit, and a system supervisor circuit. The power-up control circuit includes circuitry for managing the SOC device during power-up, as will be described in more detail below.

System-on-a-chip integrated circuit 10 also includes a clock circuit 26. Clock circuit 26 may include one or more clock sources and clock-signal-distribution systems. The number of such clocks provided on any system-on-a-chip integrated circuit fabricated according to the present invention is a matter of design choice. Such circuits and systems are well known in the art.

The inputs and outputs of the various circuit elements of the programmable logic block 12, a non-volatile memory block 14, analog ASIC circuit blocks 16a through 16d, digital ASIC circuit blocks 18a through 18d, digital input/output ("I/O") circuit blocks 20 and analog I/O circuit blocks 22, system controller circuit block 24 and clock circuit 26 may be connected together by a user by programmably connecting together their various inputs and outputs through a network of programmable interconnect conductors that is provided on the system-on-a-chip integrated circuit.

A simplified diagram of a portion of an illustrative programmable interconnect architecture that may be employed with the system-on-a-chip integrated circuit of FIG. 1 is shown in FIG. 2. FIG. 2 illustrates a portion of an illustrative interconnect architecture. Persons of ordinary skill in the art will understand that FIG. 2 is largely schematic and simplified in nature, and in no way limits the present invention to the particular interconnect architecture depicted.

As can be seen from an examination of FIG. 2, an illustrative interconnect architecture that can be implemented with the present invention may include interconnect conductors that run in horizontal and vertical directions in metal interconnect layers disposed over the surface of the silicon die comprising the system-on-a-chip integrated circuit 10. Both the horizontal and vertical interconnect conductors may be segmented to allow versatility in forming interconnect between inputs and outputs of the various circuit elements disposed in system-on-a-chip integrated circuit 10 of FIG. 1. As is known in the art, the various interconnect conductors may be of varying lengths or may be segmented into varying lengths.