Integrated clock generator and timing/frequency reference Number:7,365,614 from the United States Patent and Trademark Office (PTO) owispatent In various embodiments, the invention provides a clock generator and/or a timing and frequency reference using an LC-oscillator topology, having a frequency controller to control and provide a stable resonant frequency, which is integrated with other, second circuitry such as a processor or controller. Frequency stability is provided over variations in a selected parameter such as temperature and fabrication process variations. The various apparatus embodiments include a sensor adapted to provide a signal in response to at least one parameter of a plurality of parameters; and a frequency controller adapted to modify the resonant frequency in response to the second signal. In exemplary embodiments, the sensor is implemented as a current source responsive to temperature fluctuations, and the frequency controller is implemented as a plurality of controlled reactance modules which are selectively couplable to the resonator or to one or more control voltages. The controlled reactance modules may include fixed or variable capacitances or inductances, and may be binary weighted. Arrays of resistive modules are also provided, to generate one or more control voltages.<H Integrated, reference, Integrated, cloc, 7365614.html, Patent, pto, 7365614

Title: Integrated clock generator and timing/frequency reference

Abstract: In various embodiments, the invention provides a clock generator and/or a timing and frequency reference using an LC-oscillator topology, having a frequency controller to control and provide a stable resonant frequency, which is integrated with other, second circuitry such as a processor or controller. Frequency stability is provided over variations in a selected parameter such as temperature and fabrication process variations. The various apparatus embodiments include a sensor adapted to provide a signal in response to at least one parameter of a plurality of parameters; and a frequency controller adapted to modify the resonant frequency in response to the second signal. In exemplary embodiments, the sensor is implemented as a current source responsive to temperature fluctuations, and the frequency controller is implemented as a plurality of controlled reactance modules which are selectively couplable to the resonator or to one or more control voltages. The controlled reactance modules may include fixed or variable capacitances or inductances, and may be binary weighted. Arrays of resistive modules are also provided, to generate one or more control voltages.

Patent Number: 7,365,614 Issued on 04/29/2008 to McCorquodale, et al.

Inventors: McCorquodale; Michael Shannon (Detroit, MI), Pernia; Scott Michael (Pinckney, MI), Kubba; Sundus (Saline, MI), O'Day; Justin (Detroit, MI), Carichner; Gordon (Saline, MI)
Assignee: Mobius Microsystems, Inc. (Sunnyvale, CA)

Appl. No.: 11/384,758

Filed: March 20, 2006

Related U.S. Patent Documents


Application Number	Filing Date	Patent Number	Issue Date
11232407	Sep., 2005
11084962	Mar., 2005	7227423
11085372	Mar., 2005	7227424
11084962	Mar., 2005	7227424
60555193	Mar., 2004
60555193	Mar., 2004

Current U.S. Class: 331/179 ; 331/117FE

Current International Class: H03B 5/12 (20060101)

Field of Search: 331/1A,2,8,10,11,16-18,25,36C,36L,57,117R,117FE,117D,173,175,177R,177V,179,DIG.2

References Cited [Referenced By]

U.S. Patent Documents


7227423	June 2007	McCorquodale et al.

Primary Examiner: Mis; David
Attorney, Agent or Firm: Gamburd; Nancy R. Gamburd Law Group LLC

Parent Case Text

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation-in-part of and claims priority to McCorquodale, Michael S. et al., U.S. patent application Ser. No. 11/232,407, filed Sep. 20, 2005, entitled "Frequency Controller for a Monolithic Clock Generator and Timing/Frequency Reference", which is a continuation-in-part of and claims priority to McCorquodale, Michael S. et al., U.S. patent application Ser. No. 11/084,962, filed Mar. 21, 2005, entitled "Monolithic Clock Generator and Timing/Frequency Reference", which further claims priority to McCorquodale, Michael S. et al., U.S. Provisional Patent Application Ser. No. 60/555,193, filed Mar. 22, 2004, entitled "Monolithic and Top-Down Clock Synthesis with Micromachined Radio Frequency Reference", which are commonly assigned herewith, the contents of all of which are incorporated herein by reference, and with priority claimed for all commonly disclosed subject matter.

This application is also a continuation-in-part of and claims priority to McCorquodale, Michael S. et al., U.S. patent application Ser. No. 11/084,962, filed Mar. 21, 2005, entitled "Monolithic Clock Generator and Timing/Frequency Reference", which further claims priority to McCorquodale, Michael S. et al., U.S. Provisional Patent Application Ser. No. 60/555,193, filed Mar. 22, 2004, entitled "Monolithic and Top-Down Clock Synthesis with Micromachined Radio Frequency Reference" (the "second related application"), which are commonly assigned herewith, the contents of all of which are incorporated herein by reference, and with priority claimed for all commonly disclosed subject matter.

This application is also related to and claims priority to McCorquodale, Michael S. et al., U.S. patent application Ser. No. 11/085,372, filed Mar. 21, 2005, entitled "Transconductance and Current Modulation for Resonant Frequency Control and Selection", which further claims priority to U.S. Provisional Patent Application Ser. No. 60/555,193, which is commonly assigned herewith, the contents of all of which are incorporated herein by reference, and with priority claimed for all commonly disclosed subject matter.

Claims

The invention is claimed:

1. An integrated circuit, the integrated circuit comprising: a resonator comprising an inductor and a capacitor, the resonator adapted to provide a first reference signal having a first frequency; a voltage controller adapted to provide a plurality of voltage control signals; a plurality of switchable, controlled reactance modules coupled to the resonator and to the voltage controller, each reactance module of the plurality of reactance modules adapted to provide a selected reactance in response to a corresponding voltage control signal of the plurality of voltage control signals to modify the first frequency; and a processor operatively coupled to the resonator.

2. The integrated circuit of claim 1, further comprising: a divider circuit coupled to the resonator, the divider circuit adapted to provide a second reference signal having a second frequency; and wherein the processor is coupled through the divider to the resonator, and is adapted to receive the second reference signal.

3. The integrated circuit of claim 1, further comprising: a locking circuit coupled to the resonator, the locking circuit adapted to lock to the first reference signal and provide a second reference signal having a second frequency which is a rational multiple of the first frequency, wherein the locking circuit is at least one of the following locking circuits: a phase-locked loop, a delay-locked loop, or an injection locking circuit; and wherein the processor is coupled through the locking circuit to the resonator, and is adapted to receive the second reference signal.

4. The integrated circuit of claim 1, wherein the processor is any type of circuitry adapted to perform a function.

5. The integrated circuit of claim 1, wherein the processor is at least one of the following types of processors: a microprocessor; a digital signal processor; a controller; a microcontroller; a universal serial bus (USB) controller; a Peripheral Component Interconnect (PCI) controller; a Peripheral Component Interconnect Express (PCI-e) controller; a Firewire controller; an AT Attachment (ATA) interface controller, an Integrated Drive Electronics (IDE) controller; a Small Computer Systems Interface (SCSI) controller; a television controller; a local area network (LAN) controller; an Ethernet controller; a video controller; an audio controller; a modem processor; an MPEG controller; a multimedia controller; a communication controller; a mobile communication controller; an IEEE 802.11 controller; a GSM controller; a GPRS controller; a PCS controller; an AMPS controller; a CDMA controller; a WCDMA controller; a spread spectrum controller; a wireless LAN controller; an IEEE 802.11 controller; a DSL controller; a T1 controller; a ISDN controller; or a cable modem controller.

6. The integrated circuit of claim 1, further comprising: a memory coupled to the processor and further coupled to the locking circuit to receive the second reference signal; and an input/output interface coupled to the processor and further coupled to the locking circuit to receive the second reference signal.

7. The integrated circuit of claim 1, further comprising: a plurality of dividers or locking circuits coupled to the resonator, the plurality of dividers or locking circuits adapted to provide a corresponding plurality of second reference signals having a plurality of corresponding frequencies.

8. The integrated circuit of claim 7, further comprising: control circuitry coupled to the plurality of dividers or locking circuits, the control circuitry adapted to provide a control signal to the plurality of dividers or locking circuits to modify a divide ratio to provide a spread-spectrum second reference signal of the plurality of plurality of second reference signals.

9. The integrated circuit of claim 7, further comprising: control circuitry coupled to the plurality of switchable, controlled reactance modules, the control circuitry adapted to provide a control signal to the plurality of switchable, controlled reactance modules to selectively switch the plurality of switchable, controlled reactance modules to modify the first frequency to provide a spread-spectrum first reference signal.

10. The integrated circuit of claim 7, further comprising: switching circuitry coupled to the plurality of dividers or locking circuits and to the processor, the switching circuitry adapted to selectively couple the processor to the plurality of dividers or locking circuits by switching a selected, second reference signal of the corresponding plurality of second reference signals to the processor.

11. The integrated circuit of claim 10, further comprising: control circuitry coupled to the switching circuitry, the control circuitry adapted to provide a control signal to the switching circuitry to switch the selected, second reference signal to the processor.

12. The integrated circuit of claim 10, further comprising: a coefficient register coupled to the switching circuitry, the coefficient register adapted to provide a control coefficient to the switching circuitry to switch the selected, second reference signal to the processor.

13. The integrated circuit of claim 7, wherein each divider of the plurality of dividers or locking circuits further comprises a plurality of asynchronous or synchronous divider circuits, and wherein the plurality of corresponding frequencies are determined by corresponding divide ratios of the plurality of divider circuits.

14. The integrated circuit of claim 1, wherein the resonator, voltage controller, and plurality of switchable, controlled reactance modules are embodied in a first integrated circuit, and wherein the processor is embodied in a second integrated circuit, and wherein the second integrated circuit is coupled through a plurality of bonding wires to the first integrated circuit.

15. The integrated circuit of claim 1, wherein the resonator is configured to have at least one of the following configurations: a double-balanced, differential LC configuration; a differential n-MOS cross-coupled topology; a differential p-MOS cross-coupled topology; a single-ended Colpitts LC configuration; a single-ended Hartley LC configuration; a differential, common base Colpitts LC configuration; a differential, common collector Colpitts LC configuration; a differential, common base Hartley LC configuration; a differential, common collector Hartley LC configuration; a single-ended Pierce LC oscillator, or a quadrature LC oscillator configuration.

16. The integrated circuit of claim 1, wherein the inductor is an active inductor comprising a plurality of transistors or is a passive inductor comprising a CMOS-compatible conductive layer.

17. The integrated circuit of claim 1, further comprising: a coefficient register coupled to the plurality of switchable, controlled reactance modules, the coefficient register adapted to store a plurality of coefficients and to provide a corresponding coefficient to control switching of a corresponding controlled reactance module to the resonator.

18. The integrated circuit of claim 17, wherein the plurality of switchable, controlled reactance modules further comprise: a plurality of switches coupled to the coefficient register; and a plurality of variable capacitors correspondingly coupled to the plurality of switches and to the voltage controller, the plurality of variable capacitors adapted to provide a selected capacitance in response to a corresponding control voltage.

19. The integrated circuit of claim 18, wherein the plurality of switchable, controlled reactance modules further comprise: a plurality of fixed capacitors correspondingly coupled to the plurality of switches, the plurality of fixed capacitors adapted to provide a selected capacitance in response to a corresponding coefficient.

20. The integrated circuit of claim 19, wherein the plurality of coefficients are determined post-fabrication by calibration to a second reference frequency signal.

21. The integrated circuit of claim 1, further comprising: a transconductance amplifier coupled to the resonator, the transconductance amplifier comprising a variable current source, the variable current source adapted to provide a corresponding current in response to ambient or operating temperature.

22. An apparatus comprising: a harmonic oscillator comprising an inductor and a capacitor, the harmonic oscillator adapted to provide a first reference signal having a first frequency; a plurality of resistive modules adapted to generate a plurality of voltage control signals; a plurality of controlled reactance modules coupled to the harmonic oscillator and to the plurality of resistive modules, each reactance module of the plurality of reactance modules adapted to provide a selected reactance in response to a corresponding voltage control signal of the plurality of voltage control signals to modify the first frequency; a first coefficient register coupled to the plurality of switches, the first coefficient register adapted to store a first plurality of switching coefficients; a first plurality of switches coupled to the plurality of resistive modules and to the plurality of controlled reactance modules, each switch of the first plurality of switches responsive to a corresponding switching coefficient of the first plurality of switching coefficients to couple a selected control voltage of the plurality of control voltages to a corresponding controlled reactance module; and a processor operatively coupled to the harmonic oscillator to receive the first reference signal.

23. The apparatus of claim 22, further comprising: a locking circuit coupled to the harmonic oscillator, the locking circuit adapted to lock to the first reference signal and provide a second reference signal having a second frequency which is a rational multiple of the first frequency; and wherein the processor is coupled through the locking circuit to the harmonic oscillator, and is adapted to receive the second reference signal.

24. The apparatus of claim 23, wherein the locking circuit is at least one of the following locking circuits: a phase-locked loop, a delay-locked loop, or an injection locking circuit.

25. The apparatus of claim 22, wherein the processor is any type of circuitry adapted to perform a function.

26. The apparatus of claim 22, wherein the processor is at least one of the following types of processors: a microprocessor; a digital signal processor; a controller; a microcontroller; a universal serial bus (USB) controller; a Peripheral Component Interconnect (PCI) controller; a Peripheral Component Interconnect Express (PCI-e) controller; a Firewire controller; an AT Attachment (ATA) interface controller, an Integrated Drive Electronics (IDE) controller; a Small Computer Systems Interface (SCSI) controller; a television controller; a local area network (LAN) controller; an Ethernet controller; a video controller; an audio controller; a modem processor; an MPEG controller; a multimedia controller; a communication controller; a mobile communication controller; an IEEE 802.11 controller; a GSM controller; a GPRS controller; a PCS controller; an AMPS controller; a CDMA controller; a WCDMA controller; a spread spectrum controller; a wireless LAN controller; an IEEE 802.11 controller; a DSL controller; a T1 controller; a ISDN controller; or a cable modem controller.

27. The apparatus of claim 22, further comprising: a memory coupled to the processor and further coupled to the locking circuit to receive the second reference signal; and an input/output interface coupled to the processor and further coupled to the locking circuit to receive the second reference signal.

28. The apparatus of claim 22, further comprising: a plurality of dividers or locking circuits coupled to the harmonic oscillator, the plurality of dividers or locking circuits adapted to provide a corresponding plurality of second reference signals having a plurality of corresponding frequencies.

29. The apparatus of claim 28, further comprising: a second plurality of switches coupled to the plurality of dividers or locking circuits and to the processor, the second plurality of switches adapted to selectively couple the processor to the plurality of dividers or locking circuits by switching a selected, second reference signal of the corresponding plurality of second reference signals to the processor.

30. The apparatus of claim 29, further comprising: control circuitry coupled to the second plurality of switches, the control circuitry adapted to provide a control signal to the second plurality of switches to switch the selected, second reference signal to the processor.

31. The apparatus of claim 29, further comprising: a second coefficient register coupled to the second plurality of switches, the second coefficient register adapted to provide a control coefficient to the second plurality of switches to switch the selected, second reference signal to the processor.

32. The apparatus of claim 28, wherein each divider of the plurality of dividers or locking circuits further comprises a plurality of asynchronous or synchronous divider circuits, and wherein the plurality of corresponding frequencies are determined by corresponding divide ratios of the plurality of divider circuits.

33. The apparatus of claim 22, wherein the apparatus is embodied as a single integrated circuit.

34. The apparatus of claim 22, wherein the apparatus is embodied as a first integrated circuit coupled through a plurality of bonding wires to a second integrated circuit.

35. The integrated circuit of claim 22, wherein the first plurality of switches are further responsive to a corresponding switching coefficient of the first plurality of switching coefficients to couple a corresponding controlled reactance module of the plurality of controlled reactance modules to the harmonic oscillator to modify the first frequency.

36. The integrated circuit of claim 22, wherein the harmonic oscillator has at least one configuration of the following configurations: a double-balanced, differential LC configuration; a differential n-MOS cross-coupled topology; a differential p-MOS cross-coupled topology; a single-ended Colpitts LC configuration; a single-ended Hartley LC configuration; a differential, common base Colpitts LC configuration; a differential, common collector Colpitts LC configuration; a differential, common base Hartley LC configuration; a differential, common collector Hartley LC configuration; a single-ended Pierce LC oscillator, or a quadrature LC oscillator configuration.

37. The integrated circuit of claim 22, wherein the plurality of controlled reactance modules further comprise: a plurality of variable capacitors correspondingly coupled to the plurality of switches and to the voltage controller, the plurality of variable capacitors adapted to provide a selected capacitance in response to a corresponding control voltage; and a plurality of fixed capacitors correspondingly coupled to the plurality of switches, the plurality of fixed capacitors adapted to provide a selected capacitance in response to a corresponding switching coefficient.

38. The integrated circuit of claim 22, wherein at least one control voltage of the plurality of control voltages is responsive to a parameter of a plurality of parameters, wherein the plurality of parameters are variable and comprise at least one of the following parameters: temperature, fabrication process, voltage, age, and frequency.

39. The integrated circuit of claim 38, further comprising: a current source coupled to the plurality of resistive modules, the current source adapted to provide a parameter-dependent current to at least one resistive module of the plurality of resistive modules to generate at least one control voltage, of the plurality of control voltages, which is parameter-dependent.

40. The integrated circuit of claim 39, wherein the current source has at least one complementary to absolute temperature (CTAT) configuration, proportional to absolute temperature (PTAT) configuration, or proportional to absolute temperature squared (PTAT.sup.2) configuration.

41. The integrated circuit of claim 22, wherein the plurality of controlled reactance modules further comprise a plurality of differently-weighted fixed capacitances and variable capacitances, and wherein the plurality of switches are responsive to the plurality of switching coefficients to couple a fixed capacitance to the harmonic oscillator and to couple a first control voltage of the plurality of control voltages to a variable capacitance coupled to the harmonic oscillator.

42. The integrated circuit of claim 22, wherein the plurality of controlled reactance modules further comprise: a plurality of differently-weighted switchable capacitive modules coupled to the coefficient register and to the harmonic oscillator, each switchable capacitive module having a first fixed capacitance and a second fixed capacitance, each switchable capacitive module responsive to a corresponding coefficient of the plurality of coefficients to switch between the first fixed capacitance and the second fixed capacitance.

43. The integrated circuit of claim 22, wherein the plurality of controlled reactance modules further comprise: at least one switchable variable capacitive module coupled to the coefficient register and to the harmonic oscillator, the at least one switchable variable capacitive module responsive to a corresponding coefficient of the plurality of coefficients to switch between a first voltage and a second voltage of a plurality of control voltages.

44. The integrated circuit of claim 22, wherein the plurality of controlled reactance modules further comprise: a plurality of switchable variable capacitive modules coupled to the coefficient register and to the harmonic oscillator, each switchable variable capacitive module responsive to a corresponding coefficient of the plurality of coefficients to switch to a selected control voltage of a plurality of control voltages, the plurality of control voltages comprising a plurality of different magnitude voltages, and wherein the selected control voltage is substantially constant over temperature variations.

45. An integrated circuit comprising: a resonator comprising an inductor and a capacitor, the resonator adapted to provide a first reference signal having a first frequency; a sensor adapted to provide a second signal in response to operating temperature or fabrication process variation; a voltage controller adapted to provide a plurality of voltage control signals; a plurality of switchable, controlled reactance modules coupled to the resonator and to the voltage controller, each reactance module of the plurality of reactance modules adapted to provide a selected reactance in response to a corresponding voltage control signal of the plurality of voltage control signals to modify the first frequency; a plurality of dividers operatively coupled to the resonator, the plurality of dividers adapted to provide a corresponding plurality of second reference signals having a plurality of corresponding frequencies; and a processor adapted to receive a selected, second reference signal of the plurality of second reference signals.

46. The integrated circuit of claim 45, further comprising: switching circuitry coupled to the plurality of dividers and to the processor, the switching circuitry adapted to switch the selected, second reference signal to the processor.

47. The integrated circuit of claim 45, further comprising: at least one locking circuit coupled to the resonator and to the processor, wherein the locking circuit is at least one of the following locking circuits: a phase-locked loop, a delay-locked loop, or an injection locking circuit.

48. The integrated circuit of claim 45, wherein the processor is at least one of the following types of processors: a microprocessor; a digital signal processor; a controller; a microcontroller; a universal serial bus (USB) controller; a Peripheral Component Interconnect (PCI) controller; a Peripheral Component Interconnect Express (PCI-e) controller; a Firewire controller; an AT Attachment (ATA) interface controller, an Integrated Drive Electronics (IDE) controller; a Small Computer Systems Interface (SCSI) controller; a television controller; a local area network (LAN) controller; an Ethernet controller; a video controller; an audio controller; a modem processor; an MPEG controller; a multimedia controller; a communication controller; a mobile communication controller; an IEEE 802.11 controller; a GSM controller; a GPRS controller; a PCS controller; an AMPS controller; a CDMA controller; a WCDMA controller; a spread spectrum controller; a wireless LAN controller; an IEEE 802.11 controller; a DSL controller; a T1 controller; a ISDN controller; or a cable modem controller.

49. The integrated circuit of claim 45, further comprising: control circuitry coupled to the switching circuitry, the control circuitry adapted to provide a control signal to the switching circuitry to switch the selected, second reference signal to the processor.

50. The integrated circuit of claim 45, further comprising: a coefficient register coupled to the switching circuitry, the coefficient register adapted to provide a control coefficient to the switching circuitry to switch the selected, second reference signal to the processor.

51. The integrated circuit of claim 45, wherein the resonator is configured to have at least one of the following configurations: a double-balanced, differential LC configuration; a differential n-MOS cross-coupled topology; a differential p-MOS cross-coupled topology; a single-ended Colpitts LC configuration; a single-ended Hartley LC configuration; a differential, common base Colpitts LC configuration; a differential, common collector Colpitts LC configuration; a differential, common base Hartley LC configuration; a differential, common collector Hartley LC configuration; a single-ended Pierce LC oscillator, or a quadrature LC oscillator configuration.

52. The integrated circuit of claim 45, further comprising: a coefficient register coupled to the plurality of switchable, controlled reactance modules, the coefficient register adapted to store a plurality of coefficients and to provide a corresponding coefficient to control switching of a corresponding controlled reactance module to the resonator.

Description

FIELD OF THE INVENTION

The present invention, in general, relates to oscillation or clocking signal generation, and more particularly, relates to an integrated clock signal generator and timing/frequency reference which is free-running, self-referenced, accurate over fabrication process, voltage and temperature, has low jitter, and which may be monolithically integrated with other circuitry to form a single integrated circuit.

BACKGROUND OF THE INVENTION

Accurate clock generators or timing references have generally relied upon crystal oscillators, such as quartz oscillators, which provide a mechanical, resonant vibration at a particular frequency. The difficulty with such crystal oscillators is that they cannot be fabricated as part of the same integrated circuit ("IC") that is to be driven by their clock signal. For example, microprocessors such as the Intel Pentium processor require a separate clock IC. As a consequence, virtually every circuit requiring an accurate clock signal requires an off-chip clock generator.

There are several consequences for such non-integrated solutions. For example, because such a processor must be connected through outside circuitry (such as on a printed circuit board (PCB)), power dissipation is comparatively increased. In applications which rely on a finite power supply, such as battery power in mobile communications, such additional power dissipation is detrimental.

In addition, such non-integrated solutions, by requiring an additional IC, increase space and area requirements, whether on the PCB or within the finished product, which is also detrimental in mobile environments. Moreover, such additional components increase manufacturing and production costs, as an additional IC must be fabricated and assembled with the primary circuitry (such as a microprocessor).

Other clock generators which have been produced as integrated circuits with other circuits are generally not sufficiently accurate, particularly over fabrication process, voltage, and temperature ("PVT") variations. For example, ring, relaxation and phase shift oscillators may provide a clock signal suitable for some low-sensitivity applications, but have been incapable of providing the higher accuracy required in more sophisticated electronics, such as in applications requiring significant processing capability or data communications. In addition, these clock generators or oscillators often exhibit considerable frequency drift, jitter, have a comparatively low Q-value, and are subject to other distortions from noise and other interference.

As a consequence, a need remains for a clock generator or timing reference which may be integrated monolithically with other circuitry, as a single IC, and which is highly accurate over PVT variations. Such a clock generator or timing reference should be free-running and self-referencing, and should not require locking or referencing to another reference signal. Such a clock generator or timing reference should exhibit minimal frequency drift and have comparatively low jitter, and should be suitable for applications requiring a highly accurate system clock. Such a clock generator or timing reference should also provide multiple operating modes, including a clock mode, a reference mode, a power conservation mode, and a pulsed mode. Lastly, such a clock generator or timing reference should provide for control over output frequency, to provide a stable and desired frequency in response to variation in ambient or junction temperature or variation in other parameters such as voltage, fabrication process, frequency, and age.

SUMMARY OF THE INVENTION

In various exemplary embodiments, the invention provides an apparatus which generates a frequency reference signal. The apparatus comprises a resonator, which may be implemented using one or more inductors and capacitors (as an "LC-tank"), a transconductance amplifier, a frequency controller and a temperature compensator for use in providing open-loop frequency control and selection for a low-jitter, free-running and self-referencing clock generator and/or a timing and frequency reference which is highly accurate over PVT and aging (time) variations and which can be integrated monolithically with other circuitry, to form a singular integrated circuit. No separate reference oscillator is required, and the exemplary embodiments are not phase-locked, delay-locked or otherwise locked to any other frequency reference. Instead, the exemplary embodiments may be utilized as such a reference oscillator which generates a frequency reference signal, which may then be locked to by one or more phase-locked or delay-locked loops. Various exemplary embodiments of the invention include features for highly accurate frequency generation over fabrication process, voltage, and temperature ("PVT") variations. These features include frequency tuning and selection, and compensation for frequency variations which may be caused due to temperature and/or voltage fluctuations, fabrication process variations, and variations due to aging of the integrated circuitry.

The invention may be integrated directly with other components as a singular integrated circuit. For example, the inventive clock generator and/or a timing and frequency reference may be integrated with any other, second circuitry, of any kind or type, for any function or application, such as various processors, controllers, digital signal processors, and so on, to provide an integrated, free-running clock for the second circuitry which does not require synchronization or locking to an external reference such as a crystal oscillator. For example and without limitation, the clock generator and/or a timing and frequency reference may be integrated with any of the following types of processors: a microprocessor; a digital signal processor; a controller; a microcontroller; a universal serial bus (USB) controller; a Peripheral Component Interconnect (PCI) controller; a Peripheral Component Interconnect Express (PCI-e) controller; a Firewire controller; an AT Attachment (ATA) interface controller, an Integrated Drive Electronics (IDE) controller; a Small Computer Systems Interface (SCSI) controller; a television controller; a local area network (LAN) controller; an Ethernet controller; a video controller; an audio controller; a modem processor; an MPEG controller; a multimedia controller; a communication controller; a mobile communication controller; an IEEE 802.11 controller; a GSM controller; a GPRS controller; a PCS controller; an AMPS controller; a CDMA controller; a WCDMA controller; a spread spectrum controller; a wireless LAN controller; an IEEE 802.11 controller; a DSL controller; a T1 controller; a ISDN controller; or a cable modem controller. Innumerable other types of second circuitry for integration with the inventive clock generator and/or a timing and frequency reference are also within the scope of the invention.

For such integrated embodiments, the clock generator and/or a timing and frequency reference provides a first reference signal having a first frequency f.sub.0. The first reference signal may be utilized in any of a plurality of ways, such as: (1) utilized directly by second circuitry as a clocking or frequency reference signal; (2) provided to one or more square-wave generators or divider circuits, with the resulting substantially square or divided signal(s) provided as output (as one or more second reference signals at a selected frequency or frequencies (e.g., having frequencies f.sub.0, f.sub.1, f.sub.2, through f.sub.K)), any one or more of which are then utilized by second circuitry as a clocking or frequency reference signal; (3) utilized for locking by a locking circuit, such as one or more phase-locked loops, delay-locked loops, or injection locking circuits, or by a combination of dividers and locking circuits, also to provide as output one or more second reference (or clock) signals, at a selected frequency or frequencies (e.g., having frequencies f.sub.K+1, f.sub.K+2, through f.sub.N), to second circuitry.

These one or more second reference signals can be switched, multiplexed or provided directly to any second circuitry, such as a processor, memory and input/output interface, as a clock or reference signal at a selected frequency. These signals may also be provided in any of a plurality of forms, such as single-ended, differential, square-wave, sinusoidal, phase-shifted, spread-spectrum, quadrature, including in inverted and/or non-inverted forms.

Frequency selection for any of the frequencies (f.sub.0, f.sub.1, f.sub.2, through f.sub.N) may be provided in a plurality of ways, depending upon the selected embodiment. The frequency selection may occur as part of design and fabrication, such as through selection of the number and size of inductors and capacitors utilized in the LC oscillator of the clock generator and/or a timing and frequency reference. For example, the size(s) and/or shape(s) of the one or more inductors may be selected through a suitable metal layer mask, and capacitors may be sized for generation of particular frequencies or range of frequencies. Frequency selection also may occur post-fabrication, through the use of the various calibration and control coefficients or signals, discussed in greater detail below. In addition, frequency selection may be performed through the configuration of the one or more dividers and/or locking circuits, such as through selection of the divide ratio(s) through programmable counters in phase-locked loops, which may be as part of the design and fabrication of the IC, or may be programmed post-fabrication, also through use of calibration and control coefficients or signals, or by switching dividers in or out of the divide chain.

Additional embodiments also provide for generating a plurality of frequency reference signals, whether sinusoidal or square-wave, such as for use as one or more clock signals or reference frequency sources. In exemplary embodiments, the clock/frequency reference of the invention is coupled to one or more phase-locked loops ("PLLs") or delay-locked loops ("DLLs), to provide a corresponding plurality of output reference signals at selected frequencies. Various exemplary embodiments may be configurable or programmable, through control signals or stored coefficients, such as to adjust the divide ratios of the PLLs or DLLs for corresponding frequency selection.

For applications potentially requiring a high Q value, low jitter and low phase noise, the resonator typically comprises one or more inductors and capacitors, forming one or more LC-tanks or LC resonators. In a first embodiment, a double-balanced, differential LC oscillator topology is utilized. In other exemplary embodiments, differential or single-ended LC oscillator topologies may be utilized, such as a differential n-MOS cross-coupled topology; a differential p-MOS cross-coupled topology; a single-ended Colpitts LC oscillator, a single-ended Hartley LC oscillator, a differential Colpitts LC oscillator (both common base and common collector versions), a differential Hartley LC oscillator (also both common base and common collector versions), a single-ended Pierce LC oscillator, a quadrature oscillator (e.g., formed from at least two double-balanced, differential LC oscillators). In any of these embodiments, an active inductor may be utilized in the LC oscillator or in the other reactive components. Any of these LC topologies may be implemented to be balanced, cross-coupled, differential, or single-ended, and may utilize any type of transistors, such as n-MOS, p-MOS, or BJT, for example. Additional LC oscillator topologies, now known or which become known, are considered equivalent and within the scope of the present invention.

Exemplary embodiments of the present invention also provide several different levels and types of control. For example, both discrete and continuous control are provided, in real time, for control over output frequency of the free-running oscillator in light of such variations. In addition, such control is provided generally as an open-loop, without requiring or necessitating a feedback connection and without requiring continuous locking of the oscillator to another reference signal.

In addition, exemplary embodiments of the invention provide a clock generator and/or a timing and frequency reference having multiple operating modes, including modes such as a power conservation mode, a clock mode, a reference mode, and a pulsed mode. In addition, the various embodiments provide multiple output signals at different frequencies, and provide low-latency and glitch-free switching between these various signals.

Significantly, various exemplary embodiments of the invention generate a significantly and comparatively high frequency, such as in the hundreds of MHz and GHz range, which is then divided to a plurality of lower frequencies. Each such division by "N" (a rational number, as a ratio of integers) results in a significant noise reduction, with phase noise reduced by N and phase noise power reduced by N.sup.2. As a consequence, exemplary embodiments of the invention result in significantly less relative period jitter than other oscillators that generate their output directly or through frequency multiplications.

Various apparatus embodiments include a resonator, an amplifier, and a frequency controller, which may include various components or modules such as a temperature compensator, a process variation compensator, a voltage isolator and/or voltage compensator, an age (time) variation compensator, a frequency divider, and a frequency selector. The resonator provides a first signal having a resonant frequency. A temperature compensator adjusts the resonant frequency in response to temperature, and the process variation compensator adjusts the resonant frequency in response to fabrication process variation. In addition, the various embodiments may also include a frequency divider to divide the first signal having the resonant frequency into a plurality of second signals having a corresponding plurality of frequencies which are substantially equal to or lower than the resonant frequency; and a frequency selector to provide an output signal from the plurality of second signals. The frequency selector may further include a glitch-suppressor. The output signal may be provided in any of various forms, such as differential or single-ended, and substantially square-wave or sinusoidal.

Exemplary embodiments of the present invention provide an apparatus for frequency control of an integrated, free-running harmonic oscillator, comprising a resonator adapted to provide a first signal having a resonant frequency; a sensor adapted to provide a second signal, such as a control voltage, in response to at least one parameter of a plurality of parameters; and a frequency controller coupled to the sensor and couplable to the resonator, with the frequency controller adapted to modify a reactance element coupled to the resonator in response to the second signal to modify the resonant frequency. The plurality of parameters are variable and comprise at least one of the following parameters: temperature, fabrication process, voltage, frequency, and age (i.e., elapsed time).

In the exemplary embodiments, the frequency controller is further adapted to modify an effective reactance or impedance element coupled to the resonator in response to the second signal, such as modifying a total capacitance of the resonator in response to the second signal, coupling to the resonator or decoupling from the resonator a fixed or variable capacitance, modifying an effective reactance of the resonator by varying or switching a varactor to a selected control voltage, or equivalently, modifying an inductance or resistance of the resonator in response to the second signal, such as by coupling to the resonator or decoupling from the resonator a fixed or variable inductance or resistance. In other embodiments, differentially weighted or sized reactances, such as variable capacitors (varactors), may be switched to or from the resonator, switched to or from a plurality of different, selectable control voltages, or both. For example, in selected embodiments, the reactance of one or more variable capacitors which are coupled to the resonator may be varied by switching the one or more variable capacitors to a selected control voltage, of a plurality of control voltages, resulting in differently or differentially-weighted effective reactances coupled to the resonator.

For example, a plurality of fixed capacitances (having different, binary weighted or otherwise differentially-weighted capacitances), may be coupled to the resonator to provide a discrete level of frequency control, and a varactor coupled to the resonator may be provided with a selected control voltage, of a plurality of control voltages, which varies in response to temperature, which may be utilized to maintain a constant frequency over such temperature fluctuations, and which provides a continuous level of frequency control. In addition, any of such control voltages may either vary in response to a selected parameter, such as temperature, or may be constant with respect to such a parameter. The differing weights of the various reactances utilized may be embodied in a plurality of forms, such as binary weighted, linearly weighted, or weighted utilizing any other desirable scheme, all of which are considered equivalent and within the scope of the present invention.

It should be noted that the terms "fixed" and "variable" are utilized as known in the art, with "fixed" being understood to mean configured generally to be non-varying with respect to a selected parameter, and "variable" meaning configured generally to be varying with respect to the selected parameter. For example, a fixed capacitor generally means that its capacitance does not vary as a function of an applied voltage, while a variable capacitor (varactor) will have a capacitance which does vary as a function of applied voltage. Both, however, may have and generally will have capacitances which vary as a function of fabrication process variation. In addition, a fixed capacitor may be formed as a varactor coupled to a constant voltage, for example. Similarly, components may be coupled to each other either directly or indirectly or, stated another way, operatively coupled or coupled via signal transmission. For example, one component may be coupled to a second component via a third component, such as through a switching arrangement, a divider, a multiplier, etc. Those of skill in the art will recognize these various circumstances and contexts, as illustrated and as discussed below, and what is meant when such terms are utilized.

In the exemplary embodiments, the frequency controller may further comprise: a coefficient register adapted to store a first plurality of coefficients; and a first array having a plurality of switchable capacitive modules coupled to the coefficient register and couplable to the resonator, each switchable capacitive module having a fixed capacitance and a variable capacitance, each switchable capacitive module responsive to a corresponding coefficient of the first plurality of coefficients to switch between the fixed capacitance and the variable capacitance and to switch each variable capacitance to a control voltage. The plurality of switchable capacitive modules may be binary-weighted. The frequency controller may further comprise a second array having a plurality of switchable resistive modules coupled to the coefficient register and further having a capacitive module, the capacitive module and the plurality of switchable resistive modules further coupled to a node to provide the control voltage, with each switchable resistive module responsive to a corresponding coefficient of a second plurality of coefficients stored in the coefficient register to switch the switchable resistive module to the control voltage node. In selected embodiments, the sensor further comprises a current source responsive to temperature, wherein the current source is coupled through a current mirror to the second array to generate the control voltage across at least one switchable resistive module of the plurality of switchable resistive modules. Also in selected embodiments, the current source has at least one complementary to absolute temperature ("CTAT") configuration, proportional to absolute temperature ("PTAT") configuration, proportional to absolute temperature squared ("PTAT.sup.2") configuration, or combinations of these configurations. In addition, each switchable resistive module of the plurality of switchable resistive modules has a different temperature response for a selected current.

In other exemplary embodiments, the sensor is a parameter (temperature, process, voltage, age, etc.) sensor and varies the second signal in response to variation of the selected parameter; for example, the sensor may be a temperature or voltage sensor and varies the second signal in response to temperature or voltage variation. The selected embodiments may also include an analog-to-digital converter coupled to the sensor to provide a digital output signal in response to the second signal, and a control logic block to convert the digital output signal to the first plurality of coefficients.

In other exemplary embodiments, the frequency controller further comprises a process variation compensator couplable to the resonator and adapted to modify the resonant frequency in response to a fabrication process parameter of the plurality of parameters. The process variation compensator may further comprise a coefficient register adapted to store a plurality of coefficients; and an array having a plurality of binary-weighted switchable capacitive modules coupled to the coefficient register and to the resonator, each switchable capacitive module having a first fixed capacitance and a second fixed capacitance, with each switchable capacitive module responsive to a corresponding coefficient of the plurality of coefficients to switch between the first fixed capacitance and the second fixed capacitance. In other exemplary embodiments, the process variation compensator may further comprise a coefficient register adapted to store a plurality of coefficients; and an array having a plurality of switchable variable capacitive modules coupled to the coefficient register and to the resonator, each switchable variable capacitive module responsive to a corresponding coefficient of the plurality of coefficients to switch between a first voltage and a second voltage, such as switching to a selected control voltage.

In other exemplary embodiments, frequency controller further comprises a coefficient register adapted to store a first plurality of coefficients; and a first array having a plurality of switchable, capacitive modules coupled to the coefficient register and couplable to the resonator, each switchable capacitive module having a variable capacitance, each switchable capacitive module responsive to a corresponding coefficient of the first plurality of coefficients to switch the variable capacitance to a selected control voltage of a plurality of control voltages. In other exemplary embodiments, the process variation compensator may further comprise a coefficient register adapted to store at least one coefficient; and at least one switchable variable capacitive module coupled to the coefficient register and to the resonator, which is responsive to the at least one coefficient to switch to a selected control voltage. The sensor may comprises a current source responsive to temperature, and the frequency controller may also include a second array having a plurality of resistive modules coupled through a current mirror to the current source, the plurality of resistive modules adapted to provide the plurality of control voltages, and wherein each resistive module of the plurality of resistive modules has a different response to temperature and is adapted to provide a corresponding control voltage, of the plurality of control voltages, in response to a current from the current source.

In other exemplary embodiments, an apparatus for frequency control of a resonator comprises a coefficient register adapted to store a first plurality of coefficients; and a first array having a plurality of switchable reactance or impedance modules coupled to the coefficient register and to the resonator, each switchable reactance module responsive to a corresponding coefficient of the first plurality of coefficients to switch a corresponding reactance to modify the resonant frequency. The corresponding reactance or impedance may be a fixed or variable inductance, a fixed or variable capacitance, a fixed or variable resistance, or any combination thereof. The corresponding reactance may be switched to the resonator or, when coupled to the resonator, may be switched to a control voltage, a power supply voltage or a ground potential, and the control voltage may be determined by a current source responsive to temperature. For example, the corresponding reactance is variable and is coupled to the resonator and switched to a selected control voltage of a plurality of control voltages. In selected embodiments, the first plurality of coefficients are calibrated or are determined by a sensor responsive to at least one parameter of a plurality of variable parameters, such as temperature, fabrication process, voltage, frequency and age.

In other exemplary embodiments, an apparatus for frequency control of an integrated, free-running harmonic oscillator comprises: a plurality of resistive modules adapted to generate a plurality of control voltages; a plurality of controlled reactance modules coupled to the harmonic oscillator; and a plurality of switches coupled to the plurality of resistive modules and to the plurality of controlled reactance modules, with the plurality of switches responsive to a control signal to couple a first control voltage of the plurality of control voltages to a first controlled reactance module of the plurality of controlled reactance modules to modify a resonant frequency of the harmonic oscillator.

As illustrated above, the apparatus may also include a current source coupled to the plurality of resistive modules, with the current source adapted to provide a parameter-dependent current to at least one resistive module of the plurality of resistive modules to generate at least one control voltage, of the plurality of control voltages, which is parameter-dependent. In other embodiments, the current source is adapted to provide a substantially parameter-independent current to at least one resistive module of the plurality of resistive modules to generate at least one control voltage, of the plurality of control voltages, which is substantially parameter-independent. Depending upon the exemplary embodiment, each switchable resistive module of the plurality of switchable resistive modules may have a different temperature response for a selected current. As a consequence, when the parameter is temperature, at least one control voltage of the plurality of control voltages is temperature-dependent and at least one control voltage of the plurality of control voltages is substantially temperature-independent.

The exemplary apparatus may also comprise a coefficient register coupled to the plurality of switches and adapted to store a first plurality of coefficients, wherein the control signal is provided by at least one coefficient of the first plurality of coefficients. The plurality of controlled reactance modules may further comprise a plurality of differentially (e.g., binary) weighted fixed capacitances and variable capacitances, and wherein the plurality of switches are responsive to the first plurality of coefficients to couple a fixed capacitance to the harmonic oscillator and to couple a first control voltage of the plurality of control voltages to a variable capacitance coupled to the harmonic oscillator. The plurality of resistive modules may further comprise a plurality of switchable resistive modules coupled to the coefficient register and a capacitive module, the capacitive module and the plurality of switchable resistive modules further coupled to a node to provide the first control voltage, with each switchable resistive module responsive to a corresponding coefficient of a second plurality of coefficients stored in the coefficient register to switch the switchable resistive module to the control voltage node.

In exemplary embodiments, an analog-to-digital converter may be coupled to the plurality of switchable resistive modules to provide a digital output signal in response to the first control voltage, to, for example, convert a temperature-dependent current (as a sensor) to a digital form; and a control logic block to convert the digital output signal to the first plurality of coefficients or to the control signal.

Also in exemplary embodiments, the plurality of controlled reactance modules further comprise: a plurality of switchable capacitive modules coupled to the coefficient register and couplable to the harmonic oscillator, with each switchable capacitive module having a variable capacitance, and with each switchable capacitive module responsive to a corresponding coefficient of the first plurality of coefficients to switch the variable capacitance to a selected control voltage of the plurality of control voltages. Depending upon the embodiment, a current source which is responsive to a parameter of a plurality of variable parameters is coupled through a current mirror to the plurality of resistive modules; wherein each resistive module of the plurality of resistive modules has a different response to the parameter and is adapted to provide a corresponding control voltage, of the plurality of control voltages, in response to a current from the current source. Depending upon the embodiment, at least one control voltage of the plurality of control voltages is substantially parameter-dependent and at least one control voltage of the plurality of control voltages is substantially parameter-independent.

Also in exemplary embodiments, the plurality of controlled reactance modules further comprise: a plurality of differentially-weighted switchable capacitive modules coupled to the coefficient register and to the harmonic oscillator, each switchable capacitive module having a first fixed capacitance and a second fixed capacitance, each switchable capacitive module responsive to a corresponding coefficient of the plurality of coefficients to switch between the first fixed capacitance and the second fixed capacitance. In other embodiments, the plurality of controlled reactance modules further comprise: a plurality of switchable variable capacitive modules coupled to the coefficient register and to the harmonic oscillator, each switchable variable capacitive module responsive to a corresponding coefficient of the plurality of coefficients to switch between a first voltage and a second voltage of a plurality of control voltages. And in other embodiments, the plurality of controlled reactance modules further comprise: a plurality of switchable variable capacitive modules coupled to the coefficient register and to the harmonic oscillator, each switchable variable capacitive module responsive to a corresponding coefficient of the plurality of coefficients to switch to a selected control voltage of a plurality of control voltages, the plurality of control voltages comprising a plurality of different magnitude voltages, and wherein the selected control voltage is substantially constant over temperature variations.

Also in exemplary embodiments, the apparatus may further comprise: a plurality of switchable resistors responsive to a control signal to switch a corresponding resistance to the harmonic oscillator to modify the resonant frequency. The apparatus may include a voltage divider coupled to the plurality of controlled reactance modules and adapted to provide a selected control voltage responsive to voltage variations. In addition, an age variation compensator may be coupled to the resonator and adapted to compare a current value of a selected parameter of the plurality of parameters to an initial value of the selected parameter and to modify the resonant frequency in response to a difference between the current value and the initial value of the selected parameter.

Numerous other exemplary embodiments are illustrated and described in detail below, and include additional modulators and compensators for voltage variations and age (IC lifetime) variations.

The present invention may also include a mode selector coupled to the frequency selector, wherein the mode selector is adapted to provide a plurality of operating modes, which may be selected from a group comprising a clock mode, a timing and frequency reference mode, a power conservation mode, and a pulsed (or pulse) mode.

For a reference mode, the invention may also include a synchronization circuit coupled to the mode selector; and a controlled oscillator coupled to the synchronization circuit and adapted to provide a third signal; wherein in the timing and reference mode, the mode selector is further adapted to couple the output signal to the synchronization circuit to control timing and frequency of the third signal. Such a synchronization circuit may be a delay-locked loop, a phase-locked loop, or an injection locking circuit.

These and additional embodiments are discussed in greater detail below. Numerous other advantages and features of the present invention will become readily apparent from the following detailed description of the invention and the embodiments thereof, from the claims and from the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The objects, features and advantages of the present invention will be more readily appreciated upon reference to the following disclosure when considered in conjunction with the accompanying drawings and examples which form a portion of the specification, wherein like reference numerals are used to identify identical or similar components in the various views, in which:

FIG. 1 (or "FIG. 1") is a block diagram illustrating a first exemplary syst