Title: Integrated memory cell and method of fabrication
Abstract: A nonvolatile memory cell comprising a pair of spaced apart shallow trench isolation regions formed in a substrate and defining a substrate active region. A tunnel dielectric is formed on the substrate active region. A floating gate is formed on the tunnel dielectric and is self aligned between the spaced apart shallow trench isolation regions. A dielectric layer is formed on the floating gate and a control gate formed on the dielectric layer. A source region and a drain region are formed in the substrate active region on opposite sides of the floating gate.
Patent Number: 6,943,071 Issued on 09/13/2005 to Fazio, et al.
| Inventors:
|
Fazio; Albert (Los Gatos, CA);
Parat; Krishna (Palo Alto, CA);
Wada; Glen (Fremont, CA);
Mielke; Neal (Los Altos Hills, CA);
Stone; Rex (San Jose, CA)
|
| Assignee:
|
Intel Corporation (Santa Clara, CA)
|
| Appl. No.:
|
162173 |
| Filed:
|
June 3, 2002 |
| Current U.S. Class: |
438/201; 257/315; 257/321; 438/211; 438/257; 438/692 |
| Intern'l Class: |
H01L 021/82.38 |
| Field of Search: |
438/201,211,257,263,626,631,645,633,692
257/314,315-316,321
|
References Cited [Referenced By]
U.S. Patent Documents
| 3660819 | May., 1972 | Frohman-Bentchkowski.
| |
| 3728695 | Apr., 1973 | Frohman-Bentchkowski.
| |
| 3744036 | Jul., 1973 | Frohman-Bentchkowski.
| |
| 3755721 | Aug., 1973 | Frohman-Bentchkowski.
| |
| 4203158 | May., 1980 | Frohman-Bentchkowski.
| |
| 5087584 | Feb., 1992 | Wada et al.
| |
| 5260593 | Nov., 1993 | Lee.
| |
| 5293512 | Mar., 1994 | Nishigoori et al.
| |
| 5511020 | Apr., 1996 | Hu et al.
| |
| 5616942 | Apr., 1997 | Song.
| |
| 5650649 | Jul., 1997 | Tsukiji.
| |
| 5766997 | Jun., 1998 | Takeuchi.
| |
| 5767005 | Jun., 1998 | Doan et al.
| |
| 5864157 | Jan., 1999 | Fu.
| |
| 5901084 | May., 1999 | Ohnakado.
| |
| 5998301 | Dec., 1999 | Pham et al.
| |
| 6008112 | Dec., 1999 | Acocella et al.
| |
| 6054733 | Apr., 2000 | Doan et al.
| |
| 6060360 | May., 2000 | Lin et al.
| |
| 6060741 | May., 2000 | Huang.
| |
| 6078075 | Jun., 2000 | Widdershoven.
| |
| 6097070 | Aug., 2000 | Mandelman.
| |
| 6140182 | Oct., 2000 | Chen.
| |
| 6160297 | Dec., 2000 | Shimizu et al.
| |
| 6201275 | Mar., 2001 | Kawasaki et al.
| |
| 6265292 | Jul., 2001 | Parat et al.
| |
| 6271561 | Aug., 2001 | Doan.
| |
| 6281103 | Aug., 2001 | Doan.
| |
| 6306737 | Oct., 2001 | Mehrad et al.
| |
| 6420249 | Jul., 2002 | Doan et al.
| |
| 6713346 | Mar., 2004 | Wolstenholme.
| |
| 6780740 | Aug., 2004 | Doan et al.
| |
| 2001/0002714 | Jun., 2001 | Doan.
| |
| 2001/0040252 | Nov., 2001 | Kobayashi et al.
| |
| 2002/0003253 | Jan., 2002 | Kitamura et al.
| |
| Foreign Patent Documents |
| 4114166 | Apr., 1991 | DE.
| |
| 008551 | Aug., 1983 | EP.
| |
| 0649172 | Oct., 1994 | EP.
| |
| 1383981 | Feb., 1975 | GB.
| |
| 03198377 | Aug., 1991 | JP.
| |
| 09129757 | Jun., 1997 | JP.
| |
| 09260517 | Oct., 1997 | JP.
| |
| 10135357 | May., 1998 | JP.
| |
| 11261040 | Sep., 1999 | JP.
| |
| WO 9917371 | Apr., 1999 | WO.
| |
Other References
International Search Report PCT/US 00/29001, Oct. 18, 2000.
International Search Report PCT/US 00/2874, Aug. 17, 2000.
International Written Opinion PCT/US 00/22784, Aug. 2000.
"Planarized NVRAM Cell with Self-Aligned BL-BL and WL-BL Isolations" IBM Technical
Disclosure Bulletin, US, IBM Corp. New York, vol. 36, No. 2, Feb. 1, 1993, pp.
375-377, XP000354373.
C. Salm et al. "Gate Current and Oxide Reliability in p+ Poly MOS Capacitors
with Poly-Si and Poly-Ge0.3 Si0.7 Gate Material", IEEE Electron Device Letters,
vol. 19, No. 7, Jul. 1998, pp. 213-215.
V.E. Houtsma et al. DC-SILC in p+ Poly MOS Capacitors with Poly-Si0.7 and Ge0.3
Gate Material, 29th IEEE Semiconductor Interface Specialist Conference,
San Diego, CA, Dec. 3-5, 1998.
Steven C. Chung et al. "A Novel High Performance and Reliability p-Type Floating
Gate N-Channel Flash EEPROM", 1999 Symposium on VLSI Technology Digest of Technical Papers.
Ying Shi et al. "Polarity Dependent Gate Tunneling Currents in Dual-Gate CMOSFET's"
Abstracts, Center for Microelectronic Materials & Structures and Department of
Electrical Engineering, Yale University, New Haven, CT, IEEE Member.
Ying Shi et al. "Polarity-Dependent Tunneling Currents and Oxide Breakdown in
Dual-Gate CMOSFET's", IEEE Transactions on Electron Devices, vol. 45, No. 11, Nov.
1998, pp. 391-393.
Ying Shi et al. "Polarity Dependent Gate Tunneling Currents in Dual-Gate CMOSFET's",
IEEE Transactions on Electron Devices, vol. 45, No. 11, Nov. 1998, pp. 2355-2360.
Murray H. Woods "An E-PROM's Integrity Starts with its Cell Structure", Intel
Corporation, Santa Clara, CA, Aug. 14, 1980.
International Search Report PCT/US 00/22784, Aug. 2000.
|
Primary Examiner: Thomas; Tom
Assistant Examiner: Diaz; José R.
Attorney, Agent or Firm: Blakely, Sokoloff, Taylor & Zafman LLP
Parent Case Text
This is a Divisional application of Ser. No.: 09/454,683 filed Dec. 3, 1999,
which is presently pending.
Claims
1. A method of forming a nonvolatile memory cell comprising:
forming a pair of spaced apart shallow trench isolation regions in a substrate,
said shallow trench isolation regions defining an active region there between;
forming a tunnel dielectric on said substrate active region;
forming a floating gate material over said spaced apart shallow trench isolation
regions and said tunnel dielectric;
polishing said floating gate material until said floating gate material is substantially
planar with the top surface of said spaced apart shallow trench isolation regions
to form a floating gate with a substantially uniform height;
forming a dielectric layer on said planarized floating gate material;
forming a control gate on said dielectric;
forming a source region and a drain region in said substrate active region on
opposite sides of said floating gate;
forming a common source rail in said substrate connected to said source region;
and
forming a contact on said drain region and on one of said shallow trench isolation
regions.
2. The method of claim 1 wherein said floating gate has a work function of >4.1
electron volts.
3. The method of claim 1 wherein said floating gate is p-type polysilicon.
4. The method of claim 1 wherein said tunnel dielectric is a nitrided silicon oxide.
5. A method of forming a nonvolatile memory cell comprising:
forming a pair of spaced apart shallow trench isolation regions in a substrate,
said shallow trench isolation regions defining an active region there between;
forming a tunnel dielectric on said substrate active region;
forming a floating gate material over said spaced apart shallow trench isolation
regions and said tunnel dielectric;
polishing said floating gate material until said floating gate material is substantially
planar with the top surface of said spaced apart shallow trench isolation regions;
etching away the top portion of said spaced apart shallow trench isolation regions
so that said spaced apart shallow trench isolation regions are recessed below the
top of said planarized floating gate material to reveal a portion of the sidewalls
of the planarized floating gate material;
forming a dielectric layer on said planarized floating gate material adjacent
to the exposed sidewalls of said floating gate material;
forming a control gate on said dielectric adjacent to the exposed sidewalls of
said floating gate material;
forming a source region and a drain region in said substrate active region on
opposite sides of said floating gate;
forming a common source rail in said substrate connected to said source region;
and
forming a contact on said drain region and on one of said shallow trench isolation
regions.
6. A method of forming a nonvolatile memory cell comprising:
forming a pair of spaced apart shallow trench isolation regions in a substrate,
said shallow trench isolation regions defining an active region there between;
forming a tunnel dielectric on said substrate active region;
forming a floating gate material over said spaced apart shallow trench isolation
regions and said tunnel dielectric;
polishing said floating gate material until said floating gate material is substantially
planar with the top surface of said spaced apart shallow trench isolation regions;
etching said spaced apart shallow trench isolation regions to t reveal the sidewalls
of said planarized floating gate material;
forming a dielectric layer on said planarized floating gate material and on the
exposed sidewalls of said floating gate material;
forming a control gate on said dielectric and adjacent to said dielectric on
the exposed sidewalls of said planarized floating gate material;
forming a source region and a drain region in said substrate active region on
opposite sides of said floating gate; and
forming a common source rail in said substrate connected to said source region.
7. The method of claim 6 further comprising forming a contact on said drain region
and on one of said shallow trench isolation regions.
8. The method of claim 6 wherein said floating gate has a work function of>4.1
electron volts.
9. The method of claim 6 wherein said floating gate is p-type polysilicon.
10. The method of claim 6 wherein said floating gate is a metal film having a
work function greater than 5.1 eV.
11. The method of claim 6 wherein said tunnel dielectric is a nitrided silicon oxide.
12. A method of forming a nonvolatile memory cell comprising:
forming a pair of spaced apart shallow trench isolation regions in a substrate
to define a substrate active region there between;
forming a tunnel dielectric on said substrate active region;
forming a floating gate material over said pair of spaced apart shallow trench
isolation regions and said tunnel dielectric;
polishing said floating gate material until said floating gate material substantially
planar with the top surface of said spaced apart shallow trench isolation regions
to form said floating gate material having a substantially uniform height;
etching a top portion of said spaced apart shallow trench isolation regions so
that said spaced apart shallow trench isolation regions are recessed below said
floating gate material to reveal a portion of the sidewalls of said floating gate
material;
forming a dielectric layer to cover the floating gate material and the sidewalls
of said floating material;
forming a control gate to cove said dielectric layer and juxtaposed to the dielectric
layer formed on the exposed sidewalls of said floating gate material;
forming a source region and a drain region in said substrate active region on
opposite sides of said floating gate;
forming a common source rail in said substrate connected to said source region;
and
forming a contact on said drain region and on one of said shallow trench isolation
regions.
13. The method of claim 11 wherein said floating gate has a work function greater
than 4.1 electron volts.
14. The method of claim 11 wherein said substrate is a silicon epitaxial film
formed on a monocrystalline substrate.
15. The method of claim 12 wherein said floating gate material is a composite
of films.
16. A method of fabricating a nonvolatile memory cell comprising:
forming isolation regions in a substrate to delineate an active region there
between;
forming a tunnel dielectric on said active region;
forming a floating gate over said tunnel dielectric, said floating gte having
a work function greater than 4.1 electron volts;
forming a dielectric layer covering said floating gate;
forming a control gate on said dielectric layer;
etching predetermined sections of said isolation regions to expose said substrate
to define a source rail region;
implanting a first dopant into said active region to form a source and a drain
on opposite sides of said floating gate and into said source rail region to form
a source rail coupled to said source;
forming a mask over the drain region, said mask exposing said source region and
source rail;
implanting a second dopant into said source region and said source rail; wherein
said mask prevents the doping of said drain region with said second dopant; and
forming a contact on said drain and partially on one of said isolation regions.
17. The method of claim 16 wherein the predetermined sections of said isolation
regions are etched with an oxide etchant selective to silicon.
18. The method of claim 16 wherein said first dopant is an n-type dopant.
19. The method of claim 16 wherein the implanting step further includes implanting
said first dopant into said control gate.
20. A method for constructing a nonvolatile memory cell comprising:
forming a pair of shallow trench isolation regions in a substrate, said pair
of shallow isolation regions spaced apart to define a substrate active region there
between;
forming a tunnel dielectric over said active region having a source region and
a drain region on opposite sides of said tunnel dielectric;
depositing a floating gate material over said tunnel dielectric between said
pair of shallow trench isolation regions, said floating gate having a work function
greater than 4.1 electron volts,
planarizing said floating gate material level with said pair of shallow trench
isolation regions creating a floating gate with a substantially uniform height;
removing a top portion of said pair of shallow trench isolation regions to expose
a portion of the sidewalls of said floating gate;
forming a gate dielectric layer over said floating gate;
forming a control gate on said gate dielectric;
etching a portion of said pair of shallow trench isolation regions adjacent to
said source region to expose said substrate to form a source rail location;
implanting a dopant into said drain region, said source region, and said source
rail location to form a source, a drain, and a source rail coupled to said source;
forming a first dielectric layer over said drain, said source, said source rail,
and said control gate;
forming a second dielectric layer over said first dielectric layer;
etching a drain contact opening through said second dielectric layer with a first
etchant selective to said first layer;
removing said first dielectric layer with a second; and
depositing a conductive material onto said drain through said drain contact opening.
21. The method of claim 20 wherein said source and drain regions are doped asymmetrically.
22. The method of claim 20 wherein said dopant is an n-type dopant.
23. The method of claim 20 wherein said gate dielectric is a composite oxide
including a lower thermally grown oxide film, a middle deposited silicon nitride
film, and a top deposited oxide film.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of semiconductor manufacturing and
more specifically to a nonvolatile memory cell and its method of fabrication.
2. Discussion of Related Art
A conventional electrically erasable nonvolatile memory cell
100 is shown
in FIG.
1. Memory cell
100 includes an n+ polysilicon floating gate
102 formed on the tunnel oxide
104 which is formed on the p-type
silicon region
106. An interpoly dielectric
108 is formed on the
n+ polysilicon floating gate and a control gate
110 formed on the interpoly
dielectric layer
108 and a pair of n+ source/drain regions
109 are
formed along laterally opposite sidewalls of floating gate electrode
102.
Memory cell
100 includes fully landed metal contacts
120 which are
formed entirely on the source/drain regions. To store information in memory device
100 charge is stored on floating gate
102. To erase memory device
100 charge is removed from floating gate
102.
A problem with memory storage cell
100, shown in FIG. 1, is that it has
become difficult to further scale down its width and length to form smaller area
cells and higher density memory circuits. For example, using contacts which are
fully landed on diffusion requires a wider diffusion spacing than required for
the memory cell transistor. Fully landed contacts require a large contact to gate
and isolation spacing. Fully landed contacts prevent the reduction of both cell
width and length. Additionally, floating gate
102 is formed by standard
lithographic techniques with the cell width being limited by the minimum space
resolution and the minimum registration. Another problem with cell
100 is
that it suffers from charge leakage whereby electrons leak off the floating gate.
In order to prevent charge leakage, the source junction is typically heavily graded
leading to large under diffusion and a long gate length. Charge leakage also requires
product level device optimization of voltages for balancing adequate read current
verses charge loss margins thereby creating complexities in circuit design. Additionally,
prevention of charge leakage also requires relatively thick tunnel oxides which
in turn prevents the scaling of the device gate length. and length. Additionally,
floating gate
102 is formed by standard lithographic techniques with the
cell width being limited by the minimum space resolution and the minimum registration.
Another problem with cell
100 is that is suffers from charge leakage whereby
electrons leak off the floating gate. In order to prevent charge leakage, the source
junction is typically heavily graded leading to large under diffusion and a long
gate length. Charge leakage also requires product level device optimization of
voltages for balancing adequate read current verses charge loss margins thereby
creating complexities in circuit design. Additionally, prevention of charge leakage
also requires relatively thick tunnel oxides which in turn prevents the scaling
of the device gate length.
SUMMARY OF THE INVENTION
A nonvolatile memory cell comprising a pair of spaced apart shallow trench isolation
regions formed in a substrate and defining a substrate active region. A tunnel
dielectric is formed on the substrate active region. A floating gate is formed
on the tunnel dielectric and is self aligned between the spaced apart shallow trench
isolation regions. A dielectric layer is formed on the floating gate and a control
gate formed on the dielectric layer. A source region and a drain region are formed
in the substrate active region on opposite sides of the floating gate.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is an illustration of a cross-sectional view of a conventional electrically
erasable nonvolatile memory device.
FIG. 2
a is an illustration of a cross-sectional view of an electrically
erasable nonvolatile memory device in accordance with the present invention.
FIG. 2
b is an illustration of an energy diagram of a nonvolatile memory
device having a p-type floating gate.
FIG. 2
c is an illustration of a cross sectional view of a nonvolatile
memory cell having a self-aligned floating gate.
FIG. 2
d is an illustration of a cross sectional view of a nonvolatile
memory cell having unlanded contacts.
FIG. 3
a is an illustration of an overhead view of a portion of a flash
memory array.
FIG. 3
b is an illustration of a cross-sectional view taken along a wordline
direction through the source rail and showing a plurality of shallow trench isolation regions.
FIG. 3
c is an illustration of a cross-sectional view taken along the
wordline direction through the source rail showing the removal of a portion of
the shallow trench isolation regions from the substrate of FIG. 3
b.
FIG. 3
d is an illustration of a cross-sectional view taken along the
wordline direction through the source rail showing the formation of doped regions
in the substrate of FIG. 3
c.
FIG. 4 is an illustration of a cross-sectional view of a substrate taken along
the wordline direction showing the formation of a pad oxide and a nitride layer.
FIG. 5 is an illustration of a cross-sectional view taken along the wordline
direction showing the formation of trenches in the substrate of FIG. 4.
FIG. 6 is an illustration of a cross-sectional view taken along the wordline
direction showing the formation of a first trench oxide on the substrate of FIG. 5.
FIG. 7 is an illustration of a cross-sectional view taken along the word line
direction showing the formation of a second trench oxide and the rounding of trench
corners on the substrate of FIG. 6.
FIG. 8 is an illustration of a cross-sectional view taken along the wordline
direction showing the filling of the trench isolation regions of the substrate
of FIG. 7.
FIG. 9 is an illustration cross-sectional view taken along the wordline direction
showing the removal of the silicon nitride and pad oxide layers from the substrate
of FIG. 8.
FIG. 10 is an illustration of the cross-sectional view taken along the wordline
direction showing the formation of an n-well photoresist mask over the substrate
of FIG. 9.
FIG. 11 is an illustration of the cross-sectional view taken along the wordline
direction showing the formation of p-wells in the substrate of FIG. 10.
FIG. 12 is an illustration of a cross-sectional view taken along the wordline
direction showing the formation of a tunnel oxide on the substrate of FIG. 11.
FIG. 13 is an illustration of a cross-sectional view taken along the wordline
direction showing the formation of a polysilicon layer on the substrate of FIG. 12.
FIG. 14 is an illustration of a cross-sectional view taken along the wordline
direction showing the polishing of the floating gate material on the substrate
of FIG. 13 to form self-aligned floating gates lines.
FIG. 15 is an illustration of cross-sectional view taken along the wordline
direction showing the removal of the top portion of the STI from the substrate
of FIG. 14.
FIG. 16 is an illustration of a cross-sectional view taken along the wordline
direction showing the formation of a interpoly dielectric on the substrate of FIG. 15.
FIG. 17 is an illustration of a cross-sectional view taken along the wordline
direction showing the removal of the interpoly dielectric from the periphery portion
of the integrated circuit.
FIG. 18 is an illustration of a cross-sectional view taken along the wordline
direction showing the formation of a gate dielectric on the periphery portion of
the substrate t o FIG. 17.
FIG. 19 is an illustration of a cross-sectional view taken along the wordline
direction showing the formation of a second polysilicon film on the substrate of
FIG. 18.
FIG. 20 is an illustration of a cross-sectional view taken along the wordline
direction showing the planarization of the second polysilicon layer on the substrate
of FIG. 19.
FIG. 21
a is an illustration of a cross-sectional view taken along the
wordline direction showing the formation of a poly 2 patterning mask on the substrate
of FIG. 20.
FIG. 21
b is an illustration of a cross-sectional view taken along the
bitline direction showing the patterning of the polysilicon layer, the interpoly
dielectric and the first polysilicon lines on the substrate of FIG. 20.
FIG. 22
a is an illustration of a cross-sectional view taken along the
bitline direction showing the formation of a photoresist mask which reveals the
portions of the silicon substrate for the shared source regions and a portion of
the shallow transisolation which is to be removed.
FIG. 22
b is an illustration of a cross-sectional view taken through the
shallow trench isolation regions in the bitline direction showing the portion of
the shallow trench isolation which is to be removed to generate the source rail.
FIG. 23 is an illustration of a cross-sectional view taken along the bitline
direction showing the formation of source/drain region s in the array portion of
the integrated circuit of FIG. 22
a.
FIG. 24 is an illustration of a cross-sectional view taken along the bitline
direction showing the formation of a graded and heavily doped source region in
the substrate of FIG. 23.
FIG. 25 is an illustration of a cross-sectional view taken along the bitline
direction showing the formation of a thermal oxide and a high temperature oxide
over the substrate of FIG. 24.
FIG. 26 is an illustration of a cross-sectional view taken along the bitline
direction showing the formation of a silicon nitride layer over the substrate of
FIG. 25.
FIG. 27 is an illustration of a cross-sectional view taken along the bitline
direction showing the formation of spacers from the silicon nitride layer on the
substrate of FIG. 26.
FIG. 28 is an illustration of a cross-sectional view showing the removal of
the oxide layer from the substrate of FIG. 27.
FIG. 29 is an illustration of a cross-sectional view taken along the bitline
direction showing the formation of a metal layer of the substrate FIG. 28.
FIG. 30 is an illustration of a cross-sectional view taken along the bitline
direction showing the formation of a silicide from the substrate of FIG. 29.
FIG. 31 is an illustration of a cross-sectional view taken along the bitline
direction showing the formation of an etch stop layer and a planar interlayer dielectric
over the substrate of FIG. 30.
FIG. 32 is an illustration showing the etching of contact openings down to the
etch stop layer of the substrate of FIG. 31.
FIG. 33 is an illustration of a cross-sectional view taken along the bitline
direction showing the formation of electrical contacts in the substrate of FIG. 32.
FIG. 34 is an illustration of a cross-sectional view taken along the bitline
direction showing the formation and patterning of a first level of metallization
on the substrate of FIG. 33.
DESCRIPTION OF THE PRESENT INVENTION
The present invention is a novel nonvolatile memory cell and its method of fabrication.
In the following description numerous specific details are set forth in order to
provide a through understanding of the present invention. One of ordinary skill
in the art, however, will appreciate that these specific details are not necessary
in order to practice the present invention. In other instances well known semiconductor
fabrication processes and techniques have not been set forth in particular detail
in order to not unnecessarily obscure the present invention.
The present invention is a novel nonvolatile memory cell and its method of fabrication.
The memory cell of the present invention utilizes a combination of features and
process techniques which reduce the total area occupied by the cell and thereby
enable the fabrication of high density memory integrated circuit. In one embodiment
of the present invention the cell width is reduced to less than 550 nm by the combination
of a self-aligned floating gate, unlanded contacts, and shallow trench isolation
(STI). In another embodiment of the present invention the cell length is reduced
to less than 750 nm by a combination of a high work function floating gate, a continuous
source rail, and unlanded contacts. The features and techniques of the present
invention can form manufacturable sub 0.35 μM
2 nonvolatile memory
cells with 0.18 μm technology.
An example of a nonvolatile memory cell
201 (along the length of the cell)
in accordance with the present invention is illustrated in FIG. 2
a. The
nonvolatile memory cell
201 includes an electrically erasable non-volatile
memory
200 formed on a p-type region
202 of a single crystalline
silicon substrate (e.g., a boron doped monocrystalline silicon substrate) having
doping density between 1-9×10
17 atoms/cm
3. A thin, 60
to 120 Å, high quality tunnel dielectric
204, such as a grown silicon
dioxide film, is formed on p-type region
202. A high work function floating
gate
206 is formed over tunnel dielectric
204 formed over p-type
region
202. An interlayer or interpoly dielectric
208 comprising,
for example, an oxide/nitride/oxide composite stack having a thickness between
150-250 Å is formed on floating gate
206. A control gate
210
is formed on the interlayer dielectric
208 over floating gate
206.
In one embodiment for the present invention control gate
210 is a polycide
film (i.e., a film comprising a polysilicon/silicide stack) comprising a lower
polysilicon film
212 and an upper suicide film
214 such as but not
limited to cobalt silicide.
An n+ type source region
216 and n+ type drain region
218 are formed
along laterally opposite sidewalls of floating gate
206 and extend beneath
floating gate
206 as shown in FIG. 2
a. The portion
220 of
p-type region
202 between the source and drain regions
216 and
218
beneath the floating gate
206 defines the channel region of device
200.
Memory
200 is said to be a "n-channel" device because when device
200
is programmed channel region
220 conducts electricity between source region
216 and drain region
218 by inverting portion
220 of p-type
region
202 into n-type silicon. Source and drain regions
216 and
218 are heavily doped n-type silicon regions having a doping density of
at least 1×10
19 atoms/cm
3 and can have a silicide
222,
such as cobalt silicide, formed thereon in order to decrease the contact resistance
to the device. In an embodiment of the present invention device
200 has
asymmetric source and drain regions wherein the source region includes an additional
high energy high conductivity implant to form a deeper and graded source region
216.
Device
200 also includes a pair of spacers
224 formed along
laterally opposite sidewalls of the floating gate/dielectric/control gate stack.
In an embodiment of the present invention spacers
224 include a bulk silicon
nitride portion
226 and a buffer oxide layer
228. Spacers
224
seal and prevent contamination of tunnel oxide
204 and interlayer dielectric
208 and can be used to form silicide layers
214 and
222 by
a self-aligned silicide process.
FIGS. 2
c and
2d illustrate the cell of the present invention
along the width of the cell. FIG. 2
c is taken through the floating gate
while FIG. 2
d is taken through the drain contact. As illustrated in FIG.
2
c memory cell
201 includes shallow trench isolation (STI) regions
264 which define there between active areas in which devices
200
are formed. As shown in FIG. 2
c device
200 includes a floating gate
which has been planarized and self-aligned in the active area between the STI isolation
regions. Additionally, as shown in FIGS. 2
a and
2d, memory
cell
201 includes and etch stop layer
262 formed over the gate stack,
contact areas, and STI regions. An interlayer dielectric
266 such as a deposited
silicon oxide film is formed over the etch stop layer. The etch stop layer enables
the fabrication of unlanded contacts
260 through ILD
266.
A feature which enables a flash cell
201 to be fabricated with a reduced
length is the use of a high work function material for the floating gate
206
which dramatically improves the data retention time of the cell. According to an
embodiment of the present invention floating gate
206 is formed of a material
having an intrinsic work function greater than n-type polysilicon (about 4.1 electron
volts). Improving the data retention of the cell enables use of a thin tunnel dielectric
204, which in turn enables the fabrication of a device with a reduced gate
length (source to drain) which in turn reduces the cell length. In an embodiment
of the present invention the work function of floating gate material
206
is greater than or equal to 4.6 electron volts and ideally greater than 5.1 electron
volts. In an embodiment of the present invention floating gate
206 is formed
from p-type polysilicon doped to a concentration level between 5×10
18-5×10
19 atoms/cm
3.
Memory device
200 is erased by removing stored electrons from floating
gate
206. Memory device
200 can be erased by placing a relatively
high positive voltage (+3.0 volts) onto source region
216 while applying
a negative voltage of approximately -11.0 volts onto control gate
210. The
use of low source voltage enables scaling of the device. The positive voltage on
the source region attracts electrons on floating gate
206 and thereby pulls
electrons off floating gate
206 through tunnel oxide
204 and into
source region
216. Lack of measurable electrons on floating gate
206
is an indication of an erased memory device
200. In order to program memory
device
200, electrons are placed on floating gate
206 by grounding
source region
216 while a relatively high positive voltage of +6.0 volts
is applied to drain region
218 and while approximately 10-12 volts is applied
to control gate
210, in order to invert channel region
220 into n-type
silicon so that the channel region
220 turns on and electrons flow between
source region
216 and drain
218. The high control gate voltage pulls
electrons from the inverted channel regions
220 through tunnel dielectric
204 and onto floating gate
206.
Charge loss is reduced in device
200 because floating gate
206
is made from a material having a high intrinsic work function. A high work function
floating gate improves data retention because the barrier height seen by tunneling
electrons is higher when the work function is higher. For example, shown in FIG.
2
b is an energy diagram
250 for a device having a p-type polysilicon
floating gate. As shown in FIG. 2
b electrons tunneling from the valence
band
252 of a floating gate material have a greater barrier height than
that seen by electrons
253 tunneling from the conduction band
254.
With p-type poly there are negligible electrons in the conduction band
254.
Additionally, electron tunneling from low energy levels in high work function materials
can be suppressed by a forbidden transition effect whereby there is no available
site in the substrate silicon to tunnel to. For example, as shown in FIG. 2
b,
electrons in the valence band
252 intercept the band gap
256 of the
silicon substrate. Still further a high work function floating gate increases the
thermal equilibrium threshold voltage (V
T) of a transistor. Charge loss
cannot continue beyond a point where thermal equilibrium is reached based on the
laws of thermodynamic so charge loss must stop entirely at a more favorable (higher) V
T.
Unfortunately, the increase in barrier height seen by the tunneling
electrons which is the root cause of improvement in charge loss also inhibits the
desirable tunneling that occurs at high field during erase operations. The increased
barrier height can cause the erase to become slow. However, increasing the voltage
applied to the cell during erase can overcome the increase in barrier height. In
the case of p-type polysilicon this can also be overcome by lowering the p-type
doping to allow an inversion of the p-type poly into n-type poly during erase operations.
Another feature of the present invention which enables the reduction of cell
length is the use of unlanded contacts
260 as shown in FIGS. 2
a and
2d. Unlanded contacts
260 are contacts which do not have to
be completely positioned over a diffusion regions and can be partially formed over
the isolation regions. Unlanded contacts
260 are formed by depositing over
the device and isolation regions an etch stop layer
262, which can be selectively
etched with respect to the STI
264 and the interlayer dielectric (ILD)
266.
The etch stop layer
262 protects the isolation regions during the contact
etch. In this way it is acceptable for the contact openings to be misaligned over
a portion of the isolation regions. This enables the contacts to be directly aligned
to the gate stack, as opposed to the isolation regions, which in turn enables the
distance (d
1) between the gate and the contacts to be reduced to the
minimum space resolution and registration of the process.
Another feature of the present invention which enables a reduction in the
cell length is the use of a shared source region between the memory devices and
the use of a common source rail to connect the shared source regions together.
As shown in FIG. 2
a, source region
216 is shared with an adjacent
cell. A common source rail connects the shared source regions together thereby
alleviating the need to make separate contacts to each individual shared source
region. The use of a source rail to connect the shared source regions enables the
gate stacks to be separated by the minimum space resolution and registration enabled
by the process.
An example of a source rail is described with respect to FIGS. 3
a-
3d.
An illustration of an overhead view of a portion of a flash memory block
310
of a flash memory integrated circuit in accordance with an embodiment of the present
invention is illustrated in FIG. 3
a. It is to be appreciated that the layout
of FIG. 3
a is just one example of many possible different array configuration
for memory devices
200. The layout of FIG. 3
a is advantageous for
at least because it enables a high density placement of memory cells
200.
Each block
310 comprises a plurality of flash cells laid out in a plurality
of rows and columns. The rows are formed in the wordline direction while the columns
are formed in bit line direction. Each flash cell comprises a lower floating gate
454 having a relatively high work function (i.e., higher than n+ polysilicon),
and interlayer or interpoly dielectric (not shown), a control gate
452,
and a source region
464 and a drain region
466. A common control
gate
452, (Or wordline) couples all flash cells of a row together while
a common bit line,
330, couples all the drains
466 of a column of
flash cells together as shown in FIG. 3
a. The bit lines are formed in a
first level metallization and uses contacts
320 to couple the drains together.
As shown in FIG. 3
a, each flash cell shares a source
464 with an
adjacent flash cell in the column and shares a drain
466 with the other
adjacent cell in the column. Shallow trench isolation regions
424 isolate
a column of flash cells from an adjacent column of flash cells as shown in FIG.
3
a. A common source rail
332 which runs parallel to the wordline
direction couples a row of shared source regions
464 together. The common
source rail
332 is formed through the isolation regions by removing the
portion
462 of the isolation region
424 between the shared source
regions
464 prior to implanting ions for the formation of source regions
464 as shown in FIG. 3
c. In this way, the source implant can dope
substrate region
463 so that the common source regions
464 in a row
are coupled together as shown in FIG. 3
d thereby requiring only a single
contact
322 to be made for every two rows of flash cells (e.g., second and
third rows). Since the source rail
332 is used to couple the shared source
regions
464 together, individual contacts are not necessary at the shared
source regions enabling minimum spacing to be utilized between adjacent memory
cells having a common source thereby decreasing the length of the memory cells.
As is readily apparent the combination of a high work function floating gate,
unlanded contacts, and a common source rail enables the fabrication of a memory
cell with a greatly reduced cell length.
In an embodiment of the present invention a combination of a self-aligned floating
gate, shallow trench isolation, and unlanded contacts are used to reduce cell width.
FIG. 2
c is an illustration of the memory cell of the present invention taken
along the width (wordline direction). As shown in FIG. 2
c, the memory cell
of the present invention utilizes narrow shallow trench isolation (STI) regions
264. In an embodiment of the present invention the shallow trench isolation
regions
264 are filled with silicon dioxide by a sequential deposition/etch/deposition
process or by a simultaneous deposition-etch process such as high density plasma
(HDP). Such SiO
2 deposition processes can fill gaps with narrow openings
and large aspect ratios without creating voids therein. Such shallow trench isolation
regions greatly reduce the cell width.
Another feature used to reduce the cell width is the fact that the floating
gate
206 is self-aligned between trench isolation regions
264 as
shown in FIG. 2
c. Floating gate
206 said to be self-aligned because
no alignment or masking is necessary to pattern a blanket deposited floating gate
material into individual floating gates. Self-aligning the floating gate eliminates
a critical masking layer in the process. A self-aligned floating gate can be formed
by blanket depositing a floating gate material and then chemical mechanical polishing
back the material to the top surface of the STI regions. The top surface of the
STI regions can then be removed to recess the STI beneath the top surface of the
floating gate to enable a large surface area capacitor to be formed between control
gate
210 and floating gate
206. Self-aligning the floating gate between
shallow trench isolation regions
264 greatly reduces the width necessary
to fabricate the memory cell.
Another feature which helps reduce the width of the cell is the use of unlanded
contacts as shown in FIGS. 2
a,
2c and
2d. As
described above the use of unlanded contacts allows the contacts to be misaligned
over isolation regions
264. The etch stop layer
262 prevents the
STI oxide from being etched out during the contact etch step. In this way, isolation
regions can be separated by the minimum distance (d
3) enabled by the
process resolution and registration thereby enabling a very narrow cell width.
As is readily apparent from FIGS. 2
a,
2c, and
2d,
the combination of a self-aligned floating gate, shallow trench isolation regions,
an unlanded contacts enables the fabrication of a memory cell with a very small width.
Method of Fabrication
A method of forming a flash memory integrated circuit in accordance with embodiments
of the present invention will now be explained with respect to cross-sectional
illustrations shown in FIGS. 4-34.
According to the present invention a silicon substrate is provided in which
the flash integrated circuit of the present invention is to be fabricated. In an
embodiment of the present invention the substrate
400 includes a monocrystalline
silicon substrate
402 having a p-type epitaxial silicon film
404
with a dopant density of between 5×10
14-5×10
15 atoms/cm
3
formed thereon. The starting substrate need not, however, be a silicon epitaxial
film formed on a monocrystalline silicon substrate and can be other types of substrates.
For the purpose of the present invention a substrate is defined as the starting
material on which devices of the present invention are fabricated.
According to the present invention first isolation regions are formed in
substrate
400. In order to fabricate high density integrated circuits the
isolation region are preferably shallow trench isolations (STI) regions. An STI
can be fabricated by thermally growing a pad oxide layer
406 onto the surface
of substrate
400 and then forming a silicon nitride layer
408 having
the thickness between 1500-2500
521 onto the pad oxide layer
406,
as shown in FIG.
4.
Next, as shown in FIG. 5, a photoresist mask
410 is formed using well
known masking, exposing, and developing techniques over nitride layer
408
to define locations
412 where isolation regions are desired. Isolation regions
will be used to isolate a column of cells from an adjacent column of cells and
for isolating the periphery active regions. Next, well known etching techniques
are used to remove silicon nitride layer
408 and pad oxide layer
406
from locations
412 where isolation regions are desired. Nitride layer
408
can be plasma etched using a chemistry comprising sulfur hexaflouride (SF
6)
and helium (He) and pad oxide
406 can be plasma etched with carbon hexaflouride
(C
2F
6) and helium (He). Next, as shown in FIG. 5 silicon
substrate
406 is etched to form trenches
414 where isolation regions
are desired. The silicon trench etching step of the present invention forms a trench
414 with tapered sidewall
416. Sidewalls
416 are tapered or
sloped to help enable a low source resistance rail to be formed. Sidewalls
416
are formed with a slope of between 60° to 80° from horizontal (i.e.,
from the silicon substrate surface) and preferably at 65° from horizontal.
Tapered sidewalls
416 can be formed by plasma etching with chlorine (Cl
2)
and helium (He). In an embodiment of the present invention trenches
414
are formed to a depth between 2000 to 4000 Å into silicon substrate
400.
Next, as shown in FIG. 6, photoresist mask
410 is removed and a thin,
thermal oxide
413 is grown over the sidewalls of trench
414. Thermal
oxide
413 can be grown by heating substrate
400 to a temperature
between 900-1000° C. while exposing the substrate to an oxidizing ambient
such as but not limited to O
2. Next, the thermal oxide
413 is
etched away using a wet etchant such as hydroflouric acid (HF). Next, as shown
in FIG. 7, (along the wordline direction) a second thermal oxide
418 is
grown on the silicon sidewalls of trench
414. In an embodiment of the present
invention thermal oxide
418 is grown with a two step oxidation process,
at first oxidation occurring in a dry ambient, such as O
2, followed
by a second oxidation occurring in a wet ambient (i.e., in an ambient including
water (H2O)). The oxide growth/etch/oxide growth process of the present invention
rounds the silicon corners
419 of trench
414. It is to be appreciated
that sharp trench corners can cause a weakness in the subsequently formed tunnel
oxide at the corners. A weak tunnel oxide at the trench corners can cause cells
in a single block to erase differently when tunneling electrons off the floating
gate. By rounding the trench corners with the oxide growth/etch/oxide growth process
of the present invention corners are rounded and all memory cells in a given memory
block can erase at the same rate. Rounded corners
419 of trench
414
enable the reliable integration of shallow trench isolation (STI) regions with
flash memory cells. Corner rounding also improves the performance of CMOS devices
in the periphery.
In an alternative method for rounding trench corners
419 one can first
expose trench
414 to an HF dip to remove a portion of the pad oxide beneath
the silicon nitride film and then grow oxide film
413 to round the corners.
If desired trench oxide
413 can then be etched away followed by the formation
of oxide
418.
Next, as shown in FIG. 8 a trench fill material
420 such as silicon
oxide, is blanket deposited by chemical vapor deposition (CVD) over silicon nitride
layer
408 and thermal oxide layer
418 in trench
414. In an
embodiment of the present invention trench fill material
420 is silicon
dioxide formed by a sequential deposition/etch/deposition process or by a simultaneous
deposition-etch process, such as high density plasma (HDP). The dielectric fill
material
420 is then polished back by chemical mechanical polishing until
the top surface
422 of the isolation region is substantially planar with
the top surface of silicon nitride layer
408 and all oxide removed from
the top of the silicon nitride as shown in FIG.
8. Next, as shown in FIG.
9, silicon nitride layer
408 and pad oxide layer
406 are removed
with well known techniques to form a shallow, compact, and planar isolation regions
424.
Next, n-type and p-type well implants are made. In one embodiment of the present
invention where the peripheral circuitry utilizes CMOS circuitry (i.e. utilizes
nMOS and pMOS transistors) an n-type implant is made as shown in FIG. 10. A photoresist
mask
426 is formed over the entire array portion of the integrated circuit
and over those portions of the periphery which are to be fabricated into n-type
devices. N-type dopants, such as phosphorous or arsenic, can be ion implanted at
dose between 3-8×10
12 atom/cm
2 and at an energy between
400-800 KeV to form n-type wells in substrate
400 to act as the channel
regions for the pMOS devices in the periphery.
Next, as shown in FIG. 11, photoresist mask
426 is removed with well
known techniques, and a second photoresist mask (not shown) is formed over the
periphery of substrate
400 to define the locations where p-well implants
are to be made. The p-well implant forms p-wells
428 between shallow trench
isolation regions
424. The p-well regions extend deeper into substrate
400
then STI regions
424. P-wells
428 can be formed by well known ion
implantation techniques utilizing boron (B
11) at an energy of between
300-500 KeV and a dose of between (5×10
12-2×10
13 atoms/cm
2).
Additionally, the p-we
