Title: Isolation device over field in a memory device
Abstract: A memory device includes isolation devices located between memory cells. A plurality of isolation lines connects the isolation devices to a positive voltage during normal operations but still keeps the isolation devices in the off state to provide isolation between the memory cells. A current control circuit is placed between the isolation lines and a power node for reducing a current flowing between the isolation lines and the power node in case a deflect occurs at any one of isolation devices.
Patent Number: 7,020,039 Issued on 03/28/2006 to Tran, et al.
| Inventors:
|
Tran; Luan C. (Meridian, ID);
Porter; Stephen R. (Boise, ID);
Graham; Scot M. (Boise, ID);
Howell; Steven E. (Boise, ID)
|
| Assignee:
|
Micron Technology, Inc. (Boise, ID)
|
| Appl. No.:
|
998483 |
| Filed:
|
November 29, 2004 |
| Current U.S. Class: |
365/222; 365/149; 365/63; 257/906 |
| Current Intern'l Class: |
G11C 7/00 (20060101) |
| Field of Search: |
365/222,149,63,51
257/906,905,71,69
|
References Cited [Referenced By]
U.S. Patent Documents
| 6177333 | Jan., 2001 | Rhodes.
| |
| 6212114 | Apr., 2001 | Cowles.
| |
| 6297129 | Oct., 2001 | Tran.
| |
| 6411555 | Jun., 2002 | Tran.
| |
| 6445610 | Sep., 2002 | Porter et al.
| |
| 6545899 | Apr., 2003 | Derner et al.
| |
| 6545904 | Apr., 2003 | Tran.
| |
| 6556467 | Apr., 2003 | Derner et al.
| |
| 6590817 | Jul., 2003 | Siek.
| |
| 6594173 | Jul., 2003 | Keeth.
| |
| 6607944 | Aug., 2003 | Tran.
| |
| 6660584 | Dec., 2003 | Tran.
| |
| 6661699 | Dec., 2003 | Walker.
| |
| 6735132 | May., 2004 | Siek.
| |
| 6785157 | Aug., 2004 | Arimoto et al.
| |
| 2001/0052612 | Dec., 2001 | Tran et al.
| |
| 2002/0140348 | Oct., 2002 | Takeuchi et al.
| |
| 2002/0195670 | Dec., 2002 | Tran.
| |
| 2003/0095428 | May., 2003 | Tran.
| |
| 2003/0102515 | Jun., 2003 | Tran et al.
| |
| 2003/0198111 | Oct., 2003 | Siek.
| |
| 2003/0203565 | Oct., 2003 | McQueen et al.
| |
| 2004/0016986 | Jan., 2004 | Meyer et al.
| |
Primary Examiner: Elms; Richard
Assistant Examiner: Le; Toan
Attorney, Agent or Firm: Schwegman, Lundberg, Woessner & Kluth, P.A.
Parent Case Text
This application is a Continuation of U.S. application Ser. No. 10/233,325,
filed Aug. 29, 2002, now U.S. Pat. No. 6,834,019, which is incorporated herein
by reference.
Claims
What is claimed is:
1. A memory device comprising:
a first memory cell including a first storage node formed in a first substrate region;
a second memory cell including a second storage node formed in a second substrate region;
an isolation device having an isolation gate responsive to a potential from a
power node for preventing conductivity between the first and second storage nodes; and
a resistive device coupled between the isolation gate and the power node for
reducing current flowing from the power node to a shorted circuit path caused by
a defect.
2. The memory device of claim 1, wherein the isolation device includes a first
electrode and a second electrode, wherein the first electrode shares the first
substrate region with the first storage node, and wherein the second electrode
shares the second substrate region with the second storage node.
3. The memory device of claim 2, wherein the isolation device further includes
a gate dielectric, wherein at least one portion of the gate dielectric is formed
in a trench in the substrate.
4. The memory device of claim 1, wherein the resistive device includes a resistor
having a first resistor terminal coupled to the isolation device and a second resistor
terminal coupled to the power node.
5. The memory device of claim 1, wherein the resistive device includes a transistor
having a first terminal coupled to the isolation device, a second terminal coupled
to the power node, and a gate coupled to a bias node.
6. A memory device comprising:
a first storage node for storing a first charge;
a second storage node for storing a second charge;
an isolation device responsive to a potential from a power node for providing
isolation between the first and second storage nodes; and
a resistive device coupled in a path between the isolation device and the power node.
7. The memory device of claim 6 further comprising an access transistor for transferring
the first charge between the first storage node and a bit line.
8. The memory device of claim 7 further comprising a second access transistor
for transferring the second charge between the second storage node and the bit line.
9. The memory device of claim 8 further comprising a first word line for providing
a voltage to a gate of the access transistor, and a second word line for providing
a voltage to a gate of the second access transistor.
10. The memory device of claim 9 further including a cell plate, wherein the
cell plate combines with first storage node for forming a first capacitor, and
wherein the cell plate combines with the second storage node for forming a second capacitor.
11. The memory device of claim 6, wherein the resistive device includes a resistor
having a first resistor terminal coupled to the isolation device and a second resistor
terminal coupled to the power node.
12. The memory device of claim 6, wherein the resistive device includes a transistor
having a first terminal coupled to the isolation device, a second terminal coupled
to the power node, and a gate coupled to a bias node.
13. A memory device comprising:
a first capacitor having a capacitor plate, and a first access transistor for
transferring a charge between the capacitor plate and a bit line;
a second capacitor having a capacitor plate, and second access transistor for
transferring a charge between the capacitor plate of the second capacitor and the
bit line;
an isolation device having a first electrode coupled to the capacitor plate of
the first capacitor, a second electrode coupled to the capacitor plate of the second
capacitor, and an isolation gate responsive to a voltage from a power node to prevent
conductivity between the first and second electrodes; and
a resistive device coupled in a path between the isolation gate and the power node.
14. The memory device of claim 13, wherein the isolation device further includes
a gate dielectric between the first and second electrodes, wherein the gate dielectric
has a thickness greater than a thickness of a transistor gate dielectric of each
of the first and second access transistors.
15. The memory device of claim 13, wherein the resistive device includes a resistor
having a first resistor terminal coupled to the isolation gate and a second resistor
terminal coupled to the power node.
16. The memory device of claim 13, wherein the resistive device includes a transistor
having a first terminal coupled to the isolation gate, a second terminal coupled
to the power node, and a gate coupled to a bias node.
17. A memory device comprising:
a substrate including a first doped region, a second doped region, a third doped
region, and a fourth doped region;
a first access transistor including a gate, a first terminal formed by the first
doped region, and a second terminal formed by the second doped region;
a second access transistor including a gate, a first terminal formed by the third
doped region, and a second terminal formed by the fourth doped region;
a first capacitor including a capacitor plate formed by the second doped region;
a second capacitor including a capacitor plate formed by the third doped region;
an isolation device including an isolation gate for receiving a potential from
a power node, a first electrode formed by the second doped region, a second electrode
formed by the third doped region; and
a resistive device coupled between the isolation gate and the power node.
18. The memory device of claim 17, wherein the isolation device has a threshold
voltage greater than a supply voltage of the memory device.
19. The memory device of claim 17, wherein the isolation device includes a gate
dielectric having a thickness greater than a thickness of a gate dielectric of
each of the first and second access transistors.
20. The memory device of claim 17, wherein the isolation device includes a gate
dielectric, wherein at least a portion of the gate dielectric of the isolation
device is formed in a trench in the substrate.
21. The memory device of claim 17, wherein the isolation device is configured
to be inactive during an operation of the memory device.
22. A memory device comprising:
a plurality of memory cells arranged in row pairs, each of the row pairs including
a first cell row and a second cell row, each memory cell of the first cell row
includes a storage node, each memory cell of the second cell row includes a storage node;
a plurality of isolation rows, each of the isolation rows including a plurality
of isolation devices, each of the isolation devices including an isolation gate
responsive to a potential from a power node for providing isolation between the
storage node of one of the memory cells in the first cell row and the storage node
of one the memory cells of the second cell row;
a plurality of isolation lines, each of the isolation lines coupling to the isolation
gate of each of the isolation devices within one of the isolation rows, the isolation
lines being arranged in M groups, wherein M is an integer, each of the M groups
having a group node and multiple isolation lines coupled to the group node; and
M current control circuits, each of the M current control circuits coupling between
the power node and the group node of one of the M groups.
23. The memory device of claim 22, wherein each of the M current control circuits
is configured to provide a resistance between the power node and a corresponding
group node of one of the M groups.
24. The memory device of claim 22, wherein each of the M current control circuits
includes a resistor coupled between the power node and a corresponding group node
of one of the M groups.
25. A memory device comprising:
a plurality of memory cells arranged in row pairs, each of the row pairs including
a first cell row and a second cell row, each memory cell of the first cell row
includes a storage node, each memory cell of the second cell row includes a storage node;
a plurality of isolation rows, each of the isolation rows including a plurality
of isolation devices, each of the isolation devices including an isolation gate
responsive to a potential from a power node for providing isolation between the
storage node of one of the memory cells in the first cell row and the storage node
of one the memory cells of the second cell row;
a plurality of isolation lines, each of the isolation lines coupling to the isolation
gate of each of the isolation devices within one of the isolation rows, the isolation
lines being arranged in M groups, wherein M is an integer, each of the M groups
having a group node and having at least one isolation line coupled to the group
node; and
a plurality of resistive device, each of the resistive device coupling between
the power node and the group node of one of the M groups.
26. The memory device of claim 25, wherein each of the resistive devices is configured
to provide a resistance between the power node and a corresponding group node of
one of the M groups.
27. The memory device of claim 25, wherein each of the resistive devices includes
a resistor coupled between the power node and a corresponding group node of one
of the M groups.
28. A system comprising:
a processor; and
a memory device coupled to the processor, the memory device including:
a first storage node for storing a first data;
a second storage node for storing a second data;
an transistor coupled between the first and second storage nodes, the isolation
device is configured to be responsive to a potential from a power node for providing
isolation between the first and second storage nodes; and
a resistor coupled in a path between the isolation device and the power.
29. The system of claim 28, wherein the first and second storage nodes are formed
in a substrate of the memory device, and wherein the isolation device includes
a gate dielectric, wherein at least a portion of the gate dielectric of the isolation
device is formed in a trench between the first and second storage nodes.
30. A method comprising:
forming a first storage node;
forming a second storage node;
forming an isolation device between the first and second storage nodes, the isolation
device being configured to be responsive to a potential from a power node for providing
isolation between the first and second storage nodes; and
forming a resistive device in a path between the isolation device and the power
node for controlling a current on the path.
31. The method of claim 30, wherein the first and second storage nodes are formed
in a substrate of the memory device, and wherein the isolation device includes
a gate dielectric, wherein at least a portion of the gate dielectric of the isolation
device is formed in a trench between the first and second storage nodes.
32. The method of claim 30, wherein the resistive device includes a resistor.
33. A method comprising:
activating a first access transistor to read a charge in a first storage node
of a first memory cell of a memory device;
activating a second access transistor to read a charge in a second storage node
of a second memory cell of the memory device;
turning off an isolation device to prevent conductivity between the first and
second storage nodes, wherein the isolation device includes a gate responsive to
a potential from a power node; and
modifying a resistance of a path between the power node and the gate of the isolation device.
34. The method of claim 33, wherein modifying the resistance includes inserting
a resistive device between the power node and the gate of the isolation device.
35. The method of claim 33, wherein the resistive device includes a resistor.
36. A method comprising:
forming an isolation device between a first storage node and a second storage
node of a memory device;
forming a power node to apply a potential from the power node to a gate of the
isolation device to prevent conductivity between the first and second storage nodes; and
placing a resistive device between the power node and the gate of the isolation
device to reduce current flowing from the power node to a short circuit point caused
in by a defect in the memory device.
37. The method of claim 36, wherein the resistive device includes a resistor.
38. The method of claim 36, wherein the short circuit point includes ground.
39. A memory device comprising:
a first memory cell including a first access transistor and a first capacitor
connected at a first storage node;
a second memory cell including a second access transistor and a second capacitor
connected at a second storage node;
an isolation device including an isolation gate, a first electrode connected
to the first storage node, and a second electrode connected to the second storage
node; and
a current control circuit connected between the isolation gate and a power node
for modifying a resistance between the isolation gate and the power node.
40. The memory device of claim 39, wherein current control circuit is configured
to provide a resistance between the isolation gate and the power node for reducing
a current flowing between the isolation gate and the power node when a defect occurs
to the isolation gate.
41. The memory device of claim 39, wherein the power node connects to ground.
42. The memory device of claim 39, wherein the power node connects to a negative voltage.
43. The memory device of claim 39, wherein each of the first and second access
transistors includes a gate dielectric with a gate dielectric thickness, and the
isolation device further includes an isolation dielectric with a thickness greater
than the gate dielectric thickness.
44. The memory device of claim 39, wherein each of the first and second access
transistors includes an access threshold voltage, and the isolation device further
include a threshold voltage greater than the access threshold voltage.
45. The memory device of claim 39, wherein each of the first and second memory
cells has an area of 6F
2.
46. A memory device comprising:
a plurality of memory cells arranged in rows and columns, the rows being arranged
in row pairs, each of the row pairs including a first cell row and a second cell
row, wherein:
each memory cell of the first cell row includes a first access transistor and
a first capacitor connected at a first storage node; and
each memory cell of the second cell row includes a second access transistor and
a second capacitor connected at a second storage node; and
a plurality of isolation rows, each of the isolation rows including a plurality
of isolation devices, each of the isolation devices including an isolation gate,
a first electrode connected to the first storage node, a second electrode connected
to the second storage node, each of the isolation devices being configured to provide
electrical isolation between the first and second storage nodes;
a plurality of isolation lines, each of the isolation lines connecting to the
isolation gate of each of the isolation devices of one of the isolation rows, the
isolation lines being arranged in M groups, each of the M groups having a group
node and having at least one isolation line connected at the group node; and
M current control circuits, each of the M current control circuits connecting
between a power node and the group node of one of the M groups.
47. The memory device of claim 46, wherein M equals the number of isolation lines.
48. The memory device of claim 46, wherein M is at least one.
49. The memory device of claim 46, wherein each of the M current control circuits
is configured to provide a resistance between the power node and a corresponding
group node of one of the M groups.
50. The memory device of claim 46, wherein the current control circuit includes
a transistor having a first electrode connected to the isolation line, a second
electrode connected to the power node, and a gate connected to bias node.
51. The memory device of claim 46, wherein power node connects to a positive voltage.
52. The memory device of claim 46, wherein each of the first and second access
transistors includes a gate dielectric with a gate dielectric thickness, and each
of the isolation devices further includes an isolation dielectric with a thickness
greater than the gate dielectric thickness.
53. The memory device of claim 46, wherein each of the isolation devices includes
an isolation dielectric having a shallow trench isolation structure.
54. The memory device of claim 46, wherein each of the first and second access
transistors includes an access threshold voltage, and each of the isolation devices
further includes a threshold voltage greater than the access threshold voltage.
55. The memory device of claim 46 further comprising a plurality of word lines,
each of the word lines connecting to a gate of each of the access transistors in
one of the rows, and a plurality of bit lines, each of the bit lines connecting
to an electrode of each of the access transistors in one of the columns.
56. A memory device comprising:
a first memory cell including a first access transistor and a first capacitor,
the first access transistor including an electrode connected to the first capacitor
via a first storage node formed in a substrate;
a second memory cell including a second access transistor and a second capacitor,
the second access transistor including an electrode connected to the second capacitor
via a second storage node formed on the substrate;
an isolation device formed between the first and second storage nodes and configured
to providing electrical isolation between first and second storage nodes, the isolation
device including an isolation gate; and
an isolation line connected to the isolation gate for holding the isolation gate
at a positive voltage.
57. The memory device of claim 56, wherein each of the first and second access
transistors includes a gate dielectric with a gate dielectric thickness, and the
isolation device further includes an isolation dielectric with an isolation dielectric
thickness greater than the gate dielectric thickness.
58. The memory device of claim 56, wherein each of the first and second access
transistors including a gate dielectric formed above the substrate, and the isolation
device further includes an isolation dielectric with at least a portion of the
isolation dielectric formed within the substrate.
59. The memory device of claim 56, wherein the isolation dielectric includes
an isolation dielectric having a trench formed in the substrate between the first
and second storage nodes.
60. The memory device of claim 56, wherein the first access transistor further
includes a second electrode connected to a first bit line contact, and the second
access transistor further includes a second electrode connected to a second bit
line contact.
61. A memory device comprising:
a substrate;
a first memory cell including a first access transistor formed by a first doped
region and a second doped region of the substrate and by a gate separated from
the substrate by a first gate dielectric formed on the substrate opposing a first
channel region between the first and second doped regions;
a second memory cell including a second access transistor formed by a third doped
region and a fourth doped regions of the substrate and by a gate separated from
the substrate by a second gate dielectric formed on the substrate opposing a second
channel region between the third and fourth doped regions, each of the first and
second access transistors having an access threshold voltage;
an isolation device formed by the second and third doped regions and by an isolation
gate separated from the substrate by an isolation dielectric formed in the substrate
between the second and third doped regions, the isolation device having an isolation
threshold voltage greater than the access threshold voltage; and
an isolation line connected to the isolation gate for holding the isolation gate
at a positive voltage.
62. The memory device of claim 61, wherein:
the first memory cell further includes a capacitor having a capacitor plate corresponding
to the second doped region; and
the second memory cell further includes a capacitor having a capacitor plate
corresponding to the third doped region.
63. The memory device of claim 62, wherein the isolation threshold voltage is
at least three times greater than a supply voltage of the memory device.
64. The memory device of claim 61, wherein a thickness of the isolation dielectric
is greater than a thickness of each of the first and second gate dielectrics.
65. The memory device of claim 61, wherein the isolation dielectric includes
a trench formed in the substrate and in between the second and third doped regions.
66. The memory device of claim 61, wherein the isolation device is configured
to be inactive during a normal operation of the memory device.
67. The memory device of claim 61, wherein a each of the first and fourth doped
regions includes a halo implant portion.
68. A system comprising:
a processor; and
a memory device connected to the processor, the memory device including:
a plurality of memory cells arranged in rows and columns, the rows being arranged
in row pairs, each of the row pairs including a first cell row and a second cell
row, wherein:
each memory cell of the first cell row includes a first access transistor and
a first capacitor connected at a first storage node; and
each memory cell of the second cell row includes a second access transistor and
a second capacitor connected at a second storage node; and
a plurality of isolation rows, each of the isolation rows including a plurality
of isolation devices, each of the isolation devices including an isolation gate,
a first electrode connected to the first storage node, a second electrode connected
to the second storage node, each of the isolation devices being configured to provide
electrical isolation between the first and second storage nodes;
a plurality of isolation lines, each of the isolation lines connecting to the
isolation gate of each of the isolation devices of one of the isolation rows, the
isolation lines being arranged in M groups, each of the M groups having a group
node and having at least one isolation line connected at the group node; and
M current control circuits, each of the M current control circuits connecting
between a power node and the group node of one of the M groups.
69. The system of claim 68, wherein M equals the number of isolation lines.
70. The system of claim 68, wherein M is at least one.
71. The system of claim 68, wherein each of the M current control circuits is
configured to provide a resistance between the power node and a corresponding group
node of one of the M groups.
72. The system of claim 68, wherein each of the first and second access transistors
includes a gate dielectric with a gate dielectric thickness, and each of the isolation
devices includes an isolation dielectric with a thickness greater than the gate
dielectric thickness.
73. The system of claim 68, wherein each of the isolation devices includes an
isolation dielectric having a trench formed in the substrate between the first
and second storage nodes.
74. The system of claim 68, wherein each of the first and second access transistors
including an access threshold voltage, and each of the isolation devices including
a threshold voltage greater than the access threshold voltage.
75. A method comprising:
forming a first memory cell including forming a first access transistor and a
first capacitor, the first access transistor including an electrode connected to
the first capacitor via a first storage node formed on a substrate;
forming a second memory cell including forming a second access transistor and
a second capacitor, the second access transistor including an electrode connected
to the second capacitor via a second storage node formed on the substrate;
forming an isolation device between the first and second storage node contacts
and configured to provide electrical isolation between first and second storage
nodes, wherein forming the isolation device includes forming an isolation gate; and
forming a current control circuit between the isolation gate and a power node
for modifying the resistance between the isolation gate and the power node.
76. The method of claim 75, wherein forming each of the first and second memory
cells includes forming a gate dielectric with a gate dielectric thickness, and
forming the isolation device includes forming an isolation dielectric with an isolation
dielectric thickness greater than the gate dielectric thickness.
77. The method of claim 75, wherein forming an isolation devices includes forming
an isolation dielectric having a trench formed in the substrate between the first
and second storage nodes.
78. The method of claim 75, wherein forming each of the first and second memory
cells includes forming each of the first and second access transistors with an
access threshold voltage, and forming the isolation device includes forming the
isolation device with a threshold voltage greater than the access threshold voltage.
79. A method comprising:
providing a substrate having a first memory cells area, a second memory cell
area, and an isolation device area between the first and second memory cells areas;
forming a first memory cell on the first memory cell area, the first memory cell
having a first access transistor and a first capacitor connected together at first
storage node formed on a substrate;
forming a second memory cell on the second memory cell area, the second memory
cell having a second access transistor and a second capacitor connected together
at a second storage node on the substrate;
forming an isolation device on the isolation device area for electrically isolating
the first and second memory cells, the isolation device having an isolation gate; and
forming an isolation line connecting the isolation gate to a positive voltage.
80. The method of claim 79, wherein forming the isolation device includes forming
an isolation dielectric separating the isolation gate from the substrate, wherein
forming the isolation dielectric includes:
forming a shallow trench over the isolation device area; and
filling the shallow trench with dielectric material.
81. The method of claim 80, wherein forming each of the first and second memory
cells includes forming a gate dielectric above the substrate at each of the first
and second transistors.
82. The method of claim 80 further comprising:
implanting dopant into the shallow trench before filling the shallow trench.
83. The method of claim 79, wherein forming each of the first and second memory
cells includes:
forming the first access transistor having a first electrode connected to the
first capacitor via a first diffusion region in the substrate, and having a second
electrode connected to a bit line contact via a second diffusion region in the substrate;
forming the second access transistor having a first electrode connected to the
second capacitor a third diffusion region in the substrate, and a second electrode
connected to a second bit line contact a fourth diffusion region in the substrate; and
implanting halo implant only in the second and fourth diffusion regions.
84. The method of claim 79, wherein forming the first and second memory cells
include forming each of the first and second access transistors with an access
threshold voltage, and forming the isolation device includes forming the isolation
device with a threshold voltage greater than the access threshold voltage.
Description
FIELD
The present invention relates generally to semiconductor devices, and in particular
to memory devices.
BACKGROUND
Memory devices reside in computers and many electronic products to store data.
A typical memory device has many memory cells, each holding a charge that represents
a value of a bit of data.
Some memory devices hold the charge in a capacitor of each memory cell. The
charge in the capacitor leaks overtime. Therefore, some of these memory devices
have refresh cycles to frequently refresh the charge to maintain its original value
to keep the data valid.
In some memory devices, the charge in the capacitor of one memory cell leaks
to
the substrate or to an adjacent capacitor of another memory cell. This leakage
reduces the retention time of the memory cell and may create invalid data. Isolation
techniques have been designed to isolate adjacent memory cells to extend the retention
time of the charge in the capacitor and to reduce the number of refresh cycles.
In some cases, these isolation techniques provide inadequate isolation. Thus,
the number of the refresh cycles is increased. Increasing the number of refresh
cycles wastes power and reduces the time that the valid data is available.
Further, some memory devices use a double-row redundancy method, in which
two redundant rows of memory cells are used when a defect occurs in one of the
rows; one redundant row replaces the row with the defect and the other redundant
row replaces the adjacent row although the adjacent row has no defect. This double-row
redundancy method is used because the isolation devices in these memory devices
may not provide enough insolation between adjacent rows.
SUMMARY OF THE INVENTION
The present invention provides structures and methods for improving isolation
between adjacent memory cells to reduce the charge leakage, to improve the refresh
operation, increase the time availability of the data, and offer alternative ways
for replacing defected memory cells.
One aspect provides a memory device with a first memory cell having a first access
transistor and a first capacitor. The first access transistor connects to the first
capacitor at a first storage node. A second memory cell includes a second access
transistor and a second capacitor. The second access transistor connects to the
second capacitor at a second storage node.
The memory device also includes an isolation device having an isolation gate,
a first electrode connected to the first storage node, a second electrode connected
to the second storage node. The isolation device is configured to provide electrical
isolation between the first and second storage nodes.
The memory device further includes a current control circuit connected between
the isolation gate and a power node for modifying a resistance between the isolation
gate and the power node.
Another aspect offers a method of forming a memory device. A first memory
cell is formed on a first memory cell area in a substrate. The first memory cell
has a first access transistor and a first capacitor connected together at a first
storage node formed on a substrate. A second memory cell is formed on a second
memory cell area of the substrate. The second memory cell has a second access transistor
and a second capacitor connected together at a second storage node on the substrate.
The method also includes forming an isolation device on the isolation device area
for electrically isolating the first and second memory cells. The isolation device
has an isolation gate. The method further includes forming an isolation line for
connecting the isolation gate to a positive voltage.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic diagram of a memory array according to an embodiment of
the invention.
FIGS. 2-3 show various alternative embodiments of a portion of the memory array
of FIG. 1.
FIGS. 4-7 show examples a current control circuit of FIGS. 1-3.
FIG. 8 is a simplified top view of a circuit layout of the memory array of FIG. 1.
FIG. 9 is a cross-section of structures of a number of memory cells and an isolation
device according to an embodiment of the invention.
FIGS. 10-13 show various processing stages during the construction of the structures
of FIG. 9 according to an embodiment of the invention.
FIG. 14 is a simplified cross-section of the structures of FIG. 9 at a processing
stage according an embodiment of the invention.
FIG. 15 shows a memory device according to an embodiment of the invention.
FIG. 16 shows a system according to an embodiment of the invention.
DESCRIPTION OF EMBODIMENTS
The following description and the drawings illustrate specific embodiments of
the invention sufficiently to enable those skilled in the art to practice it. Other
embodiments may incorporate structural, logical, electrical, process, and other
changes. In the drawings, like numerals describe substantially similar components
throughout the several views. Examples merely typify possible variations. Portions
and features of some embodiments may be included in or substituted for those of
others. The scope of the invention encompasses the full ambit of the claims and
all available equivalents.
FIG. 1 is a schematic diagram of a memory array according to an embodiment of
the invention. Memory array
100 includes many memory cells (CELL) arranged
in rows (CELL ROW) and columns (CELL COL), the rows being arranged in row pairs
(ROW PAIR) with each including a first cell row (CELL ROW
1) and a second
cell row (CELL ROW
2). For simplicity, FIG. 1 shows only three row pairs
and two cell columns of memory array
100. Other row pairs and columns have
elements similar to the elements of the row pairs and cell columns shown in FIG. 1.
Each of the memory cells includes an access transistor and a capacitor. For
example, memory cell
101 of the first cell row includes an access transistor
121 connected to a capacitor
131 at a first storage node
141.
Memory cell
102 of the second cell row includes an access transistor
122
connected to a capacitor
132 at a second storage node
142. Each of
the storage nodes connects to one plate of the capacitor. The other plate of each
of the capacitors connects to a potential node (cell plate)
140, which connects
to ground or to a positive voltage to set the initial amount of charge of the capacitor.
A number of word lines (WL) extend along the cell rows. Each cell row has a corresponding
word line. In a cell row, the corresponding word line connects to all of the gates
of the access transistors in that cell row. For example, in CELL ROW
1, word
line WL
1 connects to the gates of transistors
121 and
191
and in CELL ROW
2, word line WL
2 connects to the gates of access transistors
122 and
192.
A number of bit lines (BL) extend along the cell columns. Each cell column has
a corresponding bit line. In a cell column, the corresponding line connects to
all of the access transistors in that cell column at an electrode of each of the
access transistors via a bit line contact
144. For example, in CELL COL
1,
bit line BL
1 connects to electrode
151 of access transistor
121
and electrode
152 of access transistor
122. In the description, an
electrode of a transistor corresponds to either the source or the drain of the transistor.
A number of isolation rows (ISO ROW) run in parallel with the cell rows. Each
isolation
row is located between the first and second cell rows of each row pair. For example
isolation row
1 (ISO ROW
1) is located between CELL ROW
1 and
CELL ROW
2 of ROW PAIR
1. Each of the isolation rows includes many
isolation devices (ISO).
Each of the isolation devices has an isolation gate, and a first electrode and
a second electrode connected between two adjacent storage nodes. For example, isolation
device
103 of ISO ROW
1 has a gate
110, a first electrode connected
to storage node
141, and a second electrode connected to storage node
142.
A number of isolation lines (ISOL) extend along the isolation rows and in parallel
with the word lines. Each isolation row has a corresponding isolation line. In
an isolation row, the corresponding isolation line connects to all of the isolation
gates of the isolation devices in that isolation row. For example, in ISO ROW
1,
isolation line ISOL
1 connects to isolation gates of isolation devices
103
and
193.
Memory array
100 further includes a current control circuit
160
connected between a group node
162 and a power node
164. Node
162
connects all of the isolation lines together. A voltage generator
170 connects
to node
164 for providing a voltage. In some embodiments, voltage generator
170 generates either a negative voltage or a positive voltage. Node
162
has a voltage V
1 and node
164 has a voltage V
2. In some embodiments,
V
1 equals the supply voltage (Vcc) of the memory array. In other embodiments,
V
1 is a positive voltage of about 2.4 volts. In some other embodiments,
V
1 is positive voltage ranging from about 1.4 volts to about 2.8 volts.
In alternative embodiments, V
2 equals ground. In some of these alternative
embodiments, voltage generator
170 can be omitted and node
164 can
be connected to ground.
Each of the memory cells stores a charge at the storage node of the capacitor.
The charge represents a value of a data bit. The access transistor accesses the
charge during a read operation and transfers it to the corresponding bit line.
A sense amplifier circuit (not shown) connected to the corresponding bit line translates
the charge into the value of the data bit and outputs the data bit to other circuits
for processing. A write operation writes a data bit into a memory cell in a reverse
fashion from the read operation. Sense amplifier circuits and their operations
in memory devices are well known.
To read the charge in memory cell
101, a voltage is applied to word line
WL
1 to turn on access transistor
121. When transistor
121
turns on, it transfers the charge from node
141 to bit line BL
1 via
the bit line contact
144 connected to transistor
121. Similarly,
to read the charge in memory cell
102, a voltage is applied to word line
WL
2 to turn on access transistor
122. When transistor
122
turns on, it transfers the charge from node
142 to bit line BL
1 via
the bit line contact
144 connected to transistor
122.
Each of the isolation devices is configured to provide electrical isolation
between two adjacent memory cells. To provide the isolation, each of the isolation
devices is configured to be in an inactive state (off) to prevent conductivity
between two adjacent storage nodes of two adjacent memory cells. To turn off the
isolation devices and thus to improve the isolation function, an appropriate voltage
is applied to all of the isolation gates of the isolation devices.
In one configuration, V
1 is set at a positive voltage and below a threshold
voltage of the isolation devices to turn off the isolation devices. For example,
isolation device
103 is turned off to prevent conductivity between storage
nodes
141 and
142 because the voltage at isolation gate
110
is below the threshold voltage of isolation device
103. A threshold voltage
of a device (transistor) is the voltage at which the device starts to conduct (turn
on). Since isolation gate
110 connects to isolation line ISOL
1, the
voltage on ISOL
1 is set to be less than the threshold voltage of isolation
device
103. Since ISOL
1 connects to node
162, the voltage
V
1 at node
162 is set below the threshold voltage of isolation device
103.
In some embodiments, the isolation devices are made so that their threshold voltage
is about at least three times greater than the supply voltage of memory array
100.
For example, in some embodiments, the threshold voltage of isolation device
103
is about ten volts and the supply voltage is about two to three volts. Since the
threshold voltage of the isolation devices is least three times greater than the
supply voltage allows the isolation devices, the isolation devices do not turn
on (still in the off state) but the access transistors turn on when a voltage equal
to or slightly greater than the supply voltage is applied to the isolation gates
and the gates of the access transistors. When the isolation devices are in the
off state, they provide isolations between the memory cells.
Current control circuit
160 is configured to provide a resistance
between nodes
162 and
164 to limit the flow of current between nodes
162 and
164 in case of a defect occurring at one of the isolation
lines. In some embodiments, current control circuit
160 includes a resistor
connected between node
162 and
164.
In a normal condition, the circuit path between voltage generator
170
and
isolation device
110 is an open circuit path because isolation device
110
normally turns off (non-conductive). Thus, no current flows between nodes
162
and
164, and V
1 equals V
2. In some embodiments, voltage generator
170 generates a positive voltage V
2. Thus, in these embodiments,
V
1 is also positive and equals V
2.
In some cases, a defect in memory array
100 may short one of the isolation
lines to another element. For example, a defect may short isolation line ISOL
1
to an element connected to ground. In this case, the open circuit path between
generator
170 and isolation line ISOL
1 becomes a closed circuit path
connecting generator
170, isolation line ISOL
1, and ground. Without
current control circuit
160, a certain amount of current flows between voltage
generator
170 and ground via the shorted isolation line ISOL
1. Thus,
a certain amount of power is wasted. With current control circuit
160, the
resistance provided by current control circuit
160 between nodes
164
and
162 limits (reduces) the amount of the current flowing between these
two nodes. Since the amount of current is reduced, the amount of wasted power is
also reduced.
FIGS. 2 and 3 show various alternative embodiments of a portion of the memory
array of FIG. 1. In FIG. 2, each of the isolation lines connects to a separate
group node
262 and connects to power node
164 through a separate
current control circuit
160. Node
262 corresponds to node
162
(FIG. 1). Power node
164 can be connected to a single voltage generator
such as voltage generator
170 (FIG. 1) or to a number of separate voltage generators.
In FIG. 3, the isolation lines are divided into M groups (M
1 through MX)
with each group having N isolation lines. Each of the M groups has a group node
362 connecting together all the N isolation lines within the group. Node
362 corresponds to node
162 (FIG. 1). M is at least one and N is
at least one. Each of the M groups connects to node
164 via a separate current
control circuit
160. Power node
164 can be connected to a single
voltage generator such as voltage generator
170 (FIG. 1) or to a number
of separate voltage generators.
FIGS. 4-7 show examples of the current control circuit of FIGS. 1-3. Node
162
in FIGS. 4-7 corresponds to node
162,
262, and
362 (FIGS.
1-3). In FIG. 4, current control circuit
160 includes a resistor
400
connected between node
162 and
164. The resistance between nodes
162 and
164 can be selected by choosing the resistance value of resistor
400.
FIG. 5 shows current control circuit
160 including a transistor
500
having a first electrode (source or drain) connected to node
162, a second
electrode connected to node
164, and a gate connected to a bias node. A
bias unit
502 generates a voltage V
3 to turn on transistor
500.
The resistance between nodes
162 and
164 is chosen by selecting the
appropriate size of the transistor
500, and V
3. The size of transistor
500 is selected by choosing its channel length and channel width. In some
embodiments, the channel length of transistor
500 is about ten times greater
than a channel length of a typical transistor. For example, the channel length
of transistor
500 is about one micrometer while the channel length of a
typical transistor is about 100 nanometers.
FIG. 6 shows current control circuit
160 including multiple transistors
600 and
602 connected in series between nodes
162 and
164.
A bias unit
604 generates a voltage V
4 to control the gates of transistors
600 and
602. In some embodiments, the gates of transistors
600
and
602 connect to separate bias units to receive separate voltages. The
resistance between nodes
162 and
164 is chosen by selecting appropriate
size of each of the transistors
600 and
602, and V
4. In some
embodiments, the channel length of each of the channel length of transistors
600
and
602 can be longer than a channel length of a typical transistor.
FIG. 7 shows current control circuit
160 including N transistors
700
and
799 connected in parallel between nodes
162 and
164. N
can be any integer equal to or greater than two. For simplicity, FIG. 7 shows two
transistors, thus N equals two. The channel width (W) of one of the transistors
700 and
799 is a multiple of two larger than the channel width of
another transistor. For example, transistor
700 has a channel width of W
and transistor
799 has a channel width of 2
(N-1)W=2W. In embodiments
where N equals four, the channel widths of the transistors are 1W, 2W, 4W, and
8W. This kind of pattern is a binary weighted pattern. Thus, transistors
700
and
799 are binary weighted transistors.
Since each of the binary weighted transistors
700 and
799 has
unequal channel width, each of these transistors provides unequal resistance between
its electrodes connected between nodes
162 and
164. The total resistance
between nodes
162 and
164 can be chosen by controlling voltages V
5
and V
6 at the gates of the transistors. For example, when both V
5
and V
6 are selected to be sufficient to turn on both transistors
700
and
799, the resistance between nodes
162 and
164 equals the
parallel resistances of both transistors
700 and
709. As another
example, when only one of the V
5 or V
6 is selected to turn on only
one of the transistors
700 and
709, the resistance between nodes
162 and
164 equals the resistance of the transistor that turns on.
Besides the embodiments shown in FIGS. 4-7, other circuits that create a resistance
between nodes
162 and
164 can also be used as current control circuit
160.
FIG. 8 is a simplified top view of a circuit layout of the memory array of FIG.
1. Shallow trench isolation (STI) areas
802 are represented as stippled
areas following a serpentine path across the memory array
100, with active
areas
804 intervening between adjacent STI areas
802. Active areas
804 are shown as areas that are void of the stippled STI areas
802.
Bit lines BL, shown as hatched areas, also follow a serpentine path across memory
array
100, but are typically formed much later in processing than the STI
areas
802.
Word lines WL extend along an axis intersecting the STI areas
802 and
bit lines BL, and extend across portions of the active areas
804 where word
lines BL connect the gates of access transistors such as such as gates
133
(FIG. 1).
Isolation lines ISOL interspersed between selected ones of the word lines
WL. Memory array
100 further includes capacitor containers
808, represented
as rectangles, and bit line contacts
144, represented as circles. Container
capacitors formed within the capacitor containers
808 are coupled to the
active areas via storage node contacts
812. In some embodiments, the storage
node contacts
812 include conductive material extending to selected portions
of the active area
804 and shown schematically as octagons at one end of
each of the capacitor containers
808.
A cell plate (not shown) formed of a conductive material such as doped polysilicon
extends across the tops of the capacitor containers
808 and forms a common
second plate of each of the capacitors, such as capacitors
131 and
132
(FIG. 1). The cell plate connects to either ground or a voltage.
Each memory cell (FIG. 1) within memory array
100 includes part of one
of the bit line contacts
144 (these are shared by adjacent memory cells),
a storage node contact
812, a portion of one active area
804, a portion
of one isolation line ISOL, and a portion of one STI area
802, and is bounded
on one side by a corresponding portion of another STI area
802. Isolation
between storage node contacts
812 formed in a common portion of an active
area
804 that includes one of the bit line contacts
144 results because
only one of the pair of word lines WL traversing the common portion of active area
804 is activated (applied with a voltage) at any one time.
As a result, the architecture shown in FIG. 8 provides a memory cell having an
area equal to about 3F×2F, or less, where "F" equals one-half of a minimum
pitch "P". "P" is the smallest distance of width "W" of a line plus the width of
a space immediately adjacent to the line on one side of the line between the line
and a next adjacent line in a repeated pattern "S" within the array. Thus, in FIG.
2 the consumed area of a given memory cell is no greater than about 6F
2.
Sectional line
9—
9 is a portion of the circuit layout
that is shown in sectional view in FIG. 9.
FIG. 9 is a cross-section of structures of a number of memory cells and an isolation
device according to an embodiment of the invention. For ease of understanding,
FIG. 9 also includes a corresponding schematic diagram of a portion of memory array
100 of FIG. 1. For simplicity, both the schematic diagram and the structural
diagram have the same reference numbers for similar elements. FIG. 9 shows structures
of memory cells
901 and
902, and isolation device
903, word
lines WL
1 and WL
2, and one of the bit lines BL. Other memory cells
and isolation devices have similar structures as that shown in FIG. 9.
Structures shown in FIG. 9 are formed on top of a semiconductive substrate
905, such as monocrystalline silicon. In the context of this description,
the term "semiconductive substrate" refers to any construction having semiconductive
material, including, but not limited to, bulk semiconductive materials such as
a semiconductive wafer (either alone or in assemblies including other materials
thereon), and semiconductive material layers (either alone or in assemblies including
other materials). The term "substrate" refers to any supporting structure, including,
but not limited to, the semiconductive substrates described above.
Memory cells
901 and
902, and isolation device
903 correspond
to memory cells
101 and
102, and isolation device
103 (FIG. 1).
Memory cell
901 includes diffusion regions
951 and
941
formed on substrate
905, and gate
133 formed above the substrate
and separated from the substrate by a gate dielectric
933 with a gate dielectric
thickness T
1. Diffusion regions
951 and
941, and gate
133
and gate dielectric
933 below WL
1 form an access transistor
921
corresponding to access transistor
121 (FIG. 1).
Bit line contact
144 of memory cell
901 is formed on diffusion
region
951 and is insulated from laterally adjacent structures by a conventional
dielectric sidewall
947. Bit line contact
144 of memory cell
901
connects to bit line BL formed atop via a connection shown as a dashed li
