Large-area nanoenabled macroelectronic substrates and uses therefor Number:7,135,728 from the United States Patent and Trademark Office (PTO) owispatent

Title: Large-area nanoenabled macroelectronic substrates and uses therefor

Abstract: A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.

Patent Number: 7,135,728 Issued on 11/14/2006 to Duan,   et al.

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Inventors:	Duan; Xiangfeng (Mountain View, CA), Niu; Chunming (Palo Alto, CA), Empedocles; Stephen A. (Menlo Park, CA), Romano; Linda T. (Sunnyvale, CA), Chen; Jian (Mountain View, CA), Sahi; Vijendra (Menlo Park, CA), Bock; Lawrence A. (Encinitas, CA), Stumbo; David P. (Belmont, CA), Wallace; Parce J. (Palo Alto, CA), Goldman; Jay L. (Mountain View, CA)
Assignee:	Nanosys, Inc. (Palo Alto, CA)
Appl. No.:	11/106,340
Filed:	April 13, 2005

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Current U.S. Class:	257/296 ; 257/14; 257/18; 257/19; 257/746; 257/784; 257/9; 257/E51.04; 977/762; 977/781; 977/789
Current International Class:	H01L 27/108 (20060101); H01L 29/76 (20060101); H01L 29/94 (20060101); H01L 31/119 (20060101)
Field of Search:	257/E51.006,E51.04,296,14,19,18,9,746,784 977/DIG.1,762,789

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References Cited [Referenced By]

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U.S. Patent Documents

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Other References

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Primary Examiner: Zarneke; David
Assistant Examiner: Anya; Igwe U.
Attorney, Agent or Firm: Filler; Andrew L.

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Parent Case Text

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CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 10/674,060 filed Sep. 30, 2003 which claims priority to the following U.S. Provisional Applications, all of which are incorporated herein by reference in their entireties:

Provisional Application No. 60/414,323, filed Sep. 30, 2002;

Provisional Application No. 60/414,359, filed Sep. 30, 2002;

Provisional Application No. 60/445,421, filed Feb. 5, 2003;

Provisional Application No. 60/468,276, filed May 7, 2003;

Provisional Application No. 60/474,065, filed May 29, 2003; and

Provisional Application No. 60/488,801, filed Jul. 22, 2003.

The following application is related to the present application, has the same filing date as the present application, and is herein incorporated by reference in its entirety:

"Integrated Displays Using Nanowire Transistors,", Ser. No. 10/673,669;

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Claims

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The invention claimed is:

1. A device comprising: a substrate; a thin film consisting of a plurality of nanowires or a plurality of nanowires in solution-on the substrate, wherein each of said plurality of nanowires have a same conductive property as each of the other nanowires in said thin film; a first source contact and a first drain contact formed in or on the substrate, wherein at least two or more of the plurality of nanowires form a channel between said first source and drain contacts; and a first gate contact formed on, above or below said at least two or more nanowires.

2. The device of claim 1, wherein at least five or more nanowires form a channel between said first source and drain contacts.

3. The device of claim 1, wherein at least ten or more nanowires form a channel between said first source and drain contacts.

4. The device of claim 1, whereinat least 100 or more nanowires form a channel between said first source and drain contacts.

5. The device of claim 1, wherein the plurality of nanowires comprises nanowires selected from Group II VI semiconductors, Group III V semiconductors and Group IV semiconductors.

6. The device of claim 1, wherein the plurality of nanowires comprises a plurality of nanoribbons.

7. The device of claim 1, wherein the plurality of nanowires are aligned substantially parallel to their long axis.

8. The device of claim 1, wherein said substrate comprises a flexible substrate.

9. The device of claim 1, wherein said at least two or more wires of the plurality of nanowires have a sufficient density on the substrate to provide an operational current level of at least about 2 nanoamps.

10. The device of claim 1, wherein said at least two or more nanowires of the plurality of nanowires have a sufficient density on the substrate to provide an operational current level of at least about 10 nanoamps.

11. The device of claim 1, wherein each of said plurality of nanowires comprises one or more shell layers.

12. The device of claim 11, wherein said one or more shell layers comprises an oxidized shell layer to thereby form a gate dielectric about said nanowires.

13. The device of claim 1, wherein the at least two or more nanowires of the plurality of nanowires provides an electron mobility of greater than about 10 cm.sup.2/Vs between said first source and drain contacts.

14. The device of claim 1, wherein said first gate contact is formed on said at least two or more nanowires.

15. The device of claim 1, wherein the plurality of nanowires comprises a thin film of magnetic nanowires, a thin film of ferroelectric nanowires, a thin film of thermoelectric nanowires, a thin film of piezoelectric nanowires, a thin film of metallic nanowires, a thin film of transition metal oxide nanowires, or any combination thereof.

16. The device of claim 1, wherein the plurality of nanowires are aligned on said substrate by a process selected from the group comprising spin-casting, Langmuir-Blodgett alignment, mechanical alignment, and flow-alignment.

17. The device of claim 1, further comprising one or more gate dielectric layers deposited on said substrate between said first gate contact and said at least two or more nanowires.

18. An active matrix liquid crystal display comprising one or more devices of claim 1.

19. A flat-panel display comprising one or more devices of claim 1.

20. A memory device comprising one or more devices of claim 1.

21. The device of claim 1, wherein all of said plurality of nanowires in said thin film are semiconducting.

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Description

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BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to semiconductor devices, and more particularly, to the use of thin films of nanowires in semiconductor devices.

2. Background Art

An interest exists in industry in developing low cost electronics, and in particular, in developing low cost, large area electronic devices. Availability of such large area electronic devices could revolutionize a variety of technology areas, ranging from civil to military applications. Example applications for such devices include driving circuitry for active matrix liquid crystal displays (LCDs) and other types of matrix displays, smart libraries, credit cards, radio-frequency identification tags for smart price and inventory tags, security screening/surveillance or highway traffic monitoring systems, large area sensor arrays, and the like.

The advancement of electronics has been moving towards two extremes in terms of physical scale. Rapid miniaturization of microelectronics according to Moore's law has led to increases in computing power while at the same time enabling reductions in cost. At the same time, progress has been made in the area of macroelectronics, in which electronic devices are integrated over large area substrates (e.g., having sizes measured in square meters). Current macroelectronics are primarily based on amorphous silicon (a-Si) or polycrystalline silicon (p-Si) thin film transistors (TFTs) on glass, and are finding important applications in various areas, including flat panel display (FPD), solar cells, image sensor arrays and digital x-ray imagers.

The current technology, however, is limited in what applications to which it can be applied. For example, there has been growing interest in the use of plastic as a substrate for macroelectronics due to various beneficial attributes of plastic, including flexibility, shock resistance, low weight, and low cost. However, the fabrication of high performance TFTs on plastics is difficult because process steps must be carried out below the glass transition temperature of the plastic. Significant efforts have been devoted to search for new materials (such as organics and organic-inorganic hybrids) or new fabrication strategies suitable for TFTs on plastics, but only with limited success. Organic TFTs have the potential for roll-to-roll fabrication process on plastic substrates, but with only a limited carrier mobility of about 1 cm.sup.2/Vs (centimeter squared per volt second). The limitations posed by materials and/or substrate process temperature (particularly on plastic) lead to low device performance, restricting devices to low-frequency applications. Therefore, applications that require even modest computation, control, or communication functions cannot be addressed by the existing TFT technology.

Individual semiconductor nanowires (NWs) and single walled carbon nanotubes can be used to fabricate nanoscale field effect transistors (FETs) with electronic performance comparable to and in some case exceeding that of the highest-quality single-crystal materials. In particular, carrier mobility of 300 cm.sup.2/Vs has been demonstrated for p-Si NWs, 2000 4000 cm.sup.2/Vs for n-indium InP NWs and up to 20,000 cm.sup.2/Vs for single walled carbon nanotubes. These nano-FETs are extending Moore's law toward the molecular level. They are, however, currently difficult to implement for production-scale nanoelectronics due to the complexity and limited scalability of the device fabrication processes.

Accordingly, what is needed are higher performance conductive or semiconductive materials and devices, and methods and systems for producing lower-cost, high performance electronic devices and components.

Furthermore, what is needed are high performance TFTs that can be applied to plastics and other substrates requiring low process temperatures.

What is also needed is a production scalable method for fabrication of nanoscale semiconductor devices than can be used as high performance TFTs.

BRIEF SUMMARY OF THE INVENTION

Methods, systems, and apparatuses for an electronic substrate having one or more semiconductor devices formed thereon is described. A thin film of semiconductor nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices.

In a first aspect of the present invention, a semiconductor device is formed. A plurality of nanowires are deposited onto a substrate in a thin film. First and second electrical contacts are formed on the substrate. At least one of the nanowires couples the first electrical contact to the second electrical contact. In aspects of the present invention, the deposited nanowires can be semiconducting, magnetic, ferroelectric, thermoelectric, piezoelectric, metallic or transition metal oxide nanowires.

In another aspect of the present invention, a thin film for use in one or more semiconductor devices is fabricated. A first plurality of nanowires that are p-doped are formed. A second plurality of nanowires that are n-doped are formed. The first plurality of nanowires and second plurality of nanowires are deposited onto a substrate to form a thin film of nanowires that includes n-doped and p-doped nanowires. The thin film of nanowires exhibits characteristics of both n-doped and p-doped nanowires.

In another aspect of the present invention, an electrical device is formed incorporating nanowire heterostructures. A plurality of nanowires are formed so that each nanowire has along its long axis at least one first portion doped with a first dopant and at least one second portion doped with a second dopant. Each nanowire has a spacing between consecutive junctions of the first and second portions substantially equal to a first distance. A pair of electrical contacts are formed on the substrate. A distance between the electrical contacts is approximately equal to the first distance. The plurality of nanowires are deposited onto the substrate. At least one nanowire of the plurality of nanowires couples the first electrical contact to the second electrical contact.

In another aspect of the present invention, a light emitting thin film is fabricated incorporating nanowire heterostructures. At least one light emitting semiconductor material. A plurality of nanowires are formed from the selected at least one light emitting semiconductor material. Each nanowire is doped so that each nanowire includes at least one P-N junction. The plurality of nanowires are deposited onto a substrate.

In still another aspect of the present invention, nanowires are positioned on a target surface. A first surface of a flow mask is mated with the target surface such that at least one channel formed in the first surface of the flow mask covers a portion of the target surface. A liquid that contains a plurality of nanowires is flowed through the at least one channel. Nanowires contained in the liquid flowing through the at least one channel are permitted to become positioned on the portion of the target surface covered by the at least one channel.

In still another aspect of the present invention, nanowires are applied to a target surface. A solution source provides a nanowire solution. The nanowire solution comprises a liquid containing a plurality of nanowires. A nozzle is coupled to the solution source. The nozzle has at least one output opening. The nozzle directs the nanowire solution through the output opening(s) onto the target surface. The nanowires of the nanowire solution are directed onto the target surface to be aligned on said target surface substantially parallel to each other, or to be randomly oriented with respect to each other.

In still another aspect of the present invention, conducting nanowires having high mobility of electrons are designed. A semiconductor material is selected. A maximum diameter for a nanowire made from the selected semiconductor material that provides substantial quantum confinement of electrons is determined.

In an example aspect, the diameter is determined by calculating the maximum diameter as follows:

.times..times..times..times..times..function..times. .times. ##EQU00001##

wherein: h=Planck's constant=4.14.times.10.sup.-15 eV-sec; m.sub.eff=effective mass of the selected semiconductor material; N=a predetermined factor; k.sub.b=Boltzmann's constant=8.62.times.10.sup.-5 eV/.degree. K.; and T=operating temperature; wherein at room temperature, k.sub.bT=0.0259 eV.

In still another aspect of the present invention, nanowires are configured to use electrons as conducting carriers to substantially reduce or entirely eliminate phonon scattering of electrons in the nanowires. In one aspect, the nanowires are doped with an n-type dopant material to be configured to use electrons as conducting carriers. In another aspect, the nanowires are doped with an p-type dopant material. The nanowires are operated in an inversion mode by applying a sufficient bias voltage to a thin film of the nanowires so that electrons are used as conducting carriers.

In still another aspect of the present invention, nanowires having reduced surface scattering are fabricated. A semiconductor material is selected. A plurality of nanowires are formed from the selected semiconductor material. A circumferential surface of each nanowire of the plurality of nanowires is coated with an insulating layer.

In still another aspect of the present invention, nanowires having reduced surface scattering are fabricated. A semiconductor material is selected. A plurality of nanowires are formed from the selected semiconductor material. Each nanowire of the plurality of nanowires is doped so that each nanowire comprises a core-shell structure. The shell is a doped outer layer of each nanowire surrounding a respective core. Carriers of each nanowire are thereby caused to be substantially confined to the core during operation.

In a further aspect, the present invention is directed to thin film transistors using nanowires, nanorods, or nanoribbons, and to production scalable methods for producing such transistors on a variety of substrates. In particular, an entirely new concept of macroelectronics has been developed by using oriented semiconductor nanowire or nanoribbon thin films to produce thin film transistors (TFTs) with the conducting channel parallel to the wire/ribbon axis. These new TFTs have a conducting channel formed by multiple single crystal nanowires in parallel (like a log bridge) or a single crystal nanoribbon, which crosses all the way from source to drain electrode for high carrier mobility.

In another aspect of the present invention, a NW-TFT fabrication method is provided in which a high-temperature active semiconductor materials synthesis process (e.g., used to form nanowires or nanoribbons) is carried out before the active semiconductor materials are applied to a device substrate. Subsequently, the formed NW-TFTs are applied to the device substrate via a solution assembly process, providing a general technique for applying any semiconductor material to any substrate type, including a plastic substrate.

According to aspects of the invention, both p-channel and n-channel TFTs can be formed. In an example aspect, a complementary inverter is described herein that is assembled from p-channel and n-channel TFTs using a combination of nanowires and nanoribbons.

Systems and methods to further improve performance are described herein, according to further aspects of the present invention. For example, aspects of the present invention allow NW-TFT performance to match or exceed that of bulk single crystal materials. In an example aspect, by fabricating novel core-shell NW structures and fully exploiting quantum electronic effects at reduced dimensions, carrier mobility can be enhanced to exceed that of bulk single crystal materials. In addition, approaches to fabricating NW-TFTs, according to aspects of the present invention, represent a general platform for a variety of macroelectronic applications. In aspects of the present invention, NWs made of optically active materials with various bandgaps are used to produce high performance, optically active thin films for multiple color solid-state light emitting diode (LED) displays. Furthermore, according to aspects of the present invention, NW-TFTs can be deposited from solution onto large area substrates using low-cost, low-temperature processes including micro-contact or ink-jet printing technology, for example.

In another aspect of this invention, electrical devices can be formed using a structure that includes multiple nanowire thin film layers. A first plurality of nanowires are deposited on a substrate to form a first nanowire thin film layer. A second plurality of nanowires are deposited on the first nanowire thin film layer to form a second nanowire thin film layer. Junctions, such as p-n junctions, are thereby formed at the cross points between the nanowires of the first and second thin film layers. Contacts can be formed to create electrical devices based on the properties of the junctions. Nanowires of the first thin film layer are preferably aligned parallel to each other, and nanowires of the second thin film layer are preferably aligned parallel to each other. However, in alternative aspects, the nanowires of the first and/or second thin film layers can be randomly oriented.

In another aspect of this invention, an electrical device is formed that includes a hybrid nanowire-single crystal semiconductor structure. A single-crystal semiconductor strip/thin film is formed. A plurality of nanowires are deposited on the top of the strip. Junctions, such as p-n junctions, are formed at the cross points between the nanowires and the single crystal semiconductor strip. Contacts can be formed to create electrical devices based on the properties of these junctions. The nanowires of the plurality of nanowires are preferably aligned parallel to each other, but can alternatively be randomly oriented.

In another aspect of the present invention, an electrical device is formed that includes a hybrid nanowire-amorphous/polycrystalline semiconductor structure. An amorphous or polycrystalline semiconductor thin film is deposited on a substrate. A plurality of nanowires are deposited on the thin film pattern. Junctions, such as p-n junctions, are formed at the cross points between the nanowires and the amorphous/polycrystalline semiconductor thin film pattern. Contacts can be formed to create electrical devices based on the properties of these junctions. The nanowires of the plurality of nanowires are preferably aligned parallel to each other, but can alternatively be randomly oriented.

In another aspect of the present invention, semiconductor nanowires emitting red, green and blue light in a predetermined ratio can be mixed in a solution. The wire mixture is flowed across a single-crystal, amorphous, or polycrystalline semiconductor strip/thin film. Contacts are formed to create a light emitting electrical device. Depending on the mixture of light emitting nanowires, any color of light can be emitted by the light emitting electrical device, including white light.

Thus, according to aspects of the present invention, nanowire, nanorod, nanoribbon, and nanotube thin films enable a variety of new capabilities. In aspects, these include: moving microelectronics from single crystal substrates to glass and plastic substrates; integrating macroelectronics, microelectronics and nanoelectronics at the device level; and, integrating different semiconductor materials on a single substrate. These aspects of the present invention impact a broad range of existing applications, from flat-panel displays to image sensor arrays, and enable a whole new range of universal flexible, wearable, disposable electronics for computing, storage and communication.

These and other objects, advantages and features will become readily apparent in view of the following detailed description of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate the present invention and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the pertinent art to make and use the invention.

FIG. 1 shows a view of a portion of a thin film of nanowires, according to an example embodiment of the present invention.

FIG. 2 shows a semiconductor device that includes a thin film of nanowires, according to an example embodiment of the present invention.

FIGS. 3A 3D shows nanowires doped according to various example embodiments of the present invention.

FIGS. 4A and 4B show examples of a semiconductor device, doped according to example doping embodiments of the present invention.

FIG. 5 shows a flowchart providing example steps for making a plurality of semiconductor devices, according to embodiments of the present invention.

FIGS. 6A 6F show various stages of fabrication for a substrate having a plurality of semiconductor devices thereon, according to an embodiment of the present invention.

FIG. 7 shows a flowchart providing example steps for making an electrical device that incorporates a thin film of nanowires of the present invention, according to an embodiment of the present invention

FIG. 8A shows a close up view of an example portion of a nanowire thin film that includes a homogeneous mixture of n-doped nanowires and p-doped nanowires, according to an embodiment of the present invention.

FIG. 8B shows an example portion of a nanowire thin film that includes both n-doped nanowires and p-doped nanowires.

FIG. 8C shows a thin film of nanowires that includes both n-doped nanowires and p-doped nanowires.

FIG. 9 shows a flowchart providing example steps for making a thin film of nanowires of the present invention, according to an embodiment of the present invention.

FIG. 10 shows a nanowire that is a nanowire heterostructure, according to an example embodiment of the present invention.

FIG. 11A shows an example two-terminal electrical device that includes a plurality of nanowires, according to an embodiment of the present invention.

FIG. 11B shows an example p-n-p transistor, incorporating nanowire heterostructures.

FIG. 12 shows a flowchart providing example steps for making an electrical device incorporating nanowire heterostructures, according to an embodiment of the present invention.

FIG. 13A shows a discrete pixel or light source, having a pair of electrodes, first electrical contact and second electrical contact, according to an embodiment of the present invention.

FIG. 13B shows a column of discrete pixels or light sources, each similar to pixel or light source, according to an embodiment of the present invention.

FIG. 13C shows a large area light source, which includes a plurality of light source columns, according to an embodiment of the present invention.

FIG. 14 shows a flowchart providing example steps for making a light emitting device incorporating light emitting nanowire heterostructures, according to an embodiment of the present invention.

FIGS. 15A and 15B show bottom and cross-sectional views of an example flow mask, according to an embodiment of the present invention.

FIG. 16 shows a nanowire positioning system that incorporates flow mask, according to an example embodiment of the present invention.

FIGS. 17A and 17B show plan and cross-sectional views of a flow of nanowires flowing through flow mask, according to an example embodiment of the present invention.

FIG. 18A shows an example semiconductor wafer mated with a flow mask, according to an embodiment of the present invention.

FIG. 18B shows portions of the surface of the wafer of FIG. 18A, having nanowires positioned thereon, due to operation of the present invention.

FIG. 18C shows an array of integrated circuits formed on a wafer, with nanowires positioned thereon, due to operation of the present invention.

FIG. 19A shows an integrated circuit, which can be an example of one of the integrated circuits of the wafer shown in FIG. 18C, according to an embodiment of the present invention.

FIG. 19B shows a close-up view a portion of the integrated circuit of FIG. 19A, showing detail of example electrically conductive traces, according to an embodiment of the present invention.

FIG. 19C shows nanowires having been deposited on the integrated circuit portion of FIG. 19B, by operation of an example flow mask of the present invention.

FIG. 19D shows an integrated circuit, which can be an example of one of the integrated circuits of the wafer shown in FIG. 18C, according to an embodiment of the present invention.

FIG. 19E shows a close-up view a portion of the integrated circuit of FIG. 19D, showing detail of example electrically conductive traces, according to an embodiment of the present invention.

FIG. 19F shows nanowires having been deposited on the integrated circuit portion of FIG. 19E, by operation of an example flow mask of the present invention.

FIG. 20A shows a graph related to FIGS. 19A C.

FIG. 20B shows a graph related to FIGS. 19D 19F.

FIG. 21 shows a flowchart providing example steps for positioning nanowires on a target surface using a flow mask, according to an example embodiment of the present invention.

FIG. 22 shows a block diagram of an example nanowire spray application system, according to an embodiment of the present invention.

FIG. 23 shows a detailed view of a nozzle outputting a flow of nanowires onto an example target surface, according to an embodiment of the present invention.

FIGS. 24 and 25 show plan views of a target surfaces having a plurality of nanowires positioned thereon, due to operation of the present invention.

FIG. 26 shows a plan view of a target surface with a plurality of electrical contacts formed thereon, in electrical contact with nanowires, according to an embodiment of the present invention.

FIG. 27 shows a flowchart providing example steps for positioning nanowires on a target surface using spray techniques, according to an example embodiment of the present invention.

FIG. 28 shows a graph providing a relationship between a maximum allowable diameter for a semiconductor material and effective mass m.sub.eff., according to an embodiment of the present invention.

FIG. 29 shows a table listing information about various example semiconductor materials.

FIG. 30 shows a flowchart providing example steps for designing conducting nanowires having high mobility of electrons, according to an example embodiment of the present invention.

FIG. 31 shows a table listing information about example III V semiconductor type materials.

FIGS. 32 and 33 show flowcharts providing example steps for fabricating nanowires having reduced surface scattering, according to example embodiments of the present invention.

FIG. 34A is a diagram of amorphous or polycrystalline Si TFTs.

FIG. 34B is a diagram of a nanowire TFT, according to an embodiment of the invention.

FIG. 34C is a diagram of a nanoribbon TFT, according to an embodiment of the invention.

FIG. 35A is a flow chart of a method for NW-TFT fabrication, according to an embodiment of the invention.

FIG. 35B is a diagram of an optical micrograph of a NW thin film, according to an embodiment of the invention.

FIG. 35C is a diagram of a NW-TFT with gold electrodes, according to an embodiment of the invention.

FIG. 35D is a diagram of an optical micrograph of a NW-TFT with parallel arrays of NWs bridging from source to drain electrodes, according to an embodiment of the invention.

FIG. 36A is a chart showing typical drain current (I.sub.DS) versus drain-source bias voltage (V.sub.DS) relations at different gate voltages (V.sub.GS) in the steps of 1 volt (V) for a NW-TFT, according to an embodiment of the invention.

FIG. 36B is a chart showing a plot of I.sub.DS versus V.sub.GS, for a NW-TFT according to an embodiment of the invention.

FIG. 36C is a chart showing a histogram of threshold voltage distribution for a NW-TFT, according to an embodiment of the invention.

FIG. 36D is a chart illustrating the linear-scale relation for the drain current when the device is turned on (Vgs=-10V) for a NW-TFT, according to an embodiment of the invention.

FIG. 37A is a diagram of a NW-TFT on a plastic substrate, according to an embodiment of the invention.

FIG. 37B is a diagram of several NW-TFTs on plastic substrates, according to an embodiment of the invention.

FIG. 37C is a diagram showing drain current (I.sub.DS) versus drain-source bias voltage (V.sub.DS) relations at different gate voltages (V.sub.GS) in the steps of 1 volt (V) for a NW-TFT on a plastic substrate, according to an embodiment of the invention.

FIG. 37D is a diagram showing the transfer characteristics of the same NW-TFT before and after slight flexing of the plastic substrate, according to an embodiment of the invention.

FIG. 38A is a diagram of a NW-TFT on a plastic substrate with an electrolyte solution gate, according to an embodiment of the invention.

FIG. 38B is a chart of the I.sub.DS-V.sub.DS relation as a function of various electrolyte solution gate voltages for a NW-TFT on a plastic substrate, according to an embodiment of the invention.

FIG. 38C is a chart of the I.sub.DS-V.sub.GS relation for a V.sub.DS of 10 mV for a NW-TFT on a plastic substrate with an electrolyte solution gate, according to an embodiment of the invention.

FIG. 39A is a diagram of a CdS nanoribbon TFT, according to an embodiment of the invention.

FIG. 39B is a chart of the I.sub.DS-V.sub.DS relation as a function of various gate voltages for a CdS nanoribbon TFT, according to an embodiment of the invention.

FIG. 39C is a chart of the I.sub.DS-V.sub.GS relation with a V.sub.DS of 1 V for a CdS nanoribbon TFT, according to an embodiment of the invention.

FIG. 40 is a diagram of a complementary inverter made with a p-channel NW-TFT and an n-channel CdS nanoribbon TFT along with gain characteristics, according to an embodiment of the invention.

FIG. 41A shows a scanning electron microscope image of synthesized silicon nanowires, according to an example embodiment of the present invention.

FIG. 41B shows a lattice-resolved transmission electron microscope image of individual Si nanowires, according to an example embodiment of the present invention.

FIG. 42 shows a flow diagram of a process for synthesizing and implementing high mobility nanowire thin film transistors, according to an example embodiment of the present invention.

FIG. 43 shows a silicon nanowire core-shell structure with a single crystalline core and dielectric overcoating, according to an example embodiment of the present invention.

FIGS. 44A C shows schematic views of thin film transistors (TFTs) fabricated from amorphous silicon, polysilicon, and an aligned nanowire thin film.

FIG. 45 shows a diagram of a fluidic cell for aligning nanowires over a large area, according to an embodiment of the present invention.

FIG. 46 shows a diagram illustrating the alignment of nanowires over a large area using a Langmuir-Blodgett film, according to an example embodiment of the present invention.

FIG. 47 shows plan and perspective views of a single nanowire field effect transistor, according to an example embodiment of the present invention.

FIGS. 48A and 48B show perspective views of locally gated nanowire thin film transistors, according to embodiments of the present invention.

FIG. 49 schematically illustrates an alternative embodiment of a substrate having a plurality of semiconductor devices thereon.

The present invention will now be described with reference to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Additionally, the left-most digit(s) of a reference number identifies the drawing in which the reference number first appears.

DETAILED DESCRIPTION OF THE INVENTION

Introduction

It should be appreciated that the particular implementations shown and described herein are examples of the invention and are not intended to otherwise limit the scope of the present invention in any way. Indeed, for the sake of brevity, conventional electronics, manufacturing, semiconductor devices, and nanowire (NW), nanorod, nanotube, and nanoribbon technologies and other functional aspects of the systems (and components of the individual operating components of the systems) may not be described in detail herein. Furthermore, for purposes of brevity, the invention is frequently described herein as pertaining to nanowires, and to a semiconductor transistor device. Moreover, while the number of nanowires and spacing of those nanowires are provided for the specific implementations discussed, the implementations are not intended to be limiting and a wide range of the number of nanowires and spacing can also be used. It should be appreciated that although nanowires are frequently referred to, the techniques described herein are also applicable to nanorods, nanotubes, and nanoribbons. It should further be appreciated that the manufacturing techniques described herein could be used to create any semiconductor device type, and other electronic component types. Further, the techniques would be suitable for application in electrical systems, optical systems, consumer electronics, industrial electronics, wireless systems, space applications, or any other application.

As used herein, the term "nanowire" generally refers to any elongated conductive or semiconductive material (or other material described herein) that includes at least one cross sectional dimension that is less than 500 nm, and preferably, less than 100 nm, and has an aspect ratio (length:width) of greater than 10, preferably, greater than 50, and more preferably, greater than 100. Examples of such nanowires include semiconductor nanowires as described in Published International Patent Application Nos. WO 02/17362, WO 02/48701, and 01/03208, carbon nanotubes, and other elongated conductive or semiconductive structures of like dimensions.

As used herein, the term "nanorod" generally refers to any elongated conductive or semiconductive material (or other material described herein) similar to a nanowire, but having an aspect ratio (length:width) less than that of a nanowire. Note that two or more nanorods can be coupled together along their longitudinal axis so that the coupled nanorods span all the way between electrodes. Alternatively, two or more nanorods can be substantially aligned along their longitudinal axis, but not coupled together, such that a small gap exists between the ends of the two or more nanorods. In this case, electrons can flow from one nanorod to another by hopping from one nanorod to another to traverse the small gap. The two or more nanorods can be substantially aligned, such that they form a path by which electrons can travel between electrodes.

While the example implementations described herein principally use CdS and Si, other types of materials for nanowires and nanoribbons can be used, including semiconductive nanowires or nanoribbons, that are comprised of semiconductor material selected from, e.g., Si, Ge, Sn, Se, Te, B, C (including diamond), P, B--C, B--P(BP6), B--Si, Si--C, Si--Ge, Si--Sn and Ge--Sn, SiC, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, BN/BP/BAs, AlN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, ZnO/ZnS/ZnSe/ZnTe, CdS/CdSe/CdTe, HgS/HgSe/HgTe, BeS/BeSe/BeTe/MgS/MgSe, GeS, GeSe, GeTe, SnS, SnSe, SnTe, PbO, PbS, PbSe, PbTe, CuF, CuCl, CuBr, CuI, AgF, AgCl, AgBr, AgI, BeSiN2, CaCN.sub.2, ZnGeP.sub.2, CdSnAs.sub.2, ZnSnSb.sub.2, CuGeP.sub.3, CuSi.sub.2P.sub.3, (Cu, Ag)(Al, Ga, In, Tl, Fe)(S, Se, Te).sub.2, Si.sub.3N.sub.4, Ge.sub.3N.sub.4, Al.sub.2O.sub.3, (Al, Ga, In).sub.2(S, Se, Te).sub.3, Al.sub.2CO, and an appropriate combination of two or more such semiconductors.

In certain aspects, the semiconductor may comprise a dopant from a group consisting of: a p-type dopant from Group III of the periodic table; an n-type dopant from Group V of the periodic table; a p-type dopant selected from a group consisting of: B, Al and In; an n-type dopant selected from a group consisting of: P, As and Sb; a p-type dopant from Group II of the periodic table; a p-type dopant selected from a group consisting of: Mg, Zn, Cd and Hg; a p-type dopant from Group IV of the periodic table; a p-type dopant selected from a group consisting of: C and Si.; or an n-type is selected from a group consisting of: Si, Ge, Sn, S, Se and Te.

Additionally, the nanowires or nanoribbons can include carbon nanotubes, or nanotubes formed of conductive or semiconductive organic polymer materials, (e.g., pentacene, and transition metal oxides).

Hence, although the term "nanowire" is referred to throughout the description herein for illustrative purposes, it is intended that the description herein also encompass the use of nanotubes (e.g., nanowire-like structures having a hollow tube formed axially therethrough). Nanotubes can be formed in combinations/thin films of nanotubes as is described herein for nanowires, alone or in combination with nanowires, to provide the properties and advantages described herein.

Furthermore, it is noted that a thin film of nanowires of the present invention can be a "heterogeneous" film, which incorporates semiconductor nanowires and/or nanotubes, and/or nanorods, and/or nanoribbons, and/or any combination thereof of different composition and/or structural characteristics. For example, a "heterogeneous film" can includes nanowires/nanotubes with varying diameters and lengths, and nanotubes and/or nanotubes that are "heterostructures" having varying characteristics.

In the context of the invention, although the focus of the detailed description relates to use of nanowire, nanorod, nanotube, or nanoribbon thin films on plastic substrates, the substrate to which these nano structures are attached may comprise other materials, including, but not limited to: a uniform substrate, e.g., a wafer of solid material, such as silicon, glass, quartz, polymerics, etc.; a large rigid sheet of solid materials, e.g., glass, quartz, plastics such as polycarbonate, polystyrene, etc., or can comprise additional elements, e.g., structural, compositional, etc. A flexible substrate, such as a roll of plastic such as polyolefins, polyamide, and others, a transparent substrate, or combinations of these features can be employed. For example, the substrate may include other circuit or structural elements that are part of the ultimately desired device. Particular examples of such elements include electrical circuit elements such as electrical contacts, other wires or conductive paths, including nanowires or other nanoscale conducting elements, optical and/or optoelectrical elements (e.g., lasers, LEDs, etc.), and structural elements (e.g., microcantilevers, pits, wells, posts, etc.).

By substantially "aligned" or "oriented" is meant that the longitudinal axes of a majority of nanowires in a collection or population of nanowires is oriented within 30 degrees of a single direction. Although the majority can be considered to be a number of nanowires greater than 50%, in various embodiments, 60%, 75%, 80%, 90%, or other percentage of nanowires can be considered to be a majority that are so oriented. In certain preferred aspects, the majority of nanowires are oriented within 10 degrees of the desired direction. In additional embodiments, the majority of nanowires may be oriented within other numbers or ranges of degrees of the desired direction, including randomly oriented and isotropically oriented.

It should be understood that the spatial descriptions (e.g., "above", "below", "up", "down", "top", "bottom", etc.) made herein are for purposes of illustration only, and that devices of the present invention can be spatially arranged in any orientation or manner.

The materials used for nanowires described herein also have an inherent mechanical flexibility of the high-mobility semiconductor material, allowing fabrication of truly flexible high-performance electronics. Due to the extremely small diameter and large aspect ratio (in some embodiments >1,000), nanowires possess superior mechanical flexibility and strength. Individual nanowires can easily bend with radius of curvature r<10 .mu.m before failure. Because each individual nanowire on these high-density substrates is aligned in the same direction, but physically independent of the surrounding wires, this flexibility is retained in the nanowire thin films of the present invention, including dense, inorganic and oriented nanowire thin-films (DION thin-films). Even without bending the individual nanowires within a device, the fact that each nanowire is only 100 .mu.m long allows a macroscopic r<<1 mm.

Thin Films of Nanowires Embodiments

The present invention is directed to the use of nanowires in systems and devices to improve system and device performance. For example, the present invention is directed to the use of nanowires in semiconductor devices. According to the present invention, multiple nanowires are formed into a high mobility thin film. The thin film of nanowires is used in electronic devices to enhance the performance and manufacturability of the devices.

FIG. 1 shows a close-up view of a thin film of nanowires 100, according to an example embodiment of the present invention. Thin film of semiconductor nanowires 100 can be used instead of amorphous silicon or organic thin films in conventional electronic devices to achieve improved device behavior, while allowing for a straight forward and inexpensive manufacturing process. Through the use of thin films of nanowires, the present invention is particularly adapted to making high performance, low cost devices on large and flexible substrates.

Note that thin film of nanowires 100 as described herein may be formed in a wide range of possible surface areas. For example, thin films of nanowires 100 of the present invention can be formed to have functional areas greater than 1 mm.sup.2, greater than 1 cm.sup.2, greater than 10 cm.sup.2, greater than 1 m.sup.2, and even greater or smaller areas.

As shown in FIG. 1, thin film of nanowires 100 includes a plurality of individual nanowires closely located together. Thin film of nanowires 100 can have a variety of thickness amounts that are equal to or greater than the thickness of a single nanowire. In the example of FIG. 1, the nanowires of thin film of nanowires 100 are aligned such that their long axes are substantially parallel to each other. Note that in alternative embodiments, the nanowires of thin film of nanowires 100 are not aligned, and instead can be oriented in different directions with respect to each other, either randomly or otherwise. In an alternative embodiment, the nanowires of thin film of nanowires 100 may be isotropically oriented, so that high mobility is provided in all directions. Note that the nanowires of thin film of nanowires 100 may be aligned in any manner relative to the direction of electron flow in order to enhance performance as required by a particular application.

FIG. 2 shows a semiconductor device 200 that includes thin film of nanowires 100, according to an example embodiment of the present invention. In FIG. 2, semiconductor device 200 is shown as a transistor, having a source electrode 202, a gate electrode 204, a drain electrode 206, formed on a substrate 208. Thin film of nanowires 100 is coupled between source electrode 202 and drain electrode 206 over a portion of gate electrode 204. Thin film of nanowires 100 substantially operates as a channel region for the transistor of semiconductor device 200, and allows semiconductor 200 to operate with enhanced characteristics, as further described herein. Numerous substrate types applicable to substrate 208 are described elsewhere herein.

Note that semiconductor device 200 is shown as a transistor in FIG. 2 for illustrative purposes. It would be understood to persons skilled in the relevant art(s) from the teachings herein that thin film of nanowires 100 can be included in semiconductor device types in addition to transistors, including diodes.

In embodiments, the nanowires of thin film of nanowires 100 are single crystal semiconductor nanowires that span all the way between source electrode 202 and drain electrode 206. Hence, electric carriers can transport through the single crystals nanowires, resulting in high mobility which is virtually impossible to obtain with current amorphous and polysilicon technologies.

As described above, the nanowires of thin film of nanowires 100 can be aligned or oriented. For example, the nanowires of thin film of nanowires 100 shown in FIG. 2 can be aligned parallel to the length of the channel between source electrode 202 and drain electrode 206, or can be aligned in alternative ways.

Thin film of nanowires 100 can be formed with a sufficient number of nanowires to provide desired characteristics for semiconductor device 200. For example, thin film of nanowires 100 can be formed of a sufficient number of nanowires to achieve a desired current density or current level desired for the particular semiconductor device. For instance, in the transistor example of FIG. 2, thin film of nanowires 100 can be formed to have a current level in the channel of greater than about 10 nanoamps.

In an embodiment, a thin film of nanowires 100 can be formed to have asymmetric mobility. For example, this can be accomplished by asymmetrically aligning the nanowires of thin film of nanowires 100, and/or by doping the nanowires in a particular manner. Such asymmetric mobility can be caused to be much greater in a first direction than in a second direction. For example, asymmetric mobilities can be created in the order of 10, 100, 1000, and 10000 times greater in the first direction than in the second direction, or to have any other asymmetric mobility ratio between, greater, or less than these values.

The nanowires of thin film of nanowires 100 can be doped in various ways to improve performance. The nanowires can be doped prior to inclusion in semiconductor device 200, or after inclusion. Furthermore, a nanowire can be doped differently along portions of its long axis, and can be doped differently from other nanowires in thin film of nanowires 100. Some examples of doping schemes for individual nanowires, and for thin films of nanowires are provided as follows. However, it will be apparent to persons skilled in the relevant art(s) from the teachings herein that nanowires, and thin films thereof, can be doped according to additional ways, and in any combination of the ways described herein.

FIG. 3A shows a nanowire 300 that is a uniformly doped single crystal nanowire. Such single crystal nanowires can be doped into either p- or n-type semiconductors in a fairly controlled way. Doped nanowires such as nanowire 300 exhibit improved electronic properties. For instance, such nanowires can be doped to have carrier mobility levels comparable to alternative single crystal materials. In addition, and without being bound to any particular theory of operation, due to a one-dimensional nature of the electron-wave traversing inside the nanowire channel, and a reduced scattering probability, it may be possible for such nanowires to achieve even higher mobility than a bulk single crystal material. Carrier mobility levels up to 1500 cm.sup.2/Vs have been shown for single p-type Si (silicon) nanowires, and carrier mobility levels up to 4000 cm.sup.2/Vs have been shown for n-type InP nanowires.

FIG. 3B shows a nanowire 310 doped according to a core-shell structure. As shown in FIG. 3B, nanowire 310 has a doped surface layer 302, which can have varying thickness levels, including being only a molecular mono