Liquid crystal display device and method of driving the same Number:7,385,579 from the United States Patent and Trademark Office (PTO) owispatent

Title: Liquid crystal display device and method of driving the same

Abstract: A signal of a signal line is written in the order from a pixel TFT of a pixel with a long response time of liquid crystal. A signal of a signal line is written in a pixel TFT displaying the same gray-scale among pixel TFTs connected to the same signal line. A signal of a signal line is simultaneously written in pixel TFTs displaying the same or approximate gray-scale among pixel TFTs connected to the same signal line. Then, a pixel electrode of a pixel TFT displaying an approximate gray-scale is supplied with a normal signal voltage.

Patent Number: 7,385,579 Issued on 06/10/2008 to Satake

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Inventors:	Satake; Rumo (Kanagawa, JP)
Assignee:	Semiconductor Energy Laboratory Co., Ltd. (Atsugi-shi, Kanagawa-ken, JP)
Appl. No.:	09/966,354
Filed:	September 27, 2001

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Foreign Application Priority Data

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Sep 29, 2000 [JP]			2000-300754

Current U.S. Class:	345/88 ; 345/89; 345/90; 345/97; 345/98
Field of Search:	345/88,87,90,92,97,98,100,85,89,692,55 349/49,87,129,48,34 359/15 313/493

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References Cited [Referenced By]

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U.S. Patent Documents

4090219	May 1978	Ernstoff et al.
4750813	June 1988	Ohwada et al.
4907862	March 1990	Suntola
5233447	August 1993	Kuribayashi et al.
5327229	July 1994	Konno et al.
5428366	June 1995	Eichenlaub
5465168	November 1995	Koden et al.
5473449	December 1995	Takemura et al.
5528262	June 1996	McDowall et al.
5594569	January 1997	Konuma et al.
5608558	March 1997	Katsumi
5615027	March 1997	Kuribayashi et al.
5642129	June 1997	Zavracky et al.
5643826	July 1997	Ohtani et al.
5691783	November 1997	Numao et al.
5774100	June 1998	Aoki et al.
5844533	December 1998	Usui et al.
5923962	July 1999	Ohtani et al.
5969832	October 1999	Nakanishi et al.
6046716	April 2000	McKnight
6078304	June 2000	Miyazawa
6166714	December 2000	Kishimoto
6177920	January 2001	Koyama et al.
6188379	February 2001	Kaneko
6222515	April 2001	Yamaguchi et al.
6300927	October 2001	Kubota et al.
6320568	November 2001	Zavracky
6344889	February 2002	Hasegawa et al.
6424331	July 2002	Ozawa
6473117	October 2002	Iba
6486864	November 2002	Nakajima et al.
6512503	January 2003	Kim et al.
6522319	February 2003	Yamazaki
6545653	April 2003	Takahara et al.
6671009	December 2003	Hattori et al.
6727875	April 2004	Mikami et al.
6967637	November 2005	Aoyama et al.
6980190	December 2005	Ueda
6992649	January 2006	Iba
7123225	October 2006	Chen
7233342	June 2007	Yamazaki et al.
2001/0011979	August 2001	Hasegawa et al.
2001/0017610	August 2001	Ozawa
2001/0043177	November 2001	Huston et al.
2002/0024621	February 2002	Hirakata et al.
2002/0158568	October 2002	Satake
2003/0006954	January 2003	Iba
2003/0043093	March 2003	Bolotski et al.
2003/0058210	March 2003	Yamazaki et al.
2004/0135756	July 2004	Mikami et al.
2004/0145552	July 2004	Song et al.
2005/0030258	February 2005	Satake

Other References

"Field Sequential Color LCD by Ferroelectric Liquid Crystal," Press Journal, Monthly FPD Intelligence, Feb. 1, 1999, pp. 66-69, with English translation. cited by other . S. Kobayashi, "Color Liquid Crystal Display," Display Technology Series, Industrial Books, p. 127, with English translation. cited by other . "Field Sequential Color LCD by Ferroelectric Liquid Crystal," Press Journal, Monthly FPD Intelligence, Feb. 1, 1999, pp. 66-69, with English translation. cited by other . S. Kobayashi, "Color Liquid Crystal Display," Display Technology Series, Industrial Books, p. 127, with partial English translation, Dec. 14, 1990. cited by other.

Primary Examiner: Dharia; Prabodh
Attorney, Agent or Firm: Fish & Richardson P.C.

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Claims

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What is claimed is:

1. A method of driving a liquid crystal display device comprising a first to n-th pixels (n is a natural number and n.gtoreq.2), wherein first to n-th signal voltages are to be applied to first to n-th pixel electrodes of the first to n-th pixels respectively in a first sub-frame period, wherein (n+1)-th to 2n-th signal voltages are to be applied to the first to n-th pixel electrodes respectively in a second sub-frame period, wherein response periods of liquid crystal of the first to n-th pixels from when the first to n-th signal voltages are applied to when the (n+1)-th to 2n-th signal voltages are applied respectively are calculated, and wherein in an order of the calculated response periods of liquid crystal of the first to n-th pixels from longest to shortest, the (n+1)-th to 2n-th signal voltages are applied to the first to n-th pixel electrodes in the second sub-frame period.

2. A method of driving a liquid crystal display device according to claim 1, wherein a first light emission color, a second light emission color, and a third light emission color are intermittently incident upon the liquid crystal display device.

3. A method of driving a liquid crystal display device according to claim 1, wherein the liquid crystal display device is driven in a field sequential system.

4. A method of driving a liquid crystal display device, wherein the liquid crystal display device comprises: a signal line; a first scanning line; a second scanning line; a first thin film transistor connected to the signal line and the first scanning line; a first pixel electrode connected to the first thin film transistor; a second thin film transistor connected to the signal line and the second scanning line; and a second pixel electrode connected to the second thin film transistor, wherein the method comprises the steps of: applying a first signal voltage to the first and second pixel electrodes; and applying a second signal voltage to the second pixel electrode, wherein a difference between an absolute value of the first signal voltage and the second signal voltage is larger than 0 volt and smaller than 0.5 volt.

5. A method of driving a liquid crystal display device according to claim 4, wherein a first light emission color, a second light emission color, and a third light emission color are intermittently incident upon the liquid crystal display device.

6. A method of driving a liquid crystal display device according to claim 4, wherein the liquid crystal display device is driven in a field sequential system.

7. A liquid crystal display device, comprising: a first to n-th pixels (n is a natural number and n.gtoreq.2); a means for storing first to n-th signal voltages to be applied to first to n-th pixel electrodes of the first to n-th pixels respectively in a first sub-frame period; a means for storing (n+1)-th to 2n-th signal voltages to be applied to the first to n-th pixel electrodes of the first to n-th pixels respectively in a second sub-frame period; a means for calculating response periods of liquid crystal of the first to n-th pixels from when the first to n-th signal voltages are applied to when the (n+1)-th to 2n-th signal voltages are applied respectively; and a means for applying the (n+1)-th to 2n-th signal voltages to the first to n-th pixel electrodes respectively in an order of the calculated response periods of liquid crystal of the first to n-th pixels from longest to shortest.

8. A liquid crystal display device according to claim 7, further comprising: a means for selecting a signal line connected to one of first to n-th pixel TFTs (n is a natural number and n.gtoreq.2) in the first to n-th pixels; and a means for selecting a scanning line connected to the one of the first to n-th pixel TFTs in the first to n-th pixels.

9. A liquid crystal display device according to claim 8, wherein the means for selecting a signal line has an address decoder.

10. A liquid crystal display device according to claim 8, wherein the means for selecting a scanning line has an address decoder.

11. A liquid crystal display device, wherein light sources of a liquid crystal display device according to claim 7 are composed of a light source of a first light emission color, a light source of a second light emission color, and a light source of a third light emission color.

12. A method of driving a liquid crystal display device, wherein the liquid crystal display device comprises: first to n-th pixels (n is a natural number and n.gtoreq.2); first to n-th pixel electrodes included in the first to n-th pixels respectively, wherein the method comprises: applying first to n-th signal voltages to the first to n-th pixel electrodes respectively in a first sub-frame period; applying (n+1)-th to 2n-th signal voltages to the first to n-th pixel electrodes respectively in a second sub-frame period deciding an order of applying the (n+1)-th to 2n-th signal voltages to the first to n-th pixel electrodes in accordance with voltage differences between the first to n-th signal voltages and the (n+1)-th to 2n-th signal voltages respectively.

13. A method of driving a liquid crystal display device according to claim 12, wherein the liquid crystal display device is driven in a field sequential system.

14. A method of driving a liquid crystal display device, wherein the liquid crystal display device comprises: first to n-th pixels (n is a natural number and n.gtoreq.2); first to n-th pixel electrodes included in the first to n-th pixels respectively, wherein the method comprises: applying first to n-th signal voltages to the first to n-th pixel electrodes respectively in a first sub-frame period; applying (n+1)-th to 2n-th signal voltages to the first to n-th pixel electrodes respectively in a second sub-frame period deciding an order of applying the (n+1)-th to 2n-th signal voltages to the first to n-th pixel electrodes in accordance with voltage differences between the first to n-th signal voltages and the (n+1)-th to 2n-th signal voltages respectively, so that the (n+1)-th to 2n-th signal voltages are applied to the first to n-th pixel electrodes in an order of the voltage differences from longest to shortest.

15. A method of driving a liquid crystal display device according to claim 14, wherein the liquid crystal display device is driven in a field sequential system.

16. A method of driving a liquid crystal display device, wherein the liquid crystal display device comprises: first to n-th pixels (n is a natural number and n.gtoreq.2); first to n-th pixel electrodes included in the first to n-th pixels, a first storage means; and a second storage means, wherein the method comprising comprises: applying first to n-th signal voltages to the first to n-th pixel electrodes in a first sub-frame period; storing the first to n-th signal voltages in the first storage means; storing (n+1)-th to 2n-th signal voltages in the second storage means; comparing the first to n-th signal voltages and the (n+1)-th to 2n-th signal voltages respectively, thereby obtaining voltage differences between the first to n-th signal voltages and the (n+1)-th to 2n-th signal voltages respectively; applying the (n+1)-th to 2n-th signal voltages to the first to n-th pixel electrodes respectively in a second sub-frame period; deciding an order of applying the (n+1)-th to 2n-th signal voltages to the first to n-th pixel electrodes respectively in accordance with the voltage differences.

17. A method of driving a liquid crystal display device according to claim 16, wherein the liquid crystal display device is driven in a field sequential system.

18. A method of driving a liquid crystal display device, wherein the liquid crystal display device comprises: first to n-th pixels (n is a natural number and n.gtoreq.2); first to n-th pixel electrodes included in the first to n-th pixels, a first storage means; and a second storage means, wherein the method comprising comprises: applying first to n-th signal voltages to the first to n-th pixel electrodes in a first sub-frame period; storing the first to n-th signal voltages in the first storage means; storing (n+1)-th to 2n-th signal voltages in the second storage means; comparing the first to n-th signal voltage and the (n+1)-th to 2n-th signal voltages respectively, thereby obtaining voltage differences between the first to n-th signal voltages and the (n+1)-th to 2n-th signal voltages respectively; applying the (n+1)-th to 2n-th signal voltages to the first to n-th pixel electrodes respectively in a second sub-frame period; deciding an order of applying the (n+1)-th to 2n-th signal voltages to the first to n-th pixel electrodes respectively in accordance with the voltage differences, so that the (n+1)-th to 2n-th signal voltages are applied to the first to n-th pixel electrodes in an order of the voltage differences from longest to shortest.

19. A method of driving a liquid crystal display device according to claim 18, wherein the liquid crystal display device is driven in a field sequential system.

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Description

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BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a liquid crystal display device and a method of driving the same. A liquid crystal display device conducts a light and dark display by utilizing a voltage applied to a liquid crystal layer interposed between substrates to change a polarized state, a scattered state, or wavelength characteristics of light passing through the liquid crystal layer.

In the present specification, a thin film transistor (TFT) refers to a semiconductor device having a semiconductor layer, a gate electrode, a source electrode, and a drain electrode.

2. Description of the Related Art

Liquid crystal display devices have been used widely for portable equipment, personal computers, and the like in view of their light weight and low power consumption.

In a liquid crystal display device, a field sequential system has been paid attention to, in which light sources of three primary colors (red, green, and blue) are successively lighted to conduct a color display. The field sequential system does not need a color filter, so a high-precision display can be expected.

Regarding the field sequential system, it is proposed that light sources are successively and continuously lighted with varying light emission colors (Monthly FPD Intelligence Press Journal, 1999. 2, pp. 66-69). According to this system, when light emission colors of the light sources are changed, it is required to set the entire screen at a black level so as to prevent mixed color of the light sources in the respective pixels.

It is also proposed that a light source is lighted after response of liquid crystal is completed in a screen (Shunsuke Kobayashi, Color Liquid Crystal Display, Sangyo Tosho, Japan, p. 127). According to this system, light sources are intermittently lighted, so that a complete black display can be achieved when the light sources are not lighted. This allows an impulse system that is a driving system of a cathode ray tube (CRT) to be achieved even in a liquid crystal display device, and this system can be expected to prevent a residual image peculiar to a liquid crystal display device.

The problems to be solved by the invention will be described below.

Note that, in the present specification, a TFT formed in a pixel portion is referred to as a "pixel TFT".

Furthermore, in the present specification, signal lines having addresses S.sub.1 to S.sub.m, scanning lines having addresses G.sub.1 to G.sub.n, and pixels disposed in the vicinity of crossing points between the signal lines and the scanning lines are formed in pixel portions. Each pixel has a pixel TFT. A gate electrode of the pixel TFT is connected to a scanning line, and a source electrode thereof is connected to a signal line. The address of each pixel is represented by an address of a signal line connected to a source electrode of a pixel TFT, and an address of a scanning line connected to a gate electrode thereof. For example, when a pixel TFT is connected to a signal line in an i-th column and a scanning line in a j-th row, the address of a pixel having this pixel TFT is (i, j).

Furthermore, a pixel electrode is formed so as to be connected to a drain electrode of a pixel TFT, and an opposing electrode is opposed to the pixel electrode. Liquid crystal is interposed between the pixel electrode and the opposing electrode via an alignment film. Liquid crystal is switched in accordance with a potential difference between the pixel electrode and the counter electrode.

In dot-sequential driving, a period from a time when a first scanning line is selected to a time when an n-th scanning line is selected is referred to as a "scanning period of scanning lines". Applying a predetermined potential (e.g., +8 volts to +11 volts) to a scanning line for the purpose of activating a semiconductor layer is referred to as "selecting a scanning line". A period for selecting a scanning line is referred to as a "scanning line selection period".

More specifically, the "scanning period of scanning lines" refers to a period required from the beginning of selection of a first scanning line to the end of selection of an n-th scanning line. "Selecting a scanning line" refers to applying a gate pulse to a pixel TFT connected to a scanning line, thereby bringing a conducting state between a source and a drain of the pixel TFT connected to the scanning line. Furthermore, a selection period of a scanning line refers to a period for selecting one scanning line, and the "scanning period of scanning lines" is obtained by multiplying the selection period of a scanning line by n times.

Furthermore, selecting a signal line refers to applying a signal voltage to a signal line, and applying a potential of the signal line to a pixel TFT connected to the signal line.

Furthermore, a period from a time when a potential required for an image display is applied to a pixel electrode of a pixel TFT having an address (1,1) to a time when one monochromic image is formed is referred to as a "sub-frame period". A period from a time when a potential required for an image display is applied to a pixel electrode of a pixel TFT having an address (1,1) to a time when one color image is formed is referred to as a "frame period".

According to the field sequential system, a frame period in which a color image is displayed includes a sub-frame period for forming a red image, a sub-frame period for forming a blue image, and a sub-frame period for forming a green image.

FIG. 7 shows a timing chart of the field sequential system in which light sources are lighted intermittently. According to the field sequential system, a cycle (T) of one frame period is 16.6 msec., and a cycle (T/3) of a sub-frame period is 5.5 msec.

In dot-sequential driving, one scanning line is selected, and signal lines are successively selected by a shift register of a source driver, to thereby apply a potential of a signal line to a pixel electrode of each pixel TFT connected to a selected scanning line. The sub-frame period is divided into a standby period 301, a scanning line selection period 302, a liquid crystal response period 303, and a lighting period 304 of light sources. The standby period refers to a period from a time when one frame period starts to a time when a scanning line connected a pixel TFT is selected. The liquid crystal response period refers to a period in which liquid crystal responses in accordance with a potential of a pixel electrode. A scanning period 308 of scanning lines is obtained by multiplying a scanning line selection period by the number (n) of scanning lines.

In the scanning line selection period 302, a scanning line is selected, and a pixel electrode of a pixel TFT connected to the scanning line is successively supplied with a potential of a signal line in accordance with a desired gray-scale. In the liquid crystal response period 303, optical response of liquid crystal is completed. In the lighting period 304 of light sources, light sources are lighted intermittently, whereby a first light emission color 305, a second light emission color 306, and a third light emission color 307 are successively entered into a liquid crystal display device. For example, as the first light emission color, a red color is used. As the second light emission color, a green light is used. As the third light emission color, a blue light is used. However, when the light sources are lighted intermittently, the liquid crystal response period 303 of the pixel TFTs connected to a first scanning line is different from that of the pixel TFTs connected to an n-th scanning line. When it takes a long period of time for liquid crystal to respond, or when the scanning period 308 of scanning lines is long, if it is attempted to light a light source after liquid crystal response is completed, the lighting period 304 of light sources becomes short, which decreases lightness.

According to the field sequential system, one important factor is a response time of liquid crystal. As the response time of liquid crystal becomes shorter, a lighting period of a light source can be made longer to conduct a light display.

Another important factor of the field sequential system is a scanning period of scanning lines. Assuming that there are n scanning lines, when a scanning period becomes longer, it takes a shorter period of time for a light source to be lighted after the application of a potential of a signal line to a pixel electrode toward the n-th scanning line. Therefore, before response of liquid crystal is completed, a light source is lighted. A gray-scale level is determined by the integral of lightness shown by liquid crystal when a light source is lighted. If a light source is lighted before response of liquid crystal is completed, a gray-scale level when a screen is displayed is changed. On the contrary, if a light source is lighted after response of liquid crystal is completed, a lighting period of a light source becomes shorter, which results in a dark display.

In liquid crystal display devices with a number of scanning lines, e.g., XGA (1024 pixels (horizontal direction).times.768 pixels (vertical direction)), SXGA (1280 pixels (horizontal direction).times.1024 pixels (vertical direction), the ratio of a scanning period of scanning lines in a sub-frame period is not negligible. In dot-sequential driving of the SXGA liquid crystal display device, even if a write time of a signal to one pixel is set to be 0.75 to 1.5 nsec, a scanning period of scanning lines is estimated to be 1 to 2 msec. Therefore, when a scanning period of scanning lines is removed from a sub-frame period (5.5 msec), only 3.5 to 4.5 msec remains. If liquid crystal is allowed to respond until desired lightness is obtained and a light source is lighted within this time, a lighting time of a light source becomes considerably short, making it difficult to conduct a light display.

In the present specification, optical response of liquid crystal is allowed to be completed as early as possible in driving of a liquid crystal display device of the field sequential system. Furthermore, a scanning period of scanning lines is shortened to decrease a ratio of a standby period 301 in a sub-frame period.

More specifically, in the present specification, in the field sequential system, a sum of a standby period 301 and a liquid crystal response period 303 is shortened, and a lighting period 304 of a light source is prolonged, whereby a light display is conducted.

SUMMARY OF THE INVENTION

The present invention is characterized in that, when a pixel electrode having a potential of a first signal voltage in a first sub-frame period has a potential of a second signal voltage in a second sub-frame period, a response time of liquid crystal when a voltage value is changed from the first signal voltage to the second signal voltage is calculated, and in an order from a pixel in which the calculated response time of liquid crystal is long, the potential of the second signal voltage is applied to the pixel electrode of the pixel in the second sub-frame period.

According to the present invention, a circuit configuration includes: a first means for storing a potential of a first signal voltage applied to a pixel electrode in a first sub-frame period; a second means for storing a potential of a second signal voltage applied to the pixel electrode in a second sub-frame period; a third means for calculating a response time of liquid crystal when a voltage value is changed from the first signal voltage to the second signal voltage; and a fourth means for applying, in an order from a pixel in which the calculated response time of liquid crystal is long, the second signal voltage to the pixel electrode of the pixel.

According to the field sequential system, there are a sub-frame period in which a monochromic image is formed, and a frame period in which three sub-frame periods are continuously combined to form a color image. The above-mentioned configuration is applicable to the field sequential system. Furthermore, by replacing the sub-frame period with the frame period, the present invention can be applied widely to a liquid crystal display device and a method of driving the same irrespective of the field sequential system.

In dot-sequential driving, pixels are successively selected from pixel electrodes connected to pixel TFTs connected to a scanning line in a first row to pixel electrodes having pixel TFTs connected to a scanning line in an n-th row. Therefore, when a response time of liquid crystal is long in pixels connected to a scanning line in the n-th row, liquid crystal may not respond by the time when light sources are lighted in the field sequential system. However, according to the present invention, when an image is changed from a first sub-frame period to a second sub-frame period, and liquid crystal responds, a pixel having a long response time of liquid crystal is preferentially selected. Therefore, in a timing chart of the field sequential system in FIG. 7, a standby period 301 becomes short in a pixel having a long response period 303 of liquid crystal, and the sum of the standby period 301 and the liquid crystal response period 303 can be shortened. More specifically, a lighting period 304 of a light source can be prolonged, making it possible to conduct a light display.

Furthermore, the present invention is characterized in that a potential of the same signal voltage is simultaneously applied to pixel electrodes of a plurality of pixels connected to the same signal line and displaying the same gray-scale. By simultaneously selecting a plurality of pixels, a scanning period of scanning lines can be shortened.

Furthermore, the present invention has a first stage in which a potential of a first signal voltage is applied to a first pixel electrode connected to a first pixel TFT connected to a signal line and a first scanning line and a second pixel electrode connected to a second pixel TFT connected to the signal line and a second scanning line.

The present invention also has a second stage in which the signal line and the second scanning line are selected and the second pixel electrode is supplied with a potential of a second signal voltage whose difference in an absolute value from that of the first signal voltage is larger than 0 volt and smaller than 0.5 volt.

Thus, in the first stage, a potential of a first signal voltage is applied to a second pixel electrode connected to a drain electrode of a second pixel TFT, thereby previously allowing liquid crystal to respond. It is assumed that the second pixel electrode is a pixel electrode displaying a gray-scale approximate to that of the first pixel electrode. The approximate gray-scale refers to a gray-scale displayed with an absolute value of a voltage whose difference from that of a voltage applied to the first pixel electrode is larger than 0 volt and smaller than 0.5 volt. In the second stage, a second signal voltage is applied to a second pixel electrode, thereby allowing liquid crystal to respond so as to display a normal gray-scale. By previously allowing liquid crystal to respond, when a potential of a second signal voltage is applied to a second pixel electrode, a response time required for responding to a gray-scale of a display image can be shortened.

In order to prevent burning of liquid crystal, a first pixel TFT and a second pixel TFT in which a signal of a signal line is simultaneously written may be made pixel TFTs in which a voltage with the same polarity is to be written.

Each invention as described above can be widely used as a liquid crystal display device and a method of driving the same. In particular, each invention is effective for the field sequential system in which light sources are intermittently lighted for the following reason. Light sources are intermittently lighted. Therefore, even when the order of writing signal voltages in pixels is at random, light sources are not lighted while signal voltages are written in pixels and random write is not visually recognized by a user.

A combination of the above-mentioned inventions would be widely applied to a known method of driving liquid crystal, as well as the field sequential system.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIG. 1 shows an exemplary circuit configuration of a method of driving a liquid crystal display device according to the present invention.

FIG. 2 shows an exemplary timing chart of a method of driving a liquid crystal display device according to the present invention.

FIG. 3 shows an exemplary timing chart of a method of driving a liquid crystal display device according to the present invention.

FIG. 4 shows an exemplary timing chart of a method of driving a liquid crystal display device according to the present invention.

FIG. 5 shows an exemplary circuit configuration of a method of driving a liquid crystal display device according to the present invention.

FIG. 6 shows an exemplary timing chart of a method of driving a liquid crystal display device according to the present invention.

FIG. 7 shows an exemplary timing chart in the case of conducting a color display by the field sequential system.

FIGS. 8A to 8C are cross-sectional views illustrating a method of manufacturing an active matrix substrate.

FIGS. 9A to 9C are cross-sectional views illustrating a method of manufacturing an active matrix substrate.

FIG. 10 is a cross-sectional view illustrating a method of manufacturing an active matrix substrate.

FIG. 11 is a plan view showing a pixel portion of an active matrix substrate.

FIG. 12 is a cross-sectional view of a liquid crystal display device.

FIGS. 13A to 13F show examples of electronic equipment.

FIGS. 14A to 14C show examples of electronic equipment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiment Mode 1

A circuit configuration of the present invention will be described with reference to FIG. 1. FIG. 1 shows pixels and a driving circuit of the present embodiment mode. In FIG. 1, pixels are arranged in a matrix (m columns.times.n rows) in a pixel portion. An address of a pixel disposed in an i-th column and in a j-th row is represented as (i, j) (i is an integer of 1 to m, and j is an integer of 1 to n).

One frame period includes a first sub-frame period to a third sub-frame period. A video signal 130 in the first to third sub-frame periods, and an address of a pixel for receiving the video signal 130 are input to a first means or a second means in accordance with designation of a switching circuit 131.

The video signal 130 may be an analog signal or a digital signal. In the case where the video signal 130 is an analog signal, in order to memorize the video signal 130 with good precision, the video signal 130 may be converted into a digital signal by using an analog/digital converter (A/D converter) before being input to the first means or the second means.

A first means is provided for storing a potential of a first signal voltage applied to a pixel electrode in the first sub-frame period. The first means is referred to as first storage means 101 based on its function. Furthermore, a second means is provided for storing a potential of a second signal voltage applied to a pixel electrode in the second sub-frame period. The second means is referred to as second storage means 102 based on its function.

A third means is provided for operation of a response time of liquid crystal when a first signal voltage is changed to a second signal voltage in the same pixel TFT. The third means is referred to as comparison operation means 103 based on its function. For operation of a response time of liquid crystal, a theoretical value of a response time may be calculated from physical constants such as a rotation viscosity coefficient, an elastic constant and dielectric anisotropy of liquid crystal. It may also be possible that the relationship between the response time of liquid crystal and the driving voltage thereof is previously input to the comparison operation means 103, and the data is referred to. In accordance with a calculated response time of liquid crystal, the order of writing a signal of a signal line to a pixel TFT in the second sub-frame period is determined.

First, a response time of liquid crystal when the first signal voltage is changed to the second signal voltage is calculated with respect to all the pixels. It is assumed that a response time of liquid crystal is longest in a pixel at an address (2,2), and a response time becomes shorter in the order of pixels at addresses (2, 1), (1, 1), and (1, 2). More specifically, it is assumed that, among four pixels, a response time of liquid crystal when a pixel at an address (1, 2) is changed from the first signal voltage to the second signal voltage is shortest. In this case, when an image in the second sub-frame period is displayed, a signal of a signal line is written to a pixel TFT in the order of addresses: (2, 2), (2, 1), (1, 1), and (1, 2). That is, a signal of a signal line is written in the second sub-frame period in the order from a pixel TFT of a pixel with a longest response time of liquid crystal. For convenience, four pixels are illustrated here. However, in the case of n.times.m pixels, a signal of a signal line is also written in the order from a pixel TFT of a pixel with a longest response time of liquid crystal when the first signal voltage is changed to the second signal voltage. When a response time of liquid crystal is the same in a plurality of pixels, in order to alleviate the burden on a driving circuit, a signal of a signal line is written to a pixel TFT in the order from a closest pixel.

In the first sub-frame period, the comparison operation data storage means 104 stores the order of writing a signal of a signal line to a pixel TFT in the second sub-frame period.

A fourth means is provided for supplying a second signal voltage of a pixel electrode of a pixel, in the order from a pixel with a longest response time of liquid crystal. In the present embodiment mode, the fourth means includes an X address writing control means 110 having an X address decoder 106 and video signal output means 108 connected to the X address decoder 106, and a Y address writing control means 109 having a Y address decoder 105 and a level shifter 107 connected to the Y address decoder 105.

Among the fourth means, the X address writing control means 110 having the X address decoder 106 and the video signal output means 108 has a function of selecting a signal line connected to a pixel TFT, based on X address data output from the comparison operation data storage means 104. Furthermore, the Y address writing control means 109 having the Y address decoder 105 and the level shifter 107 has a function of selecting a scanning line connected to a pixel TFT, based on Y address data output from the comparison operation data storage means 104.

Based on the Y address data output from the comparison operation data storage means 104, the Y address decoder 105 addresses a scanning line of a pixel TFT in which a signal of a signal line is to be written. In the case of the SXGA (1280 (horizontal direction).times.1024 (vertical direction)), if the number of input terminals of the Y address decoder 105 is set to be 10 in accordance with the number of pixels, 2.sup.10 scanning lines can be arbitrarily selected. Among the output terminals of the Y address decoder, an output pulse is output from an output terminal having a Y address designated by Y address data. A voltage of the output pulse is amplified by the level shifter 107, and a gate pulse is output to a scanning line having the designated Y address.

The X address decoder 106 addresses a signal line to which a potential of a signal voltage is applied. In the case of the SXGA (1280 (horizontal direction).times.1024 (vertical direction)), the number of input terminals of the X address decoder 106 may be set to be 11 in accordance with the number of pixels. An output pulse is output from an output terminal at the X address designated by the X address decoder 106, and is input to the video signal output means 108. A video signal (signal voltage) is input to the signal line of the designated X address, whereby the signal voltage is applied to the signal line. Regarding a video signal 119, the order in which a video signal is written to a pixel TFT is determined by an external circuit (comparison operation data storage means 104), whereby the video signal 119 is input to the video signal output means 108.

In the case where a video signal input to the video signal output means is a digital signal, a digital/analog converter (D/A converter) is built in the video signal output means, thereby converting the digital signal into an analog signal.

Thus, a signal of a signal line is written successively to the pixel TFT 118 in accordance with the order stored in the comparison operation data storage means 104, whereby an image in the second sub-frame period is formed.

An operation of the circuit will be described with reference to FIG. 2. By combining images displayed in the first to third sub-frame periods, a color image is displayed in the first frame period 916. A preparatory period 912 has first to third periods 900, 901, and 902. In the first period 900, the first storage means stores an address of a pixel TFT in the first sub-frame period and a first signal voltage written in the pixel TFT. In the second period 901, the comparison operation means calculates a response time of liquid crystal in each pixel when an image in the first sub-frame period is formed. In the third period 902, data in the comparison operation means is transferred to the comparison operation data storage means.

A first sub-frame period 913 has a writing period 903 for writing a signal of a signal line to a pixel TFT. The first sub-frame period 913 also has a liquid crystal response period 904 for liquid crystal to respond in accordance with the first signal voltage. The first sub-frame period 913 also has a lighting period 905 in which light sources are lighted. A first light emission color output from a light source during the first sub-frame period can be set to be red, for example, among three additive primary colors.

In the first sub-frame period 913, in order to form an image in the second sub-frame period, the order of writing a second signal voltage to a pixel TFT is simultaneously determined. The first storage means has already stored a first signal voltage in pixels at X and Y addresses in the first sub-frame period. Therefore, in a fourth period 906, the second storage means stores a second signal voltage in pixels at X and Y addresses in the second sub-frame period. Then, in a fifth period 907, the comparison operation means calculates a response time of liquid crystal when the first signal voltage is changed to the second signal voltage, and determines the order of selecting pixels from the operation results. In a sixth period 908, the data in the comparison operation means is transferred to the comparison operation data storage means.

In a second sub-frame period 914, the pixel data in the comparison operation data storage means is written in a pixel. The second sub-frame period 914 has a writing period 909 of pixel data, a liquid crystal response period 910, and a lighting period 911 of light sources. A second light emission color output from a light source can be set to be green, for example.

An image in a third sub-frame period is formed by a circuit operation in accordance with the second sub-frame period. In a third sub-frame period 915, a third light emission color output from a light source can be set to be blue, for example. Thus, in the first frame period, a color image is formed. By repeating the above-mentioned processes, animation composed of color images can be displayed.

Referring to a timing chart of the field sequential system in FIG. 7, according to the present invention, a standby period 301 of a pixel having a long response period 303 of liquid crystal can be shortened. Therefore, compared with the conventional example, the sum of the standby period 301 and the liquid crystal response period 303 can be shortened. Because of this, the lighting period 304 of a light source can be prolonged. Furthermore, a method of conducting a color display in accordance with the field sequential system in which light sources are intermittently lighted is combined with the present embodiment mode, and light sources are not lighted in a liquid crystal response period. Therefore, even if pixels are selected at random, random write is not recognized by a user.

FIG. 3 shows a timing chart of the Y address writing control means 109. A driving circuit having a level shifter and a Y address decoder is referred to as Y address writing control means. The Y address writing control means selects a scanning line connected to a pixel TFT.

The following description will be made with reference to the timing chart of the Y address writing control means. First, a plurality of Y address data 111 are input to input terminals of the Y address decoder. For example, when the number of scanning lines is 1024, the number of X address data is 10 so as to select either one of 1024 scanning lines, and each X address data has "0" or "1" information. An output pulse 112 is output from an output terminal of the Y address decoder having the Y address designated by the Y address data. The output pulse 112 has a voltage value amplified by the level shifter, and converted into a gate pulse 117. The gate pulse 117 is output to a scanning line of the designated Y address. Thus, a scanning line connected to a pixel TFT of a pixel, in which a response time of liquid crystal is long, is preferentially selected. In a first sub-frame period 132, in accordance with the order of pixel TFTs in which a first signal voltage is written, output pulses 112 to 116 are successively output to the designated Y address. The output pulses 112 to 116 are converted into gate pulses 117 to 121, and a scanning line is selected. In a second sub-frame period 133, in the same way as in the first sub-frame period 132, output pulses are converted into gate pulses, and a scanning line connected to a pixel TFT of pixel in which a response time of liquid crystal is long is selected first. Thereafter, formation of an image is repeated at a timing in accordance with the above.

For example, it is assumed that, in a VGA (640 pixels (horizontal direction).times.480 pixels (vertical direction)) display device, pixels with a long response time of liquid crystal are in the following order: (1, 5), (6, 2), (150, 4), . . . (60, 3), (200, 300). That is, it is assumed that a response time of liquid crystal is longest in the pixel (1, 5), and a response time of liquid crystal is shortest in a pixel (200, 300). In this case, a gate pulse 117 is output to a scanning line having an address of G5, and a gate pulse 118 is output to a scanning line having an address of G2, and a gate pulse 119 is output to a scanning line having an address of G4. Then, a gate pulse 120 is output to a scanning line having an address of G3, and a gate pulse 121 is output to a scanning line having an address of G300.

FIG. 4 shows a timing chart of the X address writing control means 110. A driving circuit composed of an X address decoder and a video signal output circuit is referred to as X address writing control means. The X address writing control means selects a signal line connected to a pixel TFT.

The following description will be made with reference to the timing chart of the X address writing control means. First, X address data 122 showing the order of selecting signal lines is input to an input terminal of the X address decoder. For example, in the case where the number of signal lines is 1240, the number of Y address data is 11 so as to select either one of 1240 signal lines. Each Y address data has "0" or "1" information. Output pulses 123 to 127 are output from output terminals at the X address designated by the X address data 122, among the output terminals of the X address decoder. A video signal 129 is input to a signal line at the designated X address, and supplies a potential of a signal voltage to the signal line. In the second sub-frame period, in the same way as in the first sub-frame period, a signal line connected to a pixel TFT of a pixel with a longest response time of liquid crystal is preferentially selected. Thereafter, formation of an image is repeated at a timing in accordance with the above.

For example, it is assumed that, in a VGA (640 pixels (horizontal direction).times.480 pixels (vertical direction)) display device, pixels with a long response time of liquid crystal are in the following order: (1, 5), (6, 2), (150, 4), . . . (60, 3), (200, 300). That is, it is assumed that a response time of liquid crystal is longest in the pixel (1, 5), and a response time of liquid crystal is shortest in a pixel (200, 300). In this case, after an output pulse 123 is output to a signal line having an address of S1, an output pulse 124 is output to a signal line having an address of S6, and an output pulse 125 is output to a signal line having an address of S150. Then, an output pulse 126 is output to a signal line having an address of S60, and an output pulse 127 is output to a signal line having an address of S200.

A pulse width of the output pulse output from the X address decoder is the same as that output from the Y address decoder. The number of output pulses output from the X address decoder and the Y address decoder in a pixel portion having pixels arranged in a matrix (m columns.times.n rows) is m.times.n, respectively, and data is written on the pixel basis in the order from a pixel with a longest response time.

Embodiment Mode 2

FIG. 5 shows Embodiment Mode 2 of the present invention. In FIG. 5, a plurality of address decoders, i.e., a first Y address decoder and a second Y address decoder are provided. In FIG. 5, the address of a pixel arranged in an i-th column and a j-th row is represented as (i, j) (i is an integer of 1 to m, and j is an integer of 1 to n).

First, a storage means 201 stores data of a video signal (signal voltage) 200 at an X address and a Y address in the first sub-frame period. The Y address represents an address of a signal line, and the X address represents an address of a scanning line.

More specifically, the storage means 201 stores the video signal and an address of a pixel to which the video signal is input.

A first means for detecting pixel TFTs connected to the same signal line and displaying the same gray-scale is programmed so as to simultaneously write a signal of a signal line to pixel TFTs of pixels conducting a display with the same signal voltage in a plurality of pixel TFTs 210 connected to a signal line at the same X address. In the present embodiment mode, the first means is referred to as comparison means 202 based on its function. It is assumed that, among pixel TFTs connected to a signal line at the X address of 1, pixels at the Y address of 1, 10, and n conduct a display with the same signal voltage, and the comparison means 202 detects pixel TFTs at addresses (1, 1), (1, 10), and (1, n) in the first frame period. In the present embodiment mode, for convenience of description, it is assumed that two pixel TFTs at maximum are simultaneously supplied with the same signal voltage. Furthermore, it is assumed that a pixel TFT for writing a signal of a signal line simultaneously with the pixel TFT at the address (1, 1) is the one of the remaining two pixels (1, 10) and (1, n) at a Y address with a larger value, i.e., the pixel TFT at the address (1, n). The reason for this is as follows. According to dot-sequential driving, in a pixel TFT at a Y address with a larger value, there is a tendency that it takes a longer time to write a signal of a signal line, and a standby period 301 in FIG. 7 becomes longer in the field sequential system. Therefore, it is better to preferentially select a pixel TFT at a Y address with a larger value. Needless to say, by altering the design of a driving circuit, it is also possible to simultaneously apply a signal of a signal line to three pixel TFTs, instead of that two pixel TFTs are simultaneously supplied with a signal of a signal line.

Next, the comparison data storage means 203 successively stores the order of writing a signal of a signal line to pixels, determined by the comparison means 202.

Second means is provided for simultaneously applying a potential of a signal voltage to pixel electrodes of a plurality of pixel TFTs. In the present embodiment mode, the second means includes an X address decoder 204, video signal output means 205, a first Y address decoder 206, a second Y address decoder 208, a first level shifter 207, and a second level shifter 209.

The X address decoder 204 selects an address of a signal line based on X address data output from the comparison data storage means 203. The first Y address decoder 206 and the second Y address decoder 208 select an address of a scanning line based on Y address data output from the comparison data storage means 203.

The X address decoder 204 outputs an output pulse from an output terminal at an X address designated based on the X address data output from the comparison data storage means 203. Although not shown, in the case