Liquid crystal display device having a particular conductive layer Number:7,394,516 from the United States Patent and Trademark Office (PTO) owispatent The present invention related to unifying steps of sealing material so that the yield and the reliability of a liquid-crystal display device become high. A starting film of scanning lines is patterned so that prismatic dummy wirings 301 for the first layer which are not electrically connected are formed in regions R1 and R2, and wirings 302 extending from the pixel section are formed in a region R3, and wirings 303 having connection end portions 303a are formed in a region R4. After an interlayer insulation film is formed on those surface, the starting film of the signal lines is patterned so that the dummy wirings 304 for the second layer are formed to embed the gaps between the wirings 301 to 303, and also the wirings 305 and the wirings 303 which extend from the pixel portion are connected to each other. As a result, the cross-sectional structure along the line A A' of the sealing material formation region 107 can be unified.<H conductive, particular, Liquid, crystal, , 7394516.html, Patent, pto, 7394516

Title: Liquid crystal display device having a particular conductive layer

Abstract: The present invention related to unifying steps of sealing material so that the yield and the reliability of a liquid-crystal display device become high. A starting film of scanning lines is patterned so that prismatic dummy wirings 301 for the first layer which are not electrically connected are formed in regions R1 and R2, and wirings 302 extending from the pixel section are formed in a region R3, and wirings 303 having connection end portions 303a are formed in a region R4. After an interlayer insulation film is formed on those surface, the starting film of the signal lines is patterned so that the dummy wirings 304 for the second layer are formed to embed the gaps between the wirings 301 to 303, and also the wirings 305 and the wirings 303 which extend from the pixel portion are connected to each other. As a result, the cross-sectional structure along the line A A' of the sealing material formation region 107 can be unified.

Patent Number: 7,394,516 Issued on 07/01/2008 to Zhang

Inventors: Zhang; Hongyong (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd. (Atsugi-shi, Kanagawa-ken, JP)

Appl. No.: 10/811,920

Filed: March 30, 2004

Related U.S. Patent Documents


Application Number	Filing Date	Patent Number	Issue Date
09316697	May., 1999
08768066	Dec., 1996	5995189

Foreign Application Priority Data


Dec 21, 1995 [JP]			7-350229

Current U.S. Class: 349/153 ; 349/149; 349/158; 349/190

Current International Class: G02F 1/1339 (20060101); G02F 1/1333 (20060101); G02F 1/1345 (20060101)

Field of Search: 349/153,190,155,149,151,158 345/206

References Cited [Referenced By]

U.S. Patent Documents


5148301	September 1992	Sawatsubashi et al.
5162901	November 1992	Shimada et al.
5179460	January 1993	Hinata et al.
5200847	April 1993	Mawatari et al.
5285301	February 1994	Shirahashi et al.
5323042	June 1994	Matsumoto
5327267	July 1994	Aoki et al.
5396356	March 1995	Fukuchi
5429962	July 1995	Yang
5504601	April 1996	Watanabe et al.
5508532	April 1996	Teramoto
5517344	May 1996	Hu et al.
5537235	July 1996	Ishihara et al.
5572046	November 1996	Takemura
5598283	January 1997	Fujii et al.
5619258	April 1997	Gillespie
5619358	April 1997	Tanaka et al.
5621553	April 1997	Nishiguchi et al.
5684547	November 1997	Park et al.
5684555	November 1997	Shiba et al.
5691793	November 1997	Watanabe et al.
5706069	January 1998	Hermens et al.
5744820	April 1998	Matsushima et al.
5745208	April 1998	Grupp et al.
5757450	May 1998	Fujii et al.
5760854	June 1998	Ono et al.
5798812	August 1998	Nishiki et al.
5929959	July 1999	Iida et al.
5995189	November 1999	Zhang
6011607	January 2000	Yamazaki et al.
6037005	March 2000	Moshrefzadeh et al.
6055034	April 2000	Zhang et al.
6072556	June 2000	Hirakata et al.
6088073	July 2000	Hioki et al.

Foreign Patent Documents


0 545 712	Jun., 1993	EP
0 612 102	Aug., 1994	EP
62-205320	Sep., 1987	JP
62-229234	Oct., 1987	JP
63-26631	Feb., 1988	JP
63-104025	May., 1988	JP
03-163418	Jul., 1991	JP
04-97321	Mar., 1992	JP
05-061072	Mar., 1993	JP
5-127181	May., 1993	JP
5-158015	Jun., 1993	JP
06-51332	Feb., 1994	JP
06-186578	Jul., 1994	JP
06-250224	Sep., 1994	JP
06-289413	Oct., 1994	JP
06-308510	Nov., 1994	JP
07-092477	Apr., 1995	JP
07-159811	Jun., 1995	JP
7-209659	Aug., 1995	JP
07-318965	Dec., 1995	JP
09-179130	Jul., 1997	JP
10-198292	Jul., 1998	JP

Other References

Complaint for Patent Infringement, and Demand for Jury Trial, Semiconductor Energy Laboratory Co., Ltd., Plaintiff vs. Chi Mei Optoelectronics Corp., International Display Technology Co., Ltd., International Display Technology USA, Inc., Westinghouse Digital Electronics, LLC and CTX Technology Corp., Defendants dated Nov. 3, 2004. cited by other .
Defendant Chi Mei Optoelectronics Corp.'s Answer to Complaint for Patent Infringement, Demand for Jury Trial, and Counterclaim dated Feb. 28, 2005. cited by other .
Defendant Westinghouse Digital Electronics, LLC's Answer to Complaint for Patent Infringement dated Feb. 28, 2005. cited by other .
Defendant International Display Technology Co., Ltd.'s Answer to Complaint for Patent Infringement dated Feb. 28, 2005. cited by other .
Defendant International Display Technology USA, Inc.'s Answer to Complaint for Patent Infringement dated Feb. 28, 2005. cited by other .
Defendant Chi Mei Optoelectronics Corp.'s Responses to Plaintiff Semiconductor Energy Laboratory Co., Ltd.'s First Set of Interrogatories dated Apr. 4, 2005. cited by other .
Defendant's Preliminary Proposed Claim Constructions and Preliminary Identification of Extrinsic Evidence Pursuant to Patent L.R. 4-2; 108 pages; Jul. 22, 2005. cited by other .
Semiconductor Energy Laboratory Co., Ltd.'s Proposed Preliminary Claim Constructions and Extrinsic Evidence; 7 pages; Jul. 22, 2005. cited by other .
Semiconductor Energy Laboratory Co., Ltd.'s Patent L.R. 4-2(b) Disclosure; 12 pages; Jul. 22, 2005. cited by other .
Joint Claim Construction and Prehearing Statement; 12 pages; Aug. 5, 2005. cited by other .
Semiconductor Energy Laboratory Co., Ltd.'s Opening Brief on Claim Construction and Supporting Evidence; 41 pages; Sep. 20, 2005. cited by other .
Declaration of Donald R. Harris in Support of Semiconductor Energy Laboratory Co., Ltd.'s Opening Brief on Claim Construction (2 pages) and Supporting Evidence (with Exhibits 1-12); Sep. 20, 2005. cited by other .
Defendants' Claim Construction Response Brief; 39 pages; Oct. 4, 2005. cited by other .
Declaration of Scott R. Mosko in Support of Defendants' Claim Construction Response Brief (5 pages) and Exhibits A-X; Oct. 4, 2005. cited by other .
Semiconductor Energy Laboratory Co., Ltd.'s Reply Brief on Claim Construction and Supporting Evidence; 18 pages; Oct. 11, 2005. cited by other .
Declaration of Donald R. Harris in Support of Semiconductor Energy Laboratory Co., Ltd.'s Reply Brief on Claim Construction with Exhibits; 71 pages; Oct. 11, 2005. cited by other .
"Withdrawal: Selected IBM PS/2 Mobile Systems (300, 700/700C) and Features," IBM Announcement Letter 193-268. cited by other .
Lewis et al., "Driver Circuits for AMLCDs," Conference Record of the 1994 International Display Research Conference and International Workshops on Active-Matrix LCDs & Display Materials, pp. 56-64, Oct. 1994. cited by other .
Defendant's Preliminary Invalidity Contentions and Accompanying Document Production dated Jun. 6, 2005 (13 pages) and Exhibits B-1 (11 pages), B-2 (10 pages), B-3 (7 pages), B-4 (6 pages), B-5 (5 pages), B-6 (9 pages), B-7 (9 pages) and B-8 (8 pages). cited by other .
Memorandum & Order re: Claim Construction, Semiconductor Energy Laboratory Co., Ltd., Plaintiff vs. Chi Mei Optoelectronics Corp., et al., Defendants, No. C04-04675 MHP, dated Mar. 24, 2006, 41 pages. cited by other .
Revised exhibits to Defendant's Preliminary Invalidity Contentions dated Jun. 7, 2005: Exhibits B-2 (11 pages), B-3 (7 pages), B-4 (7 pages) and B-8 (8 pages). cited by other.

Primary Examiner: Qi; Mike
Attorney, Agent or Firm: Fish & Richardson P.C.

Parent Case Text

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional application of U.S. application Ser. No. 09/316,697, filed on May 21, 1999, now allowed, which is a divisional of U.S. application Ser. No. 08/768,066, filed on Dec. 16, 1996, now U.S. Pat. No. 5,995,189, which claims the benefit of a foreign priority application filed in Japan on Dec. 21, 1995 as Ser. No. 07-350229. This application claims priority to each of these prior applications, and the disclosures of the prior applications are considered part of (and are incorporated by reference in) the disclosure of this application.

Claims

What is claimed is:

1. A display device comprising: a first substrate having at least one side edge; a plurality of first conductive lines extending over the first substrate in a first direction; a plurality of second conductive lines extending over the first substrate in a second direction orthogonal to said first direction; an interlayer insulating film disposed between said first conductive lines and said second conductive lines; a plurality of thin film transistors disposed at locations adjacent to intersections of said first conductive lines and said second conductive lines; a plurality of pixel electrodes electrically connected to said thin film transistors; a second substrate located separated from said first substrate; a sealing member disposed at a periphery of said first and second substrates, said sealing member having a portion adjacent to said side edge; a conductive layer comprising a same material as said plurality of second conductive lines and interposed between said portion of the sealing member and said first substrate; and a black matrix at least partly overlapped with said conductive layer; wherein said conductive layer continuously extends along said side edge of said first substrate for more than a pitch of adjacent ones of said second conductive lines, and is electrically isolated from both of said plurality of first conductive lines and said plurality of second conductive lines.

2. The display device according to claim 1 wherein each of said plurality of thin film transistors is a top-gate type thin film transistor.

3. The display device according to claim 1 wherein each channel region of each of said plurality of thin film transistors has a crystalline structure.

4. The display device according to claim 1 wherein said conductive layer extends in a form of a rectangular wave.

5. A display device according to claim 1 wherein the black matrix is located between the sealing member and the conductive layer.

6. A display device comprising: a first substrate having at least one side edge; a plurality of scanning lines extending over the first substrate in a first direction; a plurality of signal lines extending over the first substrate in a second direction; a plurality of thin film transistors disposed at each intersection of said scanning lines and said signal lines; a plurality of pixel electrodes electrically connected to said thin film transistors; an interlayer insulating film disposed between said scanning lines and said signal lines; a second substrate opposed to said first substrate; a sealing member disposed at a periphery of said first and second substrates, said sealing member having a portion adjacent to said side edge; a conductive layer interposed between said portion of the sealing member and said first substrate, said conductive layer comprising a same material as said plurality of scanning lines; and a black matrix at least partly overlapped with said conductive layer; wherein said conductive layer continuously extends along said side edge of said first substrate for more than a pitch of adjacent ones of said scanning lines, and is electrically isolated from both of said plurality of scanning lines and said plurality of signal lines.

7. The display device according to claim 6 wherein each of said plurality of thin film transistors is a top-gate type thin film transistor.

8. The display device according to claim 6 wherein each channel region of said plurality of thin film transistors has a crystalline structure.

9. The display device according to claim 6 wherein said conductive layer extends in a form of a rectangular wave.

10. A display device according to claim 6 wherein the black matrix is located between the sealing member and the conductive layer.

11. A display device comprising: a first substrate having at least one side edge; a plurality of first conductive lines extending over the first substrate in a first direction; a plurality of second conductive lines extending over the first substrate in a second direction orthogonal to said first direction; a plurality of first thin film transistors disposed at each intersection of said first conductive lines and said second conductive lines; a plurality of pixel electrodes electrically connected to said first thin film transistors; an interlayer insulating film disposed between said first conductive lines and said second conductive lines; a second substrate opposed to said first substrate; a sealing member disposed at a periphery of said first and second substrates, said sealing member having a portion adjacent to said side edge; a driver circuit comprising at least one second thin film transistor formed over said first substrate, said driver circuit disposed within a region surrounded by said sealing member; and a conductive layer comprising a same material as said plurality of second conductive lines and interposed between said portion of the sealing member and said first substrate; and a black matrix at least partly overlapped with said conductive layer; wherein said conductive layer continuously extends along said side edge of said first substrate for more than a pitch of adjacent ones of said second conductive lines, and is electrically isolated from both of said plurality of first conductive lines and said plurality of second conductive lines.

12. The display device according to claim 11 wherein each of said plurality of first thin film transistors is a top-gate type thin film transistor.

13. The display device according to claim 11 wherein each channel region of said plurality of first thin film transistors has a crystalline structure.

14. The display device according to claim 11 wherein said conductive layer extends in a form of a rectangular wave.

15. A display device according to claim 11 wherein the black matrix is located between the sealing member and the conductive layer.

16. A display device comprising: a first substrate having at least one side edge; a plurality of scanning lines extending over the first substrate in a first direction; a plurality of signal lines extending over the first substrate in a second direction; a plurality of first thin film transistors disposed at each intersection of said scanning lines and said signal lines; a plurality of pixel electrodes electrically connected to said first thin film transistors; an interlayer insulating film disposed between said scanning lines and said signal lines; a second substrate opposed to said first substrate; a sealing member disposed at a periphery of said first and second substrates, said sealing member having a portion adjacent to said side edge; a driver circuit comprising at least one second thin film transistor formed over said first substrate, said driver circuit disposed within a region surrounded by said sealing member; a conductive layer interposed between said portion of the sealing member and said first substrate, said conductive layer comprising a same material as said plurality of scanning lines; and a black matrix at least partly overlapped with said conductive layer; wherein said conductive layer continuously extends along said side edge of said first substrate for more than a pitch of adjacent ones of said scanning lines, and is electrically isolated from both of said plurality of scanning lines and said plurality of signal lines.

17. The display device according to claim 16 wherein each of said plurality of first thin film transistors is a top-gate type thin film transistor.

18. The display device according to claim 16 wherein each channel region of said plurality of first thin film transistors has a crystalline structure.

19. The display device according to claim 16 wherein said conductive layer extends in a form of a rectangular wave.

20. A display device according to claim 16 wherein the black matrix is located between the sealing member and the conductive layer.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a liquid-crystal display device of the active matrix system for reducing failure occurring when bonding substrates, and more particularly to a peripheral circuit integral type liquid-crystal display device.

2. Description of the Related Art

A conventional active matrix liquid-crystal display device is so designed as to control the optical characteristics such as a light transmission property of a liquid-crystal material which is held between a pair of pixel electrodes using the switching operation of a two-terminal element such as an MIM which is disposed in a pixel section in the form of a matrix or a three-terminal element such as a TFT, for display. In general, TFTs using amorphous silicon have been widely used for the switching element of the pixel electrodes.

However, because the mobility of the electric field effect of amorphous silicon is low to the degree of 0.1 to 1 cm/Vs, the TFT using amorphous silicon cannot be disposed in a peripheral drive circuit that controls the TFT connected to the pixel electrode.

For that reason, in the conventional active matrix liquid-crystal device, the peripheral drive circuit which is made up of a semiconductor integrated circuit is attached externally to a liquid-crystal panel through the tape automatic bonding (TAB) technique or the chip on glass (COG) technique.

FIG. 16 is a front view showing the outline of an active matrix liquid-crystal panel in accordance with a first conventional example, to which a peripheral drive circuit is attached externally. As shown in FIG. 16, scanning lines 2 and signal lines 3 are disposed on an element substrate 1 made of, for example, glass or quartz in a matrix, and in a pixel section 4, pixel electrodes and a switching pixel TFT for the pixel electrodes are connected to each of the cross portions of those wirings. The scanning lines 2 and the signal lines 3 extend up to the outside of a sealing material region 5, respectively, and for that reason, the number of wirings which are transverse to the sealing material is as much as the number of the scanning lines 2 and the signal lines 3 at the minimum. The ends of those wirings form extension terminals 6 as they are, and the extension terminals 6 are connected with a peripheral drive circuit not shown. Furthermore, the element substrate 1 is joined to an opposite substrate not shown through the sealing material disposed in the sealing material region 5, and a liquid-crystal material is interposed between those substrates through the sealing material.

Also, in recent years, in order to obtain a TFT with a large mobility of the electric field effect, a technique for fabricating the TFT using crystalline silicon has been intensively researched. The TFT using the crystalline silicon enables operation which is remarkably higher than that of an amorphous silicon TFT, and not only a TFT of NMOS but also a TFT of PMOS are obtained from crystalline silicon in the same manner, thereby being capable of obtaining a CMOS circuit. Hence, a display section as well as the peripheral drive circuit can be fabricated on the same substrate.

FIG. 17 is a front view showing the outline of an active matrix liquid-crystal display device in accordance with a second conventional example, in which a peripheral drive circuit and a display section are integrated on a panel. As shown in FIG. 17, a pixel section 12 is disposed on an element substrate 11 made of, for example, glass or quartz, and a signal line drive circuit 13 is disposed on an upper side of the pixel section 12 around the pixel section 12, and a scanning line drive circuit 14 is disposed on a left side thereof. Signal lines 15 and scanning lines 16 are connected to the signal line drive circuit 13 and the scanning line drive circuit 14, respectively. The signal lines 15 and the scanning lines 16 form a lattice in the pixel section 12, and the ends of the signal lines 15 and the scanning lines 16 extend up to the outside of the sealing material region 17 and are connected with a control circuit, a power supply not shown, or the like. Also, the element substrate 11 and the opposite substrate 18 are joined to each other through the sealing material formed in the sealing material region 17, and a liquid-crystal material is interposed between those substrates 11 and 14 by the shape of the sealing material. Further, an external terminal 19 is disposed on the element substrate 11.

In the first conventional example shown in FIG. 16, the wiring structure around the pixel section 4 is symmetrical with respect to top and down as well as right and left on the paper surface with the result that the steps of the sealing section are made uniform, thereby being capable of making an interval between the substrates uniform.

However, in the first conventional example, because the peripheral drive circuit is connected to the outside of the sealing material, there are a lot of wirings that are transverse to the sealing material, and moisture enters from the interfaces between the wirings which connect the drive circuit to the pixel section and the sealing material, resulting in such a problem that the liquid-crystal surface material is deteriorated. Also, because the peripheral drive circuit is disposed outside, the device is made large in size.

In order to eliminate those problems, the peripheral drive circuit integral type active matrix liquid-crystal display device in accordance with the second conventional example shown in FIG. 17 has a peripheral drive circuit disposed inside the sealing material region 17. Also, a one-side drive system is generally adopted without any provision of a redundant circuit. For that reason, as shown in FIG. 17, since wirings are transversal to the sealing material only on the right side and the lower side of the element substrate 11, the wiring structure has no symmetry with respect to top and down as well as right and left on the paper surface, the step of the sealing material on the peripheral drive circuit side is different from that of the sealing material on a wiring extending side. Hence, in bonding the substrates together, because no pressure is uniformly applied to the substrate, it is difficult to make an interval between the substrates uniform. As a result, nonuniformity occurs on display, or an image quality is deteriorated.

In particular, because the step of the sealing material on the peripheral drive circuit side is low, when bonding the substrates together, there may be a case in which the wirings are short-circuited between the top and the bottom in the peripheral drive circuit, thereby being liable to generate a line defect. Those problems lead to additional causes such as the deterioration of the yield of the peripheral drive circuit integral type liquid-crystal display device, or the lowering of the reliability.

Also, in the pixel element, a most projected portion is in a region where the scanning lines and the signal lines are superimposed one on another, and in the region, not only the scanning line, the signal line, an inter-layer insulation film for separating those lines from each other, but also a pixel electrode, a black matrix and so on are laminated one on another. In general, columnar fibers for maintaining the interval between the substrates are mixed with the sealing material. The dimensions of the fiber are set to values obtained by taking into consideration the margin in addition to the thickness of the projected portion in the pixel section and the dimensions of spacers dispersed inside the sealing material in such a manner that the step of the sealing material is higher in level than the pixel section. However, if the spacer is disposed on the projected portion of the pixel section, the pixel portion becomes higher than the sealing material, and when the substrates are bonded together under this state, the scanning lines and the signal lines are short-circuited between the top and the bottom through the spacers, thereby causing the point defect and the line defect.

SUMMARY OF THE INVENTION

The present invention has been made to eliminate the above problems with the conventional devices, and therefore an object of the present invention is to provide a peripheral drive circuit integral type liquid-crystal display device which is excellent in image quality and high in reliability.

In order to solve the above problems, according to the present invention, there is provided a liquid-crystal display device, comprising: an element substrate having a matrix circuit; an opposite substrate which is opposite to said element substrate; a sealing member for bonding said element substrate and said opposite substrate together; and substrate interval correction means having a laminate structure consisting of at least one layer and disposed in a region where said sealing material is formed.

Also, according to the present invention, there is provided a liquid-crystal display device, comprising: an element substrate matrix circuits having signal lines and scanning lines which are disposed in a matrix and separated from each other through a first interlayer insulation film, and pixel electrodes disposed on cross points of said signal lines and said scanning lines and separated from the signal lines through a second interlayer insulation film, and a peripheral drive circuit for controlling said matrix circuit; an opposite substrate which is opposite to said element substrate; a sealing material which surrounds said matrix circuit and bonds said element substrate and said opposite substrate together; and substrate interval correction means having at least first support means made of the same material as the signal lines, said first interlayer insulating film, second support means made of the same material as the signal lines, and a second interlayer insulation film formed in different layers from each other, in the formation region of said sealing material in said element substrate.

Further, according to the present invention, there is provided a liquid-crystal display device, comprising: an element substrate matrix circuits having signal lines and scanning lines which are disposed in a matrix and separated from each other through a first interlayer insulation film, pixel electrodes disposed on cross points of said signal lines and said scanning lines and separated from the signal lines through a second interlayer insulation film, and a thin-film transistor for operating the pixel electrode, and a peripheral drive circuit for controlling said matrix circuit; an opposite substrate which is opposite to said element substrate; a sealing material which surrounds said matrix circuit and bonds said element substrate and said opposite substrate together; and substrate interval correction means having at least support means made of the same material as the scanning lines, said first interlayer insulating film, and a second interlayer insulation film formed in different layers from each other, in the formation region of said sealing material in said element substrate.

The above and other objects and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings.

FIG. 1 is a front view showing the outline of an element substrate of an active matrix type liquid-crystal display device in accordance with embodiments of the present invention, in which peripheral drive circuits 103, 102 and a display section 102 are disposed on an element substrate 101.

As shown in FIG. 1, signal lines 105 and scanning lines 106 are transversal to a sealing material formation region 107 on the right and bottom sides of a paper surface, but those lines 105 and 106 are not transversal to the sealing material formation region 107 on the side of peripheral circuits 103 and 104. For that reason, in the present invention, there is formed substrate interval correction means that makes the step of the sealing material uniform.

FIG. 6 is a cross-sectional view showing substrate interval maintaining means taken along a width direction of the sealing material. As shown in FIG. 6, in the sealing material formation region, first support members 301, 302 and 303 made of the same material as that of the scanning lines 106, a first interlayer insulation layer 220 that separates the signal lines 105 from the scanning lines 106, and second support members 304 made of the same material as that of the signal lines 105 are laminated one on another. In particular, because it is designed that the second support members 304 do not exist on the first support members 301, 302 and 303, the cross-sectional structure of the substrate interval maintaining means along the edge portion of the sealing material formation region 107 is made uniform, thereby being capable of making the step of the sealing material uniform.

FIG. 15 is a cross-sectional view showing another substrate interval maintaining means taken along the width direction of the sealing material. As shown in FIG. 15, in the sealing material formation region 107, first support members 301, 302 and 303 made of the same material as that of the scanning lines 106, a first interlayer insulation layer 220 that separates the signal lines 105 from the scanning lines 106, and second support members 701 made of the same material as that of the signal lines 105 are laminated one on another. A region where the thickness of the matrix circuit is maximum is a region in which the signal lines 105 and the scanning lines 106 are superimposed one on the other. In the region, the signal lines, the interlayer insulation layer, the scanning lines and a passivation film are laminated one on another at least on the element substrate. Hence, in the present invention, the first support members 301, 302 and 303 and the second support members 701 are designed so as to be superimposed one on the other, thereby being capable of making the step of the substrate interval maintaining means nearly equal to the height of the region in which the thickness of the matrix circuit is maximum. Also, the step of the matrix circuit containing a spacer is made lower than the sealing material, thereby being capable of supporting a pressure required when bonding the substrates together by the sealing material. As a result, the spacer can prevent the scanning lines and the signal lines from being short-circuited between the upper and lower sides. It should be noted that because in the region where the signal lines 105 and the scanning lines 106 are superimposed one on the other, pixel electrodes, a black matrix and so on are further laminated one on another, the substrate interval formation means may be also designed so that the pixel electrodes, the black matrix and so on are laminated one on another in the formation means.

FIG. 4 is a top view showing the substrate interval correction means, in which linear first support members 301, 302 and 303 and second support members 304 are disposed alternately at regular intervals in the sealing material formation region 107.

The scanning lines extending from the matrix circuit are formed integrally with the first support members 302 in a region R3 transversal to the sealing material formation region 107 and extend to the outside of the sealing material formation region 107. On the other hand, the signal lines 305 that extend from the matrix circuit 102 are connected to the first support members 303 that are transversal to the sealing material formation region 107 inside the sealing material formation region 107.

As described above, according to the present invention, a wiring pattern which is transversal to the sealing material formation region 107 and electrically connected to an external circuit of the element substrate is made up of only the first support members 302 and 303, thereby making the step of the sealing material more uniform.

Also, as shown in FIG. 8, a wiring from the matrix circuit 102 or the peripheral circuits 103 and 104 is not transversal to the sealing material formation region 107 in the regions R1 and R2. The wiring is formed in the shape of a rectangular wave which is nearly equal to the width of the sealing material formation region 107 without disconnecting a first wiring layer 401. As a result, because the first wiring layer exists in an arbitrary cross-sectional structure in the width direction of the sealing material formation region 107, moisture can be prevented from entering from the exterior.

Also, in the present invention, the substrate interval maintaining means is so designed as to be formed together with a thin-film transistor that drives said pixel electrode, the first wiring layer is formed together with the signal lines, and the second wiring layer is formed together with the signal line.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a top view showing a liquid-crystal display device in accordance with embodiments 1 to 5 of the present invention;

FIGS. 2A to 2E are diagrams showing a process of fabricating a TFT in accordance with embodiments 1 to 5;

FIG. 3 is a diagram showing a process of fabricating the lower structure of a sealing material in accordance with embodiment 1;

FIG. 4 is a diagram showing a process of fabricating the lower structure of a sealing material in accordance with embodiment 1;

FIG. 5 is a cross-sectional view taken along a line A A' in FIG. 4 and a cross-sectional view taken along a line B B' in FIG. 7;

FIG. 6 is a cross-sectional view taken along a line A A' in FIG. 4 and a cross-sectional view taken along a line B B' in FIG. 8;

FIG. 7 is a diagram showing a process of fabricating a substrate interval correction means in accordance with embodiment 2;

FIG. 8 is a diagram showing a process of fabricating the substrate interval correction means in accordance with embodiment 2;

FIG. 9 is a diagram showing a process of fabricating the substrate interval correction means in accordance with embodiment 3;

FIG. 10 is a cross-sectional view taken along a line C C' in FIG. 9;

FIG. 11 is a cross-sectional view taken along a line D D' in FIG. 9;

FIG. 12 is a top view showing a substrate interval correction means in accordance with embodiment 4;

FIG. 13 is a cross-sectional view taken along the line E E' in FIG. 12;

FIG. 14 is a top view showing a substrate interval correction means in accordance with embodiment 5;

FIG. 15 is a cross-sectional view taken along the line F F' in FIG. 14;

FIG. 16 is a top view showing a liquid-crystal display device in accordance with conventional example 1; and

FIG. 17 is a top view showing a liquid-crystal display device in accordance with conventional example 2.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Now, a description will be given in more detail of embodiments of the present invention with reference to the accompanying drawings.

FIG. 1 is a front view showing an outline of an element substrate of an active matrix type liquid-crystal display device in accordance with embodiments 1 to 5 of the present invention, in which a peripheral drive circuit is integral with a display section. As shown in FIG. 1, a pixel section 102 is disposed on an element substrate 101 made of glass, quartz or the like, and a signal line drive circuit 103 is disposed on the top side in the periphery of the pixel section 102 whereas a scanning line drive circuit 104 is disposed on the left side. The signal line drive circuit 103 and the scanning line drive circuit 104 are connected to the pixel section 102 through the signal lines 105 and the scanning lines 106, respectively. The signal lines 105 and the scanning lines 106 form a lattice in the pixel section 102, and in the intersections thereof, liquid-crystal cells 111 and pixel TFTs 112 are connected in series, respectively. In the pixel TFTs 112, a gate electrode is connected to the signal lines 105, a source electrode is connected to the scanning lines 106, and a drain electrode is connected to an electrode of the liquid-crystal cell 111.

Furthermore, a sealing material region 107 is so arranged as to surround the pixel section 102, the signal line drive circuit 103, and the scanning line drive circuit 104. The element substrate 101 is bonded to an opposite substrate not shown through the sealing material formed in the sealing material region 107, and a liquid-crystal material is sealingly held between those substrates.

On the right and bottom sides of the paper surface, the signal lines 105 and the scanning lines 106 extend to the exterior of the sealing material formation region 107 so as to be connected to a control circuit outside of the panel, or the like. Furthermore, an external terminal 108 is disposed on the element substrate 101, and the external terminal 108 is connected with the signal line drive circuit 103 and the scanning line drive circuit 104 through wirings 109, respectively.

(Embodiment 1)

The active matrix liquid-crystal display device shown in FIG. 1 according to embodiment 1 is characterized in that, in order to make the step of the sealing material uniform, a wiring pattern (dummy wiring structure) which is shaped and substantially electrically insulated from a starting film of signal lines 103 and scanning lines 104 is disposed in a sealing material formation region 107 to make the structure of the lower portion of the sealing material uniform so that the step of the sealing material is unified. Also, in this embodiment, the above wiring pattern is fabricated together with TFTs disposed on the liquid-crystal panel.

A process of fabricating the active matrix liquid-crystal panel in accordance with this embodiment will be described with reference to FIGS. 2 to 6. FIG. 2 shows a cross-sectional view of a process of fabricating a TFT, in which the left side of FIG. 2 shows a process of fabricating a drive circuit TFT disposed in a peripheral drive circuit (a signal line drive circuit 203, a scanning line drive circuit 204), whereas the right side thereof shows a process of fabricating an pixel TFT disposed in a pixel section 202.

Also, FIGS. 3 to 6 show diagrams showing dummy wirings 301 for a first layer. FIGS. 3 and 4 show schematic top views of the sealing material formation region 107, which are enlarged diagrams of regions R1 to R4 indicated by ellipses in FIG. 1. Also, FIGS. 5 and 6 are cross-sectional views respectively taken along a line A A' in FIGS. 3 and 4.

In fabrication of the TFT, as shown in FIG. 2A, on a substrate 201 such as a quartz substrate or a glass substrate is formed a silicon oxide film 1000 to 3000 .ANG. in thickness as a base oxide film 202. As A method of forming the silicon oxide film, a sputtering method or a plasma CVD method may be used in an oxide atmosphere.

Subsequently, an amorphous silicon film is formed in thickness of 300 to 1500 .ANG., preferably 500 to 1000 .ANG. through the plasma CVD method or the LPCVD method. Then, the thermal annealing is conducted on the silicon film at a temperature of 500.degree. C. or higher, preferably, 800 to 950.degree. C., to thereby crystalize the silicon film. After the silicon film has been crystallized through the thermal annealing, the optical annealing may be conducted on the crystallized silicon film to further enhance crystallinity. Also, in crystallization of the silicon film through the thermal annealing, as disclosed in Japanese Patent Unexamined Publication Nos. Hei 6-244103 and Hei 6-244104, an element (catalytic element) such as nickel which promotes the crystallization of silicon may be added.

Then, the silicon film thus crystallized is etched to form active layers 203 (for a p-channel type TFT) and 204 (for an n-channel type TFT) of TFTs in an island-like peripheral drive circuit and an active layer 205 of TFTs (pixel TFTs) in the matrix circuit, respectively. Moreover, an oxide silicon 500 to 2000 .ANG. in thickness is formed as a gate insulation film 206 through the sputtering method in an oxide atmosphere. As a method of forming the silicon oxide film, the plasma CVD method may be used. In the case of forming the silicon oxide film through the plasma CVD method, it is preferable that dinitrogen monoxide (N.sub.2O) or oxygen (O.sub.2) and mono-silane (SiH.sub.4) may be used as a raw gas.

Thereafter, a starting film of a wiring for the first layer is formed. In this embodiment, a polycrystalline silicon film (containing a small amount of phosphorus that enhances the electrically conductivity) 2000 .ANG.0 to 5 .mu.m, preferably 2000 to 6000 .ANG. in thickness is formed on the overall surface of the substrate through the LPCVD method. Then, the polycrystalline silicon film thus formed is etched to form gate electrodes 207, 208 and 209 (FIG. 2A).

Furthermore, in this embodiment, the starting film of the wiring for the first layer is patterned even in the sealing material region 107 to form a wiring pattern as shown in FIG. 3, simultaneously when the gate electrodes 207 to 209 are formed.

Since it is unnecessary to form a wiring pattern which are transversal to the sealing material formation region 107 in the scanning line drive circuit side region R1 and the signal line drive circuit side region R2, linear dummy wirings 301 for the first layer are formed by patterning the silicon film in such a manner that it is disposed at regular intervals so as not to be electrically connected to each other.

In the scanning line extension side region R3, wirings 302 are formed so as to be transversal to the sealing material formation region 107. The wirings 302 correspond to the scanning lines 106 shown in FIG. 1 and are formed by the extensions of the gate electrodes 209 of the pixel TFTs.

In the signal line extension side region R4, wirings 303 are formed so as to be transversal to the sealing material formation region 107. In the end portions of the wirings 303 on the pixel section 102 side are formed connection end portions 303a for connecting with wirings extending from the pixel section 102 for the second layer.

It should be noted that the respective intervals between the dummy wirings 301 and the wirings 302, 303 are set to be identical with the intervals between the scanning lines 106, that is, to be substantially identical with the intervals between the pixels. In this embodiment, the respective intervals between the dummy wiring 301 for the first layer, the wiring 302 and the dummy wiring 301 for the first layer are set to about 50 .mu.m, and their widths are set to about 10 .mu.m.

Therefore, because the dummy wiring 301 for the first layer, the wiring 302 and the wiring 303 are disposed at regular intervals in the sealing material formation region 107 as shown in FIG. 5, the cross-sectional structure of the sealing material formation region 107 can be unified.

It should be noted that the material of the starting films of the gate electrodes 207 to 209, the dummy wirings 301, the wirings 302 and 303 for the first layer is not limited to a silicon film, and the material of the gate electrode which is usually used may be used therefor. For example, silicide, or aluminum, tantalum, chromium, molybdenum or the like which is an anodizable material may be used.

Subsequently, as shown in FIG. 2B, phosphorus is injected into all the island-like active layers 203 to 205 with a doping gas of phosphine (PH.sub.3) in the self-alignment manner, using the gate electrodes 207 to 209 as a mask, through the ion doping method. The dose amount is set to 1.times.10.sup.12 to 5.times.10.sup.13 atoms/cm.sup.2. As a result, weak n-type regions 210, 211 and 212 are formed.

Then, while a mask 213 made of photoresist which covers the active layer 203 of the p-channel type TFT is being formed, a mask 214 made of photoresist which covers the end of the gate electrode 209 to a portion apart from the end thereof by 3 .mu.m in parallel with the gate electrode 209 in the active layer 205 of the pixel TFTs is formed. Then, phosphorus is again injected into the active layers with a doping gas of phosphine through the ion doping method. The dose amount is set to 1.times.10.sup.14 to 5.times.10.sup.15 atoms/cm.sup.2. As a result, strong n-type regions (source/drain) 215 and 216 are formed. In the weak n-type regions 212 in the active layer 205 of the pixel TFTs, since phosphorus is not injected into regions 217 which have been covered with the mask 214 at this doping, it remains weak n-type (FIG. 2C).

Subsequently, the active layers 204 and 205 of the n-channel type TFT shown in FIG. 2D are covered with a mask 218 made of photoresist, and boron is injected into the island-like region 103 with a doping gas of diborane (B.sub.2H.sub.6) through the ion doping method. The dose amount is set to 5.times.10.sup.14 to 8.times.10.sup.15 atoms/cm.sup.2. In this doping, because the dose amount of boron exceeds the dose amount of phosphorus in FIG. 2C, the weak n-type region (a low-density impurity region) 210 is reverted to a strong p-type region 219.

The strong n-type regions (source/drain) 215, 216, the strong p-type region (source/drain) 219 and the weak n-type region (a low-density impurity region) 217 are formed through the doping process shown in FIGS. 2B to 2D. In this embodiment, the width x of the low-density impurity region 217 is set to about 3 .mu.m.

Thereafter, thermal annealing is conducted on the doped regions at 450 to 850.degree. C. for 0.5 to 3 hours, to thereby recover the regions damaged by doping. As a result, the doping impurities are activated, and the crystallinity of silicon is recovered.

Thereafter, as shown in FIGS. 2E and 5, a silicon oxide film 3000 to 6000 .ANG. in thickness is formed on the entire surface of the substrate as an interlayer insulator 220 through the plasma CVD method. In this embodiment, the thickness of the interlayer insulator 220 is set to 4000 .ANG.. It should be noted that the interlayer insulator 220 may be made up of a single-layer film consisting of a silicon nitride film, or a multi-layer film consisting of a silicon oxide film and a silicon nitride film. The interlayer insulator 220 is etched to form sources/drains 219, 215 and 216 as well as contact holes for connection end portions 303a of the wirings 303 shown in FIG. 3.

Then, the starting film of the wiring and electrodes for the second layer is formed. In this embodiment, a titanium film 1000 .ANG. in thickness, an aluminum film 2000 .ANG. in thickness, and a titanium film 1000 .ANG. in thickness are continuously formed through the sputtering method. The three-layer film is etched so that while electrodes/wirings 221, 522 and 523 of the peripheral circuits and electrode/wiring 224 and 225 of the pixel TFT are formed, dummy wirings 304 for the second layer which are not electrically connected to the sealing material formation region 107 are formed as shown in FIGS. 4 and 6. It should be noted that FIG. 6 is a cross-sectional view taking along a line A A' in the regions R1 to R4 of FIG. 4.

As shown in FIG. 4, the dummy wirings 304 for the second layer are disposed uniformly at the respective gaps defined between the dummy wirings 301, the wirings 302 and the wirings 303 for the first layer which are formed of the starting film (silicon film) of the electrodes and the wirings for the first layer. For that reason, as shown in FIG. 6, the lower structure of the sealing material formation region 107 can be unified. It should be noted that the dummy wirings 304 are formed so that one wiring is divided in the scanning line drive circuit side region R1 and the scanning line extension line side region R3, and likewise so that one wiring is divided in the signal line drive circuit side region R2 and the signal line extension line side region R4.

Further, in this embodiment, as shown in FIG. 3, or connection with an external circuit of the element substrate 101 or an external terminal, wiring patterns (the wirings 302 and the wirings 303) which are transversal to the sealing material formation region 107 are designed so as to be formed of the starting film of the wiring for the first layer, and the wirings for the second layer are designed so as not to extend to the exterior of the sealing material formation region 107, whereby the step of the lower structure in the sealing material formation region 107 is more unified.

Hence, in order to allow the pixel section 102 to be connected to another circuit at the exterior of the panel in the signal line extension side region R4, in patterning the starting film (titanium/aluminum/titanium film) of the electrode and the wiring for the second layer, there are formed the wirings 305 which are connected to the wirings 303 at the connection end portions 303a thereof. The wirings 303 and the wirings 305 enable the pixel section 102 to be connected to another circuit at the exterior of the panel.

It should be noted that the pitch of the dummy wirings 304 for the second layer is set to the pitch of the scanning lines 106, that is, the former is made identical with the pitch of the wirings 305, and the width of the dummy wirings 304 for the second layer is set to 30.mu.m. Because the respective intervals between the dummy wirings 301, the wirings 302 and the wirings 303 for the first layer are set to about 50 .mu.m, the intervals between the end surfaces of the dummy wirings 304 for the second layer and the end surfaces of the dummy wiring 301, the wirings 302 and the wirings 303 for the first layer are about 10 .mu.m.

Then, after the starting film (titanium/aluminum/titanium film) of the electrodes/wirings for the second layer has been patterned, a silicon nitride film 1000 to 3000 .ANG. in thickness is formed as a passivation film 226 through the plasma CVD method as shown in FIGS. 2E and 6.

As shown in FIG. 6, in the sealing material formation region 107, the dummy wirings 304 for the second layer are disposed on the interlayer insulation film 220 at regular intervals in a region where the dummy wirings 301, and the wirings 302, 303 for the first layer are not formed, thereby being capable of making identical the cross-sectional structure taken along the line A A' in FIG. 4, that is, the cross-sectional structure along the outer periphery of the sealing material formation region 107. Then, a passivation film 227 is formed on the surface of the dummy wirings 304 for the second layer, thereby being capable of flattening the surface of the sealing material formation region 107.

It should be noted that in order to make the cross-sectional structure along the outer periphery of the sealing material formation region 107 identical, only the dummy wirings 301, the wirings 302 and the wirings 303 which are formed of the starting film of the electrodes/wirings for the first layer may be disposed. In comparison with the respective intervals between those wirings 301 to 303 being about 50 .mu.m, their widths are small to about 10 .mu.m. As a result, because their strength cannot be compensated, the dummy wirings 304 for the second layer are formed so that the lower structure of the sealing material is reinforced.

Further, in this embodiment, for the purpose of making the step of the lower structure in the sealing material formation region 107 uniform, it is important that the dummy wirings 304 for the second layer are prevented from being superimposed on the dummy wirings 301, the wirings 302 and the wirings 303 for the first layer. If the intervals between the end surfaces are about 10 .mu.m, the dummy wirings 304 for the second layer are prevented from being superimposed on the dummy wirings 301, the wirings 302 and the wirings 303 for the first layer, even though taking into consideration an error in alignment of the mask, or the like.

In this embodiment, the dummy wirings 301 and 304 are formed so as to be longer than the width of the sealing material formation region 107, however, the dummy wirings 301 and 304 may be formed so as