Low complexity synchronization for wireless transmission Number:7,394,870 from the United States Patent and Trademark Office (PTO) owispatent

Title: Low complexity synchronization for wireless transmission

Abstract: A receiver, system and method for providing symbol timing recovery that allows for inexpensive and low-complexity synchronization for communication systems. A receiver receives a signal including digital data in the form of packets that is transmitted from a transmitter. The receiver uses information contained in each of the packets to align a phase of the receiver clock with a phase of the transmitter clock. The receiver further controls a sampling device such that the in-phase (I) and quadrature (Q) components are sampled at an optimum sample rate and at an optimum instance of time without requiring a numerically controlled oscillator or voltage controlled oscillator.

Patent Number: 7,394,870 Issued on 07/01/2008 to Chien,   et al.

---

Inventors:	Chien; Charles (Newbury Park, CA), Chien; David Hsueh-Chia (S. El Monte, CA)
Assignee:	Silicon Storage Technology, Inc. (Sunnyvale, CA)
Appl. No.:	10/407,572
Filed:	April 4, 2003

---

Current U.S. Class:	375/316 ; 375/150; 375/326; 375/345; 375/354
Current International Class:	H04L 27/00 (20060101)
Field of Search:	375/316,355,363,368,345,354,326,150 370/511

---

References Cited [Referenced By]

---

U.S. Patent Documents

4647864	March 1987	Rafferty et al.
5561673	October 1996	Takai et al.
5651031	July 1997	Ishizu
5757858	May 1998	Black et al.
6134282	October 2000	Ben-Efraim et al.
6208183	March 2001	Li et al.
6385259	May 2002	Sung et al.
6430172	August 2002	Usui et al.
6646980	November 2003	Yamamoto et al.
6668023	December 2003	Betts
6843597	January 2005	Li et al.
2002/0135482	September 2002	Frederick
2003/0128746	July 2003	Lerner et al.
2003/0202389	October 2003	Werner et al.
2004/0072552	April 2004	Park et al.

Other References

Charles Chien, Igor Elgorriaga, Charles McConaghy, Low-Power Direct-Sequence Spread-Spectrum Modem Architecture For Distributed Wireless Sensor Networks, Association for Computing Machinery, ISLPED '01, Aug. 6-7, 2001, Huntington Beach, California, USA, pp. 251-254. cited by other.

Primary Examiner: Ghayour; Mohammed
Attorney, Agent or Firm: DLA Piper US LLP

---

Claims

---

What is claimed is:

1. A receiver for receiving a signal including digital data formed of packets transmitted from a transmitter, and for aligning a phase of a receiver clock with a phase of a transmitter clock, the receiver comprising: a radio frequency (RF) receiver section for receiving the transmitted digital data as in-phase (I) and quadrature (Q) components of a baseband signal; a sampling device for digitizing each of the in-phase (I) and quadrature (Q) components; a clock recovery section configured to: correlate the in-phase (I) and quadrature (Q) components with information contained in each of the packets and for generating a first signal to align the phase of the receiver clock with the phase of the transmitter clock based on the correlation of the in-phase (I) and quadrature (Q) components with the information contained in each of the packets; and generate a second signal after the phase of the receiver clock is aligned with the phase of the transmitter clock, the second signal for controlling the sampling device such that the in-phase (I) and quadrature (Q) components are sampled at a symbol rate; and a multiplexer (MUX) having inputs for receiving a system clock signal and a symbol clock signal, an output electrically coupled to the sampling device, and a select line, the multiplexer (MUX) configured to multiplex a system clock signal and a symbol clock signal to the output of the multiplexer (MUX); wherein the sampling device comprises a pair of analog-to-digital converters (ADC), each for sampling one of the in-phase (I) and quadrature (Q) components, the pair of analog-to-digital converters adapted to be clocked by the output of the multiplexer (MUX), and wherein the second signal controls the sampling device by controlling the select line of the multiplexer (MUX) to select the symbol clock signal to be provided at the output of the multiplexer (MUX) such that the analog-to-digital converters (ADC) sample the in-phase (I) and quadrature (Q) components at the symbol rate.

2. A receiver for receiving a signal including digital data formed of packets transmitted from a transmitter, and for aligning a phase of a receiver clock with a phase of a transmitter clock, the receiver comprising: a radio frequency (RF) receiver section for receiving the transmitted digital data as in-phase (I) and quadrature (Q) components of a baseband signal; a sampling device for digitizing each of the in-phase (I) and quadrature (Q) components; and a clock recovery section configured to: correlate the in-phase (I) and quadrature (Q) components with information contained in each of the packets and for generating a first signal to align the phase of the receiver clock with the phase of the transmitter clock based on the correlation of the in-phase (I) and quadrature (Q) components with the information contained in each of the packets; and generate a second signal after the phase of the receiver clock is aligned with the phase of the transmitter clock, the second signal for controlling the sampling device such that the in-phase (I) and quadrature (Q) components are sampled at a symbol rate; wherein the clock recovery section comprises a correlation section for correlating the in-phase (I) and quadrature (Q) components with information contained in each of the packets by determining correlation peaks of the received signal based on the information contained in each of the packets; and wherein the correlation section comprises: a pair of matched filters for filtering the in-phase (I) and quadrature (Q) components to generate filtered outputs; squarers for squaring the filtered outputs to generate squared outputs; and an adder for adding the squared outputs to generate a correlation output; wherein the clock recovery section further comprises: an enable window section that determines if the correlation output is equal to or greater than a first threshold; and a peak detector section enabled by the enable window section for searching for a correlation peak of the correlation output when the correlation output is equal to or greater than the first threshold; and wherein enabling the peak detector section for searching for a correlation peak of the correlation output comprises enabling the peak detector section for: subtracting two temporally adjacent correlation outputs to generate a difference signal; and determining if the difference signal consists of a positive value immediately followed by a negative value.

3. The receiver recited in claim 2, wherein the clock recovery section further comprises a section for generating a third signal each time the difference signal consists of a positive value immediately followed by a negative value.

4. A receiver for receiving a signal including digital data formed of packets transmitted from a transmitter, and for aligning a phase of a receiver clock with a phase of a transmitter clock, the receiver comprising: a radio frequency (RF) receiver section for receiving the transmitted digital data as in-phase (I) and quadrature (Q) components of a baseband signal; a sampling device for digitizing each of the in-phase (I) and quadrature (Q) components; a clock recovery section configured to: correlate the in-phase (I) and quadrature (Q) components with information contained in each of the packets and for generating a first signal to align the phase of the receiver clock with the phase of the transmitter clock based on the correlation of the in-phase (I) and quadrature (Q) components with the information contained in each of the packets; and generate a second signal after the phase of the receiver clock is aligned with the phase of the transmitter clock, the second signal for controlling the sampling device such that the in-phase (I) and quadrature (Q) components are sampled at a symbol rate; and an over-sampling select line, wherein an enable window section generates a first time window having a first duration and a second time window having a second duration, the first and second time windows being selected by the over-sampling select line; wherein the clock recovery section comprises a correlation section for correlating the in-phase (I) and quadrature (Q) components with information contained in each of the packets by determining correlation peaks of the received signal based on the information contained in each of the packets; and wherein the correlation section comprises: a pair of matched filters for filtering the in-phase (I) and quadrature (Q) components to generate filtered outputs; squarers for squaring the filtered outputs to generate squared outputs; and an adder for adding the squared outputs to generate a correlation output; wherein the clock recovery section further comprises: the enable window section which determines if the correlation output is equal to or greater than a first threshold; and a peak detector section enabled by the enable window section for searching for a correlation peak of the correlation output when the correlation output is equal to or greater than the first threshold.

5. A receiver for receiving a signal including digital data formed of packets transmitted from a transmitter, and for aligning a phase of a receiver clock with a phase of a transmitter clock, the receiver comprising: a radio frequency (RF) receiver section for receiving the transmitted digital data as in-phase (I) and quadrature (Q) components of a baseband signal; a sampling device for digitizing each of the in-phase (I) and quadrature (Q) components; and a clock recovery section configured to: correlate the in-phase (I) and quadrature (Q) components with information contained in each of the packets and for generating a first signal to align the phase of the receiver clock with the phase of the transmitter clock based on the correlation of the in-phase (I) and quadrature (Q) components with the information contained in each of the packets; and generate a second signal after the phase of the receiver clock is aligned with the phase of the transmitter clock, the second signal for controlling the sampling device such that the in-phase (I) and quadrature (Q) components are sampled at a symbol rate; wherein the clock recovery section comprises a correlation section for correlating the in-phase (I) and quadrature (Q) components with information contained in each of the packets by determining correlation peaks of the received signal based on the information contained in each of the packets; and wherein the correlation section comprises: a pair of matched filters for filtering the in-phase (I) and quadrature (Q) components to generate filtered outputs; squarers for squaring the filtered outputs to generate squared outputs; and an adder for adding the squared outputs to generate a correlation output; wherein the clock recovery section further comprises: an enable window section that determines if the correlation output is equal to or greater than a first threshold; and a peak detector section enabled by the enable window section for searching for a correlation peak of the correlation output when the correlation output is equal to or greater than the first threshold; and wherein the peak detector section comprises: registers having an input for receiving the correlation output and outputs for outputting the two temporally adjacent correlation outputs; and a subtractor having inputs for receiving the two temporally adjacent correlation outputs from the registers and for subtracting the two temporally adjacent correlation outputs to generate a difference signal at an output of the subtractor.

6. The receiver recited in claim 5, wherein the peak detector section further comprises: comparators for receiving the difference signal and for determining if the difference signal consists of a positive value immediately followed by a negative value; and a logic gate having inputs electrically coupled to outputs of the comparators and an output for generating a first trigger signal when the difference signal consists of a positive value immediately followed by a negative value.

7. The receiver recited in claim 6, wherein the clock recovery section further comprises a pulse generator for generating a third signal as a pulse in response to the first trigger signal.

8. The receiver recited in claim 7, wherein the clock recovery section further comprises a first signal generation section for: receiving generated third signals; determining a duration of a predetermined number of the generated third signals; comparing the duration of the predetermined number of the generated third signals with a predetermined criteria; and generating the first signal if the duration of the predetermined number of the generated third signals meets the predetermined criteria.

9. The receiver recited in claim 8, wherein the receiver comprises a system clock, and wherein the first signal generation section comprises: a first incrementer having a first value which is incremented once for each system clock cycle; a second incrementer having a second value which is incremented once for each generated third signal; a first comparator for receiving the second value as an input and for determining if the second value is greater than a first predetermined threshold; a second comparator for determining if the first value is less than a second predetermined threshold when the second value is greater than the first predetermined threshold; a third comparator for determining if the first value is greater than a third predetermined threshold when the second value is greater than the first predetermined threshold; a first logic gate having inputs electrically coupled to outputs of the second and third comparators and an output for generating a second trigger signal when the first value is less than the second predetermined threshold and greater than the third predetermined threshold; and a pulse generator for generating the first signal as a pulse in response to the second trigger signal.

10. The receiver recited in claim 9, further comprising a second logic gate having a first input for receiving the second signal and a second input for receiving the third signal, and an output for generating a clock pulse when the second signal is not active and the third signal is active, the generated clock pulse for: enabling the first incrementer to be incremented once for each system clock cycle; and incrementing the second incrementer once for each generated third signal.

11. The receiver recited in claim 10, wherein the information contained in each of the packets comprises a number of periods of a Barker sequence in a preamble of each of the packets, and wherein at a time when the second value becomes greater than the first predetermined threshold, a number of system clock cycles having occurred since enabling the first incrementer is equal to ((the predetermined threshold x the number of periods of the Barker sequence x an oversampling ratio)+a fixed delay).

12. A receiver for receiving a signal including digital data formed of packets transmitted from a transmitter, and for aligning a phase of a receiver clock with a phase of a transmitter clock, the receiver comprising: a radio frequency (RF) receiver section for receiving the transmitted digital data as in-phase (I) and quadrature (Q) components of a baseband signal; a sampling device for digitizing each of the in-phase (I) and quadrature (Q) components; and a clock recovery section for: correlating the in-phase (I) and quadrature (Q) components with information contained in each of the packets and for generating a first signal to align the phase of the receiver clock with the phase of the transmitter clock based on the correlation of the in-phase (I) and quadrature (Q) components with the information contained in each of the packets; and generating a second signal after the phase of the receiver clock is aligned with the phase of the transmitter clock, the second signal for controlling the sampling device such that the in-phase (I) and quadrature (Q) components are sampled at a symbol rate; wherein each of the packets comprises a start of frame (SOF) field and wherein the receiver further comprises a frame synchronization section for: detecting a start of frame for each of the packets based on the start of frame (SOF) field contained in each of the packets; generating a frame start signal indicating the start of frame each time the start of frame (SOF) field is detected; detecting an end of frame for each of the packets; and providing a frame end signal to the clock recovery section when the end of frame is detected, the frame end signal causing the clock recovery section to generate a recovery signal indicating that the transmitter clock has been recovered; and wherein the receiver further comprises a received signal strength indicator (RSSI) section and an automatic gain control (AGC) section, and wherein the automatic gain control (AGC) section is enabled by the recovery signal to perform automatic gain control (AGC) based on an indicated received signal strength determined by the received signal strength indicator (RSSI) section.

13. The receiver recited in claim 12, wherein the receiver further comprises: a storage device; a first antenna; a second antenna; and an antenna select section programmed for: (a) selecting the first antenna; (b) performing a first automatic gain control (AGC) to determine a first total receiver gain; (c) storing the first total receiver gain in the storage device; (d) selecting the second antenna; (e) performing a second automatic gain control (AGC) to determine a second total receiver gain; (f) storing the second total receiver gain in the storage device; (g) determining if the second total receiver gain is equal to or greater than the first total receiver gain; (h) reselecting the first antenna if it is determined in (g) that the first total receiver gain is not equal to or greater than the second total receiver gain; and (i) enabling the clock recovery section to perform clock recovery and starting a first timer for tracking a predetermined time-out period for performing clock recovery.

14. The receiver recited in claim 13, wherein the antenna select section is further programmed for: (j) determining if a time period since the clock recovery section was enabled is less than or equal to the predetermined time-out period for performing clock recovery; (k) determining if a negative edge of the second signal is detected; (I) disabling the clock recovery section and resetting the first timer if it is determined in (j) that the time period since the clock recovery section was enabled is greater than the predetermined time-out period, or if it is determined in (k) that the negative edge of the second signal is detected, or if it is determined in (j) and (k) both that the time period since the clock recovery section was enabled is greater than the predetermined time-out period and that the negative edge of the second signal is detected; (m) waiting a predetermined time period; and (n) after waiting the predetermined time period, repeating (a)-(l).

15. The receiver recited in claim 14, wherein the antenna select section is further programmed for: (o) determining if the frame start signal is active if it is determined in (j) that the time period since the clock recovery section was enabled is less than or equal to the predetermined time-out period and if it is determined in (k) that the negative edge of the second signal is not detected; (p) repeating (j)-(k) if it is determined in (o) that the frame start signal is not active; (q) disabling the clock recovery section and resetting the first timer if it is determined in (o) that the frame start signal is active; (r) determining if an end of frame has been reached; (s) repeating (r) if it is determined in (r) that an end of frame has not been reached; (t) waiting a predetermined time period; and (u) after waiting the predetermined time period, repeating (a)-(q) if it is determined in (r) that an end of frame has been reached.

16. The receiver recited in claim 13, wherein the receiver further comprises a variable gain amplifier (VGA) and a low noise amplifier (LNA), and wherein performing an automatic gain control (AGC) to determine a total receiver gain comprises: setting a gain of the variable gain amplifier (VGA) to a maximum possible gain; setting a gain of the low noise amplifier (LNA) to a maximum possible gain; obtaining a first received signal strength indicator (RSSI) value; determining if the first received signal strength indicator (RSSI) value is less than a first threshold; and setting the gain of the variable gain amplifier (VGA) to infinity if it is determined that the first received signal strength indicator (RSSI) value is less than the first threshold.

17. The receiver recited in claim 16, wherein performing the automatic gain control (AGC) to determine the total receiver gain further comprises: determining if the first received signal strength indicator (RSSI) value is greater than a second threshold; setting the gain of the variable gain amplifier (VGA) to a minimum possible gain if it is determined that the first received signal strength indicator (RSSI) value is greater than the second threshold; obtaining a second received signal strength indicator (RSSI) value; determining if the second received signal strength indicator (RSSI) value is greater than the second threshold; and setting the gain of the low noise amplifier (LNA) to a minimum possible gain if it is determined that the second received signal strength indicator (RSSI) value is greater than the second threshold.

18. The receiver recited in claim 17, wherein performing the automatic gain control (AGC) to determine the total receiver gain further comprises: obtaining a third received signal strength indicator (RSSI) value; determining if the third received signal strength indicator (RSSI) value is greater than the second threshold; and setting the gain of the variable gain amplifier (VGA) to negative infinity if it is determined that the third received signal strength indicator (RSSI) value is greater than the second threshold.

19. The receiver recited in claim 18, wherein if it is determined that the third received signal strength indicator (RSSI) value is greater than the second threshold and the third received signal strength indicator (RSSI) value is greater than the second threshold, performing the automatic gain control (AGC) to determine the total receiver gain further comprises searching for a variable gain amplifier (VGA) gain value among all available variable gain amplifier (VGA) gain values until a predetermined condition is met.

20. The receiver recited in claim 19, wherein if it is determined that the first received signal strength indicator (RSSI) value is not less than the first threshold and is not greater than the second threshold, performing the automatic gain control (AGC) to determine the total receiver gain further comprises searching for a variable gain amplifier (VGA) gain value among all available variable gain amplifier (VGA) gain values until a predetermined condition is met.

21. The receiver recited in claim 19, wherein the predetermined condition is at least one of a first condition wherein a latest received signal strength indicator (RSSI) value is both greater than or equal to the first threshold and less than or equal to the second threshold and a second condition wherein a time period for performing automatic gain control (AGC) has been exceeded.

22. The receiver recited in claim 20, wherein the predetermined condition is at least one of a first condition wherein a latest received signal strength indicator (RSSI) value is both greater than or equal to the first threshold and less than or equal to the second threshold and a second condition wherein a time period for performing automatic gain control (AGC) has been exceeded.

23. The receiver recited in claim 19, wherein searching for a variable gain amplifier (VGA) gain value among all available variable gain amplifier (VGA) gain values is performed using a search algorithm.

24. The receiver recited in claim 23, wherein the search algorithm is a binary search algorithm.

25. The receiver recited in claim 20, wherein searching for a variable gain amplifier (VGA) gain value among all available variable gain amplifier (VGA) gain values is performed using a search algorithm.

26. The receiver recited in claim 25, wherein the search algorithm is a binary search algorithm.

27. The receiver recited in claim 16, wherein when the gain of the variable gain amplifier (VGA) is set to infinity, the total receiver gain is set to infinity.

28. The receiver recited in claim 27, wherein when the gain of the variable gain amplifier (VGA) is set to negative infinity, the total receiver gain is set to-infinity.

29. The receiver recited in claim 19, wherein the total receiver gain is equal to (the gain of the variable gain amplifier (VGA) +the gain of the gain of the low noise amplifier (LNA).

30. The receiver recited in claim 20, wherein the total receiver gain is equal to (the gain of the variable gain amplifier (VGA) +the gain of the gain of the low noise amplifier (LNA).

31. The receiver recited in claim 13, wherein the received signal strength indicator (RSSI) section comprises: squarers having inputs electrically coupled to outputs of the sampling device, the squarers for squaring outputs of the sampling device to generate squared outputs at an output of the squarers; and an adder having inputs for receiving the generated squared outputs, the adder for adding the squared outputs for providing added squared outputs at an output of the adder.

32. A receiver for receiving a signal including digital data formed of packets transmitted from a transmitter, and for aligning a phase of a receiver clock with a phase of a transmitter clock, the receiver comprising: a radio frequency (RF) receiver section for receiving the transmitted digital data as in-phase (I) and quadrature (Q) components of a baseband signal; a sampling device for digitizing each of the in-phase (I) and quadrature (Q) components; and a clock recovery section for: correlating the in-phase (I) and quadrature (Q) components with information contained in each of the packets and for generating a first signal to align the phase of the receiver clock with the phase of the transmitter clock based on the correlation of the in-phase (I) and quadrature (Q) components with the information contained in each of the packets; and generating a second signal after the phase of the receiver clock is aligned with the phase of the transmitter clock, the second signal for controlling the sampling device such that the in-phase (I) and quadrature (Q) components are sampled at a symbol rate; wherein each of the packets comprises a start of frame (SOF) field and wherein the receiver further comprises a frame synchronization section for: detecting a start of frame for each of the packets based on the start of frame (SOF) field contained in each of the packets; generating a frame start signal indicating the start of frame each time the start of frame (SOF) field is detected; detecting an end of frame for each of the packets; and providing a frame end signal to the clock recovery section when the end of frame is detected, the frame end signal causing the clock recovery section to generate a recovery signal indicating that the transmitter clock has been recovered; wherein the receiver further comprises, a received signal strength indicator (RSSI) section for determining a received signal strength, a first antenna; a second antenna; and an antenna select section programmed for: (a) selecting the first antenna; (b) measuring a first received signal strength; (c) storing the first received signal strength in a storage device; (d) selecting the second antenna; (e) measuring a second received signal strength; (f) storing the second received signal strength in the storage device; (g) determining if the second received signal strength is equal to or greater than the first received signal strength; (h) reselecting the first antenna if it is determined in (g) that the second received signal strength is not equal to or greater than the first received signal strength; (i) enabling the clock recovery section to perform clock recovery; (j) determining if a time period since the clock recovery section was enabled is less than or equal to the predetermined time-out period for performing clock recovery; (k) determining if a negative edge of the second signal is detected; (I) disabling the clock recovery section and resetting a first timer if it is determined in (j) that the time period since the clock recovery section was enabled is greater than the predetermined time-out period, or if it is determined in (k) that the negative edge of the second signal is detected, or if it is determined in (j) and (k) both that the time period since the clock recovery section was enabled is greater than the predetermined time-out period and that the negative edge of the second signal is detected; (m) waiting a predetermined time period; and (n) after waiting the predetermined time period, repeating (a)-(l).

33. The receiver recited in claim 32, wherein the antenna select section is further programmed for: (o) determining if the frame start signal is active if it is determined in (j) that the time period since the clock recovery section was enabled is less than or equal to the predetermined time-out period and if it is determined in (k) that the negative edge of the second signal is not detected; (p) repeating (j)-(k) if it is determined in (o) that the frame start signal is not active; (q) disabling the clock recovery section and resetting the first timer if it is determined in (o) that the frame start signal is active; (r) determining if an end of frame has been reached; (s) repeating (r) if it is determined in (r) that an end of frame has not been reached; (t) waiting a predetermined time period; and (u) after waiting the predetermined time period, repeating (a)-(q) if it is determined in (r) that an end of frame has been reached.

34. The receiver recited in claim 32, wherein the received signal strength indicator (RSSI) section comprises: squarers having inputs electrically coupled to outputs of the sampling device, the squarers for squaring outputs of the sampling device to generate squared outputs at an output of the squarers; and an adder having inputs for receiving the generated squared outputs, the adder for adding the squared outputs for providing added squared outputs at an output of the adder.

35. The receiver recited in claim 34, wherein the received signal strength indicator (RSSI) section further comprises an averaging block for receiving the added squared outputs and for averaging over a predetermined number of samples of the added squared outputs.

36. The receiver recited in claim 35, wherein the predetermined number of samples ranges from one to 64.

37. A receiver for receiving a signal including digital data formed of packets transmitted from a transmitter, and for aligning a phase of a receiver clock with a phase of a transmitter clock, the receiver comprising: a radio frequency (RF) receiver section for receiving the transmitted digital data as in-phase (I) and quadrature (Q) components of a baseband signal; a sampling device for digitizing each of the in-phase (I) and quadrature (Q) components; a clock recovery section for: correlating the in-phase (I) and quadrature (Q) components with information contained in each of the packets and for generating a first signal to align the phase of the receiver clock with the phase of the transmitter clock based on the correlation of the in-phase (I) and quadrature (Q) components with the information contained in each of the packets; and generating a second signal after the phase of the receiver clock is aligned with the phase of the transmitter clock, the second signal for controlling the sampling device such that the in-phase (I) and quadrature (Q) components are sampled at a symbol rate; and a non-coherent demodulator having inputs electrically coupled to outputs of the sampling device, the demodulator for recovering transmitted symbols and for providing the recovered transmitted symbols at an output of the demodulator; wherein the demodulator comprises differential detectors for multiplying the in-phase (I) and quadrature (Q) components of the baseband signal by a delayed version of the in-phase (I) and quadrature (Q) components of the baseband signal; and wherein the non-coherent demodulator further comprises: an adder having inputs for receiving outputs of the differential detectors, the adder for adding the received outputs of the differential detectors and for generating a soft decision value at an output of the adder; and a slicer having an input for receiving the soft decision value and for generating a demodulated symbol based on the soft decision value at an output of the slicer.

38. A receiver for receiving a signal including digital data formed of packets transmitted from a transmitter, and for aligning a phase of a receiver clock with a phase of a transmitter clock, the receiver comprising: a radio frequency (RF) receiver section for receiving the transmitted digital data as in-phase (I) and quadrature (Q) components of a baseband signal; a sampling device for digitizing each of the in-phase (I) and quadrature (Q) components; a clock recovery section for: correlating the in-phase (I) and quadrature (Q) components with information contained in each of the packets and for generating a first signal to align the phase of the receiver clock with the phase of the transmitter clock based on the correlation of the in-phase (I) and quadrature (Q) components with the information contained in each of the packets; and generating a second signal after the phase of the receiver clock is aligned with the phase of the transmitter clock, the second signal for controlling the sampling device such that the in-phase (I) and quadrature (Q) components are sampled at a symbol rate; and a timing generator section for receiving as an input an over-sampled clock signal having a first rate greater than the symbol rate and for generating at an output of the timing generator section, in response to the first signal, a clock signal having the symbol rate; wherein the receiver further comprises an over-sampling select line; and wherein the timing generator section comprises: a first dividing circuit for dividing the over-sampled clock signal by a first number, when the first signal is active, to generate a first symbol clock signal having a first symbol rate; a second dividing circuit for dividing the over-sampled clock signal by a second number, when the first signal is active, to generate a second symbol clock signal having a second symbol rate; and a multiplexer for multiplexing the first symbol clock signal and the second symbol clock signal based on a state of the over-sampling select line.

39. The receiver recited in claim 38, wherein each of the packets comprises a preamble, and wherein the in-phase (I) and quadrature (Q) components are correlated with information contained in the preamble of each of the packets.

40. The receiver recited in claim 39, wherein the preamble comprises a plurality of periods of a synchronization code, and wherein the correlation section correlates the in-phase (I) and quadrature (Q) components with at least one period of the synchronization code.

41. The receiver recited in claim 40, wherein the synchronization code is an 11-bit Barker sequence.

42. The receiver recited in claim 41, wherein a first portion of the synchronization code is not differentially encoded and a second portion of the synchronization code is differentially encoded.

43. The receiver recited in claim 42, wherein the synchronization code is at least one of a Barker code, a pseudo noise code, a Kasami sequence and a Gold sequence.

44. A method for receiving at a receiver a signal transmitted from a transmitter, the signal including digital data formed of packets, and for aligning a phase of a receiver clock with a phase of a transmitter clock, the method comprising: receiving the transmitted digital data as in-phase (I) and quadrature (Q) components of a baseband signal; digitizing the in-phase (I) and quadrature (Q) components; correlating the in-phase (I) and quadrature (Q) components with information contained in each of the packets; generating a first signal to align the phase of the receiver clock with the phase of the transmitter clock based on the correlation of the in-phase (I) and quadrature (Q) components with the information contained in each of the packets; and generating a second signal upon alignment of the phase of the receiver clock with the phase of the transmitter clock, the second signal for selecting a clock for sampling the in-phase (I) and quadrature (Q) components at a symbol rate; wherein generating a first signal to align the phase of the receiver clock with the phase of the transmitter clock further comprises: generating a third signal for each of a plurality of correlation peaks of the received signal determined based on the information contained in each of the packets; determining a duration of a predetermined number of the generated third signals; comparing the duration of the predetermined number of the generated third signals with a predetermined criteria; and generating the first signal if the duration of the predetermined number of the generated third signals meets the predetermined criteria.

45. The method recited in claim 44, wherein the preamble comprises a plurality of periods of a synchronization code, and wherein correlating the in-phase (I) and quadrature (Q) components with the information contained in the preamble comprises correlating the in-phase (I) and quadrature. (Q) components with at least one period of the synchronization code.

46. The method recited in claim 45, wherein the synchronization code is an 11-bit Barker sequence.

47. The method recited in claim 45, wherein the synchronization code is at least one of a Barker code, a pseudo noise code, a Kasami sequence and a Gold sequence.

48. The method recited in claim 45, wherein each of the packets further comprises a start of frame (SOF) field and a plurality of data blocks, and wherein the start of frame (SOF) field is differentially encoded.

49. The method recited in claim 48, wherein each of the packets comprises a start of frame (SOF) field, and wherein the method further comprises: detecting a start of frame for each of the packets based on the start of frame (SOF) field contained in each of the packets; generating a frame start signal indicating the start of frame each time the start of frame (SOF) field is detected; and generating a recovery signal after the frame start is generated, the recovery signal indicating that the transmitter clock has been recovered.

50. The method of claim 44, further comprising: filtering the in-phase (I) and quadrature (Q) components with corresponding matched filters to generate corresponding filtered outputs of the corresponding matched filters.

51. The method of claim 50, wherein the corresponding matched filters are finite impulse response (FIR) filters having coefficients equal to a time reverse of the information contained in each of the packets.

52. The method of claim 50, wherein the corresponding matched filters are finite impulse response (FIR) filters; and wherein the information contained in each of the packets comprises a synchronization code in a preamble of each of the packets, and wherein the finite impulse response (FIR) filters have coefficients equal to a time reverse of the synchronization code.

53. A method for receiving at a receiver a signal transmitted from a transmitter, the signal including digital data in the form of packets, and for aligning a phase of a receiver clock with a phase of a transmitter clock, the method comprising: receiving the transmitted digital data as in-phase (I) and quadrature (Q) components of a baseband signal; digitizing the in-phase (I) and quadrature (Q) components; correlating the in-phase (I) and quadrature (Q) components with information contained in each of the packets; generating a first signal to align the phase of the receiver clock with the phase of the transmitter clock based on the correlation of the in-phase (I) and quadrature (Q) components with the information contained in each of the packets; generating a second signal upon alignment of the phase of the receiver clock with the phase of the transmitter clock, the second signal for selecting a clock for sampling the in-phase (I) and quadrature (Q) components at a symbol rate, wherein each of the packets comprises a preamble, and wherein the in-phase (I) and quadrature (Q) components are correlated with information contained in the preamble of each of the packets; wherein the preamble comprises a plurality of periods of a synchronization code; wherein correlating the in-phase (I) and quadrature (Q) components with the information contained in the preamble comprises correlating the in-phase (I) and quadrature (Q) components with at least one period of the synchronization code; and wherein a first portion of the synchronization code is not differentially encoded and a second portion of the synchronization code is differentially encoded.

54. A method for receiving at a receiver a signal transmitted from a transmitter, the signal including digital data in the form of packets, and for aligning a phase of a receiver clock with a phase of a transmitter clock, the method comprising: receiving the transmitted digital data as in-phase (I) and quadrature (Q) components of a baseband signal; digitizing the in-phase (I) and quadrature (Q) components; correlating the in-phase (I) and quadrature (Q) components with information contained in each of the packets; generating a first signal to align the phase of the receiver clock with the phase of the transmitter clock based on the correlation of the in-phase (I) and quadrature (Q) components with the information contained in each of the packets; and generating a second signal upon alignment of the phase of the receiver clock with the phase of the transmitter clock, the second signal for selecting a clock for sampling the in-phase (I) and quadrature (Q) components at a symbol rate; wherein each of the packets comprises a preamble, and wherein the in-phase (I) and quadrature (Q) components are correlated with information contained in the preamble of each of the packets; and wherein each of the packets further comprises a start of frame (SOF) field, a plurality of data blocks and a header, and wherein the preamble and the start of frame (SOF) field are modulated according to a first modulation scheme and the data blocks and the header are modulated according to a second modulation scheme.

55. The method recited in claim 54, wherein correlating the in-phase (I) and quadrature (Q) components with information contained in each of the packets comprises: filtering the in-phase (I) and quadrature (Q) components with corresponding matched filters to generate corresponding filtered outputs of the corresponding matched filters; squaring the corresponding filtered outputs to generate corresponding squared outputs; and adding the corresponding squared outputs to generate a correlation output.

56. The method recited in claim 55, further comprising: determining if the correlation output is equal to or greater than a first threshold; and searching for a correlation peak of the correlation output when the correlation output is equal to or greater than the first threshold.

57. The method recited in claim 55, wherein the corresponding matched filters are finite impulse response (FIR) filters.

58. A method for receiving at a receiver a signal transmitted from a transmitter, the signal including digital data in the form of packets, and for aligning a phase of a receiver clock with a phase of a transmitter clock, the method comprising: receiving the transmitted digital data as in-phase (I) and quadrature (Q) components of a baseband signal; digitizing the in-phase (I) and quadrature (Q) components; correlating the in-phase (I) and quadrature (Q) components with information contained in each of the packets by a process that includes: filtering the in-phase (I) and quadrature (Q) components with corresponding matched filters to generate corresponding filtered outputs of the corresponding matched filters; squaring the corresponding filtered outputs to generate corresponding squared outputs; and adding the corresponding squared outputs to generate a correlation output; generating a first signal to align the phase of the receiver clock with the phase of the transmitter clock based on the correlation of the in-phase (I) and quadrature (Q) components with the information contained in each of the packets; generating a second signal upon alignment of the phase of the receiver clock with the phase of the transmitter clock, the second signal for selecting a clock for sampling the in-phase (I) and quadrature (Q) components at a symbol rate; determining if the correlation output is equal to or greater than a first threshold; and searching for a correlation peak of the correlation output when the correlation output is equal to or greater than the first threshold; wherein the receiver comprises a first counter and a second counter and wherein searching for a correlation peak of the correlation output comprises: subtracting two temporally adjacent correlation outputs to generate a difference signal; determining if the difference signal consists of a positive value immediately followed by a negative value; generating a third signal each time the difference signal consists of a positive value immediately followed by a negative value; incrementing a first counter value of the first counter each time the third signal is generated; incrementing a second counter value of the second counter for each cycle of a system clock; and enabling the first signal to be generated when the first counter value is equal to a predetermined number.

59. The method recited in claim 58, wherein the first signal is generated based on the second counter value.

60. The method recited in claim 59, wherein the first signal is generated when the second counter value is less than a second threshold and greater than a third threshold.

61. A method for receiving at a receiver a signal transmitted from a transmitter, the signal including digital data in the form of packets, and for aligning a phase of a receiver clock with a phase of a transmitter clock, the method comprising: receiving the transmitted digital data as in-phase (I) and quadrature (Q) components of a baseband signal; digitizing the in-phase (I) and quadrature (Q) components; correlating the in-phase (I) and quadrature (Q) components with information contained in each of the packets; generating a first signal to align the phase of the receiver clock with the phase of the transmitter clock based on the correlation of the in-phase (I) and quadrature (Q) components with the information contained in each of the packets; and generating a second signal upon alignment of the phase of the receiver clock with the phase of the transmitter clock, the second signal for selecting a clock for sampling the in-phase (I) and quadrature (Q) components at a symbol rate; wherein each of the packets comprises a preamble, and wherein the in-phase (I) and quadrature (Q) components are correlated with information contained in the preamble of each of the packets; wherein the preamble comprises a plurality of periods of a synchronization code, and wherein correlating the in-phase (I) and quadrature (Q) components with the information contained in the preamble comprises correlating the in-phase (I) and quadrature, (Q) components with at least one period of the synchronization code; wherein each of the packets further comprises a start of frame (SOF) field and a plurality of data blocks, and wherein the start of frame (SOF) field is differentially encoded; wherein the method further comprise: detecting a start of frame for each of the packets based on the start of frame (SOF) field contained in each of the packets; generating a frame start signal indicating the start of frame each time the start of frame (SOF) field is detected; and generating a recovery signal after the frame start is generated, the recovery signal indicating that the transmitter clock has been recovered; and wherein an automatic gain control (AGC) loop of the receiver is enabled based on the recovery signal.

62. The method recited in claim 61, wherein the receiver comprises a first timer for tracking a predetermined time-out period for performing clock recovery, and a second timer for tracking a predetermined time period to wait after enabling the automatic gain control (AGC) loop before again enabling the automatic gain control (AGC) loop; and wherein a duration of the first timer and a duration of the second timer are adjusted relative to the clock recovery signal.

63. A method for receiving at a receiver a signal transmitted from a transmitter, the signal including digital data in the form of packets, and for aligning a phase of a receiver clock with a phase of a transmitter clock, the method comprising: receiving the transmitted digital data as in-phase (I) and quadrature (Q) components of a baseband signal; digitizing the in-phase (I) and quadrature (Q) components; correlating the in-phase (I) and quadrature (Q) components with information contained in each of the packets; generating a first signal to align the phase of the receiver clock with the phase of the transmitter clock based on the correlation of the in-phase (I) and quadrature (Q) components with the information contained in each of the packets; generating a second signal upon alignment of the phase of the receiver clock with the phase of the transmitter clock, the second signal for selecting a clock for sampling the in-phase (I) and quadrature (Q) components at a symbol rate; wherein each of the packets comprises a preamble, and wherein the in-phase (I) and quadrature (Q) components are correlated with information contained in the preamble of each of the packets; wherein the preamble comprises a plurality of periods of a synchronization code, and wherein correlating the in-phase (I) and quadrature (Q) components with the information contained in the preamble comprises correlating the in-phase (I) and quadrature, components with at least one period of the synchronization code; wherein each of the packets further comprises a start of frame (SOF) field and a plurality of data blocks, and wherein the start of frame (SOF) field is differentially encoded; detecting a start of frame for each of the packets based on the start of frame (SOF) field contained in each of the packets; generating a frame start signal indicating the start of frame each time the start of frame (SOF) field is detected; generating a recovery signal after the frame start is generated, the recovery signal indicating that the transmitter clock has been recovered; determining if a predetermined number of consecutive frame start signals have not been detected; and resetting the recovery signal if the predetermined number of consecutive frame start signals have not been detected.

64. The method recited in claim 63, further comprising: determining if the second signal is active; determining if a portion of a period of the synchronization code is detected when it is determined that the second signal is active; determining if the start of frame (SOF) field is detected when the portion of the synchronization code is detected; and generating the frame start signal when the start of frame (SOF) field is detected.

65. The method recited in claim 64, further comprising: detecting an end of frame for each of the packets; and generating a frame end signal when the end of frame is detected; and resetting the second signal after the frame end signal is generated.

66. The method recited in claim 65, wherein the end of frame is detected based on a count of a number of bits received after the frame start signal is generated.

67. The method recited in claim 65, wherein the frame end signal is generated immediately after the beginning of the last bit in each of the packets.

68. The method recited in claim 64, wherein the receiver comprises a counter and wherein the method further comprises: determining if a complete period of the synchronization code is detected when the portion of the synchronization code is not detected; incrementing the counter when a complete period of the synchronization code is not detected; determining if a value of the counter is greater than a predetermined threshold; and resetting the second signal if the value of the counter is greater than the predetermined threshold.

69. The method recited in claim 64, wherein the receiver comprises a counter and wherein the method further comprises: determining if a complete period of the synchronization code is detected when the start of frame (SOF) field is not detected; incrementing the counter when a complete period of the synchronization code is not detected; determining if a value of the counter is greater than a predetermined threshold value; and resetting the second signal if the value of the counter is greater than the predetermined threshold.

70. A receiver for receiving a signal including digital data formed of packets transmitted from a transmitter, and for aligning a phase of a receiver clock with a phase of a transmitter clock, the receiver comprising: a radio frequency (RF) receiver section for receiving the transmitted digital data as in-phase (I) and quadrature (Q) components of a baseband signal; a sampling device for digitizing each of the in-phase (I) and quadrature (Q) components; and a clock recovery section comprising: a correlation section that correlates the in-phase (I) and quadrature (Q) components with information contained in each of the packets by determining correlation values of the received signal based on the information contained in each of the packets, and that generates a correlation output, an enable window section that determines if the correlation output meets a first threshold, and a detector section enabled by the enable window section to search for a correlation value of the correlation output when the correlation output meets the first threshold, wherein the clock recovery section is configured to: correlate the in-phase (I) and quadrature (Q) components with information contained in each of the packets and for generating a first signal to align the phase of the receiver clock with the phase of the transmitter clock based on the correlation of the in-phase (I) and quadrature (Q) components with the information contained in each of the packets; and generate a second signal after the phase of the receiver clock is aligned with the phase of the transmitter clock, the second signal for controlling the sampling device such that the in-phase (I) and quadrature (Q) components are sampled at a symbol rate; and a multiplexer (MUX) having inputs for receiving a system clock signal and a symbol clock signal, an output electrically coupled to the sampling device, and a select line, the multiplexer (MUX) configured to multiplex a system clock signal and a symbol clock signal to the output of the multiplexer (MUX); wherein, in searching for the correlation value, the detector section: detects two temporally adjacent correlation outputs to generate a difference signal; and determines if the difference signal consists of a positive value immediately following a negative value.

71. The receiver of claim 70, wherein the correlation section further comprises a pair of matched filters for filtering in-phase (I) and quadrature (Q) components to generate filtered outputs.

72. The receiver of claim 71, wherein the pair of matched filters comprise a finite impulse response (FIR) filer.

73. The receiver recited in claim 72, wherein the finite impulse response (FIR) filter has coefficients equal to a time reverse of the information contained in each of the packets.

74. The receiver of claim 72, wherein the information contained in each of the packets comprises a synchronization code in a preamble of each of the packets, and wherein the finite impulse response (FIR) filter has coefficients equal to a time reverse of the synchronization code.

75. The receiver recited in claim 70, wherein: the enable window section determines if the correlation output is equal to or greater than the first threshold; and the detector section is enabled by the enable window section for searching for a correlation peak of the correlation output when the correlation output is equal to or greater than the first threshold.

76. The receiver of claim 70, wherein the receiver further comprises, a received signal strength indicator (RSSI) section for determining a received signal strength, a first antenna; a second antenna; and an antenna select section programmed for: (a) selecting the first antenna; (b) measuring a first received signal strength; (c) storing the first received signal strength in a storage device; (d) selecting the second antenna; (e) measuring a second received signal strength; (f) storing the second received signal strength in the storage device; (g) determining if the second received signal strength is equal to or greater than the first received signal strength; (h) reselecting the first antenna if it is determined in (g) that the second received signal strength is not equal to or greater than the first received signal strength; and (i) enabling the clock recovery section to perform clock recovery.

77. The receiver of claim 70, wherein each of the packets comprises a start of frame (SOF) field and wherein the receiver further comprises a frame synchronization section for: detecting a start of frame for each of the packets based on the start of frame (SOF) field contained in each of the packets; generating a frame start signal indicating the start of frame each time the start of frame (SOF) field is detected; detecting an end of frame for each of the packets; and providing a frame end signal to the clock recovery section when the end of frame is detected, the frame end signal causing the clock recovery section to generate a recovery signal indicating that the transmitter clock has been recovered.

78. The receiver recited in claim 70, further comprising a demodulator having inputs electrically coupled to outputs of the sampling device, the demodulator for recovering transmitted symbols and for