Manufacturing method of a semiconductor device Number:7,521,350 from the United States Patent and Trademark Office (PTO) owispatent

Title: Manufacturing method of a semiconductor device

Abstract: A manufacturing method of a semiconductor device comprises: providing a first insulating film whose relative dielectric constant is at most a predetermined value above a substrate; providing a second insulating film whose relative dielectric constant is greater than the predetermined value on a surface of the first insulating film; forming a recess for a wire through the second insulating film and extending into the first insulating film, and also forming a recess for a dummy wire through the second insulating film and extending into the first insulating film spaced from a formed area of the recess for the wire; providing a conductive material inside the recess for the wire and the recess for the dummy wire; and providing a wire inside the recess for the wire and providing a dummy wire inside the recess for the dummy wire by polishing and removing the conductive material.

Patent Number: 7,521,350 Issued on 04/21/2009 to Kurashima,   et al.

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Inventors:	Kurashima; Nobuyuki (Yokohama, JP), Minamihaba; Gaku (Kawasaki, JP), Fukushima; Dai (Sagamihara, JP), Tateyama; Yoshikuni (Oita, JP), Yano; Hiroyuki (Yokohama, JP)
Assignee:	Kabushiki Kaisha Toshiba (Tokyo, JP)
Appl. No.:	11/370,050
Filed:	March 8, 2006

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Related U.S. Patent Documents

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	Application Number	Filing Date	Patent Number	Issue Date
	10640004	Aug., 2003	7042099

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Foreign Application Priority Data

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Aug 15, 2002 [JP]			2002-236972

Current U.S. Class:	438/618 ; 257/758; 438/584; 438/622
Current International Class:	H01L 21/4763 (20060101)
Field of Search:	438/618,584,406,622 257/758,784

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References Cited [Referenced By]

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U.S. Patent Documents

5625232	April 1997	Numata et al.
5854125	December 1998	Harvey
5966634	October 1999	Inohara et al.
6037668	March 2000	Cave et al.
6225697	May 2001	Iguchi
6351039	February 2002	Jin et al.
6376048	April 2002	Takeishi
6417575	July 2002	Harada et al.
6432811	August 2002	Wong
6504254	January 2003	Takizawa
6617690	September 2003	Gates et al.
6767826	July 2004	Abe
6815787	November 2004	Yaung et al.
6849549	February 2005	Chiou et al.
6858936	February 2005	Minamihaba et al.
2001/0027008	October 2001	Matsumoto
2001/0055872	December 2001	Fukazawa
2002/0132468	September 2002	Wong
2002/0157076	October 2002	Asakawa
2003/0183940	October 2003	Noguchi et al.
2004/0101663	May 2004	Agarwala et al.
2004/0121577	June 2004	Yu et al.
2004/0140564	July 2004	Lee et al.
2004/0155278	August 2004	Natori et al.

Foreign Patent Documents

	2000-269215		Sep., 2000		JP
	2001-168093		Jun., 2001		JP
	2001-196372		Jul., 2001		JP
	2003-197623		Jul., 2003		JP
	2003-303824		Oct., 2003		JP

Other References

Japanese Office Action, mailed by the Japanese Patent Office on Apr. 24, 2007, in counterpart Japanese Appl. No. 2002-236972. cited by other.

Primary Examiner: Vu; David
Assistant Examiner: Fox; Brandon
Attorney, Agent or Firm: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.

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Parent Case Text

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CROSS-REFERENCE TO RELATED APPLICATIONS

This is a division of application Ser. No. 10/640,004, filed Aug. 14, 2003, now U.S. Pat. No. 7,042,099 which is incorporated in its entirety by reference. This application is also based upon and claims priority from prior Japanese Patent Application No. 2002-236972, filed Aug. 15, 2002, the entire contents of which are incorporated herein by reference.

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Claims

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What is claimed is:

1. A manufacturing method of a semiconductor device, comprising: providing a first insulating film whose relative dielectric constant is at most a predetermined value above a substrate; providing a second insulating film whose relative dielectric constant is greater than the predetermined value on a surface of the first insulating film; forming a recess for an effective wire, passing through the second insulating film and extending into the first insulating film, and also forming a recess for a dummy wire, passing through the second insulating film and extending into the first insulating film in a predetermined area spaced from a formed area of the recess for the effective wire; providing a conductive material on a surface of the second insulating film, inside the recess for the effective wire, and inside the recess for the dummy wire; and providing an effective wire by leaving the conductive material inside the recess for the effective wire, and providing a dummy wire by leaving the conductive material inside the recess for the dummy wire in the predetermined area spaced from the formed area of the effective wire, by polishing and removing the conductive material on the surface of the second insulating film, wherein: the effective wire actually functions as a wire in the semiconductor device; the dummy wire does not actually function as the wire; a pattern shape in a plane view of a single unit of the dummy wire is a nonlinear shape; and the pattern shape in the plane view of the single unit of the dummy wire is not a closed shape, but is an opened shape which keeps the insulating film to remain integral; wherein the opened shape does not confine the insulating film inside the dummy wire and separating the insulating film inside the dummy wire from the insulating film outside the dummy wire; and the opened shape excludes a shape selected from a circular frame shape, an elliptical frame shape, an oval frame shape, a polygonal frame shape, a circular shape, an elliptical shape, an oval shape, and a polygonal shape, the circular shape, the elliptical shape, the oval shape and the polygonal shape being filled with the conductive material inside thereof, wherein: at least four layers of interlayer insulating films comprising the first and second insulating films are provided above the substrate; the dummy wire is provided in the interlayer insulating film of an n-th layer (n is 1 or a greater integer), passing through the second insulating film and extending into the first insulating film; the dummy wire is provided in the interlayer insulating film of a predetermined layer in an (n+2)th and subsequent layers, passing through the second and first insulating films, and that part of the dummy wire which lies at the second insulating film extends along a surface of the interlayer insulating film of the predetermined layer and over the dummy wire provided in the interlayer insulating film of the n-th layer, for a longer distance than that part which lies at the first insulating film; and at least one dummy wire is provided in at least on interlayer insulating film which lies between the n-th layer and the predetermined layer in the (n+2)th and subsequent layers, passing through the second and first insulating films and continued the dummy wires provided in interlayer insulating films of adjacent layers, and wherein: at least a pair of sets of the dummy wires is provided in the interlayer insulating films; the one set of the dummy wires comprises: the dummy wire which is provided in the interlayer insulating film of the predetermined layer in the (n+2)th and subsequent layers; and at least the one dummy wire which is provided in at least the one interlayer insulating film which lies between the n-th layer and the predetermined layer in the (n+2)th and subsequent layers; and the other set of dummy wires is provided at an upper layer than the one set of dummy wires by at least one layer, with at least a lowermost dummy wire of the other set of the dummy wires provided at lower layer than an uppermost dummy wire of the one set of the dummy wires.

2. The method according to claim 1, further comprising a series of processes at least one time, comprising: providing a third insulating film to coat the effective wire and the dummy wire, after providing the effective wire and the dummy wire; providing the first and second insulating films on a surface of the third insulating film; forming the recess for the effective wire and the recess for the dummy wire passing through the third insulating film and the first and second insulating films on the third insulating film so as to be continued to the effective wire and the dummy wire; providing a conductive material on the surface of the second insulating film above the third insulating film and inside the recess for the effective wire and the recess for dummy wire, which are formed over to the second insulating film from the third insulating film; and providing an effective wire by leaving the conductive material inside the recess for the effective wire formed over to the second insulating film from the third insulating film, and providing a dummy wire by leaving the conductive material inside the recess for the dummy wire formed over to the second insulating film from the third insulating film in the predetermined area spaced from the formed area of the effective wire, by polishing and removing the conductive material on the surface of the second insulating film above the third insulating film.

3. The method according to claim 1, further comprising: providing a third insulating film on the surfaces of the first insulating film, the effective wire, and the dummy wire, after polishing and removing the second insulating film together with the conductive material.

4. The method according to claim 1, wherein: the dummy wire which is provided in the first insulating film provided on a surface of the substrate and in the second insulating film provided on the surface of the first insulating film passes through the first and the second insulating films and is continued the surface of the substrate.

5. The method according to claim 1, wherein: the dummy wire is provided in a plurality of places in a predetermined area spaced from an area where the effective wire is provided.

6. The method according to claim 1, wherein: the predetermined area spaced from the area where the effective wire is provided is 100 .mu.m or less from the area where the effective wire is provided.

7. The method according to claim 1, wherein: the predetermined value of the relative dielectric constant is 2.5.

8. The method according to claim 1, wherein: the dummy wire which is provided in the interlayer insulating film of the n-th layer passes through the first and second insulating films, and that part of the dummy wire which lies at the second insulating film of the n-th layer extends along a surface of the interlayer insulating film, for a longer distance than that part which lies at the first insulating film.

9. The method according to claim 1, wherein: the pattern shape in the plane view of the single unit of the dummy wire represents at least one of a figure, a character, and a numeral.

10. The method according to claim 1, wherein: the pattern shape in the plane view of the single unit of the dummy wire is at least one of a linearly symmetrical figure, a figure symmetrical with respect to a point, a pair of figures linearly symmetrical with each other, and a pair of figures symmetrical with respect to a point.

11. The method according to claim 5, wherein: the dummy wires provided in a plurality of places in the predetermined area are arranged in such a manner that a shape of a whole arrangement pattern has a symmetrical property.

12. The method according to claim 6, wherein: the dummy wire is provided to occupy an area of 0.000001% or more of the area of 100 .mu.m or less from the wire-forming area.

13. The method according to claim 1, wherein: at least a pair of the other set of the dummy wires overlaps at least a part of the one set of the dummy wires with spacing apart in a direction which the interlayer insulating films are stacked.

14. The method according to claim 1, wherein: the other set of the dummy wires is provided so as to be fitted into the one set of the dummy wires in a perpendicular direction to a direction which the interlayer insulating films are stacked.

15. The method according to claim 1 wherein: the one set of dummy wires and the other set of the dummy wires are provided in symmetrical positions with each other.

16. A manufacturing method of a semiconductor device, comprising: providing a first insulating film, whose relative dielectric constant is at most a predetermined value, above a substrate; providing a second insulating film, whose relative dielectric constant is greater than the predetermined value, on a surface of the first insulating film; forming a recess for an effective wire, passing through the second insulating film and extending into the first insulating film, and also forming a recess for a dummy wire, passing through the second insulating film and extending into the first insulating film in a predetermined area spaced from a formed area of the recess for the effective wire; providing a conductive material on a surface of the second insulating film, inside the recess for the effective wire, and inside the recess for the dummy wire; providing an effective wire by leaving the conductive material inside the recess for the effective wire, and providing a dummy wire by leaving the conductive material inside the recess for the dummy wire in the predetermined area spaced from the formed area of the effective wire, by polishing and removing the conductive material on the surface of the second insulating film; and performing a series of processes at least three times, comprising: providing a third insulating film to coat the effective wire and the dummy wire, after providing the effective wire and the dummy wire; providing the first and second insulating films on a surface of the third insulating film; forming the recess for the effective wire and the recess for the dummy wire passing through the third insulating film and the first and second insulating films on the third insulating film so as to be continued to the effective wire and the dummy wire; providing a conductive material on the surface of the second insulating film above the third insulating film and inside the recess for the effective wire and the recess for the dummy wire, which are formed over to the second insulating film from the third insulating film; and providing an effective wire continuing to the effective wire by leaving the conductive material inside the recess for the effective wire formed over to the second insulating film from the third insulating film, and providing a dummy wire continuing to the dummy wire by leaving the conductive material inside the recess for the dummy wire formed over to the second insulating film from the third insulating film in the predetermined area spaced from the formed area of the effective wire, by polishing and removing the conductive material on the surface of the second insulating film above the third insulating film, wherein: the effective wires actually function as wires in the semiconductor device; and the dummy wires do not actually function as the wires; wherein: at least four layers of interlayer insulating films comprising the first and second insulating films are provided above the substrate; the dummy wire is provided in the interlayer insulating film of an n-th layer (n is 1 or a greater integer), passing through the second insulating film and extending into the first insulating film; the dummy wire is provided in the interlayer insulating film of a predetermined layer in an (n+2)th and subsequent layers, passing through the second and first insulating films, and that part of the dummy wire which lies at the second insulating film extends along a surface of the interlayer insulating film of the predetermined layer and over the dummy wire provided in the interlayer insulating film of the n-th layer, for a longer distance than that part which lies at the first insulating film; and at least one dummy wire is provided in at least one interlayer insulating film which lies between the n-th layer and the predetermined layer in the (n+2)th and subsequent layers, passing through the second and first insulating films and continued the dummy wires provided in the interlayer insulating films of adjacent layers, and wherein: at least a pair of sets of the dummy wires is provided in the interlayer insulating films; the one set of the dummy wires comprises: the dummy wire which is provided in the interlayer insulating film of the n-th layer; the dummy wire which is provided in the interlayer insulating film of the predetermined layer in the (n+2)th and subsequent layers; and at least the one dummy wire which is provided in at least the one interlayer insulating film which lies between the n-th layer and the predetermined layer in the (n+2)th and subsequent layers; and the other set of the dummy wires is provided at an upper layer than the one set of the dummy wires by at least one layer, with at least a lowermost dummy wire of the other set of the dummy wires provided at lower layer than an uppermost dummy wire of the one set of the dummy wires.

17. The method according to claim 16, wherein a pattern shape in a plane view of a single unit of the dummy wires are nonlinear shape.

18. The method according to claim 17, wherein the dummy wires are so shaped that an insulating film remains integral in the plane view of the single unit of the dummy wires.

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Description

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BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a structure in the vicinity of wiring of a semiconductor device, particularly to a semiconductor device including a multi-layered wiring structure such as a system LSI and high-speed logic LSI, in which durability of an insulating film of each layer with respect to CMP is enhanced, and a manufacturing method of the device.

2. Description of the Related Art

In recent years, in order to reduce a wiring-RC-delay of an LSI and to enhance a capability of a multi-layered wiring, a wire having low resistance and an insulating film having a low relative dielectric constant have been used. As the material of the wire having the low resistance, for example, copper (Cu) having a resistivity .rho. of about 1.8 .mu..OMEGA.cm is used. Moreover, as the insulating film has a low relative dielectric constant, for example, a low-relative-dielectric-constant film (low-k film) is used which contains organic components and whose relative dielectric constant k is about 2.5 or less.

In general, a process of using materials such as Cu, W, and Al to form a so-called damascene wire includes a chemical mechanical polishing (CMP) process. Additionally, since most low-relative-dielectric-constant films have a porous structure, the films are remarkably brittle with respect to mechanical stress (load) in the CMP process. When a low-relative-dielectric-constant film is subjected to CMP, the film itself is destroyed by the mechanical stress, and it is substantially impossible to subject the low-relative-dielectric-constant film directly to the CMP. Therefore, another insulating film including a non-porous structure is usually provided on a low-relative-dielectric-constant film to prevent the low-relative-dielectric-constant film from being destroyed by the CMP.

However, most stacked films including a insulating film and a low-relative-dielectric-constant film have remarkably weak adhesion at an interface. Therefore, when a stacked film is subjected to CMP, the insulating film peels off the low-relative-dielectric-constant film in most cases. When the stacked film is used in a single layer, the film peel at the interface cannot easily occur. However, when the stacked films are laminated in a plurality of layers, the film peel easily occurs at the interface between the layers. Therefore, to realize a multi-layered wiring structure in which interlayer insulating films as the stacked films are laminated in a plurality of layers, a film structure is required in which the adhesion of the films among the layers is stronger than the load of the CMP. Particularly, to form the interlayer insulating films in which the number of layers exceeds ten and which are required in next-generation semiconductor devices such as a system-LSI and high-speed logic-LSI, the film structure in which the adhesion of the films among the layers is larger is required.

BRIEF SUMMARY OF THE INVENTION

According to an aspect of the invention, there is provided a manufacturing method of a semiconductor device comprising: providing a first insulating film whose relative dielectric constant is at most a predetermined value above a substrate; providing a second insulating film whose relative dielectric constant is greater than the predetermined value on a surface of the first insulating film; forming a recess for an effective wire, passing through the second insulating film and extending into the first insulating film, and also forming a recess for a dummy wire, passing through the second insulating film and extending into the first insulating film in a predetermined area spaced from a formed area of the recess for the effective wire; providing a conductive material on a surface of the second insulating film, inside the recess for the effective wire, and inside the recess for the dummy wire; and providing an effective wire by leaving the conductive material inside the recess for the wire, and providing a dummy wire by leaving the conductive material inside the recess for the dummy wire in the predetermined area spaced from the formed area of the effective wire, by polishing and removing the conductive material on the surface of the second insulating film, wherein: the effective wire actually functions as a wire in the semiconductor device; the dummy wire does not actually function as the wire; a pattern shape in a plane view of a single unit of the dummy wire is a nonlinear shape; and the pattern shape in the plane view of the single unit of the dummy wire is not a closed shape, but is an opened shape which keeps the insulating film to remain integral; wherein the opened shape does not confine the insulating film inside the dummy wire and separating the insulating film inside the dummy wire from the insulating film outside the dummy wire; and the opened shape excludes a shape selected from a circular frame shape, an elliptical frame shape, an oval frame shape, a polygonal frame shape, a circular shape, an elliptical shape, an oval shape, and a polygonal shape, the circular shape, the elliptical shape, the oval shape and the polygonal shape being filled with the conductive material inside thereof, wherein: at least four layers of interlayer insulating films comprising the first and second insulating films are provided above the substrate; the dummy wire is provided in the interlayer insulating film of an n-th layer (n is 1 or a greater integer), passing through the second insulating film and extending into the first insulating film; the dummy wire is provided in the interlayer insulating film of a predetermined layer in an (n+2)th and subsequent layers, passing through the second and first insulating films, and that part of the dummy wire which lies at the second insulating film extends along a surface of the interlayer insulating film of the predetermined layer and over the dummy wire provided in the interlayer insulating film of the n-th layer, for a longer distance than that part which lies at the first insulating film; and at least one dummy wire is provided in at least on interlayer insulating film which lies between the n-th layer and the predetermined layer in the (n+2)th and subsequent layers, passing through the second and first insulating films and continued the dummy wires provided in interlayer insulating films of adjacent layers, and wherein: at least a pair of sets of the dummy wires is provided in the interlayer insulating films; the one set of the dummy wires comprises: the dummy wire which is provided in the interlayer insulating film of the predetermined layer in the (n+2)th and subsequent layers; and at least the one dummy wire which is provided in at least the one interlayer insulating film which lies between the n-th layer and the predetermined layer in the (n+2)th and subsequent layers; and the other set of dummy wires is provided at an upper layer than the one set of dummy wires by at least one layer, with at least a lowermost dummy wire of the other set of the dummy wires provided at lower layer than an uppermost dummy wire of the one set of the dummy wires.

According to another aspect of the invention, there is provided a manufacturing method of a semiconductor device, comprising: providing a first insulating film, whose relative dielectric constant is at most a predetermined value, above a substrate; providing a second insulating film, whose relative dielectric constant is greater than the predetermined value, on a surface of the first insulating film; forming a recess for an effective wire, passing through the second insulating film and extending into the first insulating film, and also forming a recess for a dummy wire, passing through the second insulating film and extending into the first insulating film in a predetermined area spaced from a formed area of the recess for the effective wire; providing a conductive material on a surface of the second insulating film, inside the recess for the effective wire, and inside the recess for the dummy wire; providing an effective wire by leaving the conductive material inside the recess for the effective wire, and providing a dummy wire by leaving the conductive material inside the recess for the dummy wire in the predetermined area spaced tram the formed area of the effective wire, by polishing and removing the conductive material on the surface of the second insulating film; and performing a series of processes at least three times, comprising: providing a third insulating film to coat the effective wire and the dummy wire, after providing the effective wire and the dummy wire; providing the first and second insulating films on a surface of the third insulating film; forming the recess for the effective wire and the recess for the dummy wire passing through the third insulating film and the first and second insulating films on the third insulating film so as to be continued to the effective wire and the dummy wire; providing a conductive material on the surface of the second insulating film above the third insulating film and inside the recess for the effective wire and the recess for the dummy wire, which are formed over to the second insulating film from the third insulating film; and providing an effective wire continuing to the effective wire by leaving the conductive material inside the recess for the effective wire formed over to the second insulating film from the third insulating film, and providing a dummy wire continuing to the dummy wire by leaving the conductive material inside the recess for the dummy wire formed over to the second insulating film from the third insulating film in the predetermined area spaced from the formed area of the effective wire, by polishing and removing the conductive material on the surface of the second insulating film above the third insulating film, wherein: the effective wires actually function as wires in the semiconductor device; and the dummy wires do not actually function as the wires; wherein: at least four layers of interlayer insulating films comprising the first and second insulating films are provided above the substrate; the dummy wire is provided in the interlayer insulating film of an n-th layer (n is 1 or a greater integer), passing through the second insulating film and extending into the first insulating film; the dummy wire is provided in the interlayer insulating film of a predetermined layer in an (n+2)th and subsequent layers, passing through the second and first insulating films, and that part of the dummy wire which lies at the second insulating film extends along a surface of the interlayer insulating film of the predetermined layer and over the dummy wire provided in the interlayer insulating film of the n-th layer, for a longer distance than that part which lies at the first insulating film; and at least one dummy wire is provided in at least one interlayer insulating film which lies between the n-th layer and the predetermined layer in the (n+2)th and subsequent layers, passing through the second and first insulating films and continued the dummy wires provided in the interlayer insulating films of adjacent layers, and wherein: at least a pair of sets of the dummy wires is provided in the interlayer insulating films; the one set of the dummy wires comprises: the dummy wire which is provided in the interlayer insulating film of the n-th layer; the dummy wire which is provided in the interlayer insulating film of the predetermined layer in the (n+2)th and subsequent layers; and at least the one dummy wire which is provided in at least the one interlayer insulating film which lies between the n-th layer and the predetermined layer in the (n+2)th and subsequent layers; and the other set of the dummy wires is provided at an upper layer than the one set of the dummy wires by at least one layer, with at least a lowermost dummy wire of the other set of the dummy wires provided at lower layer than an uppermost dummy wire of the one set of the dummy wires.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIGS. 1A to 1D are process sectional views showing a manufacturing method of a semiconductor device according to a first embodiment;

FIGS. 2A to 2C are process sectional views showing the manufacturing method of the semiconductor device according to the first embodiment;

FIGS. 3A and 3B are a process sectional view and plan view showing the manufacturing method of the semiconductor device according to the first embodiment;

FIGS. 4A and 4B are a sectional view and plan view showing the vicinity of a dummy wire of the semiconductor device according to the first embodiment;

FIG. 5A is a sectional view showing peels of insulating films inside a layer or between layers according to a conventional technique, and FIG. 5B is a sectional view showing peels of insulating films inside a layer or between layers according to a comparative example performed by the inventors;

FIGS. 6A to 6M are plan views showing a dummy wire whose pattern shape in a plane view forming a line symmetry figure;

FIGS. 7A to 7H are plan views showing the dummy wire whose pattern shape in the plane view forming a point symmetry figure;

FIGS. 8A to 8C are plan views showing a dummy wire whose pattern shape in the plane view forming a pair in the line symmetry figure;

FIGS. 9A to 9C are plan views showing the dummy wire whose pattern shape in the plane view forming the pair in the point symmetry figure;

FIG. 10 is a sectional view showing the vicinity of the dummy wire of the semiconductor device according to a second embodiment;

FIG. 11 is a sectional view showing the vicinity of the dummy wire of the semiconductor device according to a third embodiment;

FIG. 12 is a sectional view showing the vicinity of the dummy wire of the semiconductor device according to a fourth embodiment;

FIG. 13 is a sectional view showing the vicinity of the dummy wire of the semiconductor device according to a fifth embodiment; and

FIG. 14 is a sectional view showing the vicinity of the dummy wire of the semiconductor device according to a sixth embodiment.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will be described hereinafter with reference to the drawings.

FIRST EMBODIMENT

First, a first embodiment will be described. FIGS. 1A to 1D and FIGS. 2A to 2C are process sectional views showing a manufacturing method of a semiconductor device according to the first embodiment. FIGS. 3A and 3B are a process sectional view and plan view showing the manufacturing method of the semiconductor device according to the first embodiment. FIGS. 4A and 4B are a sectional view and plan view showing the vicinity of a dummy wire of the semiconductor device according to the first embodiment. FIG. 5A is a sectional view showing peels of insulating films inside a layer or between layers according to a conventional technique, and FIG. 5B is a sectional view showing peels of insulating films inside a layer or between layers according to a comparative example performed by the inventors. FIGS. 6A to 6M, FIGS. 7A to 7H, FIGS. 8A to 8C, and FIGS. 9A to 9C are plan views showing concrete examples of the dummy wire formed in the first embodiment, which are classified by types of a pattern shape in the plane views.

In the first embodiment, the semiconductor device including a multi-layered wiring structure will be described. In the structure, a wire includes a so-called dual-damascene wiring structure in which a wire main body portion and a via plug (a contact plug) are integrally formed, and the wires are stacked in four layers. The manufacturing method of the semiconductor device including the multi-layered wiring structure will also be described. The dummy wire employed in the present embodiment is a dummy wire whose pattern shape seen from above the dummy wire forms line symmetry. Concretely, the dummy wire is used whose pattern shape in a plane view has a shape similar to that of alphabet C. The semiconductor device and manufacturing method of the present embodiment will hereinafter be described together along an order of manufacturing steps.

First, as shown in FIG. 1A, a first insulating film 2 whose relative dielectric constant is not more than a predetermined value is provided on a semiconductor substrate 1 on which element isolating areas and various semiconductor elements (not shown) are formed. Concretely, as a low-relative-dielectric-constant film (a low-k film) 2 which is the insulating film having a relative dielectric constant of 2.5 or less, for example, LKD-5109 manufactured by JSR Corporation is deposited on the surface of the substrate 1 by about 300 nm by spin coating. Subsequently, a second insulating film 3 whose relative dielectric constant is more than the predetermined value is provided on the low-relative-dielectric-constant film 2. Concretely, the SiC-film 3 which is the insulating film having a relative dielectric constant greater than 2.5 is deposited on the surface of the low-relative-dielectric-constant film 2 by about 60 nm, for example, by a CVD process. Accordingly, an interlayer insulating film 4 of a first layer including the low-relative-dielectric-constant film 2 and SiC-film 3 is formed on the semiconductor substrate 1.

It is to be noted that, in the present embodiment, the same LKD-5109 manufactured by JSR Corporation as the low-relative-dielectric-constant film 2 of the first layer is assumed to be used in the low-relative-dielectric-constant film 2 of each of second to fourth layers described later. Similarly, it is assumed that the same SiC-film 3 as the insulating film 3 of the first layer is used in the insulating film 3 of each of the second to fourth layers.

Next, as shown in FIG. 1B, a recess for a wire (a trench) 5 and a recess for a dummy wire (a trench) 6 are formed into the low-relative-dielectric-constant film 2 through the SiC-film 3. The recess 5 and the recess 6 are formed in each depth of about 200 nm, for example, by an RIE process. In the present embodiment, the recess 5 is formed in parallel with the recess wire 6. This also applies to the recess for the wire and the recess for the dummy wire of all the second to fourth layers described later. That is, in the present embodiment, an effective wire actually functions as the wire in the semiconductor device, is formed in parallel with the dummy wire which does not actually function as the wire in each layer. The effective wire will hereinafter be referred to simply as the wire in the following description.

It is to be noted that in FIGS. 1A to 1D, 2A to 2C, 3A and 3B, 4A and 4B, and 5A and 5B, an area denoted with A is an area in which the wire of the first layer is formed. In FIGS. 1A to 1D, 2A to 2C, 3A and 3B, 4A and 4B, and 5A and 5B, an area denoted with B is an area in which the dummy wire of the first layer is formed. In FIGS. 2A to 2C, 3A and 3B, 4A and 4B, and 5A and 5B, an area denoted with C is an area in which the wire of the second layer is formed.

Next, as shown in FIG. 1C, on the surface of the SiC-film 3, inside the recess 5, and inside the recess 6, a TaN-film 7 as a barrier metal film is formed in a film thickness of about 20 nm. Subsequently, conductive materials forming a wire 9 and dummy wire 10 described later are provided on the surface of the TaN-film 7. Concretely, a Cu-film 8 is provided on the surface of the TaN-film 7 in a film thickness of about 800 nm. These TaN-film 7 and Cu-film 8 are formed, for example, by a sputtering process and plating, respectively.

Next, as shown in FIG. 1D, the unnecessary TaN-film 7 and Cu-film 8 are removed. Concretely, a chemical mechanical polishing (CMP) process is used to polish and remove the TaN-film 7 and Cu-film 8 on the SiC-film 3. Accordingly, the unnecessary TaN-film 7 and Cu-film 8 outside the recess 5 and the recess 6 are removed from the surface of the SiC-film 3 to leave the TaN-film 7 and Cu-film 8 only inside the recess 5 and the recess 6. That is, the TaN-film 7 forming the barrier metal film and the Cu-film 8 forming the wire 9 and dummy wire 10 are buried only inside the recess 5 and the recess 6. As a result, the Cu-wire 9 and Cu-dummy wire 10 of the first layer are formed inside the low-relative-dielectric-constant film 2 through the SiC-film 3. It is to be noted that in the present embodiment the Cu-film 8 is used to form the wire and dummy wire of all the second to fourth layers described later in the same manner as the Cu-wire 9 and Cu-dummy wire 10 of the first layer. Similarly, the TaN-film 7 is used to form the barrier metal films of all of the second to fourth layers in the same manner as the barrier metal film 7 of the first layer.

Conditions for carrying out the CMP process in forming the Cu-wire 9 and Cu-dummy wire 10 of the first layer are as follows:

(First Polishing: 1st Polish)

Slurry: CMS7303/7304 (manufactured by JSR Corporation)

Slurry flow rate: 250 cc/min

Polishing pad (Pad): IC1000 (manufactured by RODEL Corporation)

Load: 300 gf/cm.sup.2

Number of rotations of carrier and table: 100 rpm for both

Polishing time: 2 min

(Second Polishing: 2nd Polish)

Slurry: CMS8301 (manufactured by JSR Corporation)

Slurry flow rate: 200 cc/min

Polishing pad (Pad): IC1000 (manufactured by RODEL Corporation)

Load: 300 gf/cm.sup.2

Number of rotations of carrier and table: 100 rpm for both

Polishing time: 1 min

In this manner, the CMP process of the present embodiment is carried out in two stages. These conditions for carrying out the CMP process are the same as those in forming the Cu-wires and Cu-dummy wires of the second to fourth layers. The first polishing (1st Polish) is performed mainly to polish and remove the Cu-film 8. The second polishing (2nd Polish) is performed mainly to polish and remove the TaN-film 7.

Here, when the Cu-wire 9 of the first layer is formed by the CMP process, the Cu-dummy wire 10 of the present embodiment is also formed in some case, and any dummy wire is not formed in the other case. A difference between the cases will be described. According to experiments conducted by the present inventors, when the Cu-dummy wire 10 is not formed, as shown in FIG. 5A, during the first polishing, a film peel was generated at an interface between the low-relative-dielectric-constant film 2 and SiC-film 3. Additionally, in the present embodiment in which the Cu-dummy wire 10 is formed, as shown in FIG. 1D, even when not only the first polishing but also the second polishing end, the film peel was hardly generated in the interface between the low-relative-dielectric-constant film 2 and SiC-film 3. This can be described as follows.

When the Cu-dummy wire 10 is formed into the low-relative-dielectric-constant film 2 from the SiC-film 3, the Cu-dummy wire 10 indirectly contacts the SiC-film 3 via the TaN-film 7. Moreover, the Cu-dummy wire 10 indirectly contacts the low-relative-dielectric-constant film 2 via the TaN-film 7. The Cu-dummy wire 10, TaN-film 7, and SiC-film 3 are formed of different types of materials. Furthermore, Cu, TaN, and SiC have properties of adhering to one another. Similarly, the Cu-dummy wire 10, TaN-film 7, and low-relative-dielectric-constant film 2 are formed of different types of materials. Furthermore, Cu, TaN, and the material of the low-relative-dielectric-constant film 2 have properties of adhering to one another. Therefore, the SiC-film 3 is substantially connected to the low-relative-dielectric-constant film 2 via the Cu-dummy wire 10 and TaN-film 7. Accordingly, the adhesion at the interface between the SiC-film 3 and low-relative-dielectric-constant film 2 is enhanced to a size that can bear a physical load of CMP. That is, the durability of the interlayer insulating film 4 against the mechanical stress in the CMP process is enhanced in forming the Cu-wire 9 and Cu-dummy wire 10 of the first layer. Accordingly, the film peels in the layer are reduced.

According to the experiments conducted by the present inventors, it has been confirmed that the adhesion of the Cu-dummy wire 10 to SiC-film 3 increases with an increase in contact area. It has similarly been confirmed that the adhesion of the Cu-dummy wire 10 to the low-relative-dielectric-constant film 2 strengthens with the increase of the contact area.

It is to be noted that the SiC-film 3 is deposited on the low-relative-dielectric-constant film 2 mainly for the following two reasons. One reason is that to prevent the low-relative-dielectric-constant film 2 from directly receiving any mechanical stress of the CMP process (CMP stress). The other reason is that the low-relative-dielectric-constant film 2 is inhibited from absorbing water. In this manner, the SiC-film 3 is provided to inhibit the quality of the low-relative-dielectric-constant film 2 from deteriorating. Therefore, when the low-relative-dielectric-constant film 2 is used to constitute the interlayer insulating film 4, it is hard to peel the SiC-film 3 from the surface of the low-relative-dielectric-constant film 2.

It is to be noted that although not shown, the dummy wire different from that of the first embodiment is formed. Even in this case, the present inventors have confirmed that the film peel does not occur at least in the CMP process of the first layer.

Next, as shown in FIG. 2A, to prevent the Cu-wire 9 and Cu-dummy wire 10 from being oxidized and diffused, a third insulating film 11 is provided to coat the Cu-wire 9 and Cu-dummy wire 10 and to prevent the first layer from being oxidized and diffused. Concretely, the SiC-film 11 is deposited in a film thickness of about 50 nm on the surfaces of the Cu-wire 9, Cu-dummy wire 10, and SiC-film 3, for example, by a CVD process. Subsequently, the low-relative-dielectric-constant film 2 and SiC-film 3 of a second layer are provided. Accordingly, the interlayer insulating film 4 of 5 the second layer is formed. Concretely, the low-relative-dielectric-constant film 2 of the second layer is deposited in about 600 nm on the surface of the SiC-film 11, for example, by spin coat. Subsequently, the SiC-film 3 of the second layer is deposited in about 60 nm on the surface of the low-relative-dielectric-constant film 2 of the second layer, for example, by the CVD process. Accordingly, the interlayer insulating film 4 of the second layer including the low-relative-dielectric-constant film 2 and SiC-film 3 is formed on the SiC-film 11.

Next, as shown in FIG. 2B, a recess for a wire 12 and a recess for a dummy wire 13 are formed into the SiC-film 11 of the first layer from the SiC-film 3 and low-relative-dielectric-constant film 2 of the second layer. As described above, even in the second layer, the recess 12 is formed in parallel with the recess 13. That is, a wire (an effective wire) 16 of the second layer is formed in parallel with a dummy wire 17 of the second layer. In this second layer, the Cu-wire 16 is formed in a so-called dual-damascene wiring structure in which a wire main body portion 19 is formed integrally with a contact plug (a via plug) 18. Therefore, the recess 12 of the second layer is also formed in a two-stages structure whose upper part includes a recess for the wire main body portion 15 and whose lower part includes a recess for the contact plug (a recess for the via plug) 14. Moreover, the recess 15 is formed integrally with the recess 14. The recess 12 is formed to pass through the SiC-film 3 and low-relative-dielectric-constant film 2 of the second layer and the SiC-film 11 of the first layer, so that a part of the upper surface of the Cu-wire 9 of the first layer is exposed.

Concretely, the recess 14 is formed in a depth of about 300 nm, for example, by an RIE process. The recess 15 is connected to the upper portion of the recess 14, and formed to open in the surface of the SiC-film 3 of the second layer. Concretely, for example, the recess 15 is formed in a depth of about 360 nm by the RIE process.

Moreover, the recess 13 is formed so as to expose the whole upper surface of the Cu-dummy wire 10 of the first layer. Therefore, the recess 13 is also formed to pass through the SiC-film 3 and low-relative-dielectric-constant film 2 of the second layer and the SiC-film 11 of the first layer. Concretely, the recess 13 is formed, for example, by the RIE process so that the depth is about 660 nm and width is substantially the same in size as that of the recess 6 of the first layer.

Next, as shown in FIG. 2C, the TaN-film 7 which is the barrier metal film of the second layer is provided in a film thickness of about 20 nm on the surface of the SiC-film 3, inside the recess 12, and inside the recess 13 in the second layer. Subsequently, Cu forming the Cu-wire 16 and Cu-dummy wire 17 is provided on the surface of the TaN-film 7 of the second layer. Concretely, the Cu-film 8 is provided on the surface of the TaN-film 7 of the second layer in a film thickness of about 800 nm. The TaN-film 7 and Cu-film 8 of the second layer are formed, for example, by the sputtering process and plating.

Next, as shown in FIG. 3A, the unnecessary TaN-film 7 and Cu-film 8 are removed. Concretely, the CMP process is used to polish and remove the TaN-film 7 and Cu-film 8 on the SiC-film 3 of the second layer. Accordingly, the unnecessary TaN-film 7 and Cu-film 8 outside the recess 12 and the recess 13 are removed. The TaN-film 7 and Cu-film 8 are left only inside the recess 12 and the recess 13. That is, the TaN-film 7 forming the barrier metal film and the Cu-film 8 forming the wire 16 and dummy wire 17 are buried only inside the recess 12 and the recess 13. As a result, the Cu-wire 16 and Cu-dummy wire 17 are formed substantially through the SiC-film 3 and low-relative-dielectric-constant film 2 of the second layer and the SiC-film 11 of the first layer. It is to be noted that FIG. 3A is a sectional view taken along a one-dot chain line X-X in FIG. 3B. FIG. 3B is a plan view showing a part of the multi-layered wiring structure in which the Cu-wire 16 and Cu-dummy wire 17 of the second layer are formed as seen from above the structure. In FIG. 3B, to facilitate understanding a relations between the Cu-wire 9 and Cu-dummy wire 10 of the first layer and between the Cu-wire 16 and Cu-dummy wire 17 of the second layer, formed positions, dimensions, and shapes of the respective wires 9, 10, 16, 17 are shown in an intentionally deviating manner.

Here, when the Cu-wire 16 of the second layer is formed by the CMP process, the Cu-dummy wire 17 of the present embodiment is also formed in some case, and a dummy wire 24 discontinued from the Cu-dummy wire 10 of the first layer is formed in the other case. A difference between the cases will be described. The dummy wire 24 discontinued from the Cu-dummy wire 10 of the first layer is, as shown in FIG. 5B, formed in a recess for a dummy wire 23 does not pass through the interlayer insulating film 4 of the second layer. According to the experiments conducted by the present inventors, when the discontinuous dummy wire 24 is formed, as shown in FIG. 5B, during the first polishing, the film peel was generated in the interface between the SiC-film 11 of the first layer and the low-relative-dielectric-constant film 2 of the second layer. That is, the film peel was generated between the first and second layers. Additionally, in the present embodiment in which the Cu-dummy wire 17 is formed, as shown in FIG. 3A, even when not only the first polishing but also the second polishing ends, the film peel was hardly generated in and between the layers. This can be described as follows.

When the Cu-dummy wire 17 is formed into the SiC-film 11 of the first layer from the SiC-film 3 of the second layer, the SiC-film 3 and low-relative-dielectric-constant film 2 of the second layer and the SiC-film 11 of the first layer indirectly contact the Cu-dummy wire 17 via the TaN-film 7. Accordingly, in the same manner as in a case in which the Cu-dummy wire 10 of the first layer is formed, the SiC-film 3 of the second layer, the low-relative-dielectric-constant film 2 of the second layer, and the SiC-film 11 of the first layer are substantially connected to one another via the Cu-dummy wire 17 and TaN-film 7. As a result, the adhesions at the interfaces of the SiC-film 3 of the second layer, the low-relative-dielectric-constant film 2 of the second layer, and the SiC-film 11 of the first layer are enhanced to the sizes that can bear the physical load of CMP. That is, the durability of the interlayer insulating film 4 of the second layer and the SiC-film 11 of the first layer is enhanced with respect to the mechanical stress in the CMP process, and the film peels among the respective insulating films 3, 2, 11 are reduced.

Moreover, as shown in FIG. 3A, the Cu-dummy wire 17 of the second layer continues to the Cu-dummy wire 10 of the first layer in a stacking direction via the TaN-film 7 of the second layer. The Cu-dummy wire 17 of the second layer and the Cu-dummy wire 10 of the first layer are formed of Cu, and indirectly contact each other via the TaN-film 7 containing a metal element Ta as a main component. Therefore, the adhesion of the Cu-dummy wire 17 of the second layer to the Cu-dummy wire 10 of the first layer has a size that can sufficiently bear the physical load of CMP. The SiC-film 11 of the first layer is substantially connected to the SiC-film 3 of the first layer via the Cu-dummy wire 17 and TaN-film 7 of the second layer and the Cu-dummy wire 10 of the first layer. Furthermore, since the SiC-film 11 of the first layer is formed of the same material as that of the SiC-film 3 of the first layer. Therefore, the adhesions of the respective SiC-films 3, 11 at the interface are of the sizes that can sufficiently bear the physical load of CMP. As a result, the adhesions at the interfaces of the low-relative-dielectric-constant film 2 of the second layer, the SiC-film 11 of the first layer, and the SiC-film 3 of the first layer are enhanced to the sizes that can bear the physical load of CMP. That is, the durability of the interlayer insulating film 4 of the second layer and the SiC-film 11 of the first layer is enhanced with respect to the mechanical stress in the CMP process in forming the Cu-wire 16 and Cu-dummy wire 17 of the second layer. Accordingly, the film peels between the first and second layers are reduced.

In this manner, the Cu-dummy wire 17 of the second layer formed to continue to the Cu-dummy wire 10 of the first layer enhances the durability of the SiC-film 11 of the first layer, the low-relative-dielectric-constant film 2 of the second layer, and the SiC-film 3 of the second layer with respect to the CMP. As a result, not only the film peel in the second layer but also the film peel between the first layer and the second layer are reduced.

According to the experiments conducted by the present inventors, it has been confirmed that the adhesions of the Cu-dummy wire 17 of the second layer to the respective insulating films 2, 3, 11 increase with the increase in contact area in the same manner as in the Cu-dummy wire 10 of the first layer. It has also been confirmed that the adhesion of the Cu-dummy wire 17 of the second layer to the Cu-dummy wire 10 of the first layer strengthens with the increase of the contact area via the TaN-films 7 of these layers. Furthermore, it has been confirmed that the adhesion of the SiC-film 11 of the first layer to the SiC-film 3 of the first layer also strengthens with the increase of the contact area of the Cu-dummy wire 17 of the second layer with the Cu-dummy wire 10 of the first layer via the TaN-films 7.

Thereafter, a step similar to the step of forming the Cu-wire 16 and Cu-dummy wire 17 of the second layer as described above is repeated twice. Accordingly, the Cu-wire 16 and Cu-dummy wire 17 of the third layer, and the Cu-wire 16 and Cu-dummy wire 17 of the fourth layer are formed. After forming the Cu-wire 16 and Cu-dummy wire 17 of the fourth layer, the SiC-film 11 of the fourth layer is provided on the surfaces of the SiC-film 3, Cu-wire 16, and Cu-dummy wire 17 of the fourth layer. Accordingly, as shown in FIG. 4A, a desired semiconductor device 20 is obtained. That is, the semiconductor device 20 of the present embodiment including the multi-layered wiring structure of four layers is obtained.

Next, the pattern shape in the plane view of the dummy wire, and the forming area of the dummy wire according to the present embodiment will be described. First, the pattern shape in the plane view of the dummy wire will be described. FIGS. 6A to 6M, 7A to 7H, 8A to 8C, and 9A to 9C show a plurality of examples of the pattern shapes in the plane views of the dummy wires. FIGS. 6A to 6M show examples of dummy patterns whose pattern shapes in the plane views of the dummy wires are line symmetry figures. In the semiconductor device 20, as shown in FIG. 6A, the dummy pattern having a shape similar to alphabet C in the plane view was used. FIGS. 7A to 7H show examples of the dummy patterns whose pattern shapes in the plane views of the dummy wires are point symmetry figures. FIGS. 8A to 8C show examples of the dummy patterns whose pattern shapes in the plane views of the dummy wires are line symmetry figures which are a pair of two patterns. Furthermore, FIGS. 9A to 9C show examples of the dummy patterns whose pattern shapes in the plane views of the dummy wires are point symmetry figures which are a pair of two patterns.

In this manner, the dummy wire for use in the present embodiment is formed such that the pattern shape in the plane view of a single unit is formed in a nonlinear shape. For some of the dummy wires can be used in the present embodiment, the pattern shape in the plane view of the single unit is formed in a shape indicating at least one of a figure, character, and numeral. The dummy wires having these pattern shapes are simple in configuration, can therefore easily be formed, and can easily bear large stresses (external forces) such as the mechanical stress by CMP.

In the present embodiment, the dummy pattern having the shape forming the line symmetry or point symmetry as the single unit or the pair as described above is used to form the dummy wire. Accordingly, as compared with a case in which the dummy pattern having an asymmetrical shape is used to form the dummy wire, a drag (bearing force) can be enhanced with respect to the CMP stress generated i