Title: Memory circuit apparatus
Abstract: A memory circuit device comprising a plurality of memory cells connected to a plurality of bit lines and word lines, an access circuit connected to the plurality of bit lines and word lines to select predetermined memory cells from the plurality of memory cells in response to an address signal, a precharge circuit which precharges the bit lines connected to the memory cells selected by the access circuit at the time of a read mode, a common source line connected to a plurality of selected memory cells selected by the access circuit, a source line potential control circuit to connect the common source line to a ground node at a predetermined timing, and a discharge circuit which discharges the bit lines connected to non-selected memory cells other than the selected memory cells.
Patent Number: 6,950,360 Issued on 09/27/2005 to Nishida, et al.
| Inventors:
|
Nishida; Yukihiro (Yokohama, JP);
Oikawa; Kiyoharu (Kawasaki, JP)
|
| Assignee:
|
Kabushiki Kaisha Toshiba (Tokyo, JP)
|
| Appl. No.:
|
700552 |
| Filed:
|
November 5, 2003 |
Foreign Application Priority Data
| Nov 06, 2002[JP] | 2002-322887 |
| Current U.S. Class: |
365/203; 365/185.25 |
| Intern'l Class: |
G11C 007/00 |
| Field of Search: |
365/203,185.25,185.11,185.23
|
References Cited [Referenced By]
U.S. Patent Documents
Primary Examiner: Nguyen; Tan T.
Attorney, Agent or Firm: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
Claims
1. A memory circuit apparatus comprising:
a plurality of memory cells connected to a plurality of bit lines and word lines;
an access circuit connected to the plurality of bit lines and word lines to select
predetermined memory cells from the plurality of memory cells in response to an
address signal;
a precharge circuit which precharges the bit lines connected to the memory cells
selected by the access circuit at the time of a read mode;
a common source line connected to a plurality of selected memory cells selected
by the access circuit;
a source line potential control circuit to connect the common source line to
a ground node at a predetermined timing; and
a discharge circuit which discharges the bit lines connected to non-selected
memory cells other than the selected memory cells.
2. The memory circuit apparatus according to claim 1, wherein the discharge circuit
is connected to the bit lines connected to the non-selected memory cells, and includes
a plurality of discharge transistors to fix these bit lines at a ground potential.
3. The memory circuit apparatus according to claim 2, wherein the discharge circuit
includes a decoder circuit which receives the address signal and a discharge permission
signal as inputs and which produces an on signal to be supplied to the discharge transistors.
4. The memory circuit apparatus according to claim 1, wherein one end of the
bit line is connected to a precharge power supply via the access circuit and precharge
circuit, and the other end of the bit line is connected to a ground node via the
memory cell and the source line potential control circuit.
5. The memory circuit apparatus according to claim 1, wherein the source line
potential control circuit includes a switching device controlled to turn on/off
by a source line potential control signal, and connects the source line to the
ground potential, when the switching device turns on.
6. The memory circuit apparatus according to claim 1, wherein the memory cell
comprises a nonvolatile memory cell constituting E
2PROM.
7. The memory circuit apparatus according to claim 1, wherein the memory cell
comprises a MOS transistor in which a source is selectively connected to a drain
via a metal wiring, and constitutes a NOR type MROM.
8. The memory circuit apparatus according to claim 1, wherein the memory cell
comprises a MOS transistor in which a source is selectively connected to a drain
via a metal wiring, and constitutes a NAND type MROM.
9. The memory circuit apparatus according to claim 1, wherein the access circuit
includes a column decoder which selects a predetermined bit line by an input address
signal, and the discharge circuit supplies an off signal to a discharge transistor
connected to a predetermined bit line selected by the same input address signal
as that of the column decoder.
10. The memory circuit apparatus according to claim 9, wherein the discharge
circuit includes a decode circuit which produces the same decoded output as that
of the column decoder, and an inverter which reverses a polarity of the output
of the decode circuit.
11. The memory circuit apparatus according to claim 1, wherein the plurality
of memory cells are grouped/divided in a plurality of memory blocks, and the memory
cells in each block are further grouped/divided into a plurality of words.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior
Japanese Patent Application No. 2002-322887, filed on Nov. 6, 2002, the entire
contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory circuit apparatus, particularly to
a memory circuit apparatus including a memory cell array in which a discharge current
flows through a common source line from precharged bit lines via selected memory
cells at the time of read.
2. Description of the Related Art
A conventional non-volatile memory device described in U.S. Pat. No. 5,453,955,
for example, includes read charging transistors for setting bit lines at a predetermined
read potential to perform a data read operation, and read discharging transistors
for setting non-selected bit lines at the ground potential during the read operation.
A similar non-volatile memory device also described in U.S. Pat. No. 6,195,297.
In a data read operation of the non-volatile memory device, bit lines are first
precharged and are subsequently set in a floating state, and then data items are
read through the bit lines. When many selected cells are on-cells, many charges
on the corresponding bit lines are discharged, so that a ground line should be
designed to have a big capacity. This is a problem to be solved when a large-scale
integration of a memory circuit apparatus is demanded.
BRIEF SUMMARY OF THE INVENTION
According to one aspect of the present invention, there is provided a memory
circuit apparatus comprising a plurality of memory cells connected to a plurality
of bit lines and word lines; an access circuit connected to the plurality of bit
lines and word lines to select predetermined memory cells from the plurality of
memory cells in response to an address signal; a precharge circuit which precharges
the bit lines connected to the memory cells selected by the access circuit at the
time of a read mode; a common source line connected to a plurality of selected
memory cells selected by the access circuit; a source line potential control circuit
to connect the common source line to a ground node at a predetermined timing; and
a discharge circuit which discharges the bit lines connected to non-selected memory
cells other than the selected memory cells.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
FIG. 1 is a block diagram showing a constitution of a proposed memory circuit apparatus;
FIGS. 2A to 2R are timing charts showing an operation of the memory
circuit apparatus shown in FIG. 1;
FIG. 3 is an equivalent circuit diagram at the time of the read of the memory
cells all in the on-state after 16 bit lines are precharged in the memory circuit
apparatus shown in FIG. 1;
FIG. 4 is a block diagram showing a constitution of a read circuit section of
a memory circuit apparatus according to one embodiment of the present invention;
FIG. 5 is a block diagram showing a constitution example of a control circuit
shown in FIG. 4;
FIG. 6 is a block diagram showing a constitution example of a precharge control
circuit shown in FIG. 4;
FIG. 7 is a block diagram showing a constitution example of a first column decoder
shown in FIG. 4;
FIG. 8 is a block diagram showing a constitution example of a second column
decoder shown in FIG. 4;
FIG. 9 is a block diagram showing a constitution example of a row decoder shown
in FIG. 4;
FIG. 10 is a block diagram showing a constitution example of a reset circuit
shown in FIG. 4;
FIG. 11 is a block diagram showing a constitution example of the control circuit
shown in FIG. 4;
FIG. 12 is a block diagram showing a constitution example of a sense circuit
shown in FIG. 4;
FIG. 13 is a block diagram showing a constitution example of a reference voltage
generation circuit in the sense circuit shown in FIG. 12;
FIG. 14 is a block diagram showing a constitution example of a circuit of a
sense amplifier in the sense circuit shown in FIG. 12;
FIG. 15 is a block diagram showing a circuit constitution example of a flip
flop in the sense circuit shown in FIG. 12;
FIGS. 16A to 16U are timing charts showing an operation of an embodiment
of the memory circuit apparatus of the present invention shown in FIGS. 4 to 15;
FIG. 17 is an equivalent circuit diagram at the time of the read of memory cells
all in an on-state after 16 bit lines are precharged in the embodiment of FIG. 4;
FIG. 18 is a block diagram showing a circuit constitution of a part of the memory
circuit apparatus including an NOR type memory cell according to another embodiment
of the present invention;
FIG. 19 is a block diagram showing a circuit constitution example of the row
decoder shown in FIG. 18;
FIG. 20 is a block diagram showing a circuit constitution of a part of the memory
circuit apparatus including a NAND type memory cell according to another embodiment
of the present invention;
FIGS. 21A, 21B are circuit diagrams showing a constitution of the NAND
type memory cell shown in FIG. 20; and
FIG. 22 is a block diagram showing a circuit constitution example of the row
decoder shown in FIG. 20.
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will hereinafter be described with
reference to the drawings.
FIG. 1 shows a memory circuit apparatus including a constitution in which a
discharge current flows through a common source line from precharged bit lines
via selected memory cells at the time of read.
This memory circuit apparatus is a FLASH_E
2PROM (electrically erasable
and programmable ROM) of a clock synchronous system. It is to be noted that this
circuit apparatus shows only a constitution concerning read, and a circuit concerning
a write/erase operation is omitted for the sake of simplicity.
FIGS. 2A to
2R show timing charts showing a read operation of this FLASH_E
2PROM
circuit shown in FIG. 1, and FIG. 3 shows an equivalent circuit diagram at the
time of all-on-cell read after all bit lines are precharged.
In FIG. 1, it is assumed that 512 nonvolatile memory cells including memory cells
CEL
0 to CEL
15 connected to a word line WLn-
1 selected by a
row decoder DRP which decodes an address signal (not shown) are all memory cells
having an off-state (data "0") and that 512 memory cells including memory cells
CEL
0X to CEL
15X connected to a word line WLn are all in an on-state
(data "1"). It is also assumed that first the word line WLn-
1 is selected
by an address signal and next the word line WLn is selected. That is, since all
the first selected 16 memory cells CEL
0 to CEL
15 are in the off-state,
potentials of bit lines b
0 to b
15 connected to these memory cells
maintain a precharge state even after a read operation is performed. Similarly,
all the bit lines selected by the word line WLn-
1 are in the precharged
state. In this state, since the memory cells CEL
0X to CEL
15X to be
read next are all in the on-state, all the precharged bit lines b
0 to b
15
are discharged at the time of the read. At this time, 512 bit lines are similarly discharged.
The time of an operation mode in this case will be described in more detail.
In FIG. 1, prior to the read of the memory cells CEL
0 to CEL
15
disposed
in one memory block, a transistor T
1 turns on by a precharge signal PRCV
from a control circuit C
1P, and power is supplied to an input terminal IN
of a sense circuit SP and also to a transistor T
2 for power saving from
a VDD power supply which is a precharge power supply.
This transistor T
2 turns on by a bias signal BIAS from a bias generation
circuit CPP, and selector transistors T
30 to T
33 in this memory block
B
15 are selectively turned on by column decode signals SR
0 to SR
3
from a first column decoder DC
1P. It is to be noted that this bias signal
BIAS is supplied to all memory blocks B
0 to B
15, and the blocks are
simultaneously selected by the column decode signals SR
0 to SR
3 from
the first column decoder DC
1P.
The transistor T
30 is connected to eight bit lines b
0 to b
7
via eight transistors T
40 to T
47 selected by decode signals S
0
to S
7 from a second column decoder DC
2P. Therefore, when the transistors
T
40 to T
47 are selectively turned on, eight bit lines b
0 to
b
7 are successively precharged by the transistor T
30. Bit lines b
8
to b
31 in the same block B
15 are also selectively precharged via
the transistors T
31 to T
33 and transistors T
48 to T
55.
Also with respect to the remaining blocks B
0 to B
14, the respective
bit lines are similarly selectively precharged. That is, there are 32 bit lines
per block, and 512 bit lines are successively precharged in 16 blocks in total.
An operation of the read circuit shown in FIG. 1 will hereinafter be described
with reference to FIGS. 2A to
2R and FIG.
3.
In the time charts of FIGS. 2A to
2R, the selected bit line is precharged
in a period in which a clock signal CLK of
2A has an H level. In a period
of an L level, with respect to this bit line, memory cell read data is verified
and sensed. Further in a period in which a system read control signal OE of FIG.
2P inputted into a control circuit C
1P has the H level, an output of the
sense circuit SP is outputted to a data bus DBUS via a buffer BP.
In the conventional circuit example of FIG. 1, as shown in FIG. 2B, the data
is
read in order of ROM address A
0→ROM address B
8. In this case,
all the memory cells are off-cells. Therefore, in one period of the clock CLK until
the read period of the ROM address A
0 ends, 512 bit lines of 32 bit lines×16
blocks per block are all precharged, and the state is maintained.
Thereafter, at the time of on-cell read in the ROM address B
8,
all the memory cells connected to 512 bit lines are the on-cells, and therefore
the precharged electric charges flow as a large current through a common source
line SL via all the memory cells. Therefore, mainly by a parasitic resistance between
the common source line SL and VSS ground, the level of the common source line SL
floats in the vicinity of the level of the bit line in the precharge state as shown
in FIG.
2K. In this case, assuming that a memory cell current in the on-state
per cell is 50 μA, a total on-cell current flowing through the common source
line SL indicates an excessively large current value of 25 mA.
An extreme example in which the read of all the on-cells follows the read of
all
the off-cells has been described above. However, when the read of a certain number
of on-cells is performed following the read of a certain number of off-cells, there
is similarly a large possibility that float phenomenon of the source line level
is caused by a large current flowing through the common source line SL via the on-cell.
At the time of the read of the on-cell, an IN potential of FIG. 2M should originally
drop to be not more than VREF potential of
2N. For the above-described reasons,
the IN potential substantially indicates a VDD level as shown by a broken line
in
2L. As a result, read data into the data bus DBUS which is to be "1"
turns to "0", and a problem that the data is erroneously read as off-cell data.
In this manner, for a memory-loaded memory control unit (MCU) of this conventional
example, a fatal problem of a system disadvantage has been caused by on-cell erroneous
read because of the level float of the common source line SL.
As one example, calculated values at the time of the SL level float in an equivalent
circuit shown in FIG. 1 are indicated.
Precharge potential Vbit of the bit line=1.0 V
Resistance value RCL
8 of one on-cell=20 kΩ
Synthesized resistance value RCLall of 512 on-cells=39 Ω
Parasitic resistance RSLA between point A
2 and SL and VSS=300 Ω
Potential of point A
2=(RSLA/(RCLall+RSLA))×Vbit=0.88 V
In this manner, the potential of the point A
2 should originally be VSS,
but the potential rises to 0.88 V, and there is a problem that this causes the
erroneous read.
It is to be noted that a channel width W of the transistor for use in an SL control
circuit C
2P is considered to be increased in order to reduce the parasitic
resistance RSLA, but this has limitation. Moreover, because of macro size restriction,
in design of layout, it is remarkably difficult reduce the parasitic resistance
between the SL line and VSS.
FIG. 4 is a diagram showing one example of a FLASH-E
2PROM circuit
constitution according to one embodiment of a memory circuit apparatus of the present
invention. In FIG. 4, only a circuit part of a read system in the FLASH-E
2PROM
circuit of a clock synchronous system of the first embodiment is shown, and the
circuit of a write/erase system is omitted in order to avoid complicated description.
The FLASH-E
2PROM circuit of the embodiment shown in FIG. 4 comprising:
a control circuit C
1; a bias generation circuit CP for power saving; a first
column decoder DC
1 which is a selector control circuit for read; a second
column decoder DC
2 for a column selector for selecting a bit line; a row
decoder DR for selecting a memory cell; a reset circuit RS for controlling a potential
of the bit line; a control circuit C
2 of a common source line SL; and a
group of 16 memory blocks B
0 to B
15 forming a memory cell array.
Moreover, in FIG. 4, each memory block group comprises a set of 16 blocks
B
0 to B
15 each including 32 bit lines, but the number of blocks and
the number of bit lines are determined as required. This embodiment includes a
constitution in which 512×512 memory cells are divided into 16 blocks.
The constitution of the memory block B
15 as an example will be described.
To the control circuit C
1, a precharge control signal PRCVIN and system
read control signal OE of FIG. 16D having a polarity reverse to that of a clock
signal CLK of FIG. 16B are supplied. Based on these signals, the control circuit
C
1 outputs a read instruction signal CSRD and precharge signal PRCV. The
read instruction signal CSRD is supplied as an output instruction signal to a buffer
circuit B for data output of the memory block B
15, and is similarly supplied
also to data output buffer circuits similarly disposed in the other memory blocks
B
14 to B
0. The precharge signal PRCV is supplied as a precharge instruction
signal to a gate of a precharge transistor T
1 of the memory block B
15,
and is similarly supplied also to the corresponding precharge transistors of the
other memory blocks B
14 to B
0.
Further in the memory block B
15, a bias transistor T
2 is connected
in series to a VDD power supply which is a precharge power supply via the precharge
transistor T
1, and selector transistors for read T
30 to T
33
are connected in parallel with this bias transistor T
2.
A connection node between the transistors T
1, T
2 is connected to
a sense input terminal IN of a sense circuit S, the sense circuit S performs a
sense operation of an input signal based on a sense enable signal SEN shown in
FIG. 16E, and a sense output OUT is outputted to a data bus DBUS
15 via a
data output buffer circuit B. The other memory blocks B
14 to B
0 are
also similarly constituted.
A bias signal BIAS generated from the bias generation circuit CP is supplied
to
the gate of the bias transistor T
2 in response to a power save signal PSV,
and this transistor T
2 turns on. One bias transistor T
2 is disposed
in each of the memory blocks B
15 to B
0. When the power save signal
PSV is off, 16 bias transistors simultaneously turn on by this bias signal BIAS,
and are connected to the VDD power supply.
The bias transistor T
2 is connected in common to four selector transistors
T
30 to T
33 in the memory block B
15. Additionally, here a transistor
T
32 is omitted. Selection signals SR
0 to SR
3 from the first
column decoder DC
1 are supplied to the gates of these transistors T
30
to
33 to obtain an on-state. Address signals A
2, A
3 are supplied
to the first column decoder DC
1 together with a read control signal RD,
and the decoder is selectively brought into the on-state in accordance with contents
of the address signals A
2, A
3.
These selector transistors T
30 to T
33 are similarly disposed
in the other memory blocks B
14 to B
0, and 16 transistors are successively
brought into the on-state in the whole block in accordance with a combination of
the address signals A
2, A
3 by the selection signals SR
0 to
SR
3 from the first column decoder DC
1.
Eight column selector transistors T
400 to T
407 are connected
in parallel with the selector transistor T
30, and eight column selector
transistors T
408 to T
415 are similarly connected to the selector
transistor T
31. Similarly, eight column selector transistors are also connected
to each of the selector transistors T
32, T
33. In this manner, in
this memory block B
15, eight column selector transistors are connected to
the VDD power supply at once by each of four selector transistors T
30 to T
33.
Similarly in the other memory blocks B
14 to B
0, four selector
transistors are successively turned on by output signals SR
0 to SR
3
of the first column decoder DC
1, and accordingly eight of 32 column selector
transistors are successively connected to the VDD power supply.
In the memory block B
15, eight selection signals S
0 to S
7
are supplied to the gates of the column selector transistors T
400 to T
407
connected to the selector transistor T
30 from the second column decoder
DC
2 which receives three bits of address signals A
4 to A
6
to operate, and the transistors are successively brought into the on-state. The
column selector transistors T
400 to T
407 are connected to the bit
lines b
0 to b
7, respectively.
Similarly, eight selection signals S
0 to S
7 from the second
column decoder DC
2 are supplied to the gates of the column selector transistors
T
408 to T
415 connected to the selector transistor T
31, and
the transistors are successively brought into the on-state. The column selector
transistors T
408 to T
415 are connected to bit lines B
8 to
B
15, respectively.
Similarly for the remaining selector transistors T
32, T
33,
eight column selector transistors are connected, eight selection signals S
0
to S
7 from the second column decoder DC
2 are supplied to the gates,
and the column selector transistors are successively brought into the on-state.
These column selector transistors are connected to eight bit lines, respectively.
Therefore, in the memory block B
15, four transistors including
the column selector transistors T
400, T
408 are turned on, for example,
by one selection signal S
0 of the second column decoder DC
2. However,
the corresponding selector transistors T
30 to T
33 are not simultaneously
turned on, and any one transistor is only turned on by the content of the address
signal. Therefore, in one block B
15, only one of four bit lines including
bit lines b
0, b
8 is connected to the VDD power supply and precharged.
This also applies to the other selection signals S
1 to S
7.
Similarly with respect to the other memory blocks B
14 to B
0,
one selector transistor per memory block is brought into the on-state by the outputs
SR
0 to SR
3 of the first column decoder DC
1. Therefore, one
bit line per memory block is precharged by the VDD power supply selected by the
second column decoder DC
2. Therefore, 16 bit lines in total are only precharged
simultaneously in the whole memory cell array.
In the block B
15, bit lines b
0 to b
15 are connected to the
common source line SL via a first group of memory cells CEL
1 to CEL
15,
and connected to the common source line SL via a second group of memory cells CEL
0X
to CEL
15X connected in parallel with the first group memory cells CEL
1
to CEL
15. Therefore, the memory cells CEL
0 and CEL
0X are connected
in parallel, that is, OR-connected, for example, to the bit line b
0.
Similarly with respect to the remaining 16 bit lines (not shown) in the
memory block B
15 or all the bit lines in the other memory blocks B
14
to B
0, two memory cells are OR-connected to one bit line. The memory cell
for use here is a nonvolatile memory cell including a MOS structure which includes
a floating gate and control gate.
In the memory block B
15, the respective control gates of the first group
of memory cells CEL
0 to CEL
15 are connected in common to a word line
WLn-
1 connected to the row decoder DR, and the control gates of the second
group of memory cells CEL
0X to CEL
15X are connected in common to
the word line WLn.
The row decoder DR receives a control signal CNT and the above-described precharge
signal PRCV together with 12 bits of address signals A
7 to A
18, and
sends an address designation signal of a row direction, that is, a memory cell
selection signal to a plurality of word lines. In this embodiment, the total number
of word lines is 512, but in FIG. 4, only two word lines WLn-
1, WLn are
shown. Similarly, a decode output of the row decoder DR is selectively sent to
512 word lines, and supplied to the memory blocks B
15 to B
0.
In the memory block B
15, the bit lines b
0 to b
7 are connected
to a VSS power supply, that is, ground potential via discharge transistors TR
0
to TR
7, respectively. These discharge transistors TR
0 to TR
7
are set so as to turn on, when reset signals RST
0 to RST
7 from the
reset circuit RS are supplied. The reset circuit RS receives three bits of address
signals A
4 to A
6 and reset control signal RSTCNT to selectively output
the reset signals RST
0 to RST
7.
Similarly, bit lines b
8 to b
15 are connected to the VSS
power supply via discharge transistors TR
8 to TR
15. These discharge
transistors TR
8 to TR
15 are connected with respect to the discharge
transistors TR
0 to TR
7, respectively, so as to turn on by the reset
signals RST
0 to RST
7. For example, the discharge transistors TR
0,
TR
8 simultaneously turn on by the reset signal RST
0. However, as
described later, the bit line selector transistor selected by the second column
decoder DC
2 and the discharge transistor connected to the same bit line
are constituted so as to mutually reverse on/off operations. For example, the bit
line b
0 is selected, when the selector transistor T
400 turns on.
In this case, the discharge transistor TR
0 is controlled so as to turn off.
In the memory block B
15, 16 bit lines in total connected to two selector
transistors including the selector transistor T
33 are also controlled to
turn on/off by the reset signals RST
0 to RST
7 in the same manner
as in the bit lines b
0 to b
15. Therefore, for example, when the reset
signal RST
0 is outputted, four discharge transistors in total including
the discharge transistors TR
0, TR
8 are turned on, and the corresponding
four bit lines are connected to a VSS potential.
Therefore, in all the memory blocks B
15 to B
0, when one
reset signal, for example, the reset signal RST
0 is outputted, four discharge
transistors per memory block turn on. Therefore, 64 discharge transistors in total
turn on.
As described above, since one reset signal from the reset generation circuit
RS
corresponding to one selection signal from the second column decoder DC
2
turns off, the remaining seven reset signals in eight reset signals RST
0
to RST
7 turn on. Therefore, among 512 bit lines, all the bit lines excluding
64 bit lines are connected to the VSS potential.
However, as described above, among 64 bit lines connected to the discharge
transistor which turns off, only 16 bit lines are precharged at the time of the
read. This will be described later in detail.
The control signal CNT supplied to the row decoder DR is also supplied to the
source line potential control circuit C
2, and the control circuit C
2
connects the common source line SL to the power supply VSS or ground node in response
to the control signal CNT.
In this embodiment, 32 discharge transistors are used with respect to 32 bit
lines
b
0 to b
32 in the memory block B
15, and the other memory blocks
B
14 to B
0 are also similarly constituted.
Here, with reference to FIGS. 5 to
12, constitution examples of the
control circuit C
1, precharge control circuit CP, first column decoder DC
1,
second column decoder DC
2, row decoder DR, reset circuit RS, source line
potential control circuit C
2, and sense circuit S shown in FIG. 4 will be
described in detail. As described above, the respective circuits output predetermined
signals, and these signals are inputted into the group of memory blocks B
15
to B
0. Here, as one example, the respective circuits will be associated
with the memory block B
15 and hereinafter described.
The control circuit C
1 shown in FIG. 5 includes buffers NV
1 and
NV
2. Via the buffer NV
1, the precharge control signal PRCVIN is outputted
as the precharge signal PRCV inputted into the gate of the precharge transistor
T
1, the input terminal of the sense circuit S, and the row decoder DR.
Moreover, the system read control signal OE is outputted as the read instruction
signal CSRD via the buffer NV
2. The read instruction signal CSRD is inputted
into the buffer circuit B for the data output in FIG.
4. That is, when the
system read control signal OE has a HIGH level, a signal DBUS
15 from an
output terminal of the buffer circuit B of the data output is outputted to a system
bus DBUS.
The bias generation circuit CP shown in FIG. 6 includes an inverter CNVL to which
the power save signal PSV is supplied, and P-type transistor TL
1 and N-type
transistor TL
4 to which the output signal of the inverter CNVL is supplied.
Furthermore, between an output node via which the bias signal BIAS is outputted
and the VSS power supply, two N-type transistors TL
2, TL
3 are connected
in series in a state in which drains and gates are connected to each other. One
end of the P-type transistor TL
1 is connected to the VDD power supply, and
the other end thereof is connected to the output node.
When the power save signal PSV in an H level state is inputted, the P-type transistor
TL
1 turns on and the N-type transistor TL
4 turns off by the output
of the inverter CNVL in an L level state. Accordingly, the bias signal BIAS is
outputted from the output node, the transistor T
2 of FIG. 4 turns on, and
the voltage from the VDD power supply for the precharge is supplied to the selector
transistors T
30 to T
33. When the power save signal PSV indicates
L, the output node indicates L, the transistor T
2 turns off, any precharge
voltage is not supplied, and a power save mode is achieved.
The first column decoder DC
1 shown in FIG. 7 includes a 2-input decoder
DEC
1 and four AND circuits
2AD
0 to
2AD
3 which
receive the output of this decoder DEC
1. The 2-input decoder DEC
1
decodes two bits of address signals A
2, A
3. The decoded signals and
read control signal RD are supplied to the AND circuits
2AD
0 to
2AD
3.
The selection signals SR
0 to SR
3 to be sent to the gates of the selector
transistors T
30 to T
33 for the read are outputted via the output
terminals of the AND circuits
2AD
0 to
2AD
3.
Furthermore, the second column decoder DC
2 shown in FIG. 8 includes
a 3-input decoder DEC
2 and eight level shifters LVSS
0 to LVSS
7
which convert the levels of the output signals of the decoder DEC
2.
When 3 bits of address signals A
4 to A
6 are inputted as the input
signal into the second column decoder DC
2, the signals are decoded by the
3-input decoder DEC
2, and eight outputs appear at output terminals "0" to
"7". The decoded address signals are inputted into the level shifters LVSS
0
to LVSS
7 as required. The level-shifted signals S
0 to S
7 are
outputted as signals to be sent to the gates of 32 column selector transistors
including column selector transistors T
400 to T
415 which select 32
bit lines including the bit lines b
0 to b
15 of FIG.
4.
Moreover, for example, as shown in FIG. 9, the row decoder DR includes
a main decoder MDEC, sub-decoder SDEC, and sub-decoder control circuit SDECCNT.
Nine bits of address signals A
10 to A
18 are supplied to the main
decoder MDEC and decoded, and three bits of address signals A
7 to A
9
are decoded by the sub-decoder control circuit SDECCNT, respectively.
Furthermore, the precharge signal PRCV from the control circuit C
1
is supplied to the sub-decoder control circuit SDECCNT, and further the control
signal CNT is supplied in common to the main decoder MDEC and sub-decoder control
circuit SDECCNT. The control signal CNT controls whether or not to output the signals
from the main decoder MDEC and sub-decoder control circuit SDECCNT to the outside.
It is to be noted that a power voltage of a VSW level and that of a VBB level
are supplied to the power terminals of the main decoder MDEC, sub-decoder SDEC,
and sub-decoder control circuit SDECCNT. Here, the voltage of the VSW level has
a level slightly higher than the VDD level.
The main decoder MDEC decodes n signals. For example, 512 decoded signals MIn
are controlled by the control signal CNT and outputted to the sub-decoder SDEC.
Moreover, the address signals A
7 to A
9, the control signal
CNT, and the precharge signal PRCV which is the output signal of the control circuit
C
1 are inputted into the sub-decoder control circuit SDECCNT, and m, for
example, eight output signals BIm from the control circuit are decoded signals
of the address signals A
7 to A
9. Output states of the signals are
determined by the precharge signal PRCV and control signal CNT.
The output signals MIn of the main decoder MDEC and the output signals BIm of
the sub-decoder control circuit SDECCNT are inputted into the sub-decoder SDEC,
and word line selection signals WL
0 to WLn are outputted. The word line
selection signals WL
0 to WLn are outputted as the same number n of signals
as that of the decoded output signals MIn from the main decoder MDEC, for example,
512 signals from the sub-decoder SDEC. That is, the sub-decoder SDEC is a switch
circuit which selects and outputs the input signal BIm by the select signal MIn.
The word line selection signals WL
0 to WLn from the sub-decoder SDEC are
inputted into the gate of the memory cell. In the example of FIG. 4, the word line
selection signal WLn-
1 is supplied to the gates of 32 memory cells including
the memory cells CEL
0 to CEL
15 in the memory block B
15, and
the word line selection signal WLn is supplied to 32 memory cells including the
memory cells CEL
0X to CEL
15X. In the memory cell array, the word
line selection signal WLn-
1 is supplied to 512 memory cells in all the memory
blocks B
15 to B
0. The word line selection signal WLn is also supplied
to 512 memory cells.
For example, as shown in FIG. 10, the reset circuit RS shown in FIG. 4 includes:
a 3-input decoder DEC
3 into which three bits of address signals A
4
to A
6 are inputted; inverters RIV
0 to RIV
7 which reverse eight
decode outputs from the 3-input decoder DEC
3; and AND circuits RAD
0
to RAD
7 for obtaining AND outputs of the outputs of the inverters RIV
0
to RIV
7 and reset control signal RSTCNT. By the inverters RIV
0 to
RIV
7, the output reset signal from the reset generation circuit RS has a
polarity reverse to that of the column selection signal of the second column decoder DC
2.
That is, the decoded output signal from the 3-input decoder DEC
3 is inputted
into one input terminal of each of AND circuits RAD
0 to RAD
7 via
the predetermined inverters RIV
0 to RIV
7, respectively. The reset
control signal RSTCNT which is a discharge permission signal is inputted into the
other input terminal of each of the AND circuits RAD
0 to RAD
7. The
reset signals RST
0 to RST
7 outputted from the output terminals of
the AND circuits RAD
0 to RAD
7 are outputted as the signals to be
sent to the gates of 64 transistors among 512 discharge transistors including discharge
transistors TR
0 to TR
15 of the bit lines.
As shown in FIG. 11, the control circuit C
2 shown in FIG. 4 includes:
an
N channel transistor TNSL to whose gate the control signal CNT is supplied; and
a resistance RSL. A source of the transistor TNSL is connected to the power supply
VSS, and a drain is connected to the common source line SL of FIG. 4 via the resistance RSL.
In FIG. 11, when the control signal CNT has the H level, the N channel transistor
TNSL turns on, and the common source line SL is connected to the ground node or
the power supply VSS via the resistance RSL. Here, a channel section of the N channel
transistor TNSL is formed so as to obtain a W/L ratio, for example, of 500/0.7,
that is, to set W to be large to some degree. However, the W/L ratio is one example
of such a W/L ratio that any trouble is not caused in bringing the common source
line SL into the VSS level. In this embodiment, an amount of discharge current
of the bit line flowing into the common source line SL is small. Therefore, the
W/L ratio, that is, W does not have to have such a large value, and any value may
also be used within a range of the condition.
Thus, the channel width W of the source line discharge transistor TNSL is not
required to be large excessively. Further, since the parasitic resistance of the
source line SL is not required to be decreased largely, it is not necessary to
increase the source line width as well as the area of the contact size, thereby
enabling to prevent the macro-size of the memory circuit apparatus from being increased.
In other words, according to the present embodiment, it is possible to decrease
the size of the channel width of the source line discharge transistor TNSL and
the size of the source line width, thereby enabling to decrease the macro-size
of the memory circuit apparatus.
Further, according to the present embodiment, since it is possible to prevent
charges on a bit line connected to a selected nonvolatile memory cell at the read
mode from being remained, soft write operation to the floating gate of the selected
nonvolatile memory cell caused by the remaining charges can also be prevented.
Thus, when a selected memory cell is in an on-state, this on-state is not changed
to an off state due to the soft write operation, thereby providing a memory circuit
apparatus of high reliable.
Here, for example, a resistance value of the resistance RSL is set to 280 Ω,
and a resistance RON of the N channel transistor TNSL at the time of on-state is
set to 20 Ω. That is, a synthesized resistance of the resistance RSL and
the on-resistance RON of the transistor TNSL is 300 Ω. However, the synthesized
resistance value may be a certain resistance value to such an extent that the float
of the potential of the source line by the discharge current flowing through the
source line by the embodiment does not cause any read error, and does not have
to be necessarily set to 300 Ω.
As shown in FIG. 12, the sense circuit S shown in FIG. 4 includes: a sense amplifier
SA: a reference voltage generation circuit RG for supplying the reference voltage
VREF to the sense amplifier SA; and a flip flop circuit FF to which the output
signal of the sense amplifier SA is supplied.
As shown in FIG. 13, the precharge signal PRCV which is the output signal of
the
control circuit C
1 is inputted into an input terminal EN of the reference
voltage generation circuit RG, and the reference voltage VREF is outputted via
the output terminal OUT and supplied to the reference voltage terminal VREF of
the sense amplifier SA.
In addition to the reference voltage terminal VREF, the sense amplifier SA includes
input terminals VIN and EN. An input signal IN for data read from the bit line
described later is inputted into the input terminal VIN of the sense amplifier
SA. The sense enable signal SEN is inputted into the other input terminal EN. Output
terminals QN and Q of the sense amplifier SA are connected to set and reset input
terminals SN and RN of the flip flop circuit FF. The output signal OUT of the sense
circuit S is outputted via an output terminal Z of the flip flop circuit FF. The
output signal OUT is inputted into the buffer circuit B of the data output of FIG.
4.
Next, one example of the circuit arrangement of the reference voltage generation
circuit RG, sense amplifier SA, and flip flop circuit FF constituting the sense
circuit S will be described with reference to FIGS. 13 to
15.
The reference voltage generation circuit RG shown in FIG. 13 includes P channel
transistors TRP
1 to TRP
3 and N channel transistor TRN
1 connected
to one another in series between the power supply terminals VDD and VSS. The precharge
signal PRCV inputted into the input terminal EN of the reference voltage generation
circuit RG is supplied to the gates of the transistors TRP
1 and TRN
1,
and the reference voltage VREF is outputted to the output terminal OUT from the
connection node of the transistors TRP
1 and TRP
2. That is, in the
circuit of FIG. 13, when the precharge signal PRCV is off, that is, in the L level,
the positive reference voltage VREF is outputted via the output terminal OUT and
supplied to the sense amplifier SA.
As shown in FIG. 14, the sense amplifier SA includes P channel transistors TNP
1
to TNP
5 and N channel transistors TNN
1, TNN
2. The voltage
VREF which is the output from the reference voltage generation circuit RG is inputted
into the reference voltage input terminal VREF. The input signals IN and SEN are
inputted into the input terminals VIN and EN of the sense amplifier SA, respectively.
In FIG. 14, the sense enable signal SEN is inputted into the gates of the P channel
transistors TNP
3 to TNP
5 to control conduction/non-conduction of
the signals IN and VREF similarly inputted on a source side of the P channel transistors
TNP
4, TNP
5. That is, when the sense enable signal SEN has the L level,
these transistors TNP
3 to TNP
5 are turned on. The power voltages
VDD, VSS are supplied to the inverter constituted of the transistors TNP
1,
TNN
1 and that constituted of the transistors TNP
2, TNN
2. These
two inverters constitute a latch circuit.
When the transistor TNP
5 turns on, the flip flop FF is reset by output
Q from the sense amplifier SA, and the transistor TNP
2 turns off and the
transistor TNN
2 turns on by the reference voltage VREF. Accordingly, the
transistor TNP
1 turns on and the transistor TNN
1 turns off. Therefore,
this state is latched by these transistors TNP
1, TNP
2, TNN
1, TNN
2.
For example, when the read signal IN having the H level from the memory cell
is supplied to the input terminal VIN in this state, a QN signal having the H level
is sent to the flip flop FF to achieve a set state. Moreover, the transistor TNP
1
turns off, TNN
1 turns on, TNN
2 turns off, TNP
2 turns on, and
this state is latched. As a result, the signal OUT is supplied as the sense output
from the sense circuit S to the output buffer circuit B of FIG. 4 from the flip
flop circuit FF.
It is to be noted that, as shown in FIG. 15, the flip flop circuit FF includes
two NAND circuits NANDF
1 and NANDF
2. A reset input terminal RN is
connected to one input terminal of the NAND circuit NANDF
1, and a set input
terminal SN is connected to one input terminal of the NAND circuit NANDF
2.
As shown, the output of the NAND circuit NANDF
1 is supplied to the other
input terminal of the NAND circuit NANDF
2, and the output terminal of the
NAND circuit NANDF
2 is connected to an output terminal Z of the flip flop
circuit FF and also to the other input terminal of the other NAND circuit NANDF
1.
The output signal OUT from the output terminal Z is inputted into the input terminal
of the data output buffer circuit B.
Next, the operation of the memory circuit apparatus of FIG. 4 will be described
in detail with reference to time charts of FIGS. 16A to
16U. Here, it is
assumed that the word line WLn-
1 connected to the row decoder DR corresponds
to a ROM address A
0 and that all the 512 memory cells selected by the word
line WLn-
1 are off-cells ("0"). It is also assumed that the word line WLn
corresponds to a ROM address B
8 and that all the 512 memory cells selected
by the word line WLn are on-cells ("1"). A read mode will hereinafter be described
in a case where the read is performed in order of the ROM address A
0→ROM
address B
8 on this condition.
That is, there are 512 memory cells in total having the ROM address A
0
connected to the word line WLn-
1 in the memory cell array, and all these
memory cells are the off-cells. In the embodiment of the present invention shown
in FIG. 4, only the selector transistor T
30 turns on by an output SR
0
of the first column decoder DC
1 at the time of the ROM address A
0
in the memory block B
15, and only the column selector transistor T
400
turns on by the output of the second column decoder DC
2. Therefore, only
the bit line b
0 is an object of the precharge in the memory block B
15,
and only the memory cell CEL
0 is an object of the read.
Similarly in the blocks B
0 to B
14, only the memory cell corresponding
to the memory cell CEL
0 connected to the bit line corresponding to the bit
line b
0 of the memory block B
15 is the object of the read. That is,
in the ROM address A
0, one bit per memory block, that is, 16 bit lines connected
to the off-cell for 16 bits are selected in 16 memory blocks.
On the other hand, it is assumed that all the 512 memory cells of the ROM address
B
8 connected to the word line WLn are the on-cells. In the same manner as
in the off-cell selected by the word line WLn-
1, at the time of the on-cell
selection by the word line WLn, in this embodiment, the selector transistor T
31
is selected by the first column decoder DC
1 in the memory block B
15
by the ROM address B
8, and the transistor T
408 is selected by the
second column decoder DC
2. Therefore, only the memory cell CEL
8X
connected to the bit line b
8 is selected.
Similarly in the memory blocks B
0 to B
14, the memory cells
connected to the bit lines corresponding to the bit line b
8 are selected
one by one. That is, only 16 bit lines are precharged for 16 bits connected to
the selected memory cell having the on-cell state.
In this manner, the circuit operation will hereinafter be described with respect
to the read of the memory cells all in the off-state→memory cells all in
the on-state with reference to FIGS. 4 and 16A to
16U.
An operation for the read of the memory cell CEL
0 having the off-cell
state
in the ROM address A
0 will first be described. In this read mode, as shown
in FIG. 16A, the reset control signal RSTCNT supplied to the reset generation circuit
RS has the H level. In this state, one period between time t
1 and t
3
of the system clock CLK of FIG. 16B corresponds to a period of the read of the
ROM address A
0 designated by address signals A
18 to A
2 of
FIG.
16C. In this period, the address signals A
2 to A
18 shown
in FIG. 16C indicate a content required for the read of the memory cell CEL
0.
In the read mode, as predetermined signals, together with the reset control signal
RSTCNT of FIG. 16A, the read control signal RD shown in FIG. 16F is also constantly
set to the signal of the H level.
First, the precharge control signal PRCVIN shown in FIG. 16D which is a reverse
signal of the clock signal CLK is supplied to the control circuit C
1 of
FIG.
4. This precharge control signal PRCVIN is supplied as the precharge
signal PRCV to the row decoder DR via the buffer NV
1 of FIG.
5 and
also inputted to the gate of the precharge transistor T
1 at the L level.
Therefore, the precharge transistor T
1 is turned on in a period of time
t
1 to t
2 in which the precharge signal PRCV indicates the L level,
and the H level signal is supplied as the input IN of the sense circuit S. At this
time, the system read control signal OE supplied to the control circuit C
1
indicates the L level in the period of time t
1 to t
3 as shown in
FIG.
16S. Therefore, the read instruction signal CSRD also indicates the
L level as shown in FIG.
16T.
When the bias signal BIAS from the bias generation circuit CP is inputted into
the gate of the transistor T
2 at the H level in this state, the transistor
T
2 is turned on, and supplies the precharge voltage VDD to the selector
transistors T
30 to T
33. At this time, as shown in FIG. 16H, the signal
SR
0 outputted from the first column decoder DC
1 is inputted as the
H level into the gate of the selector transistor T
30 for the read, and the
signals SR
1 to SR
3 are inputted as the L level into the gates of
the selector transistors T
31 to T
33 for the read. Accordingly, only
the selector transistor T
30 for the read is brought into the turned on state.
On the other hand, as shown in FIG. 16G, the signal S
0 outputted from
the
second column decoder DC
2 is inputted as the H level into the gate of the
column selector transistor T
400, and the signals S
1 to S
7
are inputted as the L level into the gates of the column selector transistors T
401
to T
407. Accordingly, only the column selector transistor T
400 is
brought into the turned on state. As shown in FIGS. 16C,
16G, this column
selection signal S
0 indicates the H level for two periods of the system
clock CLK for the time t
1 to t
5, that is, in a read period of both
the ROM addresses A
0, B
8.
As described above, any of the precharge transistor T
1, selection transistor
T
2, and selector transistors T
30 and T
400 for the read is
brought into the turned on state. Accordingly, the precharge power supply VDD on
the drain side of the precharge transistor T
1 is connected to a desired
bit line b
0 via the transistors T
1, T
2, T
30, and T
400,
and this bit line b
0 is precharged at the VDD voltage. That is, the precharge
period of the bit line of the read of the ROM address A
0 corresponds to
the time t
1 to t
2 or time t
3 to t
4 of the clock signal
CLK indicating the H level as shown in FIG.
16B.
Here, in the memory block B
15, as shown in FIG. 16K, the reset signal
RST
0 outputted from the reset generation circuit RS indicates the L level
having the polarity reverse to that of the selection signal S
0, and therefore
four discharge transistors are off in the memory block B
15 including bit
line discharge transistors TR
0, TR
8 to which the reset signal RST
0
is supplied. Therefore, there is not any change of the potential in the bit line
connected to these discharge transistors, and the precharged potential is held
as it is.
On the other hand, output signals RST
1 to RST
7 having the H level
from the reset generation circuit RS are inputted into the gates of the bit line
discharge transistors other than four discharge transistors including the bit line
discharge transistors TR
0, TR
8. Therefore, all the discharge transistors
to which the reset signals having the H level are supplied are turned on, and all
the bit lines connected to these discharge transistors are fixed at the VSS potential.
This state is similar in 16 memory blocks B
15 to B
0. Therefore,
by the H level period by the selection of the ROM address A
0 in the word
line WLn-
1 in the time t
2 to t
3 in FIG. 16I, only 16 bit lines
including the bit line b
0 selected by the ROM address A
0 are precharged.
That is, all the 496 bit lines other than 16 bit lines are not precharged, or are
fixed at the VSS level.
For example, in the memory block B
15, 28 bit lines excluding four bit
lines including the bit lines b
0, b
8 are fixed at the VSS level.
Additionally, three bit lines other than the bit line b
0 selected in the
ROM address A
0 are not precharged at the time of the ROM address A
0.
Therefore, there is not any trouble even without any discharge operation.
Thereafter, when the clock signal CLK changes to the L level from the
H level at the time t
2, as shown in FIG. 16I, the signal of the H level
is inputted into 32 memory cells including the memory cells CEL
0 to CEL
15
from the word line WLn-
1.
Here, since the memory cell CEL
0 connected to the bit line b
0
precharged in the memory block B
15 has the off-state, and the discharge
transistor TR
0 also has the off-state, the bit line b
0 is held at
the H level in the precharged VDD level. At this time, all the selector transistors
T
401 to T
407 of the bit lines b
1 to b
7 connected to
the selector transistor T
30 have the off-state. Therefore, there is no fluctuation
in the H level inputted into the input terminal VIN of the sense circuit S.
When the sense enable signal SEN shown in FIG. 16E is similarly inputted into
the input terminal EN of the sense circuit S in this state, and only when the sense
enable signal SEN indicates the H level, the sense circuit S takes in the read
signal IN shown in FIG. 16P, and outputs the reverse signal OUT of the signal IN
toward the buffer circuit B from the output terminal Z. That is, in the period
of t
2 to t
3 in which the clock signal CLK indicates the L level,
the data of the memory cell read by the selection signal passed through the word
line WLn-
1 is verified by the reversing of the precharge control signal
PRCVIN (i.e., precharge signal PRCV), and the data is sensed in a timing adjusted
to that of the sense enable signal SEN. It is to be noted that as shown in FIG.
16Q, th
