Title: Memory device capable of stable data writing
Abstract: A memory device according to the present invention includes a memory cell array including a plurality of memory cells arranged therein, the memory cell array being divided into a plurality of regions each selectable independently of the others as an object for data writing, and further includes a plurality of current supply sections provided correspondingly to the plurality of regions, respectively. Each of the plurality of current supply sections, when a corresponding region of the plurality of regions is selected as an object for data writing, is activated to supply a data write current to the corresponding region and each of the plurality of regions includes a plurality of write select lines provided correspondingly to predetermined units of the plurality of memory cells. The plurality of write select lines are selectively supplied with the data write current from a corresponding one of the plurality of current supply sections.
Patent Number: 6,947,320 Issued on 09/20/2005 to Hidaka
| Inventors:
|
Hidaka; Hideto (Hyogo, JP)
|
| Assignee:
|
Renesas Technology Corp. (Tokyo, JP)
|
| Appl. No.:
|
045136 |
| Filed:
|
January 31, 2005 |
Foreign Application Priority Data
| Nov 27, 2002[JP] | 2002-344445 |
| Current U.S. Class: |
365/173; 365/189.09; 365/230.03 |
| Intern'l Class: |
G11C 011/15 |
| Field of Search: |
365/173,230.03,189.09
|
References Cited [Referenced By]
U.S. Patent Documents
| 5384730 | Jan., 1995 | Vinal.
| |
| 5689460 | Nov., 1997 | Ooishi.
| |
| 6212109 | Apr., 2001 | Proebsting.
| |
| 6314028 | Nov., 2001 | Kono.
| |
| 6462584 | Oct., 2002 | Proebsting.
| |
| 6462998 | Oct., 2002 | Proebsting.
| |
| 6795335 | Sep., 2004 | Hidaka.
| |
| 2004/0001353 | Jan., 2004 | Hidaka.
| |
| Foreign Patent Documents |
| 2002/-124079 | Apr., 2002 | JP.
| |
Other References
Scheuerlein, et al. "A 10ns Read and Write Non-Volatile Memory Array Using a
Magnetic Tunnel Junction and FET Switch in Each Cell" 2000 IEEE International Solid-State
Circuits Conference Digest of Technical Papers (2000) TA 7.2.
Durlam, et al. "Nonvolatile RAM Based on Magnetic Tunnel Junction Elements" 2000
IEEE International Solid-State Circuits Conference Digest of Technical Papers (2000)
TA 7.3.
Naji, et al. "A 256kb 3.0V 1T1MTJ Nonvolatile Magnetoresistive RAM" 2001 IEEE
International Solid-State Circuits Conference Digest of Technical Papers (Feb.
6, 2001) 7.6.
|
Primary Examiner: Phung; Anh
Assistant Examiner: Nguyen; Tuan T.
Attorney, Agent or Firm: McDermott Will & Emery LLP
Parent Case Text
RELATED APPLICATION
This application is a continuation of application Ser. No. 10/440,157 filed
May 19, 2003, now U.S. Pat. No. 6,898,114 issued on May 24, 2005.
Claims
1. A non-volatile memory device comprising:
a plurality of memory cells through each of which a pass current when data is
read flows at a value different according to a level of data written according
to an applied data write current;
a plurality of write select lines provided correspondingly to predetermined units
of said plurality of memory cells;
a first wire connected electrically to one end sides of said plurality of write
select lines;
a second wire, connected electrically to a first voltage, and connected electrically
to at least one of the other end sides of said plurality of write select lines
in data writing;
a current supply circuit, in said data writing, activated to connect said first
wire electrically to a second voltage and to thereby supply said data write current
to said first wire; and
a voltage setting circuit for, when said current supply circuit is in an inactive
state, connecting said first wire electrically to a third voltage different from
said second voltage, wherein
a difference between said first and third voltages is smaller than a difference
between said first and second voltages.
2. The non-volatile memory device according to claim 1, wherein said voltage
setting circuit, when power is turned on, connects said first wire electrically
to said third voltage till said current supply circuit is activated and, when said
current supply circuit enters an inactive state, disconnects said first wire electrically
from said third voltage.
3. The non-volatile memory device according to claim 1, wherein
said third voltage is almost equal to said first voltage in level.
4. A non-volatile memory device comprising:
a plurality of memory cells through each of which a pass current when data is
read flows at a value different according to a level of data written according
to an applied data write current;
a plurality of write select lines provided correspondingly to predetermined units
of said plurality of memory cells;
a first wire connected electrically to one end sides of said plurality of write
select lines;
a second wire, connected electrically to a first voltage, and connected electrically
to at least one of the other end sides of said plurality of write select lines
in data writing;
a current supply circuit, in said data writing, activated to connect said first
wire electrically to a second voltage and to thereby supply said data write current
to said first wire;
an address decode circuit for, in said data writing, selecting a write select
line to receive supply of said data write current from said plurality of write
select lines; and
a voltage setting circuit for connecting said first wire electrically to a third
voltage different from said second voltage during a predetermined period from the
start of data writing till said data write current is supplied into said write
select line selected by said address decode circuit, wherein
a difference between said first and third voltages is smaller than a difference
between said first and second voltages.
5. The non-volatile memory device according to claim 4, wherein
said predetermined period is determined according to a time required by said
address decode circuit for selection of said write select line.
6. The non-volatile memory device according to claim 4, wherein
said voltage setting circuit includes:
a dummy write select line designed and arranged in a similar way to the way that
said plurality of write select lines are designed and arranged; and
a switch connecting said third voltage electrically to said dummy write select
line during said predetermined period, and
said dummy write select line is connected electrically to said first wire.
7. The non-volatile memory device according to claim 4, wherein
each of said plurality of memory cells includes:
a first magnetic layer having a fixed magnetic direction;
a second magnetic layer magnetized in a direction corresponding to a magnetic
field generated by said data write current controlled according to a level of write
data; and
an insulating film formed between said first and second magnetic layers.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory device, and more particularly to a
nonvolatile memory device including a memory cell having a characteristic in that
a pass current at the time of data reading is changed in response to a level of
binary storage data.
2. Description of the Background Art
In recent years, attention has been focussed on an MRAM Magnetic Random Access
Memory) device as a non-volatile memory device in a new generation. An MRAM device
is a non-volatile memory device in which non-volatile data storage is performed
using a plurality of thin m magnetic elements formed in a semiconductor integrated
circuit and a random access is enabled to each of the thin film magnetic elements.
Especially, a thin film magnetic elements including a magnetic tunnel junction
(MTJ) has been used as a memory cell in recent years and thereby a drastic progress
in performance of an MRAM device has been achieved, which is disclosed in the following literature.
(Literature 1)
"A 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction
and FET Switch in each Cell" (USA), Roy Scheuerlein and 6 others, 2000 IEEE ISSCC
Digest of Technical Papers TA 7.2.
Since a memory cell having a magnetic tunnel junction therein (hereinafter,
also referred to as an "MTJ memory cell") can be constructed of one MTJ element
and one access element (e.g., a transistor), the memory cell is also advantageous
in high integration. An MTJ element has a magnetic layer capable of being magnetized
along a direction corresponding to an applied magnetic field, and an MTJ memory
cell performs data storage using a characteristic in that an electric resistance
(a junction resistance) in the MTJ element alters depending on a magnetic direction
of the magnetic layer. Whether or not a magnetic direction of the magnetic layer
alters is determined by a strength of the synthetic magnetic field of two magnetic
fields generated by data write currents flowing in a write digit line and a bit
line, respectively. Hereinafter, a write digit line and a bit line are also collectively
referred to as a write current line, and data write currents are also simply referred
to as a write current.
A necessity arises for detection of a difference in electric resistance corresponding
to a level of storage data in order to read the storage data in an MTJ memory cell.
To be concrete, data reading is performed based on a pass current through an MTJ
memory cell altering depending on an electric resistance (i.e., storage data).
In general, since data writing is performed according to supply of a write current
in an MRAM device, a supply amount of the write current is necessary to be precisely
adjusted. Therefore, the following problems have been arisen in data write operation
on an MTJ memory cell.
(1) A path length of wiring to a MTJ memory cell from a current source supplying
a current for writing data to the selected MTJ memory cell is different according
to a location of the MTJ memory cell (hereinafter, also referred to as a selected
memory cell). Therefore, wiring resistance from the current source to the selected
memory cell is different according to the location of the selected memory cell.
Therefore, a write current fluctuates in value, which leads to a loss of a margin
of data writing, thereby resulting in a possibility to produce a phenomenon to
disable data to be normally written to the selected memory cell.
(2) A current wire connected to a plurality of write current lines provided correspondingly
to each of the predetermined units of a plurality of MTJ memory cells is generally
longer than a write current line. Therefore, a large parasitic capacitance is generated
on the current wire.
A necessity exists for causing a comparatively large current to flow in a selected
write current line (in mA units) in writing data to an MTJ memory cell. Hence,
a possibility arises that a current generated by the parasitic capacitance is superimposed
on a write current for writing data to the MTJ memory cell, essentially in need.
Accordingly, an excessively large current generates in the write current line,
leading to erroneous data writing to a non-selected memory cell arranged in the
vicinity of a selected write current line.
(3) Since a necessity arises for causing much of a current to flow in a write
current line when data is written, a voltage applied to a current source for supplying
the current to the write current line is set higher than a voltage applied to other
circuits. Therefore, an address decode circuit and related circuits thereof included
the other circuits and a current source are applied with respective different power
supply voltages from each other. As a result, when power is turned on, the current
source has a fear to be activated at a timing earlier than the address decode and
related circuits thereof. Therefore, if the address decode circuit and related
circuits thereof remain in an inactive state when power is turned on, that is,
when the current source is activated before the address decode circuit and related
circuits thereof are not normally operated, an unnecessary current flows in a write
current line, leading to a problem that erroneous data writing is performed to
an MTJ memory cell.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a memory device capable of supplying
a stable current to a memory cell at the time of data writing, and reducing a probability
of erroneous writing.
In summary, a memory device according to an aspect of the present invention includes
a memory cell array in which a plurality of memory cells are arranged through each
of which a pass current when data is read flows at a value different according
to a level of data written according to an applied data write current. The memory
cell array is divided into a plurality of regions each selectable independently
of the others as an object for data writing, and the memory device further includes
a plurality of current supply sections provided correspondingly to the plurality
of regions, respectively. Each of the plurality of current supply sections, when
a corresponding region of the plurality of regions is selected as the object for
data writing, is activated to supply the data write current to the corresponding
region, each of the plurality of regions includes a plurality of write select lines
provided correspondingly to each of predetermined units of the plurality of memory
cells, and the plurality of write select lines are selectively supplied with the
data write current from a corresponding one of the plurality of current supply sections.
Therefore, a memory device according to the present invention can reduce
a wiring length from a current supply section to a region including a memory cell
selected as an object for data writing. As a result, since wiring resistance from
the current supply section to the selected memory cell is reduced, fluctuations
in writing currents can be decreased, thereby enabling reduction in probability
of erroneous writing to a memory cell.
According to another aspect of the present invention, a memory device includes:
a plurality of memory cells through each of which a pass current when data is read
flows at a value different according to a level of data written according to an
applied data write current; a plurality of write select lines provided correspondingly
to predetermined units of the plurality of memory cells; a current supply line
connected electrically to the plurality of write select lines; a plurality of current
supply circuits, when data is written, supplying the data write current to the
current supply line; and a ground wire for, when data is written, guiding the data
write current supplied to the current supply line to at least one of the plurality
of ground nodes through at least one of the plurality of write select lines. The
plurality of current supply circuits and the plurality of ground nodes are arranged
so that a path length of the data write current along the current supply line,
a write select line corresponding to a selected memory cell of the plurality of
memory cells corresponding to an input address and the ground wire is almost constant
regardless of a location of the selected memory cell.
Therefore, a main advantage of the present invention lies in that since
a path length of a data write current can be held to be almost constant regardless
of a location of a selected memory cell, a stabilization of a write current can
be achieved, thereby realization of a memory device capable of reducing a probability
of erroneous writing to a memory cell.
According to yet another aspect of the present invention, a memory device
includes: a plurality of memory cells through each of which a pass current when
data is read flows at a value different according to a level of data written according
to an applied data write current; a plurality of write select lines provided correspondingly
to predetermined units of the plurality of memory cells; a current supply line
connected electrically to the plurality of write select lines; a current supply
circuit, when data is written, activated to connect the current supply line electrically
to a first power supply voltage and to thereby supply the data write current to
the current supply line; an address decode circuit, receiving supply of a second
power supply voltage to operate and to decode an input address, and for, when data
is written, selecting a write select line to receive supply of the data write current
from the plurality of write select lines; and a voltage detecting circuit, connected
electrically to the second power supply voltage, and for detecting whether or not
the address decode circuit has been activated. The current supply circuit includes
a switch for disconnecting the current supply line electrically from the first
power supply voltage according to a result of the detection of the voltage detecting
circuit when the address decode circuit is in an inactive state, and a voltage
level supplied by the first power supply voltage is higher than that supplied by
the second power supply voltage.
Therefore, still another advantage of the present invention lies in that
the current supply circuit is activated according to an active state of the address
decode circuit, thereby enabling realization of a memory device capable of preventing
erroneous writing of data when power supply is turned on.
The foregoing and other objects, features, aspects and advantages of the present
invention will become more apparent from the following detailed description of
the present invention when taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic diagram showing a configuration of a non-volatile memory
device according to a first embodiment;
FIG. 2 is a circuit diagram showing a configuration of a memory array in a memory
array block;
FIG. 3 is a conceptual diagram describing a structure of an MTJ memory cell
and a principle of data storage therein;
FIG. 4 is a conceptual diagram showing a relationship between a data write current
in an MTJ memory cell and a magnetic direction of a tunneling magneto-resistance element;
FIGS. 5 and 6 are schematic diagrams showing configurations of non-volatile
memory devices of first and second modifications of the first embodiment, respectively;
FIGS. 7 and 8 are circuit diagrams showing configurations of memory arrays
in memory array blocks according to the first embodiment;
FIGS. 9 to 11 are schematic diagrams showing configurations of memory
arrays according to second to fourth modifications of a second embodiment, respectively;
FIG. 12 is a schematic diagram showing a configuration of a non-volatile memory
device according to a third embodiment;
FIG. 13 is a circuit diagram showing a configuration of a memory array in a
memory array block according to the third embodiment;
FIGS. 14 and 15 are schematic diagrams showing configurations of non-volatile
memory devices according to the first and second modifications of the third embodiment, respectively;
FIGS. 16 and 17 are circuit diagrams showing configurations of memory arrays
in memory array blocks according to the third embodiment;
FIGS. 18 to 20 are schematic diagrams showing configurations of memory
arrays according to second to fourth modifications of a fourth embodiment, respectively;
FIG. 21 is a diagram showing details of one of memory blocks in a memory array
mat of a non-volatile memory device according to the first embodiment;
FIG. 22 is a schematic diagram showing a configuration of a non-volatile memory
device according to a fifth embodiment;
FIG. 23 is an operating waveform diagram describing operations in generation
of a write current in a non-volatile memory device according to the fifth embodiment;
FIG. 24 is an operating waveform diagram describing operations when power is
turned on of a non-volatile memory device according to the fifth embodiment;
FIG. 25 is a schematic diagram showing a configuration of a non-volatile memory
device according to a first modification of the fifth embodiment;
FIG. 26 is an operating waveform diagram describing operations in generation
of a write current of a non-volatile memory device according to the first modification
of the fifth embodiment;
FIG. 27 is a schematic diagram showing a configuration of a non-volatile memory
device according to a second modification of the fifth embodiment;
FIG. 28 is circuit diagram showing a configuration of the interior of an address
decode control circuit;
FIG. 29 is an operating waveform diagram showing operations in generation of
a write current in a non-volatile memory device according to the second modification
of the fifth embodiment;
FIG. 30 is a diagram showing details of one of memory array blocks in a memory
array mat of a non-volatile memory device according to the third embodiment;
FIGS. 31 to 33 are schematic diagrams showing configurations of non-volatile
memory devices according to third to fifth modifications of the fifth embodiment, respectively;
FIG. 34 is a schematic diagram showing a configuration of a non-volatile memory
device to which decoupling capacitance is connected according to a sixth embodiment;
FIGS. 35 to 37 are schematic diagrams showing configurations of non-volatile
memory devices to each of which decoupling capacitance is connected according to
first to third modifications of the sixth embodiment, respectively;
FIG. 38 is a schematic diagram showing a configuration of a non-volatile memory
device according to a fourth modification of the sixth embodiment;
FIG. 39 is a circuit diagram showing an address decode circuit provided in the
interior of a row decoder;
FIG. 40 is an operating waveform diagram describing operations in a case where
a non-volatile memory device according to the fifth embodiment enters a write state
in error when power is turned on;
FIG. 41 is an operating waveform diagram describing operations when power is
turned on in a non-volatile memory device according to the fourth modification
of the sixth embodiment;
FIG. 42 is a schematic diagram showing a configuration of a non-volatile memory
device according to a fifth modification of the six embodiment;
FIG. 43 is a circuit diagram showing an address decode circuit provided in the
interior of a row decoder;
FIG. 44 is an operating waveform diagram describing operations in a case where
a non-volatile memory device according to the third modification of the fifth embodiment
enters a write state in error when power is turned on;
FIG. 45 is an operating waveform diagram describing operations when power is
turned on in a non-volatile memory device according to the fifth modification of
the sixth embodiment;
FIG. 46 is a schematic diagram showing a configuration of a non-volatile memory
device according to a sixth modification of the sixth embodiment;
FIG. 47 is a circuit diagram showing a configuration of a one-shot pulse generation
control circuit;
FIG. 48 is an operating waveform diagram describing operations in a case where
a non-volatile memory device according to the sixth modification of the sixth embodiment
enters a write state in error when power is turned on;
FIG. 49 is a schematic diagram showing a configuration of a non-volatile memory
device according to a seventh modification of the sixth embodiment;
FIG. 50 is a schematic diagram showing a configuration of a non-volatile memory
device according to a seventh embodiment;
FIG. 51 is a circuit diagram showing a configuration of a memory array in a
memory array block according to the seventh embodiment;
FIGS. 52 and 53 are schematic diagrams showing configurations of non-volatile
memory devices according to first and second modifications of the seventh embodiment, respectively;
FIG. 54 is a conceptual diagram showing a configuration of a memory array in
a memory array block according to an eighth embodiment;
FIG. 55 is a conceptual diagram showing a configuration of a memory array in
a memory array block according to a first modification of the eighth embodiment; and
FIGS. 56 to 58 are schematic diagrams showing configurations of memory
arrays according to second to fourth modifications of the eighth embodiment, respectively.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Description will be given of embodiments of the present invention below
with reference to the drawings. Note that the same symbols in the figures indicate
the same or corresponding constituents.
First Embodiment
Referring to FIG. 1, a non-volatile memory device
1000 includes
memory array mats
100 and
200, power supply terminals
10 and
20, and current sources I
1 and I
2.
Memory array mats
100 and
200 are divided into a plurality of
memory array blocks MAB, respectively. For example, memory array mats
100
and
200 are divided into four memory blocks MAB, respectively. Though details
thereof will be described later, each of memory array blocks MAB includes, as an
example, a plurality of memory cells arranged in rows and columns, an address decoder,
bit lines, write digit lines and read word lines. Note that a memory array mat
may be configured so that one address decoder selects a bit line, a write digit
line and a read word line included in a plurality of memory array blocks.
A power supply voltage Vcc is supplied to power supply terminals
10 and
20 from outside. Power supply terminals
10 and
20 supply power
supply voltage Vcc to current sources I
1 and I
2, respectively. Current
source I
1 supplies a current to each of memory array blocks MAB in memory
array mat
100 through a current source wire LE
1. Current source
12
supplies a current to each of memory array blocks MAB in memory array mat
200
through a current source wire LE
2.
Current sources I
1 and I
2 supply currents to each of memory
array blocks MAB in memory array mats
100 and
200 through current
source wires LE
1 and LE
2, respectively. Note that in the following
description, a signal having a main symbol attached with an additional symbol "/"
before itself is an inverted signal of an signal having only the main symbol not
attached with the symbol "/".
FIG. 2 is a circuit diagram showing a configuration of a memory array
500
in memory array block MAB. Note that in FIG. 2, there is also shown current source
I
1 not included in memory array
500 for convenience in description.
Referring to FIG. 2, memory array
500 includes a memory cell array
55 and a row decoder
50.
Memory cell array
55 has a plurality of MTJ memory cells. The MTJ memory
cells are classified into normal memory cells (hereinafter, also simply referred
to as a "memory cell MC") and dummy memory cells DMC arranged in a row direction.
A row on which dummy memory cells DMC are arranged is hereinafter also referred
to as a "dummy cell row." Dummy memory cells DMC have the same characteristics
(a shape and structure) as memory cell MC and arranged so as to share a memory
cell row with memory cells MC.
Herein, description will be given of a structure of an MTJ memory cell and
a principle of data storage.
Referring to FIG. 3, a tunneling magneto-resistance element TMR has a ferromagnetic
layer having a fixed magnetic direction (hereinafter, also simply referred to as
a "fixed magnetic layer) FL, and a ferromagnetic layer capable of being magnetized
in a direction corresponding to an externally applied magnetic field (hereinafter,
also simply referred to as a "free magnetic layer") VL. A tunneling barrier (tunneling
film) TB made of an insulating film is provided between fixed magnetic layer FL
and free magnetic layer VL. Free magnetic layer VL is magnetized in a direction
in parallel or anti-parallel to a magnetic direction of fixed magnetic layer FL
depending on a level of storage data to be written. A magnetic tunnel junction
is formed of fixed magnetic layer FL, tunneling barrier TB and free magnetic layer VL.
An electric resistance of tunneling magneto-resistance element TMR alters depending
on a relative relationship in magnetic direction between fixed magnetic layer FL
and free magnetic layer VL. To be concrete, an electric resistance of tunneling
magneto-resistance element TMR takes the minimum value Rmin in a case where magnetic
directions of free magnetic layer VL and fixed magnetic layer FL are the same as
(in parallel to) each other, while taking the maximum value Rmax in a case where
magnetic directions of both layers are opposite to each other (in anti-parallel).
When data is written, read word line RWL is deactivated to turn off access transistor
ATR. In this state, data write currents for magnetizing free magnetic layer VL
flow in directions depending on a level of write data in bit line BL and write
digit line WDL.
Referring to FIG. 4, the abscissa H (EA) is used for plotting a magnetic
field applied in a magnetic easy axis (EA) direction in free magnetic layer VL
in tunneling magneto-resistance element TMR. On the other hand, the ordinate H
(HA) is assigned to a magnetic field acting in a magnetic hard axis (HA) direction
in free magnetic layer VL therein. Magnetic fields H (EA) and H (HA) correspond
to magnetic fields generated by respective currents flowing in bit line BL and
write digit line WDL.
In an MTJ memory cell, a fixed magnetic direction of fixed magnetic layer FL
is
present along a magnetic easy axis of free magnetic layer VL and free magnetic
layer VL is magnetized in parallel to (the same as) or anti-parallel to (opposite
to) the magnetic direction of fixed magnetic layer FL along the magnetic easy axis
depending on a level of storage data in an MTJ memory cell. An MTJ memory cell
can store 1 bit data corresponding to one of two magnetic directions of free magnetic
layer VL.
A magnetic direction of free magnetic layer VL can be rewritten only when the
sum
of applied magnetic fields H (EA) and H (HA) amounts to a point in a region outside
an Astroid characteristic curve shown in FIG.
4. That is, if an applied
data write magnetic field is of a strength in a region inside the Astroid characteristic
curve, no change in magnetic direction occurs in free magnetic layer VL.
As shown in the Astroid characteristic curve, with application of a magnetic
field
in a magnetic hard axis direction onto free magnetic layer VL, reduction is achieved
in a magnetization threshold value necessary for altering a magnetic direction
along magnetic easy axis H (EA). An operating point when data is written, as shown
in FIG. 4, is designed to be located so that when predetermined currents are caused
to flow in write digit line WDL and bit line BL, storage data in an MTJ memory
cell, that is, a magnetic direction of tunneling magneto-resistance element TMR
can be rewritten.
A data write magnetic field in a magnetic easy axis in an MTJ memory cell, which
is an object for data writing, is designed so that a strength of the magnetic field
takes HWR at an operating point shown in FIG. 4 as an example. That is, a value
of a data write current flowing bit line BL or write digit line WDL is designed
so that the data write magnetic field H
WR is obtained. Generally, a
data write magnetic field H
WR is expressed as the sum of between a switching
magnetic field H
SW necessary for changing-over magnetic directions and
a margin AH, that is, H
WR=H
SW+ΔH.
A magnetic direction once written to tunneling magneto-resistance element TMR,
that is, storage data of an MTJ memory cell is held in a non-volatile manner till
new data writing is performed. Though an electric resistance of each memory cell
is, strictly speaking, the sum of on-resistance values of tunneling magneto-resistance
element TMR and access transistor ATR, and another parasitic resistance, a resistive
component other than that of tunneling magneto-resistance element TMR is constant
regardless of storage data; therefore, two kinds of electric resistance values
of a normal memory cell corresponding to storage data are expressed as Rmax and
Rmin and a difference between both is expressed as ΔR (i.e., ΔR=Rmax-Rmin).
Referring again to FIG. 2, in memory cell array
55, read word lines
RWL
1 to RWLn and write digit lines WDL
1 to WDLn are provided correspondingly
to memory cell rows shared between memory cells MC and dummy memory cells DMC,
respectively. A bit line pair BLP are provided correspondingly to memory cell columns
constituted of memory cells MC, respectively, and a dummy digit line DDL is provided
correspondingly to a dummy cell row. Bit line pair BLP is constituted of two bit
lines /BL and BL complementary to each other. While no dummy digit line DDL is
used in data writing, it is used when current source wires are precharged, which
will be described later.
Memory cells MC in an odd-numbered row are connected to one bit line BL, while
memory cells MC in an even-numbered row are connected to the other bit line /BL.
Each memory cell MC has tunneling magneto-resistance element TMR acting as a magnetic
storage section electric resistance of which alters depending on a level of storage
data, and an access transistor ATR acting as an access gate, both being connected
in series with each other. As described above, a MOS transistor is used as access
transistor ATR, which is a field effect transistor formed on a semiconductor substrate.
Tunneling magneto-resistance element TMR is magnetized in one of two directions
to set an electric resistance value thereof to one of Rmin and Rmax.
Memory array
500 further includes row decode transistors RD
1
to RDn, dummy row decode transistor RDd, and current source wire L
1 and L
1#.
In the following description, read word lines RWL
1 to RWLn, write digit
lines WDL
1 to WDLn and row decode transistors RD
1 to RDn are also
collectively referred to as read word line RWL, write digit line WDL and row decode
transistor RD, respectively. Furthermore, a high voltage state (power supply voltage
Vcc) and a low voltage state (ground voltage GND), which are binary values, in
combination, of a signal and on a signal line, are also referred to as "H level"
and "L level", respectively.
Moreover, in a case where only a configuration of one of the plurality
of memory array blocks is shown in the figure, a current source wire connecting
a current source outside a memory array mat electrically to the one memory array
block is connected electrically to a current source wire to which a current source
in the memory array is connected electrically when the current source is connected
electrically to the current source wire in the memory array. For example, in FIG.
1, current source wire LE
1 connecting current source I
1 electrically
to each memory array block MAB is connected electrically to current source line
L
1 in FIG. 2 to which current source I
1 is connected electrically.
Moreover, in a case where only a configuration of one of the plurality
of memory array blocks is shown in the figure, a current source wire corresponding
to current source wire L
1 for supplying a write current to desired write
digit line VVDL is also present in other memory array blocks. For example, each
of the current source lines in the other memory array blocks in memory array mat
100 is connected electrically to current source wire LE
1 outside
memory array mat
100. Therefore, in the following description, for example,
in a case where a voltage state on and a current amount flowing in current source
wire L
1 are shown in an operating waveform diagram, a similar operating
waveform diagram is also shown with respect to a current source wire in each of
the other memory array blocks.
Each row decode transistors RD is provided between write digit line WDL and
current source line L
1#. N-channel MOS transistors are used as each of row
decode transistors RD in a configuration in which a current is supplied to a memory
array from a current source, while P-channel MOS transistors are used as each of
row decode transistors RD in a configuration in which a current is supplied to
a current source from a memory array. Each of the gates of row decode transistors
RD are connected to row decoder
50.
Dummy row decode transistor RDd is provided between dummy digit line DDL and
current source L
1#. An N-channel MOS transistor is used as dummy row decode
transistor RDd in a configuration in which a current is supplied to a memory array
from a current source, while a P-channel MOS transistor is used as dummy row decode
transistor RDd in a configuration in which a current is supplied to a current source
from a memory array.
The gate of dummy row decode transistor RDd is connected to a row decoder
50.
Row decoder
50 sends a signal at H level to the gate of desired row decode
transistor RD or dummy row decode transistor RDd according to a row address signal
to connect desired write digit line WDL electrically to current source wire L
1#
or connect dummy digit line DDL electrically to current source wire L
1#.
Row decoder
50 is activated when a supplied voltage is raised to a value
equal to or more than a predetermined level.
Current source wire L
1 is connected electrically to current source
I
1 through a current source wire LE
1 (not shown). A predetermined
current is supplied to current source wire L
1 from current source I
1.
An end of current source wire L
1# is connected to ground voltage GND and
the other end thereof is set to be in a floating state.
Memory array
500 further includes a column select gate CGS, a precharge-equalize
circuit P/E and data lines DB and /DB, all being provided to each bit line pair BLP.
Column select gate SCG has N-channel MOS transistors
44 and
45.
N-channel MOS transistors
44 and
45 are provided between bit line
/BL and data line /DB and between bit line BL and data line DB, respectively. If
a column select signal CSLJ is inputted to the gates of N-channel MOS transistors
44 and
45 when data is read from memory cell MC, N-channel MOS transistors
44 and
45 connect bit lines /BL and BL electrically to data lines
/DB and DB, respectively.
Thereafter, a small difference in potential produced between bit lines
/BL and BL are inputted to a sense amplifier (not shown) through data lines /DB
and DB to be amplified there.
Precharge-equalize circuit P/E has N-channel MOS transistors
41,
42 and
43. N-channel MOS transistors
41 and
43 are
provided between bit lines /BL and BL and ground voltage GND, respectively. N-channel
MOS transistor
42 is provided between bit lines /BL and BL. When a precharge-equalize
signal BLEQ at H level is inputted to the gates of N-channel MOS transistors
41,
42 and
43, bit lines /BL and BL are precharged to and equalized at
ground voltage GND. Precharge-equalize signal BLEQ at L level, when data is read,
is inputted to the gates of N-channel MOS transistors
41,
42 and
43 to cancel precharging and equalization on bit lines /BL and BL.
Then, description will be given of configurations for supply of a data write
current to bit line BL and for data reading therefrom using FIG.
2.
Referring to FIG. 2, memory array
500 further includes bit line
drivers
30a and
30 and a data write circuit
40, which
are provided correspondingly to each memory cell column.
Bit line driver
30a has driver transistors
33 and
34
connected between one end side of a corresponding bit line BL and power supply
voltage Vcc and between the one end side of a corresponding bit line BL and ground
voltage GND, respectively. Likewise, bit line driver
30 has driver transistors
31 and
32 connected between the other end side of the corresponding
bit line BL and power supply voltage Vcc and between the other end side of the
corresponding bit line BL and ground voltage GND, respectively. Driver transistors
33 and
31 are P-channel MOS transistors and driver transistors
34
and
32 are N-channel MOS transistors.
Write control signals /WTa
0 and WTa
1 are inputted to the gates
of respective driver transistors
33 and
34, respectively, and write
control signals /WTb
0 and WTb
1 are inputted to the gates of respective
driver transistors
31 and
32, respectively.
In each of memory cell columns, bit line driver
30a drives the
one
end side of a corresponding bit line BL with power supply voltage Vcc or ground
voltage GND in response to write control signals /WTa
0 and WTa
1 or
alternatively, causes the one end side of the corresponding bit line BL to be in
a floating state without connecting any of the voltages. Likewise, bit line driver
30 drives the other end side of the corresponding bit line BL with power
supply voltage Vcc or ground voltage GND in response to write control signals /WTb
0
and WTb
1 or alternatively, causes the other end side of the corresponding
bit line BL to be in a floating state.
Data write circuit
40 controls write control signals /WTa
0, WTa
1,
/WTb
0 and WTb
1 on each memory cell column according to write data
DIN and a result of column selection. Write control signals /WTa
0, WTa
1,
/WTb
0 and WTb
1 are set so that a data write current +Iw or -Iw in
a direction corresponding to write data DIN flows into bit line BL of a selected
column. Hereinafter, data write currents +Iw and -Iw in opposed directions in bit
line BL are also collectively referred to as data write current ±Iw.
Data write circuit
40 sets write control signals /WTa
0 and /WTb
0
at H level and write control signals WTa
1 and WTb
1 at L level on
each memory cell column during a time other than when data is written. Thereby,
each bit line BL is set to be in a floating state during a time other than when
data is written.
Furthermore, data write circuit
40, when data is written, sets
each of write control signals /WTa
0, WTa
1, /WTb
0 and WTb
1
for a non-selected memory cell column to H level. Hence, both ends of bit line
BL of a non-selected column when data is written are connected to ground voltage
GND so as not to cause a current to flow therein unintentionally.
On the other hand, data write circuit
40, when data is written, sets write
control signals /WTa
0, WTa
1, /WTb
0 and WTb
1 for a selected
memory cell column according to write data DIN.
To be concrete, when write data DIN is at H level, write control signals /WTa
0
and WTa
1 are set to L level while write control signals /WTb
0 and
WTb
1 are set to H level. Thereby, data write current +Iw flows in bit line
BL of a selected column in a direction from bit line driver
30a to
bit line driver
30.
On the other hand, when write data DIN is at L level, write control signals /WTa
0
and WTa
1 are set to H level while write control signals /WTb
0 and
WTb
1 are set to L level. Thereby, data write current -Iw flows in bit line
BL of a selected column in a direction from bit line driver
30 to bit line
driver
30a. Note that drive voltages of bit line drivers
30a
and
30 can also be set to independent voltages different from ground
voltage GND or power supply voltage Vcc.
Then, description will be given of operations for causing a current to flow
into write digit line WDL when data is written. When a row address signal is inputted
to row decoder
50, desired row decode transistor RD is turned on to connect
a corresponding write digit line WDL electrically to current source wire L
1#.
Therefore, a current flows in selected write digit line WDL from current source
I
1 connected to current source wire L
1 to ground voltage GND connected
to current source wire L
1#.
A data write magnetic field along a magnetic easy axis (EA) is applied MTJ memory
cell MC by data write current ±Iw. In MTJ memory cell MC for which data write
currents are caused to flow in both of corresponding write digit line WDL and corresponding
bit line BL, respectively, write data corresponding to a direction of data write
current ±Iw in bit line BL is written magnetically.
While in the above description, description has been given of configurations
for supply of a data write current into bit line BL and for data reading therefrom,
configurations for supply of a data write current to bit line /BL and for data
reading therefrom is similar to the case of bit line BL, so no detailed description
thereof will be repeated.
Referring again to FIG. 1, non-volatile memory device
1000 further
includes a control circuit
800.
Control circuit
800 outputs a current control signal ICNT
1
or ICNT
2 according to a control signal CT generated in an internal circuit
(not shown) according to an address signal. Current sources I
1 and I
2
are activated by current control signals ICNT
1 and ICNT
2, respectively.
Control signal CT is set so that control circuit
800 transmits current
control signal ICNT
1 to current source I
1 when a write operation
is performed on a memory cell in a memory array block MAB of memory array mat
100,
that is, when memory array mat
100 is selected as an object for data writing.
On the other hand, control signal CT is set so that control circuit
800
transmits current control signal ICNT
2 to current source
12 when
a write operation is performed on a memory cell in a memory array block MAB of
memory array mat
200. Note that no specific limitation is imposed on one
memory array block, which becomes an object for writing, but a plurality of memory
array blocks may simultaneously be objects for writing.
That is, one memory array mat is divided into two parts and current sources
are provided correspondingly to each of the parts of the memory array mat and the
current sources are selectively activated, thereby enabling a wiring length from
a current source to a selected memory cell to be halved. Therefore, since wiring
resistance from a current source to a selected memory cell is also halved, fluctuations
in write currents can be reduced.
In non-volatile memory device
1000 according to the first embodiment,
as
described above, a stable current, when data is written, can be supplied to a memory
cell to reduce a probability for erroneous writing.
First Modification of First Embodiment
Referring to FIG. 5, a non-volatile memory device
1100 is different
from non-volatile memory device
1000 according to the first embodiment shown
in FIG. 1 by comparison in an aspect that wiring lengths of current source wire
LE
1 from current source I
1 to memory array blocks MAB of memory array
mat
100 are equal to each other and wiring lengths current source wire LE
2
from current source
12 to memory array blocks MAB of memory array mat
200
are equal to each other. Since the other constituents in the configuration and
operations therein are the same as in non-volatile memory device
1000, none
of detailed descriptions thereof will be repeated.
Accordingly, non-volatile memory device
1100 can reduce fluctuations
in wiring lengths from a current source to memory array blocks MAB to a lower value
than non-volatile memory device
1000.
As a result, non-volatile memory device
1100 can further reduce fluctuations
in write currents to a lower value than non-volatile memory device
1000
in addition to the effect exerted by non-volatile memory device
1000.
Second Modification of First Embodiment
Referring to FIG. 6, a non-volatile memory device
1200 is different
from non-volatile memory device
1000 according to the first embodiment shown
in FIG. 1 by comparison in an aspect that provided are power supply terminals
10#
1,
10#
2,
20#
1 and
20#
2 and current sources
I
1#
1, I
1#
2, I
2#
1 and I
2#
2
instead of power supply terminals
10 and
20 and current sources I
1
and I
2.
Power supply voltage Vcc is supplied to power supply terminals
10#
1,
10#
2,
20#
1 and
20#
2 from outside. Power
supply terminals
10#
1,
10#
2,
20#
1 and
20#
2 supply power supply voltage Vcc to current sources I
1#
1,
I
1#
2, I
2#
1 and I
2#
2. Current sources
I
1#
1 and I
1#
2 supply currents to memory array blocks
MAB of memory array mat
100 through current source wire LE
1. Current
sources I
2#
1 and I
2#
2 supply currents to memory array
blocks MAB of memory array mat
200 through current source wire LE
2.
Since the other constituents in the configuration are the same as in non-volatile
memory device
1000, none of detailed descriptions thereof will be repeated.
Control circuit
800 transmits current control signal ICNT
1
to current sources I
1#
1 and I
1#
2 according to control
signal CT. Control circuit
800 further transmits current control signal
ICNT
2 to current sources I
2#
1 and I
2#
2 according
to control signal CT.
Current sources I
1#
1 and I
1#
2 are activated in
response to current control signal ICNT
1 and current sources I
2#
1
and I
2#
2 are activated in response to current control signal ICNT
2.
In a case where a write operation is performed on a memory cell in memory array
block MAB of memory array mat
100, control signal CT is set so that control
circuit
800 transmits current control signal ICNT
1 to current sources
I
1#
1 and I
1#
2. On the other hand, in a case where a
write operation is performed on a memory cell-in memory array block MAB of memory
array mat
200, control signal CT is set so that control circuit
800
transmits current control signal ICNT
2 to current sources I
2#
1
and I
2#
2. Note that no specific limitation is imposed on one memory
array block, which becomes an object for writing, but a plurality of memory array
blocks may simultaneously be objects for writing.
Therefore, non-volatile memory device
1200 has an advantage that
reduction occurs in wiring lengths to each of memory blocks MAB of memory array
mats
100 and
200 from the current sources by connecting two current
sources to each of current source wires LE
1 and LE
2 to smaller values
than non-volatile memory device
1000 in addition the effect exerted by non-volatile
memory device
1000.
As a result, non-volatile memory device
1200 can further reduce fluctuations
in write currents to a lower value than non-volatile memory device
1000
in addition to the effect exerted by non-volatile memory device
1000.
Note that in this embodiment, a configuration has been shown in which two current
sources are connected to a current source wire, write currents to memory array
blocks of a memory array mat can be further stabilized by connecting three or more
current sources to a current source wire. Furthermore, while in this embodiment,
an example has been shown in which a plurality of current sources connected to
one current source wire are all activated, the present invention is not limited
to such a configuration. The present invention can also be applied to a configuration
in which a signal from a control circuit is transmitted to each of current sources
independently of the other to enable only a desired current source to be selectively
activated by the control circuit.
Second Embodiment
FIG. 7 is a circuit diagram showing a configuration of a memory array
505
in memory array block MAB according to the first embodiment. Note that since an
operation in data write circuit
40 has been described in the first embodiment,
no data write circuit
40 is shown in the figure.
Referring to FIG. 7, memory array.
505 is different from memory
array
500 according to the first embodiment by comparison in an aspect that
current source I
1 is connected to one end of current source wire L
1
instead of a point in the vicinity of a center between locations thereon to which
write digit lines WDL
1 and WDLn are connected. Since the other constituents
in the configuration are the same as in memory array
500 shown in the first
embodiment, none of detailed descriptions thereof will be repeated.
Current source I
1 connected to current source wire L
1 is located
at a position thereon diagonal with respect to ground voltage GND connected to
current source wire L
1#. Therefore, for example, a wiring length from current
source I
1 to ground voltage GND connected to current source wire L
1#
when row decode transistor RD
1 is turned on is equal to a wiring length
from current source I
1 to ground voltage GND connected to current source
wire L
1# when row decode transistor RD
2 is turned on. That is, even
if any memory cell is selected when data is written, a wiring length from current
source I
1 to ground voltage GND connected to current source wire L
1#
is constant. Therefore, wiring resistance between current source I
1 and
current source wire L
1# is constant. Accordingly, almost no fluctuation
occurs in write currents when data is written.
In memory array
505 according to the second embodiment, as described above,
write currents can be stabilized.
First Modification of Second Embodiment
Referring to FIG. 8, a memory array
510 is different from memory
array
500 according to the first embodiment by comparison in an aspect that
ground voltage GND is connected to both ends of current source wire L
1#
instead of one end of current source wire L
1#. Note that in memory array
510 shown in FIG. 8, since the configuration is the same as memory array
500 except for current source I
1, current source wires L
1
and L
1#, write digit line WDL, dummy digit line DDL, row decode transistor
RD, dummy row decode transistor RDd and row decoder
50, only part necessary
for description thereof is shown in the figure.
Since in memory array
510, ground voltage GND is connected to both ends
of current source wire L
1#, a stronger force is exerted that fixes current
source wire L
1# to ground voltage GND than in the case of memory array
500
in which ground voltage GND is connected to one end of current source wire L
1#.
Therefore, a current flowing in current source wire L
1# of memory array
510 is stabilized more than in the configuration of memory array
500.
Furthermore, a wiring length from current source I
1 to ground voltage GND
is shorter in memory array
510 than in the configuration of memory array
500 by connecting ground voltage GND to current source wire L
1# not
at only one end but at both ends thereof. Therefore, fluctuations in write currents
can be further reduced.
In memory array
510 according to the first modification of the second
embodiment,
as described above, write currents can be further stabilized to a higher level
than in memory array
500 according to the second embodiment.
Second Modification of Second Embodiment
Referring to FIG. 9, a memory array
520 is different from memory
array
510 according to the first modification of the second embodiment by
comparison in an aspect that current sources I
1#
1 and I
1#
2
are provided instead of current source I
1.
Memory array
520 is further different from memory array
510
by comparison in an aspect that current sources I
1#
1 and I
1#
2
are connected to one end and the other end, respectively, of current source wire
L
1 instead of current source I
1 connected to a point in the vicinity
of the center between locations on current source wire L
1 to which write
digit lines WDL
1 and WDLn are connected. Current sources I
1#
1
and
112 supply the same amount of currents as the amount that current source
I
1 does. Since the other constituents in the configuration are similar to
corresponding constituents in the configuration of memory array
510, none
of detailed descriptions thereof will be repeated. Note that in the following description,
current sources I
1#
1 and I
1#
2 are also collectively
referred to as current source I
1.
Since current source I
1 supplied with power supply voltage Vcc is connected
to both ends of current source wire L
1 in memory array
520, a stronger
force is exerted that fixes current source wire L
