Memory with self-aligned trenches for narrow gap isolation regions Number:7,402,886 from the United States Patent and Trademark Office (PTO) owispatent Self-aligned trench filling is used to isolate devices in high-density integrated circuits. A deep, narrow trench isolation region is formed in a substrate between devices. The trench region includes two trench portions. A first trench portion, located above a second trench portion, is filled with a deposited dielectric. The second trench portion is filled with a grown dielectric. Filling the lower trench portion by growing a dielectric material provides for an even distribution of dielectric material within the lower portion. Filling the upper trench portion by depositing a dielectric material provides for an even distribution of material in the upper portion while also protecting against encroachment of the dielectric into device channel regions, for example. Devices can be fabricated by etching the substrate to form the trench region after or as part of etching one or more layers formed above the substrate for the device. This can ensure alignment of the gate and channel regions of a device between trench isolation regions.<H isolation, trenches, Memory, with, sel, 7402886.html, Patent, pto, 7402886

Title: Memory with self-aligned trenches for narrow gap isolation regions

Abstract: Self-aligned trench filling is used to isolate devices in high-density integrated circuits. A deep, narrow trench isolation region is formed in a substrate between devices. The trench region includes two trench portions. A first trench portion, located above a second trench portion, is filled with a deposited dielectric. The second trench portion is filled with a grown dielectric. Filling the lower trench portion by growing a dielectric material provides for an even distribution of dielectric material within the lower portion. Filling the upper trench portion by depositing a dielectric material provides for an even distribution of material in the upper portion while also protecting against encroachment of the dielectric into device channel regions, for example. Devices can be fabricated by etching the substrate to form the trench region after or as part of etching one or more layers formed above the substrate for the device. This can ensure alignment of the gate and channel regions of a device between trench isolation regions.

Patent Number: 7,402,886 Issued on 07/22/2008 to Yuan

Inventors: Yuan; Jack H. (Cupertino, CA)
Assignee: SanDisk Corporation (Milpitas, CA)

Appl. No.: 11/251,400

Filed: October 14, 2005

Related U.S. Patent Documents


Application Number	Filing Date	Patent Number	Issue Date
10996030	Nov., 2004

Current U.S. Class: 257/510 ; 257/464; 257/522; 257/E21.545; 438/424; 438/431

Current International Class: H01L 29/00 (20060101)

Field of Search: 438/424-427,400,438 257/510,522,464

References Cited [Referenced By]

U.S. Patent Documents


5043940	August 1991	Harari
5070032	December 1991	Yuan
5095344	March 1992	Harari
5168465	December 1992	Harari
5172338	December 1992	Mehrota
5198380	March 1993	Harari
5268318	December 1993	Harari
5268319	December 1993	Harari
5297148	March 1994	Harari et al.
5313421	May 1994	Guterman
5315541	May 1994	Harari
5343063	August 1994	Yuan
5346842	September 1994	Bergemont
5380672	January 1995	Yuan
5464999	November 1995	Bergemont
5512505	April 1996	Yuan
5528547	June 1996	Aritome et al.
5534456	July 1996	Yuan
5554553	September 1996	Harari
5579259	November 1996	Samachisa
5595924	January 1997	Yuan
5640032	June 1997	Tomioka
5650345	July 1997	Ogura et al.
5654217	August 1997	Yuan
5661053	August 1997	Yuan
5661055	August 1997	Hsu et al.
5677872	October 1997	Samachisa
5680345	October 1997	Hsu et al.
5712179	January 1998	Yuan
5712180	January 1998	Guterman et al.
5747359	May 1998	Yuan
5756385	May 1998	Yuan
5786988	July 1998	Harari
5847425	December 1998	Yuan
5867429	February 1999	Chen
5883409	March 1999	Guterman
5895253	April 1999	Akram
5923976	July 1999	Kim
5965913	October 1999	Yuan
5976950	November 1999	DiSimone et al.
5981335	November 1999	Chi
5999448	December 1999	Kurihara
6008526	December 1999	Kim
6028336	February 2000	Yuan
6033970	March 2000	Park
6046935	April 2000	Takeuchi et al.
6057580	May 2000	Watanabe et al.
6103573	August 2000	Harari
6151248	November 2000	Harari
6166409	December 2000	Ratnam
6177317	January 2001	Huang et al.
6177333	January 2001	Rhodes
6204122	March 2001	Joo
6208545	March 2001	Leedy
6222225	April 2001	Nakamura et al.
6222762	April 2001	Guterman et al.
6232646	May 2001	Sun et al.
6235586	May 2001	Au
6239003	May 2001	Rao et al.
6251750	June 2001	Lee
6258665	July 2001	Shimizu
6268249	July 2001	Ha
6274419	August 2001	Omid-Zohor
6281075	August 2001	Yuan et al.
6294423	September 2001	Malik et al.
6297097	October 2001	Jeong
6417538	July 2002	Choi
6429076	August 2002	Ratnam
6440817	August 2002	Trivedi
6455889	September 2002	Sakui
6512262	January 2003	Watanabe et al.
6512263	January 2003	Yuan
6579777	June 2003	Yen
6620681	September 2003	Kim et al.
6657251	December 2003	Meguro
6689658	February 2004	Wu
6700159	March 2004	Kobayashi
6713834	March 2004	Mori et al.
6762092	July 2004	Yuan
6856001	February 2005	Rhodes
6881994	April 2005	Lee et al.
6888755	May 2005	Harari et al.
6894930	May 2005	Chien
6897522	May 2005	Harari et al.
6903434	June 2005	Shrivastava
6921688	July 2005	Shrivastava
6925007	August 2005	Harari et al.
6936887	August 2005	Harari
2002/0096704	July 2002	Fukumoto et al.
2002/0190312	December 2002	Lee
2003/0001204	January 2003	Kobayashi
2003/0030089	February 2003	Sumino et al.
2003/0080370	May 2003	Harari et al.
2003/0143815	July 2003	Shimizu
2004/0099900	May 2004	Tadashi
2004/0212006	October 2004	Harari
2005/0072999	April 2005	Matamis
2005/0162927	July 2005	Chien
2005/0180186	August 2005	Lutze et al.
2005/0218445	October 2005	VanDuuren
2006/0108647	May 2006	Yuan
2006/0110880	May 2006	Yuan

Foreign Patent Documents


0555039	Sep., 1998	EP
0509697	Sep., 1999	EP

Other References

Y Takeuchi, et al., "A Self-Aligned STI Process Integration for Low Cost and Highly Reliable 1Gbit Flash Memories," 1998 Symposium on VLSI Technology--Digest of Technical Papers, Jun. 9-11, 1998, pp. 102. cited by other .
Seiichi Aritome, "Advanced Flash Memory Technology and Trends for File Storage Application," 2000 International Electron Devices Meeting, Dec. 10-13, 2000, pp. 33.1.1-33.1.4. cited by other .
Non-Final Office Action, United States Patent & Trademark Office, U.S. Appl. No. 10/996,030, filed Nov. 23, 2004, Aug. 7, 2007. cited by other .
Non-Final Office Action, United States Patent & Trademark Office, U.S. Appl. No. 11/251,386, filed Oct. 14, 2005, Jun. 1, 2007. cited by other .
Kato, Masataka, et al., "A Shallow-Trench-Isolation Flash Memory Technology with a Source-Bias Programming Method," IEDM, 1996, pp. 177-180. cited by other .
Response to Non-Final Office Action, U.S. Appl. No. 11/251,386, filed Oct. 14, 2005, Nov. 30, 2007. cited by other .
Final Office Action, United States Patent & Trademark Office, U.S. Appl. No. 11/251,386, filed Oct. 14, 2005, Jan. 25, 2008. cited by other .
Notice of Allowance and Fee(s) Due, United States Patent & Trademark Office, U.S. Appl. No. 10/996,030, filed Nov. 23, 2004, Jan. 28, 2008. cited by other .
Response to Non-Final Office Action, U.S. Appl. No. 10/996,030, filed Nov. 23, 2004, Dec. 13, 2007. cited by other .
Notice of Allowance and Fee(s) Due, United States Patent & Trademark Office, U.S. Appl. No. 11/251,386 filed on Oct. 14, 2005, May 14, 2008. cited by other .
Response to Final Office Action, U.S. Appl. No. 11/251,386 filed on Oct. 14, 2005, Apr. 25, 2008. cited by other.

Primary Examiner: Le; Dung A.
Attorney, Agent or Firm: Vierra Magen Marcus & DeNiro LLP

Parent Case Text

PRIORITY CLAIM

The present application is a continuation-in-part application of U.S. patent application Ser. No. 10/996,030, entitled "SELF-ALIGNED TRENCH FILLING WITH HIGH COUPLING RATIO," by Jack H. Yuan, filed Nov. 23, 2004, incorporated by reference herein in its entirety.

Claims

I claim:

1. An integrated circuit, comprising: a substrate; a first portion of a layer formed above said substrate; a second portion of said layer formed above said substrate; and a trench isolation region formed in said substrate between said first and second portions of said layer, said trench isolation region including a first trench portion and a second trench portion, said first trench portion including two sidewalls, said second trench portion is at least partially filled with a grown dielectric; a first sidewall spacer coupled to a first sidewall of said first trench portion; a second sidewall spacer coupled to a second sidewall of said first trench portion; said first portion of said layer includes two sidewalls; said second portion of said layer includes two sidewalls; said integrated circuit includes a third sidewall spacer formed on a sidewall of said first portion of said layer and a fourth sidewall spacer formed on a sidewall of said second portion of said layer, said third sidewall spacer is adjacent to said fourth sidewall spacer; said first sidewall spacer is further coupled to said third sidewall spacer; and said second sidewall spacer is further coupled to said fourth sidewall spacer.

2. The integrated circuit of claim 1, wherein: said first sidewall spacer and said second sidewall spacer are formed prior to said second trench portion; said second trench portion is formed by: etching said substrate at a bottom of said first trench portion between said first sidewall spacer and said second sidewall spacer, and growing said grown dielectric to at least partially fill said second trench portion.

3. The integrated circuit of claim 1, wherein: said first portion is a charge storage region for a memory cell of a first NAND string; and said second portion is a charge storage region for a memory cell of a second NAND string.

4. The integrated circuit of claim 1, wherein: said first portion of said layer is a gate region of a first MOS transistor; and said second portion of said layer is a gate region of a second MOS transistor.

5. The integrated circuit of claim 1, wherein: said integrated circuit includes an array of multi-state flash memory devices.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

The following applications are cross-referenced and incorporated by reference herein in their entirety:

U.S. patent application Ser. No. 11/251,386, entitled, "SELF-ALIGNED TRENCH FILLING FOR NARROW GAP ISOLATION REGIONS," by Jack H. Yuan, filed concurrently.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Embodiments of the present invention are directed to high density semiconductor devices, such as nonvolatile memory, and systems and methods for isolating components in high density semiconductor devices.

2. Description of the Related Art

Integrated circuits are constructed by electrically connecting multiple isolated devices that share a common substrate. When multiple devices are formed on or in a common substrate, it is necessary to isolate the individual devices using isolation technology. As the density of integrated circuits continues to increase, the space available for isolating devices tends to decrease. With decreased device dimensions, inter-device parasitic currents and charges can become more problematic, making isolation technology a critical component of integrated circuit fabrication.

For example, in nonvolatile semiconductor memory devices such as flash memory, many individual storage elements are constructed from a common substrate to form a memory array. These individual storage elements must be isolated from one another using isolation technology. In one example of a flash memory system, the NAND structure is used. The NAND structure includes multiple transistors arranged in series, sandwiched between two select gates. The transistors in series and the select gates are referred to as a NAND string. Isolation technologies are typically employed during the device fabrication process to provide electrical isolation between adjacent NAND strings sharing a common substrate.

Numerous techniques exist for isolating devices in NAND flash memory and other types of semiconductor devices. In Local Oxidation of Silicon (LOCOS) techniques, an oxide is grown or deposited on the surface of a substrate, followed by the deposition of a nitride layer over the oxide layer. After patterning these layers to expose the desired isolation areas and cover the desired active areas, a trench is etched into these layers and a portion of the substrate. An oxide is then grown on the exposed regions. The grown oxide typically grows under the deposited nitride causing the encroachment of oxide into the active regions (often referred to as a bird's beak). This encroachment can cause stresses and ultimately defects in the silicon. Furthermore, the encroachment decreases the available active area for constructing devices which limits the density that can be achieved in the integrated circuit. Additionally, the LOCOS technique can cause alignment issues since the trench is formed prior to forming layers such as the conductive layer used to fabricate the floating gate of a device. The subsequently formed floating gate material may not properly align between two predefined trenches.

Improvements to these processes have been made by employing such techniques as sidewall-masked isolation (SWAMI) to decrease encroachment into active areas. In SWAMI, a nitride is formed on the trench walls prior to forming the oxide to decrease the oxide's encroachment and formation of bird's beaks. While this process provides an improvement to conventional LOCOS, the nitride in the trench rises during oxidation, causing encroachment into the active areas. This technique also yields excessive stress in the corners of the trench since oxide growth in that region is restrained. Moreover, the trenches are formed prior to device fabrication leading to the aforementioned alignment issues.

Accordingly, there is a need for isolation technology that can effectively isolate devices in high density semiconductor integrated circuits while addressing the shortcomings of the prior art identified above.

SUMMARY OF THE INVENTION

Self-aligned trench filling to isolate devices regions in high-density integrated circuits is provided. A deep, narrow trench isolation region is formed in a substrate between devices. The trench region includes two trench portions. A first trench portion, located above a second trench portion, is filled with a deposited dielectric. The second trench portion is filled with a grown dielectric. Filling the lower trench portion by growing a dielectric material provides for an even distribution of dielectric material within the lower portion. Filling the upper trench portion by depositing a dielectric material provides for an even distribution of material in the upper portion while also protecting against encroachment of the dielectric into device channel regions, for example. Devices can be fabricated by etching the substrate to form the trench region after or as part of etching one or more layers formed above the substrate for the device. This can ensure alignment of the gate and channel regions of a device between trench isolation regions.

In one embodiment, a method of fabricating a nonvolatile memory device is provided that includes forming a trench isolation region in a substrate between a first charge storage region and a second charge storage region formed above the substrate. Forming the trench isolation region includes forming a first trench portion in the substrate between the first and second charge storage regions and a second trench portion in the substrate between the first and second charge storage regions. The first charge storage region and the second charge storage region are formed prior to forming the isolation trench. A first dielectric material is deposited to at least partially fill the first trench portion. A second dielectric material is grown to at least partially fill the second trench portion.

In one embodiment, a nonvolatile memory is provided that includes a substrate, a first charge storage region formed above the substrate, and a second charge storage region formed above the substrate. The memory further includes a trench isolation region formed in the substrate between the first charge storage region and the second charge storage region. The trench isolation region includes a first trench portion and a second trench portion. The first trench portion is at least partially filled with a deposited dielectric and the second trench portion is at least partially filled with a grown dielectric.

In one embodiment, a method of fabricating an integrated circuit is provided that includes forming at least one layer above a substrate, etching through the at least one layer to define a first portion and a second portion of the at least one layer above the substrate, etching at least a first portion of the substrate to define a first trench portion in the substrate between the first portion and the second portion of the at least one layer, etching at least a second portion of the substrate to define a second trench portion in the substrate between the first and second portions of the at least one layer, depositing a first dielectric material to fill at least a portion of the first trench portion, and growing a second dielectric material to fill at least a portion of the second trench portion.

In one embodiment, an integrated circuit is provided that includes a substrate, a first portion of a layer formed above the substrate, a second portion of the layer formed above the substrate, and a trench isolation region formed in the substrate between the first and second portions of the layer. The trench isolation region includes a first trench portion and a second trench portion. The second trench portion is at least partially filled with a grown dielectric. The integrated circuit further includes a first sidewall spacer coupled to a first sidewall of the first trench portion and a second sidewall spacer coupled to a second sidewall of the first trench portion.

Other features, aspects, and objects of the invention can be obtained from a review of the specification, the figures, and the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a top view of a NAND string.

FIG. 2 is an equivalent circuit diagram of the NAND string depicted in FIG. 1.

FIG. 3 is a circuit diagram depicting three NAND strings.

FIG. 4 is a two-dimensional block diagram of one embodiment of a flash memory cell that can be fabricated in accordance with one embodiment.

FIG. 5 is a three dimensional drawing of a pair of four word line long portions of two NAND strings that can be fabricated in accordance with one embodiment.

FIGS. 6A-6L depict NAND string stacks in accordance with one embodiment at various stages of a fabrication process in accordance with one embodiment.

FIG. 7 is flowchart of a method of fabricating flash memory cells in accordance with one embodiment.

FIG. 8 is a block diagram of one example of a memory system that can be used to implement the present invention.

FIG. 9 illustrates an example of an organization of a memory array.

FIG. 10 is a flow chart describing one embodiment of a process for programming non-volatile memory devices.

FIG. 11 is a flow chart describing one embodiment of a process for reading non-volatile memory devices.

FIG. 12 is flowchart of a method for fabricating MOS devices in accordance with one embodiment.

DETAILED DESCRIPTION

FIG. 1 is a top view showing one NAND string. FIG. 2 is an equivalent circuit thereof. Trench isolation techniques in accordance with embodiments are presented with respect to nonvolatile flash memory and NAND type memory for purposes of explanation. It will be appreciated by those of ordinary skill in the art, however, that the techniques set forth are not so limited and can be utilized in many fabrication processes to fabricate various types of integrated circuits. For example, these techniques can be used in metal-oxide semiconductor (MOS) technology to isolate devices such as NMOS and PMOS transistors or circuits.

The NAND string depicted in FIGS. 1 and 2 includes four transistors 100, 102, 104 and 106 in series and sandwiched between a first select gate 120 and a second select gate 122. Select gate 120 connects the NAND string to bit line 126. Select gate 122 connects the NAND string to source line 128. Each of the transistors 100, 102, 104 and 106 includes a control gate and a floating gate. For example, transistor 100 has control gate 100CG and floating gate 100FG. Transistor 102 includes control gate 102CG and a floating gate 102FG. Transistor 104 includes control gate 104CG and floating gate 104FG. Transistor 106 includes a control gate 106CG and a floating gate 106FG. Control gate 100CG is connected to word line WL3, control gate 102CG is connected to word line WL2, control gate 104CG is connected to word line WL1, and control gate 106CG is connected to word line WL0.

Note that although FIGS. 1 and 2 show four memory cells in the NAND string, the use of four transistors is only provided as an example. A NAND string can have less than four memory cells or more than four memory cells. For example, some NAND strings will include eight memory cells, 16 memory cells, 32 memory cells, etc.

A typical architecture for a flash memory system using a NAND structure will include several NAND strings. For example, FIG. 3 shows three NAND strings 202, 204 and 206 of a memory array having many more NAND strings. Each of the NAND strings of FIG. 3 includes two select transistors and four memory cells. Each string is connected to the source line by its select transistor (e.g. select transistor 230 and select transistor 250). A selection line SGS is used to control the source side select gates. The various NAND strings are connected to respective bit lines by select transistors 220, 240, etc., which are controlled by select line SGD. Each word line (WL3, WL2, WL1 and WL0) is connected to the control gate of one memory cell on each NAND string forming a row of cells. For example, word line WL2 is connected to the control gates for memory cell 224, 244, and 252. As can be seen, each bit line and the respective NAND string comprise the columns of the array of memory cells. In NAND structures, it is necessary to isolate the individual NAND strings and associated storage elements from one another using isolation technology.

FIG. 4 is a two-dimensional block diagram of one embodiment of a flash memory cell such as those depicted in FIGS. 1-3 that can be fabricated in accordance with embodiments. The memory cell of FIG. 4 includes a triple well comprising a P-substrate, an N-well, and a P-well. The P-substrate and the N-well are not depicted in FIG. 4 in order to simplify the drawing. Within P-well 320, are N+doped regions 324, which serve as source/drain regions for the memory cell. Whether N+doped regions 324 are labeled as source regions or drain regions is somewhat arbitrary. Therefore, the N+doped source/drain regions 324 can be thought of as source regions, drain regions, or both.

Between N+doped regions 324 is a channel 322. Above channel 322 is a first dielectric area or layer 330. Above dielectric layer 330 is a conductive area or layer 332 that forms a floating gate of the memory cell. The floating gate, under low-voltage operating conditions associated with read or bypass operations, is electrically insulated/isolated from channel 322 by the first dielectric layer 330. Above floating gate 332 is a second dielectric area or layer 334. Above dielectric layer 334 is a second conductive layer 336 that forms a control gate of the memory cell. In other embodiments, various layers may be interspersed within or added to the illustrated layers. For example, additional layers can be placed above control gate 336, such as a hard mask. Together, dielectric 330, floating gate 332, dielectric 332, and control gate 336 comprise a stack. An array of memory cells will have many such stacks. As used herein, the term stack can refer to the layers of memory cells at different times during the fabrication process and thereafter. Thus, a stack can include more or fewer layers than depicted in FIG. 4 dependent upon which phase of fabrication the cell is in.

In one type of memory cell useful in flash EEPROM systems, a non-conductive dielectric material is used in place of a conductive floating gate to store charge in a nonvolatile manner. Such a cell is described in an article by Chan et al., "A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device," IEEE Electron Device Letters, Vol. EDL-8, No. 3, March 1987, pp. 93-95. A triple layer dielectric formed of silicon oxide, silicon nitride and silicon oxide ("ONO") is sandwiched between a conductive control gate and a surface of a semi-conductive substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a limited region. This stored charge then changes the threshold voltage of a portion of the channel of the cell in a manner that is detectable. The cell is erased by injecting hot holes into the nitride. See also Nozaki et al., "A 1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application," IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, April 1991, pp. 497-501, which describes a similar cell in a split-gate configuration where a doped polysilicon gate extends over a portion of the memory cell channel to form a separate select transistor. The foregoing two articles are incorporated herein by reference in their entirety. The programming techniques mentioned in section 1.2 of "Nonvolatile Semiconductor Memory Technology," edited by William D. Brown and Joe E. Brewer, IEEE Press, 1998, incorporated herein by reference, are also described in that section to be applicable to dielectric charge-trapping devices. The memory cells described in this paragraph can also be used with the present invention.

Another approach to storing two bits in each cell has been described by Eitan et al., "NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell," IEEE Electron Device Letters, vol. 21, no. 11, November 2000, pp. 543-545. An ONO dielectric layer extends across the channel between source and drain diffusions. The charge for one data bit is localized in the dielectric layer adjacent to the drain, and the charge for the other data bit localized in the dielectric layer adjacent to the source. Multi-state data storage is obtained by separately reading binary states of the spatially separated charge storage regions within the dielectric. The memory cells described in this paragraph can also be used with the present invention.

When programming in tunneling-based, electrically erasable programmable read-only memory (EEPROM) or flash memory devices, a program voltage is typically applied to the control gate and the bit line is grounded. Electrons from the channel are injected into the floating gate as electrons tunnel across dielectric 330. Dielectric 330 is often referred to as a tunnel dielectric or tunnel oxide. When electrons accumulate in floating gate 332, the floating gate becomes negatively charged, and the threshold voltage of the memory cell is raised to one of the threshold voltage distributions pre-defined to represent the storage of one or more bits of data. Typically, the program voltage applied to the control gate is applied as a series of pulses. The magnitude of the pulses is increased with each successive pulse by a predetermined step size.

As previously described, when constructing semiconductor-based integrated circuits, it is necessary to provide isolation between individual devices. In the example of flash memory, it is necessary to electrically isolate select memory cells, such as that depicted in FIG. 4, from other memory cells of the storage array. FIG. 5 is a three-dimensional block diagram of two typical NAND strings 302 and 304 that may be fabricated as part of a larger flash memory array. FIG. 5 depicts four memory cells on strings 302 and 304. However, more or less than four memory cells can be used. Each of the memory cells of the NAND string has a stack as described above with respect to FIG. 4. FIG. 5 further depicts N-well 326 below P-well 320, the bit line direction along the NAND string, and the word line direction perpendicular to the NAND string. The P-type substrate below N-well 336 is not shown in FIG. 5. In one embodiment, the control gates form the word lines. A continuous layer of conductive layer 336 is formed which is consistent across a word line in order to provide a common word line or control gate for each device on that word line.

When fabricating a NAND-based nonvolatile memory system, including NAND strings as depicted in FIG. 5, it is necessary to provide electrical isolation between adjacent strings. For example, NAND string 302 must be electrically isolated from NAND string 304 in order to provide discreet devices with independent electrical characteristics. Isolation of the memory cells on NAND string 302 from the memory cells on NAND string 304 is typically accomplished by providing an electrical barrier between the strings in order to inhibit or prevent parasitic currents and charges between adjacent memory cells.

In the embodiment depicted in FIG. 5, NAND string 302 is separated from NAND string 304 by an open area or void 306. In typical NAND configurations, a dielectric material is formed between adjacent NAND strings and would be present at the position of open area 306. As previously described, many prior art techniques include forming a dielectric isolation region prior to forming the stacks for each memory cell using a LOCOS process, for example.

The ability to provide electrical isolation is often measured in terms of a field threshold. The field threshold represents the amount of charge or current that a particular isolation technique can withstand. For example, an isolation region may provide a 10 volt field threshold such that it can withstand a charge of 10 volts placed across it. In many modern nonvolatile flash memory devices, the charge levels within the circuit are continuing to increase. As device dimensions decrease, the influence of a floating gate over the channel region can decrease. To properly program nonvolatile flash memory devices having such small dimensions, high program voltages are applied to the control gates. For example, in many nonvolatile flash memory devices, a program voltage of 20 volts or more can be applied. Accordingly, it is necessary to provide a field threshold level between NAND strings, equal to or greater than the maximum expected voltage level present in the device. In addition to higher charge levels within devices, the decrease in device dimensions makes it more difficult to provide electrical isolation between devices, given the smaller amount of area within which to isolate the devices. Looking at FIG. 5, as NAND strings 302 and 304 are progressively fabricated closer and closer together, it is more difficult to provide an effective isolation therebetween.

FIGS. 6A-6L depict a sequential process for forming isolation regions between charge storage regions in an integrated circuit in accordance with one embodiment. FIG. 7 is a flow chart depicting a process for forming isolation regions during the fabrication of nonvolatile memory devices such as that depicted in FIGS. 6A-6L. FIGS. 6A-6L and FIG. 7 depict a specific example with respect to a NAND flash memory device. However, it will be appreciated by those of ordinary skill in the art that the techniques described herein are easily extendible to many types of semiconductor devices and can be incorporated with numerous types of fabrication processes. In FIGS. 6A-6L, the bit line direction, relative to the page, runs in and out of the page while the word line direction runs left to right relative to the page.

FIG. 6A depicts a substrate 300 on and in which multiple nonvolatile NAND-type flash memory devices are to be fabricated. Substrate 300 is used generically to represent a substrate, but can also include P-wells and/or N-wells formed therein, as appropriate for various implementations. For example, a P-well and N-well may be formed in substrate 300 as depicted in FIGS. 4 and 5.

At step 402 of FIG. 7, implanting and associated annealing of a triple well including substrate 300 is performed. After implanting and annealing the triple well, a dielectric layer 330 is formed above substrate 300 at step 404. Dielectric 330 can form the tunnel oxide of storage elements. Dielectric layer 330 can include an oxide or other suitable dielectric material in various embodiments. Dielectric layer 330 can be deposited using known chemical vapor deposition (CVD) processes, metal organic CVD processes, physical vapor deposition (PVD) processes, atomic layer deposition (ALD) processes, grown using a thermal oxidation process, or formed using another suitable process. In one embodiment, dielectric 330 is about 70-100 angstroms in thickness. However, thicker or thinner layers can be used in accordance with various embodiments. Additionally (and optionally), other materials may be deposited on, deposited under, or incorporated within the dielectric to form dielectric layer 330.

At step 406, a charge storage layer is deposited on top of the tunnel oxide layer. In FIG. 6B, the charge storage layer is first conductive layer 332 which will comprise the floating gates for the memory devices of the strings being fabricated. In one embodiment, conductive layer 332 is polysilicon deposited using known processes as described above. In other embodiments, other conductive materials can be used. In one embodiment, conductive layer 332 is about 500 angstroms in thickness. However, conductive layers thicker or thinner than 500 angstroms can be used in accordance with embodiments.

The charge storage layer deposited at step 406 can include conductive floating gate materials (e.g., polysilicon) or dielectric charge storage materials (e.g., silicon nitride). If an ONO triple layer dielectric is used, step 404 can include depositing the first silicon oxide layer and step 406 can include depositing the nitride charge storage layer. The second silicon oxide layer can be deposited in later steps to form the inter-gate dielectric (discussed hereinafter).

In one embodiment, a tailored dielectric layer is used and the charge storage regions formed therein. For example, a tailored layer of silicon rich silicon dioxide can be used to trap and store electrons. Such material is described in the following two articles, which articles are incorporated herein in their entirety by this reference: DiMaria et al., "Electrically-alterable read-only-memory using Si-rich SI02 injectors and a floating polycrystalline silicon storage layer," J. Appl. Phys. 52(7), July 1981, pp. 4825-4842; Hori et al., "A MOSFET with Si-implanted Gate-Si02 Insulator for Nonvolatile Memory Applications," IEDM 92, April 1992, pp. 469-472. As an example, the thickness of the layer can be about 500 Angstroms. Steps 404 and 406 can be combined as the tailored dielectric layer will form the tunnel dielectric layer, charge storage layer, and optionally the inter-gate dielectric layer.

After depositing the floating gate or other charge storage layer, a nitride layer 340 is deposited at step 408 and an oxide layer 342 deposited at step 410. These oxide and nitride layers serve as sacrificial layers for various later-performed steps and optionally, can form or form part of the inter-gate dielectric region for the device. Both the oxide and nitride layers can be formed using known processes, and each layer can be about 400 angstroms in thickness. However the thickness of each of these layers can be more or less than 400 angstroms in accordance with various embodiments. Layers 330, 332, 340, and 342 are preliminary NAND string stack layers that are used to form a plurality of devices. Multiple NAND strings will be constructed using these layers as starting layers.

After layers 330, 332, 340, and 342 have been formed, a hard mask can be deposited (step 412) over oxide layer 342 to begin the process of defining the individual NAND strings of the device. After depositing a hard mask over the oxide layer, photolithography can be used to form strips of photoresist over the areas to become the NAND strings. After forming the strips of photoresist, the exposed mask layers can be etched using anisotropic plasma etching, for example.

At step 414, the oxide layer, nitride layer, and floating gate layer are etched using the photoresist and mask to form the individual NAND string stack regions 380, 382, and 384. The result of such a process is depicted in FIG. 6B. FIG. 6B depicts floating gate layer 332, nitride layer 340, and oxide layer 342, after etching to form three distinct preliminary NAND string stack regions that will become individual NAND strings for the memory device. The three NAND string stack regions are adjacent to one another in the word line direction. In one embodiment, step 414 can include etching through all or a portion of dielectric layer 330.

After defining the NAND string stack regions, a layer of oxide is deposited on the exposed surfaces (step 416) to form sidewall spacers for each defined string. After depositing the oxide, it is etched back from substrate 300 to form sidewall spacers 344 for each NAND string. FIG. 6C depicts oxide spacers 344 after having been deposited and etched. Sidewall spacers 344 can include multiple layers in some embodiments. For example, after depositing and etching the oxide, a layer of nitride can be deposited and etched to further define sidewall spacers 344. Dielectric 330 can also be etched at step 416 to expose those areas of substrate 300 outside the spacer and in between the preliminary stack regions. In one embodiment, dielectric 330 is etched to substrate 300 if the dielectric was not etched prior to forming the sidewall spacers.

The sidewall spacers serve as a mask for the trench region etching steps to follow in order to narrow the width of the trench regions that will be formed between adjacent NAND strings in the memory device. For example, the sidewall spacer on NAND string stack region 380 and the adjacent sidewall spacer on NAND string stack region 382 will be used to define a trench region between stack regions 380 and 382.

After forming the sidewall spacers, a first portion for the trench region is formed (step 418) in between adjacent NAND string stack regions by etching into substrate 300 to begin the formation of isolation regions between adjacent NAND strings. FIG. 6D depicts the substrate after etching to form first trench portions 350. The first trench portions have slanted walls which become narrower towards the bottom of the trench. Because of the formation of sidewall spacers 344 prior to etching, the width of the trench can be narrow in comparison to trenches formed using prior art techniques. In one embodiment, trenches 350 are about 1,000 angstroms deep and about 300 angstroms in width at the top. However, it will be understood by those of ordinary skill in the art, that devices of other dimensions can also be constructed in accordance with various embodiments. As illustrated in FIG. 6D, oxide layer 342 serves as a sacrificial layer for the etching process. The thickness of oxide layer 342 is decreased during the etching process.

After forming first trench portions 350, a layer of nitride is deposited on the exposed surfaces (step 420) to begin formation of second sidewall spacers 346 for each defined NAND string and first trench portion. After depositing the nitride, it is etched back from substrate 300 to form second sidewall spacers 346 for each NAND string. FIG. 6E depicts nitride spacers 346 after having been deposited and etched. Sidewall spacers 346 can include multiple layers in some embodiments as previously described. The second sidewall spacers 346 serve as a mask for the second trench portion etching steps to follow. These sidewalls protect the sides of the first trench portions from etching and also narrow the width of the second trench portion