Method and apparatus for calibrating data-dependent noise prediction Number:7,165,000 from the United States Patent and Trademark Office (PTO) owispatent Disclosed herein is an apparatus and method of calibrating the parameters of a Viterbi detector 138 in which each branch metric is calculated based on noise statistics that depend on the signal hypothesis corresponding to the branch. An offline algorithm for calculating the parameters of data-dependent noise predictive filters 304A D is presented which has two phases: a noise statistics estimation or training phase, and a filter calculation phase. During the training phase, products of pairs of noise samples are accumulated in order to estimate the noise correlations. Further, the results of the training phase are used to estimate how wide (in bits) the noise correlation accumulation registers need to be. The taps [t.sub.2.sup.[k],t.sub.1.sup.[k],t.sub.0.sup.[k]] of each FIR filter are calculated based on estimates of the entries of a 3-by-3 conditional noise correlation matrix C.sup.[k] defined by C.sub.ij.sup.[k]=E(n.sub.i-3n.sub.j-3|NRZ condition k).<H calibrating, prediction, Method, and, appa, 7165000.html, Patent, pto, 7165000

Title: Method and apparatus for calibrating data-dependent noise prediction

Abstract: Disclosed herein is an apparatus and method of calibrating the parameters of a Viterbi detector 138 in which each branch metric is calculated based on noise statistics that depend on the signal hypothesis corresponding to the branch. An offline algorithm for calculating the parameters of data-dependent noise predictive filters 304A D is presented which has two phases: a noise statistics estimation or training phase, and a filter calculation phase. During the training phase, products of pairs of noise samples are accumulated in order to estimate the noise correlations. Further, the results of the training phase are used to estimate how wide (in bits) the noise correlation accumulation registers need to be. The taps [t.sub.2.sup.[k],t.sub.1.sup.[k],t.sub.0.sup.[k]] of each FIR filter are calculated based on estimates of the entries of a 3-by-3 conditional noise correlation matrix C.sup.[k] defined by C.sub.ij.sup.[k]=E(n.sub.i-3n.sub.j-3|NRZ condition k).

Patent Number: 7,165,000 Issued on 01/16/2007 to Ashley, et al.

Inventors: Ashley; Jonathan J. (Los Gatos, CA), Stockmanns; Heinrich J. (Santa Cruz, CA)
Assignee: Infineon Technologies AG (DE)

Appl. No.: 11/109,207

Filed: April 18, 2005

Related U.S. Patent Documents


Application Number	Filing Date	Patent Number	Issue Date
10402033	Mar., 2003	6889154
60373877	Apr., 2002

Current U.S. Class: 702/107 ; 375/262; 375/341; 702/190; 702/85; 704/242; 714/795; 714/799

Current International Class: G06F 19/00 (20060101)

Field of Search: 702/85,107,190,196,197 714/795,799 704/242 375/262,341

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Primary Examiner: Tsai; Carol S. W.
Assistant Examiner: Desta; Elias
Attorney, Agent or Firm: Katz; James L. Brinks Hofer Gilson & Lione

Parent Case Text

RELATED APPLICATIONS

This application is a continuation under 37 C.F.R. .sctn. 1.53(b) of U.S. patent application Ser. No. 10/402,033 filed Mar. 28, 2003 now U.S. Pat. No. 6,889,154, the entire disclosure of which is hereby incorporated by reference, which claims the benefit of the filing date pursuant to 35 U.S.C. .sctn.119(e) of Provisional Application Ser. No. 60/373,877, filed Apr. 18, 2002, the disclosure of which is hereby incorporated by reference.

U.S. patent application Ser. No. 10/402,033 incorporated by reference U.S. patent application Ser. No. 10/402,654 "METHOD AND APPARATUS FOR A DATA-DEPENDENT NOISE PREDICTIVE VITERBI", filed Mar. 28, 2003, pending.

Claims

We claim:

1. A detector for deriving a digital representation of an unknown digital data stream from a first digital data stream generated from an analog data stream obtained from an analog medium having a first analog representation of the unknown digital data stream imparted therein, the first digital data stream including first noise data, at least a portion of the first noise data being correlated with at least a portion of the unknown digital data stream, the detector comprising: a filter configurator operative to impart a first known digital data stream in a second analog representation within the analog medium, generate a second digital data stream from the analog data stream obtained from the analog medium based on the second analog representation, the second digital data stream being characterized by second noise data, at least a portion of the second noise data being dependent upon at least a portion of the first known digital data stream, and compare at least a portion of the first known digital data stream with at least a portion of the second digital data stream so as to determine a first correlation between the portion of the second noise data and the portion of the first known digital data stream, the filter configurator being further operative to configure a filter based on the first correlation, the filter, so configured, being operative to substantially remove at least the portion of the first noise data from the first digital data stream prior to the derivation of the digital representation of the unknown data stream.

2. The detector of claim 1 wherein, the filter configurator is further operative to impart a second known digital data stream in a third analog representation within the analog medium, generate a third digital data stream from the analog data stream obtained from the analog medium based on the third analog representation, the third digital data stream being characterized by third noise data, at least a portion of the third noise data being dependent upon at least a portion of the second known digital data stream, and compare at least a portion of the second known digital data stream with at least a portion of the third digital data stream so as to determine a second correlation between the portion of the third noise data and the portion of the second known digital data stream, the filter configuration being further operative to configure the filter based on the first and second correlations.

3. The detector of claim 1, wherein the filter configuration is further operative to configure the filter by computing at least one filter coefficient based on the first correlation.

4. The detector of claim 1 further comprising: a branch metric unit coupled with the filter and operative to compute a branch metric for each of a plurality of states of a trellis data structure based on the first digital data stream, wherein the filter is operative to substantially remove at least the portion of the first noise data from the first digital data stream prior to computing the branch metrics.

5. The detector of claim 1 wherein the filter configuration is operative to configure the filter prior to the derivation.

6. The detector of claim 1 wherein the filter configuration is operative to configure the filter substantially coincident with the derivation.

7. The detector of claim 1 wherein the unknown data stream is characterized by variability, the first noise data being characterized by variability having a correlation to the variability in the unknown data stream.

8. A method for deriving a digital representation of an unknown digital data stream from a first digital data stream generated from an analog data stream obtained from an analog medium having a first analog representation of the unknown digital data stream imparted therein, the first digital data stream including first noise data, at least a portion of the first noise data being correlated with at least a portion of the unknown digital data stream, the method comprising: imparting a first known digital data stream in a second analog representation within the analog medium; generating a second digital data stream from the analog data stream obtained from the analog medium based on the second analog representation, the second digital data stream being characterized by second noise data, at least a portion of the second noise data being dependent upon at least a portion of the first known digital data stream; comparing at least a portion of the first known digital data stream with at least a portion of the second digital data stream so as to determine a first correlation between the portion of the second noise data and the portion of the first known digital data stream; and configuring a filter based on the first correlation, the filter, so configured, being operative to substantially remove at least the portion of the first noise data from the first digital data stream prior to the derivation of the digital representation of the unknown data stream.

9. The method of claim 8 further comprising: imparting a second known digital data stream in a third analog representation within the analog medium; generating a third digital data stream from the analog data stream obtained from the analog medium based on the third analog representation, the third digital data stream being characterized by third noise data, at least a portion of the third noise data being dependent upon at least a portion of the second known digital data stream; comparing at least a portion of the second known digital data stream with at least a portion of the third digital data stream so as to determine a second correlation between the portion of the third noise data and the portion of the second known digital data stream; and configuring the filter based on the first and second correlations.

10. The method of claim 8, wherein the configuring further comprises computing at least one filter coefficient based on the first correlation.

11. The method of claim 8 further comprising: computing a branch metric for each of a plurality of states of a trellis data structure based on the first digital data stream, wherein the filter is operative to substantially remove at least the portion of the first noise data from the first digital data stream prior to the computing of the branch metrics.

12. The method of claim 8 wherein the configuring further comprises configuring the filter prior to the derivation.

13. The method of claim 8 wherein the configuring further comprises configuring the filter substantially coincident with the derivation.

14. The method of claim 8 wherein the unknown data stream is characterized by variability, the first noise data being characterized by variability having a correlation to the variability in the unknown data stream.

15. A detector for deriving a digital representation of an unknown digital data stream from a first digital data stream generated from an analog data stream obtained from an analog medium having a first analog representation of the unknown digital data stream imparted therein, the first digital data stream including first noise data, at least a portion of the first noise data being correlated with at least a portion of the unknown digital data stream, the detector comprising: means for imparting a first known digital data stream in a second analog representation within the analog medium; means for generating a second digital data stream from the analog data stream obtained from the analog medium based on the second analog representation, the second digital data stream being characterized by second noise data, at least a portion of the second noise data being dependent upon at least a portion of the first known digital data stream; means for comparing at least a portion of the first known digital data stream with at least a portion of the second digital data stream so as to determine a first correlation between the portion of the second noise data and the portion of the first known digital data stream; and means for configuring a filter based on the first correlation, the filter, so configured, being operative to substantially remove at least the portion of the first noise data from the first digital data stream prior to the derivation of the digital representation of the unknown data stream.

Description

BACKGROUND

Computer hard disk drives, also known as fixed disk drives or hard drives, have become a de facto standard data storage component of modern computer systems and are making further inroads into modern consumer electronics. Their proliferation can be directly attributed to their low cost, high storage capacity and high reliability, wide availability, low power consumption, high data transfer speeds and decreasing physical size.

These disk drives typically consist of one or more rotating magnetic platters encased within an environmentally controlled housing that further includes all of the electronics and mechanics to read and write data and interface with other devices. Read/write heads are positioned above each of the platters, and typically on each face, to record and read data. The electronics of a hard disk drive are coupled with these read/write heads and include numerous components to control the position of the heads and generate or sense the electromagnetic fields representing data. These components receive data from a host device, such as a personal computer, and translate that data into magnetic encodings written onto the disk platters by the heads. Further, when a host device requests data from the drive, the electronics locates the desired data, senses the magnetic encodings which represent that data and translates those encodings back into the binary digital information which the host device can understand. Further, error detection and correction algorithms are applied to ensure accurate storage and retrieval of data.

One area in which significant advancements have been made has been in the area of read/write head technology and the methods of interpreting the magnetic fluctuations sensed by these heads. The read/write head, of which a typical hard disk has several, is the interface between magnetic platters and the disk drive electronics. The read/write head actually reads and writes the magnetically encoded data as areas of magnetic flux on the platters. Data, consisting of binary 1's and 0's, are encoded by sequences of the presence or absence of flux reversals recorded or detected by the read/write head. A flux reversal is a change in the magnetic flux in two contiguous areas of the disk platter. Traditional hard drives read data off the platters by detecting the voltage peak imparted in the read/write head when a flux reversal passes underneath the read/write head as the platters rotate. This is known as "peak detection." However, increasing storage densities require reduced peak amplitudes and better signal discrimination and higher platter rotational speeds are pushing the peaks closer together thus making peak detection more difficult to accomplish.

Magneto-resistive ("MR") read/write heads have been developed with increased sensitivity to sense smaller amplitude magnetic signals and with increased signal discrimination to address some of the problems with increasing storage density. In addition, another technology, known as Partial Response Maximum Likelihood ("PRML"), has been developed to further address the problems with peak detection as densities and rotational speeds increase. Borrowed from communications technology, PRML is an algorithm implemented in the disk drive electronics to interpret the magnetic signals sensed by the read/write heads. PRML-based disk drives read the analog waveforms generated by the magnetic flux reversals stored on the disk. However, instead of looking for peak values to indicate flux reversals, PRML-based drives digitally sample this analog waveform (the "Partial Response") and use advanced signal processing technologies to determine the bit pattern represented by that wave form (the "Maximum Likelihood"). This technology, in conjunction with magneto-resistive ("MR") heads, have permitted manufacturers to further increase data storage densities. PRML technology further tolerates more noise in the sensed magnetic signals permitting the use of lower quality platters and read/write heads which increases manufacturing yields and lowers costs.

With many different drives available from multiple manufacturers, hard disk drives are typically differentiated by factors such as cost/megabyte of storage, data transfer rate, power requirements and form factor (physical dimensions) with the bulk of competition based on cost. Most competition between hard disk drive manufacturers is coming in the area of cost, hence there is a need for enhanced hard disk drive components which prove cost effective in increasing supplies and driving down manufacturing costs all while increasing storage capacity, operating speed, reliability and power efficiency.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A depicts block diagram of an exemplary hard disk drive coupled with a host device.

FIG. 1B depicts a block diagram of read/write channel for use with the disk drive of FIG. 1A.

FIG. 2 depicts a block diagram of an exemplary Viterbi detector according to one embodiment.

FIG. 3A depicts a block diagram of a Branch Metric Unit for use with the Viterbi detector of FIG. 2 according to one embodiment.

FIG. 3B depicts a block diagram of a FIR filter for use with the Viterbi detector of FIG. 2 according to one embodiment.

FIG. 4 depicts an exemplary graph showing maximum mis-prediction of the Viterbi detector of FIG. 2 according to one embodiment.

FIG. 5 depicts an exemplary graph showing maximum mis-prediction of FIG. 4 as a contour plot.

FIGS. 6 11 depicts exemplary graphs showing the magnitude of any expected noise products in simulation of the Viterbi detector of FIG. 2 according to one embodiment.

FIG. 12 depicts a block diagram of on-chip hardware for implementing the disclosed calibration algorithm according to one embodiment.

DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED EMBODIMENTS

The embodiments described herein relate to a PRML-based read/write channel device for hard disk drive controllers. The read/write channel is a device coupled with the read/write heads of the hard disk drive. Herein, the phrase "coupled with" is defined to mean directly connected to or indirectly connected with through one or more intermediate components. Such intermediate components may include both hardware and software based components. The read/write channel converts binary/digital data from the host device into the electrical impulses which drive the read/write head to magnetically record the data to the disk drive platters. Further, the read/write channel receives the analog waveform magnetically sensed by the read/write heads and converts that waveform back into the binary/digital data stored on the drive.

Referring to FIG. 1A, there is shown a block diagram of an exemplary hard disk drive 100 coupled with a host device 112. For clarity, some components, such as the servo/actuator motor control, are not shown. The drive 100 includes the magnetic platters and spindle motor 102, the read/write heads and actuator assembly 104, pre-amplifiers 106, a read/write channel 108 and a controller 110. The pre-amplifiers 106 are coupled with the read/write channel 108 via interfaces 114, 116. The controller 110 interfaces with the read/write channel 108 via interfaces 118, 120.

For reads from the hard disk 100, the host device 112 provides a location identifier which identifies the location of the data on the disk drive, e.g. a cylinder and sector address. The controller 110 receives this address and determines the physical location of the data on the platters 102. The controller 110 then moves the read/write heads into the proper position for the data to spin underneath the read/write heads 104. As the data spins underneath the read/write head 104, the read/write head 104 senses the presence or absence of flux reversals, generating a stream of analog signal data. This data is passed to the pre-amplifiers 106 which amplifies the signal and passes it to the read/write channel 108 via the interface 114. As will be discussed below, the read/write channel receives the amplified analog waveform from the pre-amplifiers 106 and decodes this waveform into the digital binary data that it represents. This digital binary data is then passed to the controller 110 via the interface 118. The controller 110 interfaces the hard drive 100 with the host device 112 and may contain additional functionality, such as caching or error detection/correction functionality, intended to increase the operating speed and/or reliability of the hard drive 100.

For write operations, the host device 112 provides the controller 110 with the binary digital data to be written and the location, e.g. cylinder and sector address, of where to write it. The controller 110 moves the read/write heads 104 to the proper location and sends the binary digital data to be written to the read/write channel 108 via interface 120. The read/write channel 108 receives the binary digital data, encodes it and generates analog signals which are used to drive the read/write head 104 to impart the proper magnetic flux reversals onto the magnetic platters 102 representing the binary digital data. The generated signals are passed to the pre-amplifiers 106 via interface 116 which drive the read/write heads 104.

Referring to FIG. 1B, there is shown an exemplary read/write channel 108 supporting Partial Response Maximum Likelihood ("PRML") encoding technology for use with the hard disk drive 100 of FIG. 1A. For clarity, some components have been omitted. The read/write channel 108 is implemented as an integrated circuit using a complementary metal oxide semiconductor ("CMOS") process at 0.18 micron. It will be appreciated that CMOS processes include processes which use metal gates as well as polysilicon gates. It will further be appreciated that other process technologies and feature sizes may used and that the circuitry disclosed herein may be further integrated with other circuitry comprising the hard disk electronics such as the hard disk controller logic. As was described, the read/write channel 108 converts between binary digital information and the analog signals representing the magnetic flux on the platters 102. The read/write channel 108 is divided into two main sections, the read path 156 and the write path 158.

The write path 158 includes a parallel-to-serial converter 144, a run-length-limited ("RLL") encoder 146, a parity encoder 148, a write pre-compensation circuit 150 and a driver circuit 152. The parallel-to-serial converter 144 receives data from the host device 112 via interface 120 eight bits at a time. The converter 144 serializes the input data and sends the serial bit stream to the RLL encoder 146. The RLL encoder 146 encodes the serial bit stream into symbolic binary sequences according to a known run-length limited algorithm for recording on the platters 102. The exemplary RLL encoder uses a 32/33 bit symbol code to ensure that flux reversals are properly spaced and that long runs of data without flux reversals are not recorded. The RLL encoded data is then passed to the parity encoder 148 which adds a parity bit to the data. In the exemplary parity encoder 148, odd parity is used to ensure that long run's of 0's and 1's are not recorded due to the magnetic properties of such recorded data. The parity encoded data is subsequently treated as an analog signal rather than a digital signal. The analog signal is passed to a write pre-compensation circuit 150 which dynamically adjusts the pulse widths of the bit stream to account for magnetic distortions in the recording process. The adjusted analog signal is passed to a driver circuit 152 which drives the signal to the pre-amplifiers 106 via interface 116 to drive the read/write heads 104 and record the data. The exemplary driver circuit 152 includes a pseudo emitter coupled logic ("PECL") driver circuit which generates a differential output to the pre-amplifiers 106.

The read path 156 includes an attenuation circuit/input resistance 122, a variable gain amplifier ("VGA") 124, a magneto-resistive asymmetry linearizer ("MRA") 126, a continuous time filter ("CTF") 128, a buffer 130, an analog to digital converter ("ADC") 132, a finite impulse response ("FIR") filter 134, an interpolated timing recovery ("ITR") circuit 136, a Viterbi algorithm detector 138, a parity decoder 140 and a run-length-limited ("RLL") decoder 142. The amplified magnetic signals sensed from the platters 102 by the read/write head 104 are received by the read/write channel 108 via interface 114. The analog signal waveform representing the sensed magnetic signals is first passed through an input resistance 122 which is a switching circuit to attenuate the signal and account for any input resistance. The attenuated signal is then passed to a VGA 124 which amplifies the signal. The amplified signal is then passed to the MRA 126 which adjusts the signal for any distortion created by the recording process. Essentially, the MRA 126 performs the opposite function of the write-pre-compensation circuit 150 in the write path 158. The signal is next passed through the CTF 128, which is essentially a low pass filter, to filter out noise. The filtered signal is then passed to the ADC 132 via the buffer 130 which samples the analog signal and converts it to a digital form. The digital signal is then passed to a FIR filter 134 and then to a timing recovery circuit 136. The timing recovery circuit 136 is connected (not shown in the figure) to the FIR filter 134, the MRA 126 and the VGA 124 in a feedback orientation to adjust these circuits according to the signals received to provide timing compensation. The exemplary FIR filter 134 is a 10 tap FIR filter. The digital signal is then passed to the Viterbi algorithm detector 138 which determines the binary bit pattern represented by the digital signal using digital signal processing techniques. The exemplary Viterbi algorithm detector 138 uses a 32 state Viterbi processor. The binary data represented by the digital signal is then passed to the parity decoder 140 which removes the parity bit and then to the RLL decoder 142 which decodes the binary RLL encoding symbols back into the actual binary data that they represents This data is then passed to the controller 110 via the interface 118.

The read/write channel 108 further includes a clock synthesizer 154. The clock synthesizer 154 generates the clock signals required for operating the read/write channel 108. The exemplary clock synthesizer 154 includes a phased lock loop ("PLL") (not shown) with a voltage controlled oscillator and various clock dividers to generate the necessary frequencies.

In accordance with one preferred embodiment, a method and apparatus for calibrating a noise predictive Viterbi detector 138 is described. The Viterbi detector 138 is a maximum likelihood detector or Viterbi decoder implementing the Viterbi algorithm for analyzing the partial response signal provided by the discrete, equalized signal of the FIR filter 134 and the ITR circuit 136, as illustrated in FIG. 1B and 2. The Viterbi detector 138 generates a digital binary data output signal in response, which is received by the parity decoder 140. In performing maximum likelihood detection, the Viterbi algorithm provides an iterative method for determining the best path along branches of a trellis diagram. The maximum likelihood detection involves analyzing a number of consecutive data samples to determine the most likely path. Thus, by analyzing a number of consecutive samples, the most likely sequence can be chosen. The Viterbi detector 138 implements a predetermined trellis diagram by having a given number of states, wherein for each state, the Viterbi detector 138 determines a branch metric value for each branch entering the state, a state metric value, and a survivor branch. In order to accomplish this task, the Viterbi detector 138 includes a branch metric unit (BMU) 202, an add-compare-select unit (ACSU) 204, and a survivor memory unit (SMU) 206, as illustrated in FIG. 2. An example of one implementation of a Viterbi detector is described in greater detail in a paper entitled "A 100 MBIT/S Viterbi Detector Chip: Novel Architecture And Its Realization," written by Gerhard Fettweis and Heinrich Meyr, presented to the ICC in 1990, in Atlanta, Ga., on Apr. 16 19, 1990, given paper no. 257, at session 307A, the entire disclosure of which is incorporated herein by reference.

For simplicity, the following description of the Viterbi detector 138 will be limited to describing only one state, even though the Viterbi detector 138 may have more than one state, as known by those skilled in the art. In one preferred embodiment, the Viterbi detector is a 32 state detector wherein each state comprises 4 bits.

During a read cycle, the branch metric unit 202 receives a stream of binary digital data 208 from the FIR filter 134 and the ITR circuit 136, determines a branch metric value (Q) for each state at a time k+1, and outputs the branch metric value (Q) for time k+1 within a branch metric signal 210. The branch metric signal 210 includes the branch metric value (Q) for each discrete, equalized value of the binary data 208. The branch metric value (Q) is provided in a binary representation, and has a length of (g) bits. The branch metric value (Q) may be calculated using any one of a number of algorithms commonly used for calculating branch metric values.

The branch metric signal 202 containing the branch metric value (Q) for time k+1 is then input into the ACSU 204 along with a state metric signal (not shown) containing a state metric value (M) for time k. The ACSU 204 includes an adding unit, a comparator, a selector, and a latch, all not shown. At any time k, the state metric value (M) indicates a cost associated with the best path through the trellis diagram to the state, and is therefore a measure for the likelihood of this particular path. Preferably, the state metric value (M) is stored in a memory device, such as the latch (not shown). If a latch is used to store the state metric value (M), the latch must be able to store g+h binary bits.

The adding unit of the ACSU, details not shown in figures, adds the branch metric value (Q) for time k+1 for a given state to the state metric value (M) for time k for a given state to obtain a state metric value (M) for time k+1 for a given state. The state metric value (M) for time k is stored in the latch in the ACSU 204, and received by adding unit. The adding unit outputs the state metric value (M) for time k+1 for a given state to the comparator and the selector. Typically, more than one state metric value (M) for time k+1 exists for any given state, and all these value are output by the adding unit 200. The comparator receives the output of the adding unit containing all the state metric values (M) for time k+1 for a given state and then compares all the state metric values (M) for time k+1 for the given state. The comparator then generates a control input for the selector. Additionally, the comparator outputs a control signal which is received by the SMU 206. The selector receives the control input from the comparator and the output from the adding unit containing all the state metric values (M) for time k+1 for a given state, and selects a state metric value (M) for time k+1, which is then stored in the latch. Preferably, the selector selects the largest state metric value (M) for time k+1 for a given state, and outputs that value to the latch.

The survivor memory unit (SMU) 206 receives and processes the control signal 212 from the ACSU 204, and more particularly from the comparator in the ACSU 234. The SMU 206 processes the signal received from the ACSU 204, and generates a digital binary data output signal in response which is received by the parity decoder 140, as illustrated in FIG. 1B. For more detail, refer to U.S. patent application Ser. No. 09/896,134, entitled "METHOD AND APPARATUS FOR VITERBI DETECTOR STATE METRIC RE-NORMALIZATION", filed Jun. 29, 2001, and incorporated by reference herein.

Disclosed herein is a method of calibrating the parameters of a Viterbi detector 138 in which each branch metric is calculated based on noise statistics that depend on the signal hypothesis corresponding to the branch. For more detail, refer to the above captioned patent application entitled "METHOD AND APPARATUS FOR A DATA-DEPENDENT NOISE PREDICTIVE VITERBI", herein incorporated by reference. While the disclosed embodiments are discussed in relation to Viterbi detectors used in hard disk read channels, it will be appreciated that the disclosed embodiments may also be used with Viterbi detectors utilized for other purposes such as other recording or communications technologies.

The Viterbi detection algorithm for estimating the transmitted signal in noisy received data is well known. The algorithm uses dynamic programming to compute the maximum likelihood estimate of the transmitted signal from the received data, where the likelihood is computed assuming a particular model of the noise statistics in the received data.

In prior Viterbi detectors, the maximum likelihood estimate of transmitted data is computed assuming that the noise is stationary. In particular, it is assumed that the noise is independent of the transmitted signal. This assumption allows a simplified detector, but with stronger correlations between noise and the transmitted signal, the simplified detector's performance increasingly falls below true maximum likelihood performance.

In recording technologies as practiced today, physical imperfections in the representation of recorded user data in the recording medium itself are becoming the dominate source of noise in the read back data. This noise is highly dependent on what was (intended to be) written in the medium. Prior Viterbi detectors, that assume a stationary noise model, cannot exploit this statistical dependence of the noise on the signal.

An exemplary architecture 300 for a branch metric unit 202 for use with a noise predictive Viterbi detector is shown in FIG. 3A. A feature of this architecture 300 is that the branch metrics 306 (and their corresponding square difference operators) are clustered into multiple groups 306A D, where all the members of each group draw input from a single, shared noise predictive filter 304A D corresponding to the group. In the case illustrated, the 32 branch metrics 306 are divided into eight groups, four of which 306A D are shown, each group having four members. For more detail, refer to the above captioned patent application "METHOD AND APPARATUS FOR A DATA-DEPENDENT NOISE PREDICTIVE VITERBI".

An exemplary three tap 310A C FIR filter 304A D for use with the branch metric unit 202 of FIG. 3A is shown in FIG. 3B. The FIR filter 304A D is designed to filter out as much noise from the signal as possible prior to Viterbi processing where the detector tries to figure out what the signal is. The problem is that noise is generally unpredictable as it comes from many different factors. The unpredictable nature of noise makes it difficult to separate the noise from the signal. Typical FIR filters strike a balance between filtering as much noise as possible and ensuring that only a minimal amount of the signal is lost in the process. If the noise being looked for can be predicted, it becomes easier to more accurately separate and remove that noise from the signal without compromising the signal.

1 Overview

An algorithm for calculating the parameters, such as optimized filter coefficients, of data-dependent noise predictive filters 304A D is presented. The algorithm has two phases: a noise statistics estimation or training phase and a filter calculation phase. The training phase is typically performed using hardware built into the read channel device 108, as will be described below. Alternatively, training may be performed using off-chip hardware and/or software or a combination of off-chip and on-chip hardware and/or software. During the training phase, products of pairs of noise samples are accumulated in order to estimate the noise correlations. During this phase, the read channel device 108 acts as a noise statistic measurement tool which acquires noise statistics while reading back "known" data from the disk drive 100 as would be done during normal operation. These noise statistic measurements are then provided to external hardware and/or software to perform the calculation phase of the disclosed calibration method, as described below. Typically, the read channel device 108 is instructed by an external device to perform such measurements. In one embodiment, the hard disk drive 100 including the read channel device 108 further includes a micro-controller 110 which, in addition to the hardware and/or software/firmware to operate the drive 100, includes hardware and/or software/firmware to calibrate the read channel device 108 as described. The micro-controller 110 controls the read channel device 108 to acquire the necessary statistic samples and perform the calculations as described below. In an alternate embodiment, the read channel device 108 itself contains the hardware and/or software necessary to perform self-calibration.

The calculation phase is typically performed off-chip, i.e. not on the read channel device 108, and is described in below. The calculation phase may be performed by any device capable of performing the requisite computations and capable of interfacing with the read channel device 108 to receive the measured noise statistics and provide the computed Viterbi parameters. In one embodiment, as described above, the calculation phase is performed by the micro-controller 110 of the hard disk drive 100 which includes the read channel device 108.

Further, calibration, including both the training and calculation phases, is typically performed during manufacturing of the device, such as a hard disk drive 100, which will include the read channel device 108. During manufacture of a particular hard disk drive 100, the optimal parameters for the noise predictive Viterbi detector of that drive are determined, as disclosed. Once these parameters are determined, they are stored in the drive 100 in some form of non-volatile storage which permits the parameters to be downloaded into the read channel device 108 during operation. In one alternative device, the read channel device 108 itself provides non-volatile storage to store these parameters. In yet another alternative device, hardware to support both the training and calculation phases for calibration is provided to permit calibration in the field, periodic re-calibration of an installed device and/or real time adaptive calibration.

The question of how much training is enough is also considered below. Further, the results of the training phase are used to estimate how wide (in bits) the noise correlation accumulation registers need to be. Finally, a minimal implementation to support the calibration algorithm for the read channel device 108 of FIG. 1B is presented.

2 Calculating the Taps

In a noise-predictive version of a FIR filter, each branch metric is the sum of two squared noise sample estimates: the earlier, and the later. Each noise sample is the difference between the output of a noise-predictive FIR and an expected ideal output. The taps [t.sub.2.sup.[k],t.sub.1.sup.[k],t.sub.0.sup.[k]] of each FIR are calculated based on estimates of the entries of 3-by-3 conditional noise correlation matrix C.sup.[k] defined by: C.sub.ij.sup.[k]=E(n.sub.i-3n.sub.j-3|NRZ condition k).

Here, the Non-Return to Zero ("NRZ") bit string b.sub.1-q . . . b.sub.-1b.sub.0 forming the data hypothesis is indexed by k=b.sub.1-q+2b.sub.2-q+ . . . +2.sup.q-1 b.sub.0. The final bit b.sub.0 of the hypothesis is the last NRZ bit on which the expected ideal FIR signal output depends.

The taps for the noise-predictive filter conditioned on k are given, up to a scalar multiple, by the solution u.sup.[k] to the two equations

.times..alpha..times..times..times. ##EQU00001## where .alpha.>0 is determined shortly.

The notation u.sup.[k] is used for the tap weight vector rather than the t.sub.i.sup.[k] notation we used in the description of the online algorithm. There are two reasons for this change. First, u.sup.[k] is the ideal (real-valued) solution to the equations. It has not been scaled or quantized as the actual taps are. Second, the order of the indices is reversed: u.sub.i.sup.[k] corresponds to

##EQU00002##

The solution u.sup.[k] is given by the formula

.DELTA..times..times..function. ##EQU00003##

where .DELTA.=det (C.sup.[k]) and x.sub.ij is the ij-th cofactor of the matrix C.sup.[k], specifically,

##EQU00004## It follows that .alpha.= {square root over (.DELTA./x33)}. 3 How Much Training? Mis-prediction

The accuracy of the noise prediction done under data condition k depends on the accuracy of the calculation of the tap vector u.sup.[k], which in turn depends on the accuracy of the training estimate of the conditional noise correlation matrix C.sup.[k]. Roughly speaking, the more samples averaged to estimate C.sup.[k], the more accurate the noise prediction based on this estimate will be. The discussion below quantifies this statement.

Let C.sup.[k] be the empirical estimate of C.sup.[k] calculated by averaging N (what is assumed to be independent) samples of each random noise product n.sub.i-3n.sub.j-3. Let u.sup.[k] be the corresponding solution to equations 1 and 2. Then the expected square of the difference between 1. the predicted noise using u.sup.[k], and 2. the predicted noise using the ideal taps u.sup.[k]is m.sup.2=(u.sup.[k]-u.sup.[k]).sup.TC.sup.[k](u.sup.[k]-u.sup.[k]).

This formula is re-casted in terms of the covariance of the random vector u.sup.[k]. Spectrally decompose the positive definite matrix C.sup.[k] as

.times..lamda..epsilon. .times..epsilon. ##EQU00005## where .epsilon..sub.l is the right eigenvector of C.sup.[k] for eigenvalue .lamda..sub.l>0. Then

.times..lamda. .function..times..epsilon. .times..times..epsilon. .times..times. .times..lamda. .times..times..epsilon. .times..times..times..times..times..times..epsilon. ##EQU00006##

Now u.sup.[k] is a random variable we are using to estimate u.sup.[k]. Define U=E.sub.off((u.sup.[k]-u.sup.[k])(u.sup.[k]-u.sup.[k]).sup.T), where the notation off to the expectation operator is added to emphasize that the expectation is taken over the ensemble of random (offline) training sessions. Then the expression for the expected square prediction error becomes

.function. .times..lamda. .times..times..epsilon. .times..times..times..times..epsilon. ##EQU00007##

One could estimate U directly, running the training algorithm many times, each time estimating C.sup.[k] using an average of many noise product samples. To save simulation time, an estimate of U is calculated indirectly based on (a much smaller number of) simulations. Here is the method. Denote the entries of C.sup.[k] by c.sub.ij. Then u.sup.[k] is calculated based on the random vector .gamma.=[c.sub.11, c.sub.22,c.sub.33, c.sub.12, c.sub.23, c.sub.13].

By accumulating the products (n.sub.3-in.sub.3-j) (n.sub.3-kn.sub.3-l) during simulation, the 6-by-6 matrix .GAMMA. of expectations E.sub.off(c.sub.ij-c.sub.ij)(c.sub.kl-c.sub.kl) can be estimated. By approximating the function u: .sup.6.fwdarw..sup.3 defined by equation 3 above (that maps the six correlation estimates c.sub.ij to the corresponding tap vector u.sup.[k]) by the first order Taylor expansion based at the vector .gamma..sub.0 corresponding to C.sup.[k], the approximation U.apprxeq.(.differential.u/.differential..gamma.).sup.T.GAMMA.(.different- ial.u/.differential..gamma.) is determined where .differential.u/.differential..gamma. is the 6-by-3 matrix of partial derivatives .differential.u.sub.i.sup.[k]/.differential.c.sub.kl evaluated at the point .gamma..sub.0.

Now how E.sub.off(m.sup.2) depends on the number N of samples used for training is analyzed. One will recall that c.sub.ij is the average of N samples from the random variable {tilde over (c)}.sub.ij=n.sub.3-in.sub.3-j having mean c.sub.ij. Assuming these samples are independent, it is determined that

.times..times..times..times..times..times. .times..times. .times..times..function..times..times..times..times. .times..times. ##EQU00008##

So defining .GAMMA..sub.0 to be the 6-by-6 matrix with entries E.sub.off({tilde over (c)}.sub.ij-c.sub.ij) ({tilde over (c)}.sub.kl-c.sub.kl), then .GAMMA.=(1/N).GAMMA..sub.0. Setting U.sub.0=(.differential.u/.differential..gamma.).sup.T.GAMMA..sub.0(.diffe- rential.u/.differential..gamma.) then U.apprxeq.(1/N )U.sub.0, and defining m.sub.0 by

.times..lamda. .times..times..epsilon. .times..times..times..times..epsilon. .times..times..apprxeq..times..times..times. .times..lamda. .times..times..epsilon. .function..differential..differential..gamma..times..times..GAMMA..functi- on..differential..differential..gamma..times..times..epsilon. ##EQU00009##

Both .GAMMA..sub.0 and C.sup.[k] can be accurately estimated with a few thousand noise samples. The spectral decomposition of C.sup.[k] can then be calculated and used along with the estimate of .GAMMA..sub.0 to calculate m.sub.0.sup.2.

Finally, the expected square noise at the square noise output s.sup.[k] of what we called a "square difference operator" in the description of the online detection algorithm is shown to be 1+m.sub.0.sup.2/N. Ideally, the expected square should be 1, so it seems reasonable to measure the expected dB cost in Signal-to-Noise-Ratio ("SNR") due to mis-prediction as 10 log.sub.10(1+m.sub.0.sup.2/N).

The online expectation (due to runtime noise) of s.sup.[k], where s.sup.[k] is calculated using the taps u.sup.[k], is E.sub.on(s.sup.[k])=(u.sup.[k]).sup.TC.sup.[k] u[k]. So

.times..times..times..times..times..times..times..times..times..times..tim- es..times. .times..lamda. .times..times..epsilon. .times..times..times..times..times..times..epsilon. .times..lamda. .times..times..epsilon. .times..times..times..times..times..times..times..times..epsilon. ##EQU00010##

Decomposing u.sup.[k]=(u.sup.[k]-u.sup.[k])+u.sup.[k], and assuming E.sub.offu.sup.[k]=u.sup.[k], the product u.sup.[k](u.sup.[k]).sup.T is broken up into four terms, so that the above expression becomes

.times..times..times..times..lamda..times..di-elect cons..times..function..times..di-elect cons..times..times..lamda..times..di-elect cons..times..times..di-elect cons..times..times..times..times..times..apprxeq..times. ##EQU00011## as was desired to show.

The above method is used to estimate m.sub.0.sup.2 from simulations for various combinations of total SNR and media noise share. FIG. 4 graphs the maximum mis-prediction m.sub.0.sup.2 over the 32 NRZ hypotheses, as a function of the media noise share for the six SNRS 13, 14, up to 18. FIG. 5 presents the same data as a contour plot.

For small values of the mis-prediction, the expected dB cost .delta. of mis-prediction can be approximated by

.delta..times..times..times..times..times..times. ##EQU00012##

For example, if m.sub.0.sup.2=4, in order to achieve .delta.=0.01, the number of training samples must be approximately

.times..times..apprxeq. ##EQU00013##

Equation 4 shows that the number of training samples N needed to achieve a given expected mis-prediction dB cost target .delta. is proportional to the mis-prediction m.sub.0.sup.2.

4 Bit Width of Accumulators

This section combines the results of Section 3 estimating the number of noise product samples needed to achieve a given expected mis-prediction cost with simulation estimates of expected noise product magnitudes to calculate necessary bit widths for the six noise product accumulators.

In the previous section, it was calculated that at m.sub.0.sup.2=4, in order to achieve an expected mis-prediction dB cost of 0.01, approximately N=1737 noise product samples are needed.

At an input SNR of 13 dB, the maximum magnitude of any expected noise product is approximately 68, as is shown in FIGS. 6 through 11 (actually the maximum magnitude is achieved by the expected noise squares). To provide scale, recall that the ideal PR4 equalized signal takes on the three values {-32, 0, +32}.

Thus, under the pessimistic scenario of m.sub.0.sup.2=4 and an SNR of 13 dB, we need at least 1+.left brkt-top.log.sub.2(68).right brkt-bot.+.left brkt-top.log.sub.2(1737).right brkt-bot.=19 bits to represent the accumulated square noise. Notice that we took separate ceiling terms for the two factors 68 and 1737 because, almost certainly, the number N of accumulated samples will be a power to two (2.sup.11 in this case).

This estimate would decrease by 1 bit for every 3 dB increase in SNR.

Also, 1 bit could be dropped from accumulators tailored for off-diagonal products as shown in FIGS. 9 through 11.

Bit Width of Noise Bias Accumulators

The (un-squared) noise samples can safely be saturated to the integer range [-32, 31] (where the PR4 signal is normalized to take on the three values {-32, 0, 32}). Even at 9 dB SNR at the PR4 equalized signal, this gives .+-.4 standard deviations of play, since the noise variance at this SNR is about 64 least significant bits ("LSBs"). Enough noise samples should be accumulated to push the variance in the mean well below 1 LSB. For this, an accumulator width of 10+6 bits would suffice.

It is recommended that the unrounded accumulation results be available off-chip as input to the off-chip tap calculation algorithm.

5 On-board Calibration Support

Referring to FIG. 12, the minimal on-board hardware needed to support the calibration algorithm is described. In one embodiment, this hardware is used by a filter tap coefficient generator algorithm 1312 (hardware, software/firmware or a combination thereof) executed by the micro-controller 110 to measure noise statistics and compute the filter coefficients as described above. A critical issue in the calibration algorithm is the alignment between the three noise samples (n.sub.i-2, n.sub.i-l, n.sub.i) and the condition block of NRZ bits b.sub.i-3b.sub.i-2b.sub.i-lb.sub.i(in the case of q=4) or b.sub.i-2b.sub.i-lb.sub.i(in the case q=3). As a notation, the NRZ data bits b.sub.i, the noise samples n.sub.i the noisy PR4 data samples r.sub.i, and the ideal PR4 data samples {tilde over (r)}.sub.i are indexed so that r.sub.i={tilde over (r)}.sub.i+n.sub.i, and {tilde over (r)}.sub.i=32(b.sub.i-b.sub.i-2).

For each NRZ data condition c.sub.-q+1 . . . c.sub.-1c.sub.0, nine distinct statistics are accumulated: the three noise samples n.sub.i-2, n.sub.i-l, n.sub.i; and their six possible products n.sub.i-2.sup.2, n.sub.i-2n.sub.i-1, n.sub.i-2n.sub.i, n.sub.i-1.sup.2, n.sub.i-1n.sub.i and n.sub.i.sup.2; where i is an index at which the NRZ data (the Pseudo Random Bit Sequence ("PRBS") pattern has b.sub.i-q+1 . . . b.sub.i-lb.sub.i=c.sub.-q+1 . . . c .sub.-1c.sub.0.

An algorithm to do this that employs that least possible on-chip support would accumulate only one of the nine statistics for only one of the 2.sup.q data conditions on any one data-read operation. The same written data would be reread 92.sup.q times, each time accumulating one of the nine statistics at one of the 2.sup.q NRZ conditions.

To support this scheme, at bare minimum, the following on-chip hardware may be provided for use/control by the micro-controller 110, or other external calibration hardware and/or software, as shown in FIG. 12.

Linear Feedback Shift Register ("LFSR") 1302

An LFSR 1302 is needed to generate the periodic PRBS pattern of NRZ bits synchronized with the read-back data. The PRBS pattern is used in two distinct ways: (1) to generate ideal data values {tilde over (r)}.sub.i=32(b.sub.i-b.sub.i-2) 1316 used to subtract from the ITR 136 output r.sub.i 1314 to leave the noise samples n.sub.i=r.sub.i-{tilde over (r)}.sub.i; 1318 and (2), to drive a `condition selector` 1304 that zeroes out all samples 1318 feeding the accumulator 1308 except the samples aligned with a given NRZ condition.

Condition Selector 1304

The condition selector 1304 contains a q-bit register c.sub.cond to hold any one of the 2.sup.q NRZ condition blocks c.sub.-q+1 . . . c.sub.-1c.sub.0. The output of the condition selector 1304 is a single-bit signal 1320 that flags bit cycles i at which the NRZ data pattern matches the NRZ condition block: b.sub.i-q+1 . . . b.sub.i-1b.sub.i=c.sub.-q+1 . . . c.sub.-1c.sub.0. The flag 1320 is used to enable the addition of a corresponding noise statistic (one of the nine mentioned above) into a `statistic accumulator` 1308. In one embodiment, the NRZ condition block is read as a static input parameter, and responsibility of cycling through the 2.sup.q values is performed by the microcontroller 110.

Statistic Selector 1306

The statistic selector 1306 selects which of the nine noise statistics described above is to be accumulated and performs the required multiplication of two noise samples to generate the product terms of the noise statistics. In one embodiment, the microcontroller 110 cycles through the nine settings.

Statistic Accumulator 1308

The statistic accumulator 1308 is an accumulator wide enough to accommodate the `biggest` of the nine statistics (see Section 4 above for a calculation of this width). At a minimum, an overflow condition should be flagged and made available to the micro-controller 110. A more flexible `halt at fill line` scheme would involve a threshold, which would be set to some value below the capacity of the accumulator 1308 (In one embodiment, at 1/2.sup.n of its capacity). When the magnitude of the accumulated result exceeds this value, a process is set in motion to halt the accumulation before overflow occurs. At the same time, a `statistic counter` 1310 is halted so that the counter's 1310 value records the number of samples that have been accumula