Title: Method and system of lithography using masks having gray-tone features
Abstract: A method forms patterns on a substrate by exposing the substrate a first time and exposing the substrate a second time using a mask containing gray-tone features. The gray-tone features locally adjust an exposure dose in regions corresponding to features defined in the primary exposure. Moreover, the gray-tone features enable the forming of features having different critical dimensions on a substrate. The gray-tone features may be sub-resolution features and formed by pixellation. The trim mask containing gray-tone features may have regions with different transmissivities.
Patent Number: 6,884,551 Issued on 04/26/2005 to Fritze, et al.
| Inventors:
|
Fritze; Michael (Acton, MA);
Tyrrell; Brian (Pawtucket, RI)
|
| Assignee:
|
Massachusetts Institute of Technology (Cambridge, MA)
|
| Appl. No.:
|
234783 |
| Filed:
|
September 4, 2002 |
| Current U.S. Class: |
430/5 |
| Intern'l Class: |
G03F 009//00 |
| Field of Search: |
430/5,311,394
716/19,21
|
References Cited [Referenced By]
U.S. Patent Documents
| 4902899 | Feb., 1990 | Lin et al.
| |
| 5415835 | May., 1995 | Brueck et al.
| |
| 5635316 | Jun., 1997 | Dao.
| |
| 5674650 | Oct., 1997 | Dirksen et al.
| |
| 5858580 | Jan., 1999 | Wang et al.
| |
| 6114071 | Sep., 2000 | Chen et al.
| |
| 6238850 | May., 2001 | Bula et al.
| |
| 6312854 | Nov., 2001 | Chen et al.
| |
| 6420073 | Jul., 2002 | Suleski et al.
| |
| 6466373 | Oct., 2002 | Pforr et al.
| |
| 2001/0041306 | Nov., 2001 | Cole et al.
| |
| 2002/0045136 | Apr., 2002 | Fritze et al.
| |
| 2002/0177047 | Nov., 2002 | Park.
| |
| Foreign Patent Documents |
| WO 0125852 | Apr., 2001 | WO.
| |
Other References
"Simulation Assisted Design of Processes for Gray-tone Lithography," Henke et
al. Microelctronic Engineering. 1995. vol. 27. p. 267-270.
"Refractive Micro Lens Made of Dichromate Gelatin with Gray-Tone Photolithography,"
Yao et al. Microelectronic Engineering. 2001. vol. 57-58. p. 729-735.
|
Primary Examiner: Rosasco; S.
Attorney, Agent or Firm: Gauthier & Connors LLP
Goverment Interests
SPONSORSHIP INFORMATION
This invention was made with government support under Contract Number F19628-00-C-0002
awarded by the Air Force. The government has certain rights in the invention.
Parent Case Text
CROSS-REFERENCE TO RELATED PROVISIONAL APPLICATION
The present patent application claims priority under 35 U.S.C. §119 from
U.S. Provisional Patent Application Ser. No. 60/361,612 filed on Mar. 4, 2002.
The entire contents of U.S. Provisional Patent Application Ser. No. 60/361,612
filed on Mar. 4, 2002 are hereby incorporated by reference.
Claims
1. A method of forming a pattern of fine features on a substrate, comprising:
(a) forming a pattern of fine features of a critical dimension on a substrate;
and
(b) trimming the pattern of fine features formed on the substrate by exposing
the substrate using a mask containing gray-tone features to modify the critical
dimension of the fine features.
2. The method as claimed in claim 1, wherein said (a) consists of photolithographically
exposing the substrate.
3. The method as claimed in claim 1, wherein said (a) consists of interferometrically
exposing the substrate.
4. The method as claimed in claim 1, wherein said (a) consists of pattern formation
using an imprint method.
5. The method as claimed in claim 1, wherein said (a) is performed using a photomask.
6. The method as claimed in claim 5, wherein the photomask is a phase shift mask.
7. The method as claimed in claim 6, wherein the phase shift mask has regions
that shift the relative phase of the transmitted light by different phase angles.
8. The method as claimed in claim 7, wherein the relative phase angle corresponding
to each region is between +180 degrees and -180 degrees, inclusive.
9. The method as claimed in claim 6, wherein the phase shift mask is a strong
phase shift mask.
10. The method as claimed in claim 6, wherein the phase shift mask is a weak
phase shift mask.
11. The method as claimed in claim 5, wherein the photomask has regions with
different transmissivities.
12. The method as claimed in claim 11, wherein the transmissivity of each region
is between one and zero, inclusive.
13. The method as claimed in claim 5, wherein the photomask is a binary photomask.
14. The method as claimed in claim 1, wherein said (b) consists of photolithographically
exposing the substrate using a gray-tone mask.
15. The method as claimed in claim 1, wherein the mask containing gray-tone features
is a photomask.
16. The method as claimed in claim 1, wherein the mask containing gray-tone features
has regions with different transmissivities.
17. The method as claimed in claim 16, wherein the transmissivity of each region
is between one and zero, inclusive.
18. The method as claimed in claim 1, wherein the gray-tone features on the mask
containing gray-tone features are formed using pixellation.
19. The method as claimed in claim 1, wherein the gray-tone features on the mask
containing gray-tone features are sub-resolution features, which when exposed produce
regions of varying intensity at the substrate plane.
20. The method as claimed in claim 19, wherein the sub-resolution features are
features that are not resolvable for a particular configuration of an exposure system.
21. The method as claimed in claim 19, wherein a partial coherence of an exposure
system is detuned, thereby allowing for larger sub-resolution features on the mask.
22. The method as claimed in claim 19, wherein a numerical aperture of an exposure
system is decreased, thereby allowing for larger sub-resolution features on the mask.
23. The method as claimed in claim 1, wherein an exposure system's parameters
are separately optimized for said (a) and said (b).
24. The method as claimed in claim 1, wherein the substrate includes a resist layer.
25. The method as claimed in claim 24, wherein at a substrate plane, the combined
exposure dose corresponding to said (a) and said (b) locally causes a reaction
in the resist layer.
26. The method as claimed in claim 25, wherein the reaction in the resist layer
is dependent on the combined exposure dose.
27. The method as claimed in claim 26, wherein the reaction in the resist layer
is used to form features in the resist layer.
28. The method as claimed in claim 27, wherein each feature in the resist layer
has a desired critical dimension.
29. The method as claimed in claim 27, wherein features of multiple critical
dimensions are desired on the substrate.
30. The method as claimed in claim 27, wherein a critical dimension of each feature
is determined by the design of the gray-tone mask.
31. The method as claimed in claim 27, wherein features in the resist layer correspond
to transistor gates.
32. The method as claimed in claim 27, wherein features in the resist layer correspond
to interconnect features.
33. The method as claimed in claim 27, wherein features in the resist layer correspond
to contact features.
34. The method as claimed in claim 27, wherein features in the resist layer correspond
to via features.
35. The method as claimed in claim 27, wherein features in the resist layer correspond
to isolation features.
36. The method as claimed in claim 24, wherein the resist layer is a positive
resist layer.
37. The method as claimed in claim 24, wherein the resist layer is a negative
resist layer.
38. The method as claimed in claim 5, wherein the photomask includes regular features.
39. The method as claimed in claim 38, wherein the photomask includes regular
dense features.
40. The method as claimed in claim 5, wherein the photomask includes locally
regular features.
41. The method as claimed in claim 40, wherein the photomask includes locally
regular dense features.
42. A method of designing a mask in which a primary exposure is assumed, comprising:
(a) placing gray-tone features on a layout of the mask to locally adjust an exposure
dose in regions corresponding to fine features defined in the primary exposure
so as to modify a critical dimension of the fine features defined in the primary
exposure; and
(b) placing other features on the layout of the mask.
43. The method as claimed in claim 42, wherein features defined in the primary
exposure are partially defined.
44. The method as claimed in claim 42, wherein the primary exposure uses a phase
shift mask.
45. The method as claimed in claim 42, wherein locally adjusting the exposure
dose results in a local adjustment of critical dimension.
46. The method as claimed in claim 44, wherein the phase shift mask includes
gray-tone features.
47. The method as claimed in claim 46, wherein the gray-tone features are formed
by pixellation.
48. The method as claimed in claim 46, wherein the gray-tone features are regions
with different transmissivities.
49. The method as claimed in claim 48, wherein the transmissivity of each region
is between one and zero, inclusive.
50. The method as claimed in claim 46, wherein the gray-tone features correspond
to regions with sub-resolution features, which when exposed produce regions of
varying intensity at a substrate plane.
51. The method as claimed in claim 50, wherein the sub-resolution features are
features that are not resolvable for a particular configuration of an exposure system.
52. The method as claimed in claim 42, wherein said placing gray-tone features
on a layout of the mask to locally adjust an exposure dose in regions corresponding
to fine features defined in the primary exposure removes fine features defined
in the primary exposure.
53. A trim mask comprising:
gray-tone features to modify a critical dimension of fine features defined in
a primary exposure.
54. The trim mask as claimed in claim 53, wherein the trim mask is designed for
use in a multiple exposure lithography method.
55. The trim mask as claimed in claim 53, wherein a position of said gray-tone
features on the trim mask is a function of the position of fine features on a separate
fine feature definition mask.
56. The trim mask as claimed in claim 53, wherein said gray-tone features are
produced by pixellation.
57. The trim mask as claimed in claim 53, wherein said gray-tone features are
regions with different transmissivities.
58. The trim mask as claimed in claim 57, wherein the transmissivity of each
region is between one and zero, inclusive.
59. The trim mask as claimed in claim 53, wherein said gray-tone features correspond
to regions with sub-resolution features, which when exposed produce regions of
varying intensity at a substrate plane.
60. The trim mask as claimed in claim 59, wherein the sub-resolution features
are features that are not resolvable for a particular configuration of an exposure system.
61. The method as claimed in claim 44, wherein the phase shift mask is a strong
phase shift mask.
62. The method as claimed in claim 44, wherein the phase shift mask is a weak
phase shift mask.
63. The method as claimed in claim 1, wherein said (a) uses an exposure dose
above a resist exposure threshold.
64. The method as claimed in claim 1, wherein said (a) uses an exposure dose
below a resist exposure threshold.
65. The method as claimed in claim 1, wherein said (b) uses an exposure dose
above a resist exposure threshold.
66. The method as claimed in claim 1, wherein said (b) uses an exposure dose
below a resist exposure threshold.
67. The trim mask as claimed in claim 53, wherein said gray-tone features remove
fine features defined in a primary exposure.
68. A method of forming a fine feature, having a critical dimension, on a substrate, comprising:
(a) exposing the substrate using a trim mask containing gray-tone features to
modify the critical dimension of the fine feature.
69. The method as claimed in claim 68, wherein said (a) consists of photolithographically
exposing the substrate using a gray-tone mask.
70. The method as claimed in claim 68, wherein the trim mask containing gray-tone
features is a photomask.
71. The method as claimed in claim 68, wherein the trim mask containing gray-tone
features has regions with different transmissivities.
72. The method as claimed in claim 71, wherein the transmissivity of each region
is between one and zero, inclusive.
73. The method as claimed in claim 68, wherein the gray-tone features on the
trim mask containing gray-tone features are formed using pixellation.
74. The method as claimed in claim 68, wherein the gray-tone features on the
trim mask containing gray-tone features are sub-resolution features, which when
exposed produce regions of varying intensity at the substrate plane.
75. The method as claimed in claim 74, wherein the sub-resolution features are
features that are not resolvable for a particular configuration of an exposure system.
76. The method as claimed in claim 68, wherein said exposing the substrate using
a trim mask containing gray-tone features removes fine features.
77. A mask set for a process for providing patterns on a substrate, comprising:
a fine feature mask containing a pattern of dense fine features, each fine feature
having a critical dimension; and
a trim mask containing gray-tone features to modify the critical dimension of
the fine features so as to produce multiple trimmed patterns of fine features.
78. The mask set as claimed in claim 77, further comprising:
an additional mask or set of masks to provide additional features with the imaging
substantially independent of the previous exposures.
79. The mask set as claimed in claim 77, wherein said fine feature mask contains
a pattern of regular dense features.
80. The mask set as claimed in claim 77, wherein said fine feature mask contains
a pattern of dense features of a predetermined pitch and critical dimension.
81. The mask set as claimed in claim 77, wherein said gray-tone features on said
trim mask correspond to transistor gates located on a regular pattern.
82. The mask set as claimed in claim 77, wherein said gray-tone features on said
trim mask correspond to hole or pillar features located on a regular pattern.
83. The mask set as claimed in claim 77, wherein said gray-tone features on the
trim mask correspond to interconnect segments located on a regular pattern.
84. The mask set as claimed in claim 77, wherein said gray-tone features on said
trim mask correspond to transistor gates located on a regular pattern.
85. The mask set as claimed in claim 77, wherein said gray-tone features on said
trim mask correspond to hole or pillar features located on an optically dense feature pattern.
86. The mask set as claimed in claim 77, wherein said gray-tone features on the
trim mask correspond to interconnect segments located on an optically dense feature pattern.
87. The mask set as claimed in claim 78, wherein said additional mask or set
of masks includes a fine feature mask containing a pattern of dense features of
a predetermined pitch and critical dimension and a trim mask containing gray-tone
features to produce multiple trimmed patterns of fine features.
88. The mask set as claimed in claim 77, wherein said fine feature mask is replaced
by an interferometric pattern.
89. The mask set as claimed in claim 77, wherein said trim mask containing gray-tone
features removes fine features.
90. A mask set for a process for providing patterns of fine features, having
a critical dimension, on a substrate, comprising:
a fine feature mask; and
a trim mask containing gray-tone features to modify the critical dimension of
the fine features so as to produce multiple trimmed patterns of fine features.
91. The mask set as claimed in claim 90, further comprising:
an additional mask or set of masks to provide additional features with the imaging
substantially independent of the previous exposures.
92. The mask set as claimed in claim 90, wherein said gray-tone features on said
trim mask correspond to transistor gates located on a regular pattern.
93. The mask set as claimed in claim 90, wherein said gray-tone features on said
trim mask correspond to hole or pillar features located on a regular pattern.
94. The mask set as claimed in claim 90, wherein said gray-tone features on said
trim mask correspond to interconnect segments located on a regular pattern.
95. The mask set as claimed in claim 90, wherein said gray-tone features on said
trim mask correspond to transistor gates located on a regular pattern.
96. The mask set as claimed in claim 90, wherein said gray-tone features on said
trim mask correspond to hole or pillar features located on an optically dense feature pattern.
97. The mask set as claimed in claim 90, wherein said gray-tone features on said
trim mask correspond to interconnect segments located on an optically dense feature pattern.
98. The mask set as claimed in claim 90, wherein said fine feature mask is replaced
by an interferometric pattern.
99. The mask set as claimed in claim 90, wherein said trim mask containing gray-tone
features removes fine features.
100. A method of forming a pattern on a substrate, comprising:
(a) imprinting a pattern of fine features, having a critical dimension, on a
substrate; and
(b) exposing the substrate to change the critical dimension of the fine features
of the imprinted pattern.
101. The method as claimed in claim 100, wherein (b) photolithographically exposes
the substrate.
102. The method as claimed in claim 100, wherein (b) exposes the substrate using
a trim mask.
103. The method as claimed in claim 101, wherein the trim mask is a gray-tone mask.
104. The method as claimed in claim 102, wherein features on the gray-tone mask
are regions of various transmissivities.
105. The method as claimed in claim 102, wherein features on the gray-tone mask
are pixellated regions.
106. The method as claimed in claim 102, wherein features on the gray-tone mask
are sub-resolution features.
107. The method as claimed in claim 1, wherein said trimming the pattern of fine
features formed on the substrate by exposing the substrate using a mask containing
gray-tone features removes fine features.
108. The method as claimed in claim 100, wherein said exposing the substrate
removes fine features of the imprinted pattern.
Description
FIELD OF THE PRESENT INVENTION
The present invention is directed to fabrication methods, such as double exposure
lithography, which initially form a pattern on a substrate and then trims the formed
pattern. More particularly, the present invention is directed to a process and
methodology of controlling feature critical dimension using gray-tone mask features.
BACKGROUND OF THE PRESENT INVENTION
Conventional optical projection lithography has been the standard silicon
patterning technology for the past 20 years. It is an economical process due to
its inherently high throughput, thereby providing a desirable low cost per part
or die produced. A considerable infrastructure (including steppers, photomasks,
resists, metrology, etc) has been built up around this technology.
In this process, a mask, or "reticle", includes a semiconductor circuit layout
pattern typically formed of opaque chrome, on a transparent glass (typically SiO
2)
substrate. A stepper includes a light source and optics/lenses that project light
coming through the reticle and image the circuit pattern, typically with a 4×
to 5× reduction factor, on a photo-resist film formed on a silicon wafer.
The term chrome refers to an opaque masking material that is typically but not
always comprised of chrome. The transmission of the opaque material may also vary
such as in the case of an attenuating phase shift mask.
FIG. 1 is an example of a conventional optical projection lithography apparatus.
As illustrated in FIG. 1, the optical projection lithography apparatus includes
a light source 20, a photomask 22, and reduction optics 24.
A wafer 26, having a layer of photo-resist 28 thereon, is placed
within the optical projection lithography apparatus, and the light-source 20
generates a beam of light 21 that is incident upon the photomask 22.
The reduction optics 24 projects the light beam to cause a pattern 30
that exposes the photo-resist layer 28, creating the pattern 30 of
reacted material in the resist layer 28. In this manner, a pattern 32,
provided on the mask 22, is transferred to the photo-resist layer 28
on the wafer 26.
The photo-resist pattern 30 is then transferred to the underlying wafer
26 through standard etching processes using standard semiconductor fabrication
techniques. Both positive and negative tone resists can be used to produce either
positive or negative images of the mask pattern on the wafer.
An example of a phase shift mask is illustrated in FIGS. 2 and 3. As illustrated
in FIGS. 2 and 3, a dense-feature mask example 220 is a phase-shift mask
comprising a grating pattern of periodic features. It is noted that a dense grating
pattern is only one example of a dense-feature mask. FIGS. 2 and 3 are top and
side views, respectively, of the phase-shift mask 220. The phase-shift mask
220 may be formed of, for example, fused SiO
2. Periodic trenches
23 are formed in the mask 220 to provide an interference pattern
upon illumination that results in the desired photoresist pattern 30 on
the wafer 26.
In the chromeless phase shift mask 220, periodic features or trenches 23
are typically etched into the transparent mask material, which is typically quartz.
The depth of these etched features 23 results in a relative phase difference
in the illumination that is transmitted on either side of a phase boundary 36.
When the relative phase difference is 180 degrees, an interference null corresponding
to the phase edge 36 is produced at the image plane, which is typically
the wafer or substrate 26. It is noted that chromeless phase shift masks
illustrated here are only one type of phase shift mask. There are many other types
of phase shift masks.
As the semiconductor industry continues to evolve and grow, feature sizes of
the
pattern are driven to an ever-smaller resolution. The driving force is the desire
of these industries to remain on the "Moore's Law" growth curve. The "Moore's Law"
growth curve calls for an exponential increase of circuit density versus production
year that is typically accomplished by decreasing feature sizes. However, the resolution
of an optical stepper is limited by the wavelength of the light source, and is
further limited by the numerical aperture ("NA") of the lens.
The basic lithographic imaging relationships are:
1) Resolution=k
1λ/NA; and
2) Depth of Focus=k
2 λ/(NA)
2;
where λ is the illumination wavelength, NA is the lens numerical aperture,
and k
1 and k
2 are process constants.
In general, a shorter wavelength light source and/or a higher numerical aperture
lens afford a higher-resolution system. State-of-the-art light sources provide
a beam having a wavelength of approximately 193 nanometers. As stated above, the
semiconductor industry has been driving the need for critical feature sizes to
decrease exponentially over time, while exposure light source wavelengths have
only been decreasing linearly with time.
Carrying this scenario forward, current and future optical lithography will
be required to image feature sizes of sub-wavelength dimensions. Sub-wavelength
optical lithography has been introduced with the 180-nm Node device generation,
fabricated using 248-nm optical lithography.
As noted above, the numerical aperture of the lens also drives resolution. In
this field, the cost of lenses having very high numerical apertures ("NA") approaching
0.9 to 1.0 is very high. Moreover, linear NA increases are not sufficient to maintain
pace with the need for exponentially decreasing feature sizes.
To meet this demand, Resolution-Enhanced optical lithography Technologies ("RET")
have become popular as techniques for providing patterns with sub-wavelength resolution.
These methods include off-axis illumination ("OAI"), optical proximity correction
("OPC"), and phase-shift masks ("PSMs"). Such resolution-enhanced optical lithography
methods are especially useful for generating physical devices on a wafer that require
small size and tight design tolerance. Examples of such physical devices are the
gate length of a transistor or the dimensions of contact cuts formed in inter-layer
dielectrics. However, the conventional RET methods face problems of layout complexity
and data size, mask fabrication complexity and resulting cost, and optical proximity
and spatial frequency effects which are discussed below.
In many circuit applications, it is an important design constraint that the respective
sizes of the narrow lines are consistent throughout the circuit. For example, in
a semiconductor device, the narrow lines may form transistor gates, and it is important
that the transistor gates are similar in size so that the circuit has consistent
and predictable gate delay values.
In general, in any optical lithography technique, the resulting optical image
intensity is a function of the proximity of features. Contrast is lost as feature
pitch values decrease. As a result, the resulting size of features located in densely
populated regions can be different than the size for those features that are isolated
from the densely populated features. This is known as the "optical proximity" effect.
With respect to optical proximity effect, the critical dimension of features
depends on feature density. Moreover, optical proximity effects can become more
severe in sub-wavelength lithography. The optical proximity effects can result
in dense lines 261 and an isolated line 262 on wafer 26 being
printed with different sizes, even if the same size on the mask, as illustrated
in FIG. 4, or dense contacts 263 and an isolated contact 264 on wafer
26 being printed with different sizes, even if the same size on the mask,
as illustrated in FIG. 5. Since the performance of the circuit depends on
the size and size tolerance of the gates, this is an undesirable result.
Spatial frequency effects are caused by the "low-pass filter" behavior of
a projection lithography lens wherein high spatial frequencies do not pass through
the lens. This results in corner rounding and line end shortening. An example of
this effect is illustrated in FIG. 6. As illustrated in FIG. 6, a desired
image is represented by mask 2200, but the actual image pattern 265
on the wafer is shortened and rounded.
To compensate for optical proximity and spatial frequency effects, additional
features have been conventionally introduced on the mask that can involve both
printable as well as sub-resolution elements. In these methods, extra features
such as serifs, mousebites, hammerheads, and scattering bars are added to the mask
features in order to correct for optical proximity effects and other spatial frequency
effects. These conventional methods involve sophisticated algorithms with very
large data size, as different corrections are required for each separation distance
between the features. For this reason, conventional feature size correction ("OPC"
or optical proximity correction) is a costly and time-consuming process.
Conventional OPC generally involves the processing of an enormous data
volume. The hierarchical data processing algorithms used for conventional circuit
design are of limited utility because optical proximity effects are based on the
nature of geometries surrounding a particular circuit element. For example, a 1×
AND gate surrounded by registers on all sides will perform differently than a 1×
AND gate surrounded by other 1× AND gates. Other examples of conventional
lithography methods addressing the need for finer features or higher-resolution
features will be discussed below.
U.S. Pat. No. 5,415,835-B1 ("Brueck et al.") discusses a method of fine-line
imaging based on laser interferometry. In Brueck et al., dense gratings formed
by laser interferometry are customized by additional exposures using both interferometric
and conventional lithography. Brueck et al.does not address optical proximity and
spatial frequency effect problems thus limiting the ultimate density and flexibility
of the patterns produced. In addition, the multiple exposures are not substantially
independent in the optical sense due to the resist's "memory" of previous exposure
patterns. It is also difficult to make an arbitrary two-dimensional pattern in
this way.
EP-0915384-A2 ("Suzuki et al.") expands upon interferometric lithography.
Suzuki et al.discloses using interferometric one-dimensional gratings to realize
fine-line lithography together with subsequent customization exposures using multiplex
(sub-threshold) exposure doses. Suzuki et al.does not address optical proximity
and spatial frequency effect problems thus limiting the ultimate density and flexibility
of the patterns produced. The multiple exposures are not substantially optically
independent due to the resist's "memory" of the previous exposures. It is also
difficult to realize an arbitrary 2D pattern with this method. Since the fine features
are only realized in one orientation, it is difficult to form patterns with fine
features in both the x & y directions.
WO-1/06320-A1 ("Levenson") discloses re-usable "master" fine feature
phase-shift masks that can be customized by multiple exposure methods using conventional
masks. Levensondiscloses a "trade-off between a maximum density of features against
the cost for low volume runs". Thus, the target application is primarily ASIC and
thin-film head patterns where the pattern density is not too great. Just as in
the previous Patents discussed above, this method does not mitigate optical proximity
and spatial frequency effects. It does not include substantially independent multiple exposures.
Finally, U.S. Pat. No. 6,184,151-B1 ("Adair et al.") discloses a method
for forming square shape images wherein a first plurality of lines running in a
first direction is defined in a first layer, and then a second resist is defined
wherein the lines run in an intersecting pattern to those of the first layer, thereby
creating sharp corners wherever the first and second layers intersect and in open
areas between the lines. This process addresses the spatial frequency effect problems
of corner rounding and line-end shortening, but does not resolve the optical proximity
effect problem. The control of fine features through pitch is important in order
to realize the maximum pattern density and flexibility for applications.
One of the most common commercial implementations of phase shift mask technology
is the double exposure method. In this method, the critical features are imaged
using a phase shift mask and the non-critical and trim features are imaged in a
second exposure using a conventional chrome-on-glass mask.
An example of a double exposure phase shift method is illustrated in FIG. 7.
Double exposure imaging has become an accepted method in the field of resolution
enhancement lithography.
In this method, fine features 42 are typically imaged on the substrate
26 in the first exposure, using a phase shift mask 31, and definition
of other features 204 and trimming of undesired phase edges are performed
in a second exposure using a trim mask 38. The phase shift mask may contain
additional opaque features 203.
A typical double exposure phase shift method uses a conventional chrome-on-glass
binary photomask for the trim mask 38. In this case, chrome regions 40
on the trim mask 38 prevent desired features produced by the phase shift
mask 31 from being exposed in the trim exposure.
Multiple critical dimensions are typically formed by varying the width of
a chrome regulator structure 201 placed at each phase edge 36, as
is illustrated in the mask of FIGS. 8 and 9.
More specifically, an alternating aperture phase shift mask, which has chrome
regulators at each phase edge, is illustrated in FIGS. 8 and 9. FIG. 8 is a top
view and FIG. 9 is a cross sectional view. Unlike the chromeless phase shift mask,
the alternating aperture phase shift mask 122 has chrome regulators 201
placed at each phase edge 36.
Phase shift masks work by employing the principle of destructive interference
of light to generate fine dark lines in photoresist. A phase shift photomask is
typically made of quartz (SiO
2) in which features are etched to a depth
corresponding to a 180-degree phase difference for the illumination light wavelength
used. The equation for determining etch depth for optimum destructive interference is:
where d is the etch depth, λ is the exposure wavelength and n is the
index of refraction of the glass mask at the exposure wavelength.
Upon illumination by the lithography apparatus as shown in FIG. 1, each feature
edge 36 forms a fine dark line in the photoresist 28. Note that since
these dark line features correspond to phase boundaries 36, these dark line
features are topologically closed which has lead to the development of double exposure
phase shift methods in order to trim away the undesired fine lines in a second exposure.
In this process, the critical features are imaged using a phase shift mask and
noncritical and trim features are imaged in a second exposure using a conventional
chrome-on-glass mask. One of the challenges of this approach is the imaging of
a variety of near minimum width feature sizes, by varying widths of chrome regulator
features at each phase transition.
As feature sizes continue to scale into the deep sub-wavelength regime, it becomes
more difficult to fabricate multiple sizes of critical dimension features by varying
chrome regulator width. In addition, state of the art chromeless phase shift lithography
methods, which are capable of the largest resolution enhancement, cannot be used
to image multiple fine feature critical dimensions in a single die.
Another example of a double exposure method is disclosed in U.S. Pat. No.
5,858,580 (Wang et al.). Wang et al. discloses creating a phase shifting mask and
a structure mask for shrinking integrated circuit designs. One disclosed embodiment
includes using a two-mask process. The first mask is a phase shift mask and the
second mask is a single-phase structure mask. The phase shift mask primarily defines
regions requiring phase shifting. The single-phase structure mask primarily defines
regions not requiring phase shifting. The single-phase structure mask also prevents
the erasure of the phase shifting regions and prevents the creation of undesirable
artifact regions that would otherwise be created by the phase shift mask.
As feature sizes continue to move ever deeper into the sub-wavelength regime,
it becomes increasingly difficult to image a variety of critical dimensions using
this method. In addition, chromeless phase shift masks, which have great resolution
enhancement potential, cannot be used to image multiple critical dimensions.
The methods discussed above are also applicable to the case where fine features
are defined using interferometric processes or using nanoimprint processes. In
interferometric technology, a substrate is exposed interferometrically, using two
or more coherent illumination sources to generate an interference pattern on the
substrate. In nanoimprint technology, a topographic pattern on a master template
is transferred to a substrate by direct mechanical contact.
It is therefore desirable to develop a method that mitigates optical proximity
and spatial frequency effects without adding complex optical proximity correction
features to the mask, while preserving the resolution enhancement aspects required
by sub-wavelength lithography. This is especially desirable since conventional
optical proximity correction approaches are becoming quite difficult to implement
as imaging requirements continue to move deeper into the sub-wavelength regime.
It is also desirable to eliminate basic optical proximity effects, involving
the
defining or forming of fine lines in the x and y directions through a variety of
pitch values and to minimize spatial frequency effects such as corner rounding
and line-end shortening.
It is further desirable to simplify circuit layout and mask fabrication, resulting
in lower cost and substantially decreased data volume required for a typical design,
thereby allowing for design of standard cells that can be accurately characterized
independently of their eventual placement in a larger circuit.
Moreover, it is desirable to develop a method that incorporates sub-resolution
features to allow for lithographic definition of features with locally variable
critical dimension, which can be used in a variety of lithographic processes, such
as phase shift lithography, interferometric lithography, or nanoimprint technology.
It is also desirable to provide local control of the effective exposure dose
that
defines the critical dimension of the feature so that a wide variety of small features
can be imaged without the need for chrome regulators or additional exposures.
Lastly, it is desirable to develop a method that incorporates sub-resolution
features to allow for lithographic definition of features with locally variable
critical dimension, which can be used in customizing a master pattern on an individual
substrate wherein the master pattern was formed using a master template and nanoimprint technology.
SUMMARY OF THE PRESENT INVENTION
One aspect of the present invention is a method of forming a pattern on a substrate.
The method forms a pattern on a substrate and exposes the substrate using a mask
containing gray-tone features.
Another aspect of the present invention is a method of designing a mask in
which a primary exposure is assumed. The method places gray-tone features on a
layout of the mask to locally adjust an exposure dose in regions corresponding
to features defined in the primary exposure and places other features on the layout
of the mask.
A further aspect of the present invention is a trim mask having gray-tone features.
A fourth aspect of the present invention is a method of forming a feature having
a critical dimension on a substrate. The method exposes the substrate using a mask
containing gray-tone features.
A fifth aspect of the present invention is a mask set for a process for providing
patterns on a substrate. The mask set includes a fine feature mask containing a
pattern of dense features and a trim mask containing gray-tone features to produce
multiple trimmed patterns of fine features.
A sixth aspect of the present invention is a method of forming a random contact
array on a substrate. The method exposes the substrate to provide a pattern of
dense contact features of a predetermined pitch and critical dimension and exposes
the substrate with a trim mask containing gray-tone features to provide multiple
trimmed patterns on the substrate, the trimmed patterns including both densely
populated and sparsely populated regions of features, the critical dimension of
the features in the densely populated regions and sparsely populated regions being
substantially independent of feature density.
A seventh aspect of the present invention is a mask set for a process for providing
patterns on a substrate. The mask set includes a fine feature mask and a trim mask
containing gray-tone features to produce multiple trimmed patterns of fine features.
An eighth aspect of the present invention is a method of forming patterns on a
substrate. The method produces fine features using nanoimprint methods and exposes
the substrate using a mask containing gray-tone features.
A ninth aspect of the present invention is a computer aided design method for
designing
a mask. The method specifies, through an input of a user, a geometric property
of a desired substrate feature and determines automatically, based upon the user
specified geometric property of the desired substrate feature, mask features for
a gray-tone mask.
A tenth aspect of the present invention is a method of forming a pattern on a
substrate.
The method imprints a pattern on a substrate and exposes the substrate to change
the imprinted pattern.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention may take form in various components and arrangements of
components, and in various steps and arrangements of steps. The drawings are only
for purposes of illustrating a preferred embodiment or embodiments and are not
to be construed as limiting the present invention, wherein:
FIG. 1 is a schematic of a prior art optical projection lithography apparatus;
FIG. 2 is a top view schematic of a chromeless phase shift mask;
FIG. 3 is a cross sectional view of a chromeless phase shift mask;
FIG. 4 is an illustration of an optical proximity effect with respect to fabricating lines;
FIG. 5 is an illustration of an optical proximity effect with respect to fabricating
contact holes or pillars;
FIG. 6 is an illustration of a spatial frequency effect with respect to fabricating lines;
FIG. 7 is a schematic illustration of a prior art double exposure lithography approach;
FIG. 8 is a top view schematic of prior art use of chrome regulators to locally
modify the critical dimension;
FIG. 9 is a cross sectional view of prior art use of chrome regulators to locally
modify the critical dimension;
FIGS. 10-13 are top views of various dense-feature mask pattern configurations
in accordance with the present invention;
FIG. 14 is a top view of a wafer exposed by the dense feature mask of FIG. 10
in accordance with the present invention;
FIG. 15 is a graphical flow diagram illustrating top views of a wafer undergoing
a trimming process in accordance with the present invention;
FIG. 16 is a graphical flow diagram illustrating top views of a wafer undergoing
an interconnect process in accordance with the present invention;
FIG. 17 is a top view of trimmed fine features formed according to the technique
of the present invention illustrating the absence of optical proximity effects;
FIG. 18 is a top view of a dense feature mask including both printable features
and sub-resolution features in accordance with the present invention;
FIG. 19 is a graphical flow diagram illustrating a trimming operation performed
on a wafer including solid patterns formed by exposure of the sub-resolution features
of the dense feature mask of FIG. 15; and
FIG. 20 is a graphical flow diagram illustrating the extension of this method
to produce sets of fine features with different orientations and position offsets;
FIG. 21 is a top view schematic of one embodiment of a gray-tone trim mask according
to the concepts of the present invention;
FIG. 22 is a schematic of a double exposure phase shift process using the gray-tone
trim mask of FIG. 21 to locally modify the critical dimension, according to the
concepts of the present invention;
FIG. 23 is a top view schematic of another embodiment of a gray-tone trim mask
according to the concepts of the present invention; and
FIG. 24 is a schematic of a double exposure phase shift process using the gray-tone
trim mask of FIG. 23 to locally modify the critical dimension, according to the
concepts of the present invention.
DETAILED DESCRIPTION OF THE PRESENT INVENTION
The present invention is directed to an imaging approach that overcomes the limitations
of the conventional techniques, and confers a number of advantages. It addresses
the problems of optical proximity and spatial frequency effects while maintaining
the resolution-enhancement performance required by sub-wavelength lithography.
Moreover, the present invention addresses the problems associated with lithographically
defining features with locally variable critical dimension. The present invention
also provides local control of the effective exposure dose that defines the critical
dimension of the feature so that a wide variety of small features can be imaged
without the need for chrome regulators or additional exposures.
In the following description, the phrase, "lines," refers to either the trenches
or the raised areas; e.g., plateaus; on a wafer. Moreover, the phrase, "contacts,"
refers to either the holes or pillars on a wafer. The described photoresists may
either be a negative tone or a positive tone. The descriptions are applicable to
either positive or negative imaging of the wafer or substrate.
With respect to spatial frequency effects and optical proximity effects, any
image that is lithographically exposed can be thought of in Fourier space, where
components of various spatial frequencies sum to form the complete image. The lens
acts as a low-pass filter because it has a finite aperture. Spatial frequency effects
cause corner rounding and line-end shortening because higher diffraction orders
are filtered out. Optical proximity effects cause the same features spatially apart
from each other on a substrate to realize a size differential even though these
features were formed using the same mask feature size. This effect is typically
described quantitatively in terms of critical dimension versus pitch.
Lastly, the phrase, "dense features," refers to an area on the substrate
having a multitude of features positioned very closely to each other.
In describing the concepts of the present invention below, examples primarily
directed to double exposure photolithography have been used. However, it is noted
that the various below described concepts of the present invention are also applicable
to the case where fine features are defined using interferometric processes or
using nanoimprint processes. In interferometric technology, a substrate is exposed
interferometrically, using two or more coherent illumination sources to generate
an interference pattern on the substrate. In nanoimprint technology, a topographic
pattern on a master template is transferred to a substrate by direct mechanical contact.
In the present invention, a mask is provided including a dense repetitive structure
of features that results in a large array of densely populated features on the
film or substrate. The pattern of dense features may be locally or globally periodic.
The mask is designed to print dense features near the resolution limit of the lithography
stepper used, thus defining a pattern "grid." The minimum width features (such
as transistor gates and contacts) are laid out on this grid. The allowed feature
grid locations are integer multiples of the minimum grid pitch.
Using this mask, the substrate is exposed to provide a pattern of regular dense
features of a predetermined pitch and critical dimension. Following this first
dense feature formation exposure, a trimming exposure is performed to remove any
unwanted pattern features.
It is noted that a pattern of regular dense features of a predetermined pitch
and critical dimension can be formed using interferometric lithography, and a trimming
exposure is performed, thereafter, to remove any unwanted pattern features.
It is further noted that the present invention may utilize a template and nanoimprinting
to create a pattern of dense features having a predetermined pitch and critical
dimension, the pattern of dense features may be locally or globally periodic. In
this embodiment, a trimming exposure is performed to remove any unwanted pattern features.
Optionally, an additional exposure is performed, adding further features
as well as interconnecting the previously formed features to form a circuit. This
exposure is substantially independent of the previous exposures, thus minimizing
effects such as spatial frequency effects (corner rounding and line end shortening).
For example, when using less general dense fine feature masks, only two exposures
are necessary: dense-grating and trim. On the other hand if a simple one-dimensional
grating mask is used, three exposures are required: dense-grating, trim, and interconnect.
In addition to the grid layout restriction, this particular embodiment also requires
the minimum width features to be oriented in the same direction.
In the present invention, all small features are generated using the exact same
density optical image patterns; and therefore, maximum consistency between features
is established. The small features may comprise gates of transistors or contact
holes. Small features are thus produced without the proximity effects realized
by the conventional techniques using simple, reusable dense-grating masks. Customized
and less expensive trimming masks can then be used to complete the desired pattern
as well as interconnect the circuit components.
In this manner, only a single dense-grating is required for generating any of
a number of different circuits and patterns. The re-usability of the dense-grating
mask is desirable since this is often the most difficult and expensive mask to
fabricate. This is especially true if the dense grating mask is a phase-shift mask.
A phase-shift mask is capable of imaging dense features very close to the Rayleigh
limit for optical projection steppers. (Pitch
MIN=0.5λ/(NA)). Dense
regular patterns also are routinely obtained using interference lithography.
As noted above, FIG. 1 is a schematic block diagram of a conventional optical
projection lithography apparatus. The conventional optical projection lithography
apparatus includes a light source
20, a photomask
22, and reduction
optics
24. A wafer
26 having a layer of photoresist
28 is
presented to the conventional optical projection lithography apparatus, and the
light-source
20 generates a beam of light
21 that is incident upon
the photomask
22 and reduced by reduction optics
24 to cause a pattern
30 to be exposed in the photoresist layer
28. In this manner, a pattern
32 provided on the mask
22 is transferred to the photoresist layer
28 on the wafer
26.
In a preferred embodiment of the present invention, the dense-feature mask
220
is a phase-shift mask comprising a grating pattern of periodic features. FIGS.
2 and 3 are top and side views, respectively, of a phase-shift mask that is a preferred
embodiment of mask
220 used with respect to the present invention. The phase-shift
mask
220 may be formed of, for example, fused SiO
2. Periodic
trenches
23 are formed in the mask
220 to provide an interference
pattern upon illumination that results in the desired photoresist pattern
30
on the wafer
26.
Although a simple one-dimensional mask grating is shown in FIGS. 2 and 3,
the present invention is applicable to phase-shift masks of a variety of patterns.
The present invention is also applicable to other types of phase-shift masks such
as alternating aperture (AAPSM) or attenuating phase-shifters (APSM).
A more detailed discussion of these phase-shift masks is set forth in co-pending
U.S. patent application Ser. No. 09/952,185, filed on Sep. 13, 2001, entitled "Method
Of Design And Fabrication Of Integrated Circuits Using Regular Arrays And Gratings."
The entire contents of U.S. patent application Ser. No. 09/952,185, filed on Sep.
13, 2001, are hereby incorporated by reference.
With reference to FIGS. 10-13, the line features
23A,
23B, and
23C can be formed in a variety of configurations. In the configuration of
FIG. 10, horizontal line features
23A of mask
2203 are formed parallel
to each other in the X-direction, while in FIG. 11, vertical line features
23B
of mask
2204 are formed parallel to each other in the Y-direction. The mask
shown in FIG. 12 includes features formed in a horizontal orientation
23A
in a first region of the mask
2205 and features formed in a vertical orientation
23B in a second region of the mask
2206.
Note, however, that in alternative embodiments, the features may be formed
in other patterns, including locally regular patterns. For example, in the mask
of FIG. 13, a unique feature pattern
23C is employed. Other such unique
combinations of patterns are applicable to the present invention.
FIG. 14 is a top view of the resulting pattern formed on the wafer
26,
assuming exposure by the dense feature mask
2203 of FIG. 10. A plurality
of periodic thin lines
34 of photoresist material is formed on the wafer
26 (in the case of a positive resist). A preferred embodiment of the present
invention produces these grating features with a phase-shift mask; however it is
noted that the present invention may also use interferometric or imprint definition
processes to produce these grating features.
As noted above, the present invention is directed to fabricating physical structures
on a substrate or wafer. FIGS. 15 and 16 graphically illustrate a process for forming
these structures according to the concepts of the present invention.
As shown in FIG. 15, a wafer or substrate
26 is exposed using a grating
31 which including a line pattern
34 to provide a pattern of regular
dense lines or features of a predetermined pitch and critical dimension on the
substrate
26. Thereafter, a trim mask
38, which may include gray-tone
features, is exposed on the wafer
26.
It is noted that a pattern of regular dense lines or features of a predetermined
pitch and critical dimension on substrate
26 can be formed using interferometric
lithography, and a trimming exposure, using trim mask
38 that may include
gray-tone features, is performed, thereafter, on the wafer
26 to remove
any unwanted pattern features.
It is further noted that the present invention may utilize a template and nanoimprinting
to create a pattern of dense lines or features having a predetermined pitch and
critical dimension on substrate
26, the pattern of dense features may be
locally or globally periodic. In this embodiment, a trimming exposure, using trim
mask
38 that may include gray-tone features, is performed on the wafer
26
to remove any unwanted pattern features or to customize the wafer
26.
For example, in the case of transistors having a consistent, narrow gate length,
the gate length of each transistor corresponding to the width of each line, trim
features
40 are formed on the customized trim mask
38 and exposed
on the wafer
26 at corresponding locations
41 to form a resulting
trimmed pattern
42, comprising a plurality of transistors of equal gate
length along their critical dimension. In this manner, a standardized and relatively
inexpensive dense fine feature mask can be used to form the critical dimension
of the transistor length under tight tolerance conditions.
This is combined with the customized trim mask
38, which may contain
gray-tone features, of relatively loose tolerance constraints to provide a trimmed
pattern
42 on the wafer
26. A certain degree of misalignment can
be tolerated on the trim mask
38 along with oversize and undersize error
in the trim features
40, as well as exposure error. These loose tolerance
constraints are acceptable because of the often relatively wide pitch, or distance,
between centers of the narrow feature lines
34 and loose tolerance constraints
are typical of trim exposures. Additionally, the critical dimension, width, of
the feature lines
42 is not determined by the trim-mask features
40.
It is generally easier to erase existing features than to accurately place new
features. Thus, the present invention is especially amenable to applications involving
a dense array of features at a minimal critical dimension.
Following formation of the trimmed pattern
42 on the wa
