Method for calibrating semiconductor test instruments Number:7,111,490 from the United States Patent and Trademark Office (PTO) owispatent

Title: Method for calibrating semiconductor test instruments

Abstract: A method for calibrating a semiconductor test instrument leading cost reduction, simplified work, and short working time. Drivers are related to comparators in one-to-one correspondence. A clock signal and a strobe signal have a one-to-one correspondence. The phase of either a clock signal or a strobe signal is adjusted with reference to the phase of the other signal. The relative phase difference between clock signals or between strobe signals are determined. The phases of the clock and strobe signals are adjusted with reference to the relative phase difference.

Patent Number: 7,111,490 Issued on 09/26/2006 to Ibane

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Inventors:	Ibane; Toru (Tokyo, JP)
Assignee:	Advantest Corporation (Tokyo, JP)
Appl. No.:	11/352,096
Filed:	February 11, 2006

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Related U.S. Patent Documents

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	Application Number	Filing Date	Patent Number	Issue Date
	10479726		7043959
	PCT/JP02/05604	Jun., 2002

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Foreign Application Priority Data

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Jun 07, 2001 [JP]			2001-172210
Feb 07, 2002 [JP]			2002-30576
Mar 19, 2002 [JP]			2002-75316

Current U.S. Class:	73/1.42
Current International Class:	G01R 35/00 (20060101)
Field of Search:	73/1.42 324/766

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References Cited [Referenced By]

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U.S. Patent Documents

	4929888		May 1990		Yoshida
	5894081		April 1999		Ashuri
	6327678		December 2001		Nagal
	6417682		July 2002		Suzuki et al.
	6570397		May 2003		Mayder et al.
	6812727		November 2004		Kobayashi
	2006/0123878		June 2006		Ibane
	2006/0123879		June 2006		Ibane
	2006/0123880		June 2006		Ibane
	2006/0123882		June 2006		Ibane

Foreign Patent Documents

	10061962		Mar., 2002		DE
	919823		Jun., 1999		EP
	63-015179		Jan., 1988		JP
	02-062983		Mar., 1990		JP
	04-127073		Apr., 1992		JP
	04-225180		Aug., 1992		JP
	8-226957		Sep., 1996		JP
	9-80118		Mar., 1997		JP
	2638274		Apr., 1997		JP
	11-190760		Jul., 1999		JP
	11-287844		Oct., 1999		JP
	2000-199781		Jul., 2000		JP
	2000-31464		Nov., 2000		JP
	2001-183432		Jul., 2001		JP
	2002-139556		May., 2002		JP

Primary Examiner: Noland; Thomas P.
Attorney, Agent or Firm: Dellett & Walters patenttm.us

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Claims

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The invention claimed is:

1. A method for calibrating a semiconductor test instrument having drivers for generating signals synchronizing with clock signals and comparators for performing comparisons synchronizing with strobe signals, comprising: a first step of adjusting phases of said clock signals corresponding to an in-group common driver by using one of said drivers included in each group as the in-group common driver on the basis of said strobe signals corresponding to a common comparator by using one of said comparators as the common comparator while said drivers and said comparators are divided into m number of groups so that two or more of said drivers or said comparators are included; a second step of adjusting phases of said strobe signals corresponding to said comparator included in the same group on the basis of said clock signals corresponding to said in-group common driver in each of said m number of groups; and a third step of adjusting phases of said clock signals corresponding to said drivers included in the same group on the basis of said strobe signals corresponding to any one of said comparators in each of said m number of groups.

2. The method for calibrating a semiconductor test instrument according to claim 1, characterized in that the phase adjustment to be executed in said first step is performed by varying phases of said clock signals input to each of the in-group common drivers so that the timing for performing comparison by said common comparator in accordance with said strobe signals coincides with the timing at which a signal output from each of said in-group common drivers and input to said common comparator is changed.

3. The method for calibrating a semiconductor test instrument according to claim 1, characterized in that the phase adjustment to be executed in said second step is performed by varying phases of said strobe signals so that timings for performing comparisons by said comparators in accordance with said strobe signals coincide with timings at which signals output from said in-group common drivers and input to said comparators are changed.

4. The method for calibrating a semiconductor test instrument according to claim 1, characterized in that the phase adjustment to be executed in said third step is performed by varying phase of said clock signals input to said driver so that timings for performing comparisons by said comparators in accordance with said strobe signals coincide with timings at which signals output from said drivers and input to said comparators are changed.

5. The method for calibrating a semiconductor test instrument according to claim 1, characterized in that a delay element for varying the phase of a signal is inserted into each of supply routes of said clock signals to said drivers and each of supply routes of said strobe signals to said comparators.

6. The method for calibrating a semiconductor test instrument according to claim 1, characterized in that said first step is executed by using a first calibration board in which input ends of said comparators and output ends of said in-group common drivers are connected each other through a first common short connection point.

7. The method for calibrating a semiconductor test instrument according to claim 6, characterized in that said second and third steps are executed by using a second calibration board in which output ends of said drivers and input ends of said comparators are connected each other through a second common short connection point for each of said groups.

8. The method for calibrating a semiconductor test instrument according to claim 7, characterized in that lengths of wirings for connecting said drivers with said first and second short connection points and lengths of wirings for connecting said comparators with said first and second short connection points are set so as to be all equalized.

9. The method for calibrating a semiconductor test instrument according to claim 7, characterized in that a fourth step of exchanging said first calibration board with said second calibration board is included between said first step and said second step.

10. The method for calibrating a semiconductor test instrument according to claim 1, characterized in that said first step is executed by using a third calibration board in which the input end of said common comparator and output ends of said in-group common drivers included in said m number of groups are connected to each other through wirings having equal time lengths for all of said groups, and said second and third steps are executed by changing over wiring states of said third calibration board so that output ends of said drivers included in each of said groups and input ends of said comparators are connected to each other through wirings having equal time lengths for all of said groups.

11. The method for calibrating a semiconductor test instrument according to claim 10, characterized in that said third calibration board includes a plurality of changeover switches for changing over wiring states and operations in said first, second and third steps are executed by changing over connection states of these changeover switches.

12. The method for calibrating a semiconductor test instrument according to claim 1, characterized in that said first step is executed by using a first calibration device in which the input end of said common comparator and the output end of said in-group common drivers are connected to each other through a first common short connection point.

13. The method for calibrating a semiconductor test instrument according to claim 12, characterized in that said second and third steps are executed by using a second calibration device in which output ends of said drivers and input ends of said comparators are connected to each other through a second common short connection point for each of said groups.

14. The method for calibrating a semiconductor test instrument according to claim 13, characterized in that a fourth step of exchanging said first calibration device with said second calibration device by a handler is included between said first step and said second step.

15. The method for calibrating a semiconductor test instrument according to claim 1, characterized in that said first step is executed by using a first region in a first calibration wafer in which the input end of said common comparator and output ends of the in-group common drivers are connected to each other through a first common short connection point, and said second and third steps are executed by using a second region in a second calibration wafer in which output ends of said drivers and input ends of said comparators are connected to each other through a second common short connection point for each of said groups.

16. The method for calibrating a semiconductor test instrument according to claim 15, characterized in that said first calibration wafer and said second calibration wafer are the same wafer and said first and second regions are formed in said same wafer.

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Description

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TECHNICAL FIELD

The present invention relates to a method for calibrating a semiconductor test instrument for adjusting operation timings of a driver and a comparator in pin electronics of the semiconductor test instrument.

BACKGROUND ART

The pin electronics of a semiconductor test instrument includes a driver for applying a signal to a device under test and a comparator for determining the logic of a signal output from the device under test correspondingly to the signal. The driver outputs a signal synchronizing with an input clock signal. Moreover, the comparator determines synchronously with an input strobe signal.

In the initial state of the semiconductor test instrument, because the time length of a signal route for each input/output pin of the device under test fluctuates, the timing for outputting a signal from the driver or the determination timing of the comparator shifts from an expected timing. Therefore, timing calibration is applied to the device under test before various tests are executed.

FIG. 73 is an illustration showing a conventional configuration of a semiconductor test instrument for performing timing calibration. In FIG. 73, a semiconductor test instrument 90 is connected to a socket board 94 through an exclusive cable 93 provided for a performance board 92. For example, to apply various tests to a device under test having a BGA (Ball Grid Array) type package, the socket board 94 on whose surface many pogo pins are provided. A test board 96 is used to simplify the operation for bringing a probe 99 extended from a reference driver/comparator (DR/CP) section 98 into contact with these pogo pins provided for the surface of the socket board 94 and has a structure in which pads provided for the surface and back are electrically connected each other.

FIG. 74 is an electrical layout diagram of the conventional configuration shown in FIG. 73. The semiconductor test instrument 90 is provided with a plurality of sets of drivers and comparators and each set of a driver and a comparator is connected to a common device socket end through the performance board (PB) 92 and socket board (SB) 94. In FIG. 74, a test board 96 is omitted.

FIGS. 75, 76, and 77 are illustrations showing the outline of conventional timing calibration. As shown in FIG. 75, phases (skews) of clock signals CLK1 to CLKn and strobe signals STB1 to STBn input to n drivers DR1 to DRn and n comparators CP1 to CPn respectively are shifted in the initial state of a semiconductor test instrument.

First, the probe 99 of the reference driver/comparator section 98 is connected to any device socket end through the test board 96 to make the phase of the strobe signal STB1 (timing of comparison by comparator CP1) coincide with the rise timing of a reference driver signal (reference DR) (FIG. 76). Then, after the phase of a reference comparator signal (reference CP) is made to coincide with the rise timing of an output signal of the reference driver, the phase of the clock signal CLK1 input to the driver DR1 is adjusted so that the rise timing of a signal output from the driver DR1 coincides with the output timing of the reference comparator signal (timing of comparison by reference comparator) (FIG. 77). The above timing calibration operation is performed every device socket end.

Because the timing calibration method of the above conventional semiconductor test instrument performs timing correction at a device socket end, it is necessary to repeat movement of the probe 99 provided for the reference driver/comparator section 98 and contact of the front end of the probe 99. Therefore, to automate the above operation, a special apparatus is necessary. It is considered to make a robot perform the above operation. However, this type of the robot is generally expensive and it is not easy to handle the robot in order to secure a high optional accuracy in many cases. Therefore, there is a problem that operation contents are complicated. It is possible to manually align the probe 99 without using a robot. However, when a device under test has many pins or there are many devices under test that are tested at the same time, the number of times for repeating movement and contact of the probe 99 greatly increases. Therefore, there is a problem that the working time until timing calibration is completed increases.

DISCLOSURE OF THE INVENTION

The present invention is created to solve the above problems and its object is to provide a method for calibrating a semiconductor test instrument capable of reducing the cost, simplifying operation contents, and shortening the working time.

A method of the present invention for calibrating a semiconductor test instrument is constituted by including first to third steps in order to perform the timing calibration of a semiconductor test instrument provided with a driver for generating a signal synchronizing with a clock signal and a comparator for performing the comparison synchronizing with a strobe signal. In the first step, phases of one of clock signals and strobe signals set in one-to-one correspondence are adjusted on the basis of the other while each of a plurality of drivers corresponds to each of a plurality of comparators. In the second step, relative phase differences between clock signals corresponding to a plurality of drivers respectively or relative phase differences between strobe signals corresponding to a plurality of comparators respectively are obtained. In the third step, phases of a plurality of clock signals and phases of a plurality of strobe signals are adjusted in accordance with relative phase differences. Because an exclusive reference driver/comparator section for performing only timing calibration, a probe connected to the section, and an exclusive robot for automating movement and contact of a probe are unnecessary though they have been necessary so far, it is possible to greatly reduce the cost.

Particularly, it is preferable to perform the phase adjustment to be executed in the above first step by varying the phase of a clock signal so that timings for performing comparisons by comparators in accordance with strobe signals coincide with timings for changing signals output from drivers and input to comparators. Or, it is preferable to perform the phase adjustment to be executed in the above first step by varying phases of strobe signals so that timings for performing comparisons by comparators in accordance with strobe signals coincide with timings for changing signals output from drivers and input to comparators. Moreover, it is preferable to perform phase difference obtainment to be executed in the above second step by measuring the phase difference of either of clock signals and strobe signals set in one-to-one correspondence on the basis of the other signals while changing combinations of drivers with comparators in the first step. By varying phases of clock signals or strobe signals while observing results of comparisons by comparators, it is possible to easily adjust phases or measure relative phase differences.

Moreover, it is preferable to insert delay elements for varying phases of signals into supply routes of clock signals to drivers and supply routes of strobe signals to comparators. By individually varying the delay value of each delay element, it is possible to adjust the phase of each clock signal and strobe signal corresponding to each device socket end to an optional value.

Furthermore, it is preferable that the first step is executed by using a first calibration board in which the output end of a corresponding driver and the input end of a corresponding comparator are connected to each short connection point through wirings having equal time lengths. Furthermore, it is preferable that the second step is executed by using a second calibration board different in wiring combination from the first calibration board in which the output end of a corresponding driver and the input end of a corresponding comparator are connected to each short connection point through wirings having equal time lengths. It is possible to adjust phases of clock signals and strobe signals and measure phase differences of strobe signals or phase differences of clock signals by using the first or second calibration board. Therefore, it is possible to simplify operation contents compared to a conventional method in which the phase of a clock signal or probe signal is adjusted every device socket end by using a probe.

Furthermore, it is preferable to include the fourth step of exchanging the first calibration board with the second calibration board between the first step and the second step. Because mechanical working includes only exchange of the first calibration board with the second calibration board, it is possible to greatly shorten the working time in the whole timing calibration.

Furthermore, it is preferable that the first step is executed by using a third calibration board in which the output end of a corresponding driver and the input end of a corresponding comparator are connected to each short connection point through wirings having equal time lengths and the second step is executed by changing wiring states of the third calibration board so that the output end of a corresponding driver and the input end of a corresponding comparator are connected to each short connection point through wirings having equal time lengths. By using the third calibration board capable of changing wiring contents, the exchange of calibration boards is unnecessary. Therefore, it is possible to further shorten the whole working time.

Furthermore, because a plurality of changeover switches for changing wiring states is included in the third calibration board, it is preferable to perform operations in the first and second steps by changing connection states of these switches. Thereby, it is possible to easily change wiring states of the third calibration board.

Furthermore, instead of using the above various calibration boards, it is allowed to use a calibration device or calibration wafer in which the same wiring is made. Particularly, by exchanging calibration devices by using a handler, it is possible to automate the exchanging operation.

Furthermore, a method of the present invention for calibrating a semiconductor test instrument is constituted by including the first to third steps in order to perform the timing calibration of the semiconductor test instrument provided with a driver for generating a signal synchronizing with a clock signal and a comparator for performing the comparison synchronizing with a strobe signal. In the first step, phases of a clock signal and a strobe signal are adjusted by making timings for changing signals output from a plurality of drivers and input to a plurality of comparators coincide with timings for performing comparisons by a plurality of comparators every group when the drivers and the comparators are divided into m number of groups so that two or more drivers or comparators are included. In the second step, relative phase differences of clock signals corresponding to the drivers or relative phase differences of strobe signals corresponding to the comparators are obtained for different groups. In the third step, phases of clock signals corresponding to drivers and phases of strobe signals corresponding to comparators included in a plurality of groups are adjusted in accordance with relative phase differences. Because an exclusive reference driver/comparator section for performing only timing calibration, a probe connected to the section, and an exclusive robot for automating movement and contact of the probe are unnecessary though they have been necessary so far, it is possible to greatly reduce the cost. Moreover, by performing calibration every group, it is possible to average adjustment errors in the group. Therefore, it is possible to reduce calibration errors caused by fluctuation of measurement results.

Furthermore, it is preferable to insert a delay element for varying the phase of a signal into each of supply routes of clock signals to the drivers and each of supply routes of strobe signals to the comparators. By individually varying the delay value of each delay element, it is possible to adjust phases of a clock signal and a strobe signal to optional values and thereby, it is simplified to adjust phases of these signals.

Furthermore, it is preferable that the first step is executed by using a first calibration board in which the output end of a driver and the input end of a comparator are connected each other through a first common short connection point for each of groups. Furthermore, it is preferable that the second step is executed by using a second calibration board in which the output end of a driver included in one group and the input end of a comparator included in the other group are connected each other through a second common connection point. Because calibration is performed by exchanging the first calibration board with the second calibration board, it is possible to simplify working contents compared to a conventional method for individually adjusting phases of a clock signal and a strobe signal by using a probe.

Furthermore, it is preferable to equally set the length of the wiring for connecting the driver with the first and second short connection points and the length of the wiring for connecting the comparator with the first and second short connection points. Thereby, it is possible to adjust every clock signal and strobe signal under the same condition and realize calibration by observing the output of a comparator.

Furthermore, it is preferable to include a fourth step of changing the first calibration board to the second calibration board between the first and second steps. Because mechanical working includes only exchange of the first calibration board with the second calibration board, it is possible to greatly shorten the working time in the whole timing calibration.

Furthermore, it is preferable that the first step is executed by using a third calibration board in which the output end of a driver and the input end of a comparator included in each group are connected through wirings having equal time lengths for every group and the second step is executed by changing wiring states of the third calibration board so that the output end of a driver included in one group and the input end of a comparator included in the other group are connected each other through wirings having equal time lengths. By using the third calibration board capable of changing wiring contents, it is unnecessary to exchange calibration boards and thereby it is possible to further shorten the whole working time.

Furthermore, because a plurality of changeover switches for changing wiring states is included in the third calibration board, it is preferable to perform operations in the first and second steps by changing connection states of these switches. Thereby, it is possible to easily change wiring states of the third calibration board.

Furthermore, instead of using the above various calibration boards, it is allowed to use a calibration device or calibration wafer in which the same wiring is made. Particularly, by exchanging calibration devices by using a handler, it is possible to automate the exchanging operation.

Furthermore, a method of the present invention for calibrating a semiconductor test instrument is constituted by including first to third steps in order to perform the timing calibration of the semiconductor test instrument provided with a driver for generating a signal synchronizing with a clock signal and a comparator for performing the comparison synchronizing with a strobe signal. In the first step, while a plurality of drivers and a plurality of comparators are divided into m number of groups so that two or more drivers or comparators are included, the phase of a clock signal corresponding to an in-group common driver included in each group is adjusted on the basis of a strobe signal corresponding to a comparator serving as a common comparator. In the second step, phases of strobe signals corresponding to comparators included in the same group are adjusted on the basis of a clock signal corresponding to the in-group common driver in each of m number of groups. In the third step, phases of clock signals corresponding to drivers included in the same group are adjusted on the basis of the phase of a strobe signal corresponding to an optional comparator in each of m number of groups.

Or, a method of the present invention for calibrating a semiconductor test instrument is constituted by including first to third steps in order to perform the timing calibration of the semiconductor test instrument provided with a driver for generating a signal synchronizing with a clock signal and a comparator for performing the comparison synchronizing with a strobe signal. In the first step, while a plurality of drivers and a plurality of comparators are divided into m number of groups so that two or more drivers or comparators are included, the phase of a strobe signal corresponding to an in-group common comparator included in each group is adjusted on the basis of a clock signal corresponding to a driver serving as a common driver. In the second step, phases of clock signals corresponding to drivers included in the same group are adjusted on the basis of a strobe signal corresponding to an in-group common comparator in each of m number of groups. In the third step, phases of strobe signals corresponding to comparators included in the same group are adjusted on the basis of the phase of a clock signal corresponding to an optional driver in each of m number of groups.

Because an exclusive reference driver/comparator section for performing only timing calibration, a probe connected to the section, and an exclusive robot for automating movement and contact of the probe are unnecessary though they have been necessary so far, it is possible to greatly reduce the cost. Moreover, because adjustments in the second and third steps can be performed in parallel every group, it is possible improve the working efficiency and shorten the working time.

It is preferable to perform the adjustment of a phase to be executed in each of the first to third steps by varying the phase of a clock signal or strobe signal so that the timing for performing comparison by a comparator in accordance with a strobe signal coincides with the timing for changing a signal output from each driver and input to each comparator. By varying the phase of a clock signal or strobe signal while observing a result of the comparison by a comparator, it is possible to easily adjust these phases and measure relative phase differences.

Moreover, it is preferable that a delay element for varying the phase of a signal is inserted into the supply route of a clock signal to the driver and that of a strobe signal to the comparator. By individually varying the delay value of each delay element, it is possible to adjust phases of a clock signal and a strobe signal to optional values and the phasing of these signals is simplified.

Furthermore, it is preferable that the first step is executed by using a first calibration board in which the input end of a common comparator and the output end of an in-group common driver are connected each other through a first common short connection point. Or, it is preferable that the first step is executed by using a first calibration board in which the output end of the common driver and the input end of an in-group common comparator are connected each other through the first common connection point. Moreover, it is preferable that the second and third steps are executed by using a second calibration board in which the output end of a driver and the input end of a comparator are connected each other through a second common short connection point for each of groups. Because calibration is performed by exchanging the first calibration board with the second calibration board, it is possible to simplify working contents compared to a conventional method for individually adjusting phases of a clock signal and strobe signal by using a probe.

Furthermore, it is preferable to set the length of a wiring for connecting the driver with the first and second short connection points and the length of a wiring for connecting the comparator with the first and second short connection points so that the lengths are all equalized. Thereby, it is possible to adjust every clock signal and strobe signal under the same condition and thereby, calibration is realized by observing an output of a comparator.

Furthermore, it is preferable to include a fourth step of exchanging the first calibration board with the second calibration board between the first and second steps. Because mechanical working includes only exchange of the first calibration board with the second calibration board, it is possible to greatly shorten the working time in the whole timing calibration.

Furthermore, it is preferable that the first step is executed by using a third calibration board in which the input end of a common comparator and the output end of an in-group common driver included in each of m number of groups are connected each other through wiring having equal time lengths for all groups and the second and third steps are executed by changing wiring states of the third calibration board so that the output end of a driver and the input end of a comparator included in each group are connected each other through wirings having equal time lengths for all groups. Or, it is preferable that the first step is executed by using the third calibration board in which the output end of a common driver and the input end of an in-group common comparator included in each of m number of groups are connected each other through wirings having equal time lengths for all groups and the second and third steps are executed by changing wiring states of the third calibration board so that the output end of a driver and the input end of a comparator included in each group are connected each other through wirings having equal time lengths for all groups. By using the third calibration board capable of changing wiring states, exchange of calibration boards is unnecessary. Therefore, it is possible to further shorten the whole working time.

Furthermore, because a plurality of changeover switches for changing wiring states is included in the third calibration board, it is preferable to perform operations in the first, second, and third steps by changing connection states of these changeover switches. Thereby, it is possible to easily change wiring states of the third calibration board.

Furthermore, instead of using the above various calibration boards, it is also allowed to use a calibration device or calibration wafer in which the same wiring is made. Particularly, by exchanging calibration devices by using a handler, it is possible to automate the exchanging operation.

Furthermore, a method of the present invention for calibration a semiconductor test instrument is constituted by including first and second steps in order to perform the timing calibration of the semiconductor test instrument provided with a driver for generating a signal synchronizing with a clock signal and a comparator for performing the comparison synchronizing with a strobe signal. In the first step, the phase of a strobe signal corresponding to each of a plurality of comparators is adjusted on the basis of a clock signal corresponding to a driver. In the second step, the phase of a clock signal corresponding to each of a plurality of drivers is adjusted on the basis of a strobe signal whose phase adjustment is completed in the first step.

Or, a method of the present invention for calibrating a semiconductor test instrument is constituted by including first and second steps in order to perform the timing calibration of the semiconductor test instrument provided with a driver for generating a signal synchronizing with a clock signal and a comparator for performing the comparison synchronizing with a strobe signal. In the first step, the phase of a clock signal corresponding to each of a plurality of drivers is adjusted on the basis of a strobe signal corresponding to a comparator. In the second step, the phase of a strobe signal corresponding to each of a plurality of comparators is adjusted on the basis of a clock signal whose phase adjustment is completed in the first step.

Because an exclusive reference driver/comparator section for performing only timing calibration, a probe connected to the section, and an exclusive robot for automating movement and contact of the probe are unnecessary, it is possible to greatly reduce the cost.

Moreover, it is preferable to perform adjustments of phases to be executed in the first and second steps by varying the phase of a clock signal or strobe signal so that the timing for performing comparison by a comparator in accordance with the strobe signal coincides with the timing for changing a signal output from each driver and input to each comparator. By varying the phase of the clock signal or strobe signal while observing a result of the comparison by the comparator, it is possible to easily adjust these phases and measure relative phase differences.

Furthermore, it is preferable that a delay element for varying the phase of a signal is inserted into the supply route of a clock signal to the driver and that of a strobe signal to the comparator. By individually varying the delay value of each delay element, it is possible to adjust phases of a clock signal and strobe signal to optional values and the phasing of these signals is simplified.

Furthermore, it is preferable that the first step is executed by using a plurality of first calibration boards in which the output end of a driver and the input end of each of a plurality of comparators are separately connected each other through a first short connection point. Or, it is preferable that the first step is executed by a plurality of first calibration boards in which the output end of each of a plurality of drivers and the input end of a comparator are separately connected each other through the first short connection point. Moreover, it is preferable that the second step is executed by using a second calibration board in which each of a plurality of drivers corresponds to each of a plurality of comparators and the output end of a corresponding driver and the input end of a corresponding comparator are connected each other. Because calibration is performed by exchanging the first calibration board with the second calibration board, it is possible to simplify working contents compared to a conventional method in which phases of a clock signal and strobe signal are individually adjusted by a probe.

Furthermore, it is preferable to set the length of a wiring for connecting the driver with the first and second short connection points and the length of a wiring for connecting the comparator with the first and second short connection points so that the lengths are equalized. Thereby, it is possible to adjust every clock signal and strobe signal under the same condition and realize the calibration by observing an output of the comparator.

Furthermore, instead of using the above various calibration boards, it is also allowed to use a calibration device or calibration wafer in which the same wiring is made. Particularly, by exchanging calibration devices by using a handler, it is possible to automate the exchanging operation.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an illustration showing a general configuration of a semiconductor test instrument to which timing calibration will be applied;

FIG. 2 is an illustration showing a wiring state of one calibration board;

FIG. 3 is an illustration showing a wiring state of the other calibration board;

FIG. 4 is a flow chart showing a calibration procedure of a first embodiment;

FIG. 5 is an illustration showing a state in which one calibration board (CB) is set to a semiconductor test instrument;

FIG. 6 is an illustration showing the outline of the clock signal phasing to be executed in step 101;

FIG. 7 is an illustration showing details of the adjustment of phases of clock signals shown in FIG. 6;

FIG. 8 is an illustration showing a state in which the other calibration board is set to the semiconductor test instrument;

FIG. 9 is an illustration showing the outline of the strobe signal phase difference obtainment to be executed in step 103;

FIG. 10 is an illustration showing outlines of the strobe signal correction value decision and strobe signal correction to be executed in steps 104 and 105;

FIG. 11 is an illustration showing the outline of the clock signal phase correction to be executed in step 106;

FIG. 12 is an illustration showing a configuration of a calibration board of a second embodiment having functions of two types of calibration boards different from each other in wiring contents;

FIG. 13 is an illustration showing a configuration of the second embodiment having functions of two types of calibration boards different from each other in wiring contents;

FIG. 14 is an illustration showing a wiring state of one calibration board used to perform calibration in a third embodiment;

FIG. 15 is an illustration showing a wiring state of the other calibration board used to perform calibration in the third embodiment;

FIG. 16 is an illustration showing initial states of a clock signal and a strobe signal in a semiconductor test instrument before performing calibration;

FIG. 17 is a flow chart showing a calibration procedure of the third embodiment;

FIG. 18 is an illustration showing drivers and comparators to or from which signals are input or output correspondingly to step 201 shown in FIG. 17;

FIG. 19 is an illustration showing the outline of the strobe signal phase adjustment to be executed in step 201 in FIG. 17;

FIG. 20 is an illustration showing drivers and comparators to or from which signals are input or output correspondingly to step 202 shown in FIG. 17;

FIG. 21 is an illustration showing the outline of the clock signal phase adjustment to be executed in step 202 shown in FIG. 17;

FIG. 22 is an illustration showing a driver and a comparator to or from which signals are input or output correspondingly to step 204 shown in FIG. 17;

FIG. 23 is an illustration showing the outline of the strobe signal phase difference measurement to be executed in step 204 shown in FIG. 17;

FIG. 24 is an illustration showing the outline of the strobe signal phase correction to be executed in step 206 shown in FIG. 17;

FIG. 25 is an illustration showing drivers and comparators to or from which signals are input or output correspondingly to step 207 shown in FIG. 17;

FIG. 26 is an illustration showing the outline of the clock signal correction to be executed in step 207 shown in FIG. 17;

FIG. 27 is an illustration showing a configuration of a calibration board of a fourth embodiment having functions of two types of calibration boards different from each other in wiring contents;

FIG. 28 is an illustration showing a configuration of a calibration board of the fourth embodiment having functions of two types of calibration boards different from each other in wiring contents;

FIG. 29 is an illustration showing a wiring state of one calibration board of a fifth embodiment;

FIG. 30 is an illustration showing a wiring state of the other calibration board of the fifth embodiment;

FIG. 31 is a flow chart showing a calibration procedure of the fifth embodiment;

FIG. 32 is an illustration showing a driver and a comparator to or from which signals are input or output correspondingly to step 301 shown in FIG. 31;

FIG. 33 is an illustration showing the outline of the clock signal phase adjustment to be executed in step 301 shown in FIG. 31;

FIG. 34 is an illustration showing drivers and comparators to or from which signals are input or output correspondingly to step 303 shown in FIG. 31;

FIG. 35 is an illustration showing the outline of the strobe signal phase adjustment to be executed in step 303 shown in FIG. 31;

FIG. 36 is an illustration showing drivers and comparators to or from which signals are input or output correspondingly to step 304 shown in FIG. 31;

FIG. 37 is an illustration showing the outline of the clock signal phase adjustment to be executed in step 304 shown in FIG. 31;

FIG. 38 is an illustration showing a configuration of one calibration board of a sixth embodiment;

FIG. 39 is a flow chart showing a calibration procedure of the sixth embodiment;

FIG. 40 is an illustration showing a configuration of a calibration board of a seventh embodiment having functions of two types of calibration boards different from each other in wiring contents;

FIG. 41 is an illustration showing a configuration of a calibration board of the seventh embodiment having functions of two types of calibration boards different from each other in wiring contents;

FIG. 42 is an illustration showing a configuration of a calibration board of a modification having functions of two types of calibration boards different from each other in wiring contents;

FIG. 43 is an illustration showing a configuration of a calibration board of a modification having functions of two types of calibration boards different from each other in wiring contents;

FIG. 44 is an illustration showing a wiring state of a calibration board used for a calibration method of an eighth embodiment;

FIG. 45 is an illustration showing a wiring state of a calibration board used for the calibration method of the eighth embodiment;

FIG. 46 is an illustration showing a wiring state of a calibration board used for the calibration method of the eighth embodiment;

FIG. 47 is an illustration showing a wiring state of a calibration board used for the calibration method of the eighth embodiment;

FIG. 48 is an illustration showing a wiring state of a calibration board used for the calibration method of the eighth embodiment;

FIG. 49 is a flow chart showing a calibration procedure of the eighth embodiment;

FIG. 50 is an illustration showing a modification of a calibration board of the eightht embodiment;

FIG. 51 is an illustration showing a configuration of a calibration board of a ninth embodiment having functions of n+1 types of calibration boards different from each other in wiring contents;

FIG. 52 is an illustration showing a modification of the calibration board shown in FIG. 51;

FIG. 53 is an illustration showing a modification in which the setting state of a calibration board is changed;

FIG. 54 is an illustration of the clock signal phase adjustment corresponding to the configuration shown in FIG. 53;

FIG. 55 is an illustration showing a connection state between a calibration device and a semiconductor test instrument;

FIG. 56 is an illustration showing the outline of the timing calibration using a calibration device;

FIG. 57 is an illustration showing a connection state between a calibration wafer and a semiconductor test instrument;

FIG. 58 is an illustration showing the outline of the timing calibration using a calibration wafer;

FIG. 59 is an illustration showing a calibration device realizing the same wiring state as the case of the calibration board used for the first embodiment;

FIG. 60 is an illustration showing a calibration device realizing the same wiring state as the case of a calibration board used for the first embodiment;

FIG. 61 is an illustration showing a calibration device realizing the same wiring state as the case of the calibration board used for the third embodiment;

FIG. 62 is an illustration showing a calibration device realizing the same wiring state as the case of the calibration board used for the third embodiment;

FIG. 63 is an illustration showing a calibration device realizing the same wiring state as the case of the calibration board used for the fifth embodiment;

FIG. 64 is an illustration showing a calibration device realizing the same wiring state as the case of the calibration board used for the eighth embodiment;

FIG. 65 is an illustration showing a calibration device realizing the same wiring state as the case of the calibration board used for the eighth embodiment;

FIG. 66 is an illustration showing a calibration device realizing the same wiring state as the case of the calibration board used for the eighth embodiment;

FIG. 67 is an illustration showing a calibration device realizing the same wiring state as the case of the calibration board used for the eighth embodiment;

FIG. 68 is an illustration showing a calibration device realizing the same wiring state as the case of the calibration board used for the eighth embodiment;

FIG. 69 is an illustration showing a calibration wafer realizing the same wiring state as the case of the calibration boards used for the first embodiment;

FIG. 70 is an illustration showing a calibration wafer realizing the same wiring state as the case of the calibration board used for the third embodiment;

FIG. 71 is an illustration showing a calibration wafer realizing the same wiring state as the case of the calibration board used for the fifth embodiment;

FIG. 72 is an illustration showing a calibration wafer realizing the same wiring state as the case of the calibration board used for the eighth embodiment;

FIG. 73 is an illustration showing a conventional configuration for performing the timing calibration of a semiconductor test instrument;

FIG. 74 is an electrical layout diagram of the conventional configuration shown in FIG. 73;

FIG. 75 is an illustration showing the outline of conventional timing calibration;

FIG. 76 is an illustration showing the outline of conventional timing calibration; and

FIG. 77 is an illustration showing the outline of conventional timing calibration.

BEST MODE FOR CARRYING OUT THE INVENTION

A method of an embodiment providing the present invention for calibrating a semiconductor test instrument is described below in detail.

[First Embodiment]

FIG. 1 is an illustration showing a general configuration of a semiconductor test instrument to which the timing calibration performed in the first embodiment will be applied. The semiconductor test instrument is constituted by including a semiconductor test instrument 10 and a work station (WS) 40 in order to apply a predetermined test to a device under test (DUT) (not illustrated).

The work station 40 controls a series of test operations such as a functional test and the whole timing calibration and realizes an interface with users.

The semiconductor test instrument 10 applies various tests to a DUT by executing a predetermined test program transferred from the work station 40. Moreover, the semiconductor test instrument 10 performs timing calibration by executing an exclusive program transferred from the work station 40. To execute the above operations, the semiconductor test instrument 10 has a tester control section (TP) 12, a timing generator (TG) 14, a pattern generator (PG) 16, a data selector (DS) 18, a format control section (FC) 20, and a pin electronics 22.

The tester control section 12 is connected with component sections of the timing generator 14 or the like through a bus to perform the control necessary for various test operations and calibrations for the component sections.

The timing generator 14 sets a basic cycle of test operations and generates various timing edges included in the basic cycle. The pattern generator 16 generates pattern data to be input to each pin of a DUT. The data selector 18 relates various pattern data values output from the pattern generator 16 with pins of the DUT for receiving the various pattern data values. The format control section 20 controls waveforms of the DUT in accordance with the pattern data generated by the pattern generator 16 and selected by the data selector 18 and the timing edge generated by the timing generator 14.

The pin electronics 22 forms a physical interface between the pin electronics 22 and the DUT and generates signals to be transferred actually to and from the DUT in accordance with a clock signal CLK or strobe signal STB generated through the waveform control by the format control section 20. To execute the above operations, the pin electronics 22 is constituted by including n drivers DR1 to DRn and n comparators CP1 to CPn.

The driver DR1 generates a signal synchronizing with a clock signal CLK1 and changes an output signal from low level to high level when the clock signal CLK1 rises. Similarly, the drivers DR2 to DRn generate signals synchronizing with input clock signals CLK2 to CLKn and respectively change an output signal from low level to high level when a corresponding clock signal rises.

In the case of not only this embodiment but also other embodiments, an output signal of a driver changes the same as the case of a clock signal, that is, the output signal of the driver rises synchronously with the rise of the clock signal and falls synchronously with the fall of the clock signal. However, it is also allowed that the output signal of the driver falls synchronously with the rise of the clock signal and rises synchronously with the fall of the clock signal.

The comparator CP1 performs the comparison synchronizing with a strobe signal STB1 output from the format control section 20 and determines the logic of a signal input from a corresponding pin of the DUT when the strobe signal STB1 is input. Similarly, the comparators CP2 to CPn perform comparisons synchronizing with input strobe signals STB2 to STBn and respectively determine the logic of a signal input from a corresponding pin of the DUT when a corresponding strobe signal is input.

To perform the comparison synchronizing with a strobe signal by a comparator, the following cases are considered: a case of performing comparison by a comparator synchronously with the rise of a strobe signal and a case of performing comparison by the comparator synchronously with the fall of the strobe signal. In the case of not only this embodiment but also other embodiments, it is allowed to use either of comparison timings because there is no essential difference in the relation with the present invention.

The above driver DR1 and comparator CP1 correspond to one input/output pin of the DUT as one set. Moreover, the driver DR2 and comparator CP2 correspond to another input/output pin as one set. Thus, a set of a driver and a comparator is provided by relating them to each input/output pin of the DUT.

Furthermore, a performance board 30 is mounted on the semiconductor test instrument 10 and the above pin electronics 22 is connected to a calibration board 50A (or 50B) through the performance board 30.

Special internal wirings different from each other are applied to the calibration boards 50A and 50B in order to perform timing calibration.

FIG. 2 is an illustration showing a wiring state of the calibration board 50A. In FIG. 2, two terminals 1a and 1b are connected with a short connection point (device socket end) 1c in common and moreover, set so that their wiring lengths (time lengths) in terms of signal delay time are equalized. Moreover, two terminals 2a and 2b are connected with a short connection point 2c in common and moreover, set so that their wiring lengths in terms of signal delay time are equalized. Furthermore, two terminals na and nb are connected with a short connection point nc in common and set so that their wiring lengths in terms of signal delay time are equalized. Furthermore, the above wiring lengths are equally set for all short connection points.

FIG. 3 is an illustration showing a wiring state of the other calibration board 50B. In FIG. 3, two terminals 1a and nb are connected with the short connection point 1c in common and set so that their wiring lengths in terms of signal delay time are equalized. Moreover, two terminals 2a and 1b are connected with the short connection point 2c in common and set so that their wiring lengths in terms of signal delay time are equalized. Furthermore, two terminals na and 2b are connected with the short connection point nc in common and set so that their wiring lengths in terms of signal delay time are equalized. Furthermore, the above wiring lengths are equally set for all short connection points of two types of calibration boards 50A and 50B.

A semiconductor test instrument of the present invention has the above configuration and the calibration using the instrument is described below.

FIG. 4 is a flow chart showing a calibration procedure of this embodiment. After one calibration board 50A is set to the performance board 30 (step 100), the tester control section 12 adjusts the phase of a clock signal on the basis of a strobe signal every short connection point of the calibration board 50A (step 101).

In the above step 101, the phase adjustment of a clock signal is performed by observing the level of an output signal when a strobe signal is output (raised) and comparison is performed by a comparator while changing the rise timing of a clock signal little by little and obtaining the phase of the clock signal when the level of the output signal of the comparator is just inverted.

FIG. 5 is an illustration showing a state in which the calibration board (CB) 50A is set to the semiconductor test instrument 10 through the performance board (PB) 30. In FIG. 5, Tx1 to Txn respectively denote a delay time caused by a wiring from the output end of each driver up to a terminal of the calibration board 50A, Ty1 to Tyn respectively denote a delay time caused by a wiring from a terminal of the calibration board 50A up to the input end of each comparator, and Ta denotes a delay time caused by each wiring in the calibration board 50A. For example, it is assumed that Tx1 to Txn and Ty1 to Tyn are all set to the same value.

As shown in FIG. 5, a delay element T is set to routes through which a clock signal is supplied to the drivers DR1 to DRn in order to adjust the phase (change timing) of the clock signal. By varying the element constant of each delay element, it is possible to optionally and independently adjust phases of clock signals to the drivers DR1 to DRn. Similarly, a delay element T is set to routes through which a strobe signal is supplied to the comparators CP1 to CPn in order to adjust the phase of the strobe signal. By varying element constants of the delay elements T, it is possible to optionally and independently adjust the phase of the strobe signal to the comparators CP1 to CPn.

For this embodiment and embodiments from the second embodiment downward, a case is described in which wiring lengths from terminals of a calibration board up to the output end of a driver and the input end of a comparator are equally set. However, it is also allowed to differentiate these wiring lengths and adjust differences between the wiring lengths by the above delay element T.

FIG. 6 is an illustration showing the outline of the clock signal phase adjustment to be executed in the above step 101. Moreover, FIG. 7 is an illustration showing details of the clock signal phase adjustment shown in FIG. 6. In FIG. 7, "DR", "short connection point", and "CP" shown correspondingly to each