Method for forming programmable logic arrays using vertical gate transistors Number:7,164,294 from the United States Patent and Trademark Office (PTO) owispatent One aspect disclosed herein relates to a method for forming a programmable logic array. Various embodiments of the method include forming a first logic plane and a second logic plane, each including a plurality of logic cells interconnected to implement a logical function. Forming the logic cells includes forming a horizontal substrate with a source region, a drain region, and a depletion mode channel region separating the source and the drain regions, and further includes forming a number of vertical gates located above different portions of the depletion mode channel region. At least one vertical gate is separated from the depletion mode channel region by a first oxide thickness, and at least one of the vertical gates is separated from the depletion mode channel region by a second oxide thickness. Other aspects and embodiments are provided herein.<H programmable, transistors, Method, for, form, 7164294.html, Patent, pto, 7164294

Title: Method for forming programmable logic arrays using vertical gate transistors

Abstract: One aspect disclosed herein relates to a method for forming a programmable logic array. Various embodiments of the method include forming a first logic plane and a second logic plane, each including a plurality of logic cells interconnected to implement a logical function. Forming the logic cells includes forming a horizontal substrate with a source region, a drain region, and a depletion mode channel region separating the source and the drain regions, and further includes forming a number of vertical gates located above different portions of the depletion mode channel region. At least one vertical gate is separated from the depletion mode channel region by a first oxide thickness, and at least one of the vertical gates is separated from the depletion mode channel region by a second oxide thickness. Other aspects and embodiments are provided herein.

Patent Number: 7,164,294 Issued on 01/16/2007 to Forbes, et al.

Inventors: Forbes; Leonard (Corvallis, OR), Ahn; Kie Y. (Chappaqua, NY)
Assignee: Micron Technology, Inc. (Boise, ID)

Appl. No.: 10/929,831

Filed: August 30, 2004

Related U.S. Patent Documents


Application Number	Filing Date	Patent Number	Issue Date
10185155	Jun., 2002	6794246
09643296	Aug., 2000	6437389

Current U.S. Class: 326/107 ; 257/302; 257/314; 257/315; 326/102; 326/38; 326/40; 326/41; 326/47

Current International Class: G11C 8/00 (20060101); G06F 7/38 (20060101); H01L 29/76 (20060101); H03K 19/084 (20060101)

Field of Search: 326/107

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Primary Examiner: Barnie; Rexford
Assistant Examiner: White; Dylan
Attorney, Agent or Firm: Schwegman, Lundberg, Woessner & Kluth, P.A.

Parent Case Text

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Divisional of U.S. Ser. No. 10/185,155 filed Jun. 28, 2002 is now a U.S. Pat. No. 6,794,246, which is a Divisional of U.S. Ser. No. 09/643,296 filed on Aug. 22, 2000, now issued as U.S. Pat. No. 6,437,389, which applications are incorporated herein by reference.

This application is related to the following co-pending, commonly assigned U.S. patent applications: entitled "Static Pass Transistor Logic with Transistors with Multiple Vertical Gates," Ser. No. 09/580,901; and "Vertical Gate Transistors in Pass Transistor Logic Decode Circuits," Ser. No. 09/580,860, both filed on May 30, 2000 and which disclosures are herein incorporated by reference.

Claims

What is claimed is:

1. A method for operating a programmable logic array, comprising: applying a number of input signals to a number of logic cells in a first logic plane, wherein each logic cell includes a source region, a drain region, a depletion mode channel region therebetween, and a number of vertical gates located above different portions of the depletion mode channel region, wherein at least one of the vertical gates is separated from the depletion mode channel by a first oxide thickness, wherein at least one of the vertical gates is separated from the depletion mode channel by a second oxide thickness, and wherein applying a number of input signals to the number of logic cells in the first logic plane includes applying a potential to the number of vertical gates in each logic cell; outputting a number of output signals from the first logic plane to a number of logic cells in a second logic plane, wherein each logic cell in the second logic plane includes a source region, a drain region, a depletion mode channel region therebetween, and a number of vertical gates located above different portions of the depletion mode channel region, wherein at least one of the vertical gates is separated from the depletion mode channel by a first oxide thickness, wherein at least one of the vertical gates is separated from the depletion mode channel by a second oxide thickness, and wherein outputting a number of output signals from the first logic plane to a number of logic cells in a second logic plane includes applying a potential to the number of vertical gates for the logic cells in the second logic plane; and wherein the number of logic cells in the second logic plane are arranged in rows and columns to receive the output signals from the first logic plane and are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function.

2. The method of claim 1, wherein applying a potential to the number of vertical gates includes applying the potential to a number of active inputs for each logic cell.

3. The method of claim 2, wherein applying the potential to the number of active inputs controls conduction in the depletion mode channel such that each logic cell functions as a NAND gate.

4. The method of claim 2, wherein applying the potential to the number of active inputs includes applying a negative potential of approximately -0.6 Volts to at least one of the active inputs such that the active input turns off conduction in the depletion mode channel.

5. The method of claim 1, wherein applying a potential to the number of vertical gates includes applying the potential to a number of passing lines.

6. A method for operating a programmable logic array, comprising: applying a number of input signals to a number of logic cells in a first logic plane, wherein applying a number of input signals to the number of logic cells in the first logic plane includes applying a potential to a number of vertical gates located above different portions of a horizontal depletion mode channel, wherein at least one of the vertical gates is separated from the depletion mode channel by a first oxide thickness, and wherein at least one of the vertical gates is separated from the depletion mode channel by a second oxide thickness; outputting a number of output signals from the first logic plane to a number of logic cells in a second logic plane, wherein outputting the number of output signals from the first logic plane to the number of logic cells in the second logic plane includes applying a potential to a number of vertical gates located above different portions of a horizontal depletion mode channel, wherein at least one of the vertical gates is separated from the depletion mode channel by a first oxide thickness, and wherein at least one of the vertical gates is separated from the depletion mode channel by a second oxide thickness; wherein the number of logic cells in the second logic plane are arranged in rows and columns to receive the output signals of the first logic plane and are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function; using at least one of the number of vertical gates in any logic cell as a passing line such that a potential on the passing line does not effect conduction in the depletion mode channel; and using at least two of the number of vertical gates in any logic cell as a number of active inputs such that the active inputs control conduction in the depletion mode channel.

7. The method of claim 6, wherein the method further includes independently applying potential values to the number of vertical gates.

8. The method of claim 7, wherein independently applying potential values to the number of vertical gates includes performing a logic function.

9. The method of claim 8, wherein performing a logic function includes performing a NAND logic function.

10. The method of claim 6, wherein using at least two of the number of vertical gates in any logic cell as a number of active inputs includes applying a negative potential to the active inputs of approximately -0.6 Volts to turn off conduction in the depletion mode channel region.

11. The method of claim 6, wherein using at least one of the number of vertical gates in any logic cell as a passing line includes using at least one of the number of vertical gates separated from the depletion mode channel by the second oxide thickness as the passing line, wherein the second oxide thickness is greater than the first oxide thickness.

12. The method of claim 6, wherein applying a potential to a number of vertical gates located above different portions of a horizontal depletion mode channel includes applying the potential to a number of edge defined vertical gates such that the vertical gates have a horizontal width which is sub-lithographic in dimension.

13. The method of claim 12, wherein applying the potential to a number of edge defined vertical gates such that the vertical gates have a horizontal width which is sub-lithographic in dimension includes using less than one MOSFET for a number of logic inputs in each logic cell of the programmable logic array.

14. A method for operating a programmable logic array, comprising: applying a first plurality of input signals to a second plurality of logic cells in a first logic plane, wherein each logic cell includes a source region, a drain region, a depletion region therebetween, and a third plurality of vertical gates disposed above the depletion region; wherein each individual one of the third plurality of vertical gates is separated from the depletion region by an individual dielectric thickness selected to be one of, a first thickness to controllably turn off the depletion region upon application of an input signal to the vertical gate, and a second thickness to not turn off the horizontal depletion region upon application of an input signal to the vertical gate; wherein applying the first plurality of input signals to the second plurality of logic cells includes applying the first plurality of input signals to the third plurality of vertical gates to implement a logic function and produce a fourth plurality of signals; outputting the fourth plurality of signals from the first logic plane as input signals to a fifth plurality of logic cells in a second logic plane, wherein each logic cell includes a source region, a drain region, a depletion region therebetween, and a sixth plurality of vertical gates disposed above the depletion region; wherein each individual one of the sixth plurality of vertical gates is separated from the depletion region by an individual dielectric thickness selected to be one of, a third thickness to controllably turn off the depletion region upon application of an input signal to the vertical gate, and a fourth thickness to not turn off the horizontal depletion region upon application of an input signal to the vertical gate; wherein applying the fourth plurality of input signals to the fifth plurality of logic cells includes applying the fourth plurality of input signals to the sixth plurality of vertical gates to implement a logic function.

15. The method for operating a programmable logic array of claim 14, wherein the second plurality of logic cells in the first logic plane are arranged in rows and columns to receive the first plurality of input signals and are interconnected to produce a number of logical outputs for the second logic array.

16. The method for operating a programmable logic array of claim 14, wherein the second plurality of logic cells in the second logic plane are arranged in rows and columns to receive the fourth plurality of input signals from the first logic plane and are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function.

17. A method for operating a programmable logic array, comprising: applying a first plurality of input signals to a second plurality of logic cells in a first logic plane, wherein each logic cell includes a source region, a drain region, a depletion region therebetween, and a third plurality of vertical gates disposed above the depletion region; wherein each individual one of the third plurality of vertical gates is separated from the depletion region by an individual dielectric thickness selected to be one of, a first thickness to controllably turn off the depletion region upon application of an input signal to the vertical gate, and a second thickness to not turn off the horizontal depletion region upon application of an input signal to the vertical gate; wherein applying the first plurality of input signals to the second plurality of logic cells includes applying the first plurality of input signals to the third plurality of vertical gates to implement a logic function and produce a fourth plurality of signals; outputting the fourth plurality of signals from the first logic plane as input signals to a fifth plurality of logic cells in a second logic plane, wherein each logic cell includes a source region, a drain region, a depletion region therebetween, and a sixth plurality of vertical gates disposed above the depletion region; wherein each individual one of the sixth plurality of vertical gates is separated from the depletion region by an individual dielectric thickness selected to be one of, a third thickness to controllably turn off the depletion region upon application of an input signal to the vertical gate, and a fourth thickness to not turn off the horizontal depletion region upon application of an input signal to the vertical gate; wherein applying the fourth plurality of input signals to the fifth plurality of logic cells includes applying the fourth plurality of input signals to the sixth plurality of vertical gates to implement a logic function; and wherein individual ones of the second plurality of logic cells in the first logic plane are programmed to be logically inactive by selecting the individual dielectric thickness of everyone of the third plurality of vertical gates to be the second thickness to not turn off the horizontal depletion region upon application of an input signal.

18. The method for operating a programmable logic array of claim 17, wherein individual ones of the fifth plurality of logic cells in the second logic plane are programmed to be logically inactive by selecting the individual dielectric thickness of everyone of the sixth plurality of vertical gates to be the fourth thickness to not turn off the horizontal depletion region upon application of an input signal.

19. The method for operating a programmable logic array of claim 17, wherein applying the first plurality of input signals to the third plurality of vertical gates includes applying a potential to more than one of the third plurality of vertical gates.

20. The method for operating a programmable logic array of claim 17, wherein each one of the second plurality of logic cells includes at least two of the third plurality of vertical gates with an individual dielectric thickness selected to controllably turn off the depletion region upon application of the input signal.

21. A method for operating a programmable logic array, comprising: applying a first plurality of input signals to a second plurality of logic cells in a first logic plane, wherein each logic cell includes a source region, a drain region, a depletion region therebetween, and a third plurality of vertical gates disposed above the depletion region; wherein each individual one of the third plurality of vertical gates is separated from the depletion region by an individual dielectric thickness selected to be one of, a first thickness to controllably turn off the depletion region upon application of an input signal to the vertical gate, and a second thickness to not turn off the horizontal depletion region upon application of an input signal to the vertical gate; wherein applying the first plurality of input signals to the second plurality of logic cells includes applying the first plurality of input signals to the third plurality of vertical gates to implement a logic function and produce a fourth plurality of signals; outputting the fourth plurality of signals from the first logic plane as input signals to a fifth plurality of logic cells in a second logic plane, wherein each logic cell includes a source region, a drain region, a depletion region therebetween, and a sixth plurality of vertical gates disposed above the depletion region; wherein each individual one of the sixth plurality of vertical gates is separated from the depletion region by an individual dielectric thickness selected to one of, a third thickness to controllably turn off the depletion region upon application of an input signal to the vertical gate, and a fourth thickness to not turn off the horizontal depletion region upon application of an input signal to the vertical gate; wherein applying the fourth plurality of input signals to the fifth plurality of logic cells includes applying the fourth plurality of input signals to the sixth plurality of vertical gates to implement a logic function; and wherein each one of the fifth plurality of logic cells includes at least two of the sixth plurality of vertical gates with an individual dielectric thickness selected to be the third thickness to controllably turn off the depletion region upon application of the input signal to the vertical gate.

22. The method for operating a programmable logic array of claim 21, wherein each of the fourth plurality of output signals from the first logic plane are applied to output amplifier circuits before inputting the fourth plurality of output signals to the fifth plurality of logic cells in the second logic plane.

23. The method for operating a programmable logic array of claim 21, wherein each of the fourth plurality of output signals from the first logic plane are applied to level shift circuits before inputting the fourth plurality of output signals to the fifth plurality of logic cells in the second logic plane.

24. The method for operating a programmable logic array of claim 21, wherein at least some of the second plurality of logic cells in the first logic plane are arranged such that the application of the first plurality of input signals results in the logic cell functioning as a NAND logic gate.

25. The method for operating a programmable logic array of claim 21, wherein applying the first plurality of input signals to the second plurality of logic cells in the first logic plane includes applying a signal having a negative potential of approximately six tenths of a volt.

26. The method for operating a programmable logic array of claim 25, wherein the individual dielectric thickness selected to controllably turn off the depletion region upon application of an input signal is less than 5 nanometers.

27. The method for operating a programmable logic array of claim 25, wherein the individual dielectric thickness selected to not turn off the depletion region upon application of an input signal is approximately 30 nanometers.

28. A method for operating a programmable logic array, comprising: applying a first plurality of input signals to a second plurality of logic cells in a first logic plane, wherein each logic cell includes a source region, a drain region, a depletion region therebetween, and a third plurality of vertical gates disposed above the depletion region; wherein each individual one of the third plurality of vertical gates is separated from the depletion region by an individual dielectric thickness selected to be one of, a first thickness to controllably turn off the depletion region upon application of an input signal to the vertical gate, and a second thickness to not turn off the horizontal depletion region upon application of an input signal to the vertical gate; wherein applying the first plurality of input signals to the second plurality of logic cells includes applying the first plurality of input signals to the third plurality of vertical gates to implement a logic function and produce a fourth plurality of signals; outputting the fourth plurality of signals from the first logic plane as input signals to a fifth plurality of logic cells in a second logic plane, wherein each logic cell includes a source region, a drain region, a depletion region therebetween, and a sixth plurality of vertical gates disposed above the depletion region; wherein each individual one of the sixth plurality of vertical gates is separated from the depletion region by an individual dielectric thickness selected to be one of, a third thickness to controllably turn off the depletion region upon application of an input signal to the vertical gate, and a fourth thickness to not turn off the horizontal depletion region upon application of an input signal to the vertical gate; wherein applying the fourth plurality of input signals to the fifth plurality of logic cells includes applying the fourth plurality of input signals to the sixth plurality of vertical gates to implement a logic function; and wherein each individual one of the third plurality of vertical gates in each logic cell is disposed over a different portion of the depletion region.

29. The method for operating a programmable logic array of claim 28, wherein the logic cell includes four vertical gates, each vertical gate separated from the depletion region by the first individual dielectric thickness selected to controllably turn off the depletion region upon application of an input signal, and arranged so that the logic cell performs the logic function of a positive logic four input NAND gate.

30. The method for operating a programmable logic array of claim 28, wherein applying the first plurality of input signals to the second plurality of logic cells in the first logic plane includes applying input signals to selected ones of the third plurality of vertical gates, wherein the third plurality of vertical gates comprise edge defined conductive material having a horizontal width which is sub-lithographic in dimension.

31. The method for operating a programmable logic array of claim 30, wherein the conductive material comprises doped polycrystalline silicon.

32. A method for operating a programmable logic array, comprising: applying a first plurality of input signals to a second plurality of logic cells in a first logic plane, wherein each logic cell includes a source region, a drain region, a depletion region therebetween, and a third plurality of vertical gates disposed above the depletion region; wherein each individual one of the third plurality of vertical gates is separated from the depletion region by an individual dielectric thickness selected to be one of, a first thickness to controllably turn off the depletion region upon application of an input signal to the vertical gate, and a second thickness to not turn off the horizontal depletion region upon application of an input signal to the vertical gate; wherein applying the first plurality of input signals to the second plurality of logic cells includes applying the first plurality of input signals to the third plurality of vertical gates to implement a logic function and produce a fourth plurality of signals; outputting the fourth plurality of signals from the first logic plane as input signals to a fifth plurality of logic cells in a second logic plane, wherein each logic cell includes a source region, a drain region, a depletion region therebetween, and a sixth plurality of vertical gates disposed above the depletion region; wherein each individual one of the sixth plurality of vertical gates is separated from the depletion region by an individual dielectric thickness selected to be one of, a third thickness to controllably turn off the depletion region upon application of an input signal to the vertical gate, and a fourth thickness to not turn off the horizontal depletion region upon application of an input signal to the vertical gate; wherein applying the fourth plurality of input signals to the fifth plurality of logic cells includes applying the fourth plurality of input signals to the sixth plurality of vertical gates to implement a logic function; and wherein applying the fourth plurality of output signals to the fifth plurality of logic cells in the second logic plane includes applying the signals to selected ones of the sixth plurality of vertical gates, wherein the sixth plurality of vertical gates comprise edge defined conductive material having a horizontal width which is sub-lithographic in dimension.

33. The method for operating a programmable logic array of claim 32, wherein each individual one of the third and the sixth pluralities of vertical gates is separated from others of the third and the sixth plurality of vertical gates by a dielectric layer.

34. The method for operating a programmable logic array of claim 33, wherein the dielectric material comprises thermally grown silicon dioxide.

35. The method for operating a programmable logic array of claim 32, wherein the pluralities of vertical gates are disposed in parallel to one another.

36. The method for operating a programmable logic array of claim 35, wherein each one of the pluralities of vertical gates are approximately one hundred nanometers wide and approximately 500 nanometers high.

37. A method for operating a programmable logic array, comprising: at least one row of logic cells in a first logic plane, wherein each individual logic cell includes at least a first and a second gate disposed to accept signal potentials; wherein each of the at least first and second gates of the logic cell are separated from a depletion conduction region connecting a source diffusion and a drain diffusion of the logic cell by either a first dielectric thickness to turn off at least a region of the depletion region upon application of a signal potential to the first or second gate, or a second dielectric thickness to not turn off any region of the depletion region upon application of the signal potential to the first or second gate; applying a first input signal potential to the first gate of the logic cell and a second input signal potential to the second gate of the logic cell to produce at least one logical function output of the first logic plane.

38. The method for operating a programmable logic array of claim 37, wherein further at least one row of logic cells in a second logic plane are arranged to accept as an input the at least one logical function output of the first logic plane; wherein each individual logic cell of the second logic plane includes at least a third and a fourth gate are separated from a depletion conduction region connecting a source diffusion and a drain diffusion of the logic cells of the second logic plane by either a third dielectric thickness to turn off at least a region of the depletion region upon application of a signal potential to the third or fourth gate, or a fourth dielectric thickness to not turn off any region of the depletion region upon application of the signal potential to the third or fourth gate.

39. The method for operating a programmable logic array of claim 38, wherein further applying a third input signal potential to the third gate of the logic cell and a fourth input signal potential to the fourth gate of the logic cell produces at least one logical function output of the second logic plane.

Description

TECHNICAL FIELD OF THE INVENTION

This invention relates generally to integrated circuits and in particular to vertical gate transistors in pass transistor programmable logic arrays.

BACKGROUND OF THE INVENTION

Many programmable logic arrays include multiple transistors arrayed such that a combination of activated transistors produce a logical function. Such transistors in the array are activated, in the case of MOSFET devices, by either applying or not applying a potential to the gate of the MOSFET. This action either turns on the transistor or turns off the transistor. Conventionally, each logical input to the programmable logic array is applied to an independent MOSFET gate. Thus, according to the prior art, a full MOSFET is required for each input to the programmable logic array. Requiring a full MOSFET for each logic input consumes a significant amount of chip surface area. Conventionally, the size of each full MOSFET, e.g. the space it occupies, is determined by the minimum lithographic feature dimension. Thus, the number of logical functions that can be performed by a given programmable logic array is dependent upon the number of logical inputs which is dependent upon the available space to in which to fabricate an independent MOSFET for each logic input. In other words, the minimum lithographic feature size and available surface determine the functionality limits of the programmable logic array.

Pass transistor logic is one of the oldest logic techniques and has been described and used in NMOS technology long before the advent of the CMOS technology currently employed in integrated circuits. A representative textbook by L. A. Glasser and D. W. Dobberpuhl, entitled "The design and analysis of VLSI circuits," Addison-Wesley, Reading Mass., 1985, pp. 16 20, describes the same. Pass transistor logic was later described for use in complementary pass transistor circuits in CMOS technology. Items which outline such use include a textbook by J. M. Rabaey, entitled "Digital Integrated Circuits; A design perspective," Prentice Hall, Upper Saddle River, N.J., pp. 210 222, 1996, and an article by K. Bernstein et al., entitled "High-speed design styles leverage IBM technology prowess," MicroNews, vol. 4, no. 3, 1998. What more, there have been a number of recent applications of complementary pass transistor logic in microprocessors. Articles which describe such applications include articles by T. Fuse et al., entitled "A 0.5V 200 mhz 1-stage 32b ALU using body bias controlled SOI pass-gate logic," Dig. IEEE Int. Solid-State Circuits Conf., San Francisco, pp. 286 287, 1997, an article by K. Yano et al., entitled "Top-down pass-transistor logic design," IEEE J. Solid-State Circuits, Vol. 31, no. 6, pp. 792 803, June 1996, and an article by K. H. Cheng et al., entitled "A 1.2V CMOS multiplier using low-power current-sensing complementary pass-transistor logic", Proc. Third Int. Conf. On Electronics, Circuits and Systems, Rodos, Greece, 13 16 October, vol. 2, pp. 1037 40, 1996.

In another approach, differential pass transistor logic has been developed to overcome concerns about low noise margins in pass transistor logic. This has been described in an article by S. I. Kayed et al., entitled "CMOS differential pass-transistor logic (CMOS DPTL) predischarge buffer design," 13th National Radio Science Conf., Cairo, Egypt, pp. 527 34, 1996, as well as in an article by V. G. Oklobdzija, entitled "Differential and pass-transistor CMOS logic for high performance systems," Microelectronic J., vol. 29, no. 10, pp. 679 688, 1998. Combinations of pass-transistor and CMOS logic have also been described. S. Yamashita et al., "Pass-transistor? CMOS collaborated logic: the best of both worlds," Dig. Symp. On VLSI Circuits, Kyoto, Japan, 12 14 June, pp. 31 32, 1997. Also, a number of comparisons of pass transistor logic and standard CMOS logic have been made for a variety of different applications and power supply voltages. These studies are described in an article by R. Zimmerman et al., entitled "Low-power logic styles: CMOS versus pass transistor logic," IEEE J. Solid-State Circuits, vol. 32, no. 7, pp. 1079 1790, July 1997, and in an article by C. Tretz et al., "Performance comparison of differential static CMOS circuit topologies in SOI technology," Proc. IEEE Int. SOI Conference, October 5 8, FL, pp. 123 4, 1998.

However, all of these studies and articles on pass transistor logic have not provided a solution to the constraints placed on programmable logic arrays by the limits of the minimum lithographic feature size and the deficit in the available chip surface space. An approach which touches upon overcoming the limits of the minimum lithographic feature size and the deficit in the available chip surface space, is disclosed in the following co-pending, commonly assigned U.S. patent applications by Len Forbes and Kie Y. Ahn, entitled: "Programmable Logic Arrays with Transistors with Vertical Gates," Ser. No. 09/583,584, "Horizontal Memory Devices with Vertical Gates," Ser. No. 09/584,566, and "Programmable Memory Decode Circuits with Vertical Gates," Ser. No. 09/584,564. Those disclosures are all directed toward a non volatile memory cell structure having vertical floating gates and vertical control gates above a horizontal enhancement mode channel region. In those disclosures one or more of the vertical floating gates is charged by the application of potentials to an adjacent vertical gate. The devices of those disclosures can be used as flash memory, EAPROM, EEPROM devices, programmable memory address and decode circuits, and/or programmable logic arrays. Those applications, however, are not framed to address overcoming the limits of the minimum lithographic feature size and the deficit in the available chip surface space for purposes of pass transistor logic in programmable logic arrays.

Therefore, there is a need in the art to provide improved pass transistor logic in programmable logic arrays which overcome the aforementioned barriers.

SUMMARY OF THE INVENTION

The above mentioned problems with pass transistor logic in programmable logic arrays and other problems are addressed by the present invention and will be understood by reading and studying the following specification. Systems and methods are provided for pass transistor logic in programmable logic arrays having transistors with multiple vertical gates. The multiple vertical gates serve as multiple logic inputs. The multiple vertical gates are edge defined such that only a single transistor is required for multiple logic inputs. Thus, a minimal surface area is required for each logic input.

In one embodiment of the present invention, a novel programmable logic array is provided. The novel programmable logic array includes a plurality of input lines for receiving an input signal, a plurality of output lines, and one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines. The first logic plane and the second logic plane comprise a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to the received input signal. According to the teachings of the present invention, each logic cell includes a source region and a drain region in a horizontal substrate. A depletion mode channel region separates the source and the drain regions. A number of vertical gates are located above different portions of the depletion mode channel region. At least one of the vertical gates is located above a first portion of the depletion mode channel region and is separated from the channel region by a first thickness insulator material. At least one of the vertical gates is located above a second portion of the channel region and is separated from the channel region by a second thickness insulator material. According to the present invention, there is no source nor drain region associated with each input and the gates have sub-lithographic horizontal dimensions by virtue of being edge defined vertical gates.

These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A illustrates a novel static pass transistor according to the teachings of the present invention.

FIG. 1B is a schematic illustration of the novel static pass transistor shown in FIG. 1A.

FIG. 1C is an illustration of the operation of the novel static pass transistor described in connection with FIGS. 1A and 1B.

FIG. 1D is another characterization of the novel static pass transistor of FIG. 1C.

FIG. 1E is a further illustration showing that depletion mode n-channel MOSFETs are "on" with zero gate voltage and that a negative applied gate voltage turns "off" the depletion mode n-channel.

FIG. 2A illustrates one embodiment for the variance between the first oxide thickness (t1) and the second oxide thickness (t2) in the novel static pass transistor of the present invention.

FIG. 2B is an energy band diagram illustrating the effect on the conduction in the depletion mode channel beneath the first oxide thickness (t1) when a zero Volts gate potential (Vg) is applied above according to one embodiment of the present invention.

FIG. 2C is an energy band diagram illustrating the effect on the conduction in the depletion mode channel beneath the first oxide thickness (t1) with a negative applied gate potential (Vg) of approximately -0.6 Volts.

FIG. 3A is an illustration of another embodiment configuration for the novel static pass transistor of the present invention.

FIG. 3B is another characterization of the novel static pass transistor of FIG. 3A.

FIG. 4A is an illustration of another operational state for the novel static pass transistor shown in FIGS. 3A and 3B.

FIG. 4B is another characterization of the novel static pass transistor of FIG. 4A.

FIG. 5 illustrates a programmable logic array according to the teachings of the prior art.

FIG. 6 illustrates an embodiment for a novel programmable logic array according to the teachings of the present invention.

FIGS. 7A 7F illustrate one method for forming the novel static pass transistors of the present invention.

FIG. 8A 8D illustrate an embodiment of a variation on the fabrication process shown in FIGS. 7A 7F.

FIGS. 9A 9C illustrate another embodiment of a variation on the fabrication process to make all of the gates over thin gate oxides.

FIGS. 10A 10D illustrate another embodiment of a variation on the fabrication process to allow the fabrication of different gate oxide thicknesses under various gates to make some lines active and others as passing lines.

FIGS. 11A and 11B are an illustration of an embodiment in which a number of input lines which collectively pass over multiple MOSFET logic cells is a logic circuit block, can be contacted at the edge of a logic circuit according to the teachings of the present invention.

FIG. 12 illustrates a block diagram of an embodiment of an electronic system according to the teachings of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The terms wafer and substrate used in the following description include any structure having an exposed surface with which to form the integrated circuit (IC) structure of the invention. The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. The term conductor is understood to include semiconductors, and the term insulator is defined to include any material that is less electrically conductive than the materials referred to as conductors. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.

According to the teachings of the present invention, a pass transistor logic is described where transistors with multiple vertical gates are employed in static CMOS combinational logic circuits. The pass transistors are similar to a regular series connection of individual transistors except here because of the close proximity of the gates of address lines separate and individual source/drain regions are not required between the gates. An implanted depletion mode channel serves to form the conductive region not only under each gate region but also between different gate regions.

FIG. 1A illustrates a novel static pass transistor 101 according to the teachings of the present invention. As shown in FIG. 1A, the static pass transistor 101 includes a source region 110 and a drain region 112 in a horizontal substrate 100. A depletion mode channel region 106 separates the source region 110 and the drain region 112. A number of vertical gates 104-1, 104-2, . . . , 104-N, are located above different portions of the depletion mode channel region 106. According to the teachings of the present invention, the number of vertical gates 104-1, 104-2, . . . , 104-N, are edge defined vertical gates such that each of the number of vertical gates 104-1, 104-2, . . . , 104-N, has a horizontal width (W) which is sub-lithographic in dimension. In one embodiment, each of the number of vertical gates 104-1, 104-2, . . . , 104-N, has a horizontal width of approximately 100 nanometers (nm). According to one embodiment of the present invention, the number of vertical gates 104-1, 104-2, . . . , 104-N, includes a number of polysilicon vertical gates 104-1, 104-2, . . . , 104-N. At least one of the vertical gates, e.g. vertical gate 104-3, is located above a first portion 108 of the depletion mode channel region 106 and is separated from the depletion mode channel region 106 by a first thickness insulator material (t1). In one embodiment, the first thickness insulator material (t1) includes a first oxide thickness (t1). At least one of the vertical gates, e.g. vertical gate 104-N, is located above a second portion 109 of the depletion mode channel region 106 and is separated from the depletion mode channel region 106 by a second thickness insulator material (t2). In one embodiment, the second thickness insulator material (t2) includes a second oxide thickness (t2). As shown in FIG. 1A, the second oxide thickness (t2) is greater than the first oxide thickness (t1). In one embodiment, the first oxide thickness (t1) is less than 50 Angstroms (.ANG.) and the second oxide thickness (t2) is less than 350 Angstroms (.ANG.). In one embodiment, the first oxide thickness (t1) is approximately 33 .ANG. and the second oxide thickness (t2) is approximately 330 .ANG..

As shown in FIG. 1A, the number of vertical gates 104-1, 104-2, . . . , 104-N, are parallel and opposing one another. The number of vertical gates 104-1, 104-2, . . . , 104-N, are separated from one another by an intergate dielectric 114. In one embodiment, the intergate dielectric 114 includes silicon dioxide (SiO.sub.2). In one embodiment, the number of vertical gates 104-1, 104-2, . . . , 104-N, have a vertical height of approximately 500 nanometers (nm). Also, in one embodiment of the present invention, the horizontal depletion mode channel has a depth (tsi) in the horizontal substrate of approximately 400 .ANG.. According to the teachings of the present invention, the number of vertical gates 104-1, 104-2, . . . , 104-N, serve as logic inputs 104-1, 104-2, . . . , 104-N, for the static pass transistor 101.

FIG. 1B is a schematic illustration of the novel static pass transistor shown in FIG. 1A. The schematic of FIG. 1B shows the number of vertical gates 104-1, 104-2, . . . , 104-N, as multiple conductive nodes A, B, C, and D above the horizontal depletion mode channel. An independent potential can be applied to each of the conductive nodes A, B, C, and D. Conductive nodes A and C are represented as gates since they are separated from the depletion mode channel by the first oxide thickness. Conductive nodes B and D are shown just as nodes since they are separated from the depletion mode channel by the second oxide thickness. The static pass transistor 101 is further shown coupled to a buffer mode amplifier 102 to provide gain. The channel is uniformly depletion mode or normally "on" and can conduct with zero potential applied to the conductive nodes A, B, C, and D. In operation, the conductive nodes A and C serve as multiple logic inputs, or active inputs, and can effect conduction in the depletion mode channel. Conductive nodes B and D, on the other hand cannot effect conduction in the depletion mode channel because they are further distanced from the depletion mode channel by the second oxide thickness. In other words, conductive nodes B and D have no control over the depletion mode channel and can not turn the depletion mode channel "off." Conductive nodes B and D thus function as passing lines over the depletion mode channel. In one operation embodiment, if a negative potential is applied to either of the conductive nodes A and C this negative potential works to turn "off" a portion of the depletion mode channel beneath that particular conductive node or gate. In one operation embodiment, a negative potential of approximately -0.6 Volts applied to either conductive node A or C will block conduction in the depletion mode channel. On the other hand, if conductive nodes A and C both have an applied potential of approximately zero Volts then the novel static pass transistor 101 conducts. Thus, in this embodiment, the novel static pass transistor 101 operates as a two input positive logic NAND gate. The conductive nodes A, B, C, and D make up a logic chain. And, the novel static pass transistor can function with an operating voltage range of approximately +/-0.5 Volts.

FIG. 1C is an illustration of the operation of the novel static pass transistor described in connection with FIGS. 1A and 1B. FIG. 1C shows four vertical gates 104-1, 104-2, 104-3, and 104-4 formed of heavily doped n+ type polysilicon. The four vertical gates 104-1, 104-2, 104-3, and 104-4 are located above a horizontal depletion mode channel 106 which separates heavily doped n+ type source and drain regions, 110 and 112 respectively. The horizontal depletion mode channel includes a lightly doped n type channel. In FIG. 1C, a independent potential of -0.6 Volts is applied to each of the four vertical gates 104-1, 104-2, 104-3, and 104-4. Vertical gates 104-1 and 104-3 are separated by a first oxide thickness (t1) from the depletion mode channel which is less than a second oxide thickness (t2) separating vertical gates 104-2 and 104-4 from the depletion mode channel. Thus, the negative potential on vertical gates 104-1 and 104-3 turns off conduction in that portion of the depletion mode channel beneath those vertical gates as shown in FIG. 1C. By contrast, the negative potential on vertical gates 104-2 and 104-4 does not control or effect conduction in the depletion mode channel.

FIG. 1D is another characterization of the novel static pass transistor of FIG. 1C. Conductive nodes A, B, C, and D represent the four vertical gates 104-1, 104-2, 104-3, and 104-4. The regions beneath conductive nodes A and C with their negative applied potentials can be characterized as "gated," but "off." The regions beneath conductive nodes B and D with their negative applied potentials can be characterized as "not gated," or "on" since these conductive nodes are separated from the depletion mode channel by the thicker second oxide thickness. Conductive node B and D thus function as passing lines. FIG. 1E is a further illustration showing that depletion mode n-channel MOSFETs are "on" with zero gate voltage and that a negative applied gate voltage turns "off" the depletion mode n-channel. In one embodiment, the threshold voltage (Vt) required to turn "off" the depletion mode n-channel is approximately -0.6 Volts.

FIGS. 2A 2C illustrate an operating voltage range for the novel static pass transistor of the present invention for certain values of a first oxide thickness (t1) and a second oxide thickness (t2). FIG. 2A illustrates one embodiment for the variance between the first oxide thickness (t1) and the second oxide thickness (t2). As shown in FIG. 2A, the first oxide thickness (t1) and the second oxide thickness (t2) are located above a horizontal depletion mode channel 206. In the embodiment shown in FIG. 2A, first oxide thickness (t1) is less than the second oxide thickness (t2). In one embodiment, the first oxide thickness (t1) is approximately 33 .ANG. and the second oxide thickness is approximately 330 .ANG.. As shown in FIG. 2A, the depletion mode channel extends a thickness (tsi) into the horizontal substrate. In one embodiment, th