Method of constructing a capacitor stack for a flat capacitor Number:6,763,265 from the United States Patent and Trademark Office (PTO) owispatent In one aspect, a method of manufacturing a capacitor includes disposing one or more conductive layers of a first electrode stack in a recess of an alignment mechanism, where the recess is positioned relative to two or more alignment elements. The method further includes placing a separator over the one or more conductive layers where an outer edge of the separator contacts the two or more alignment elements. In one embodiment, a capacitor includes anode and cathode foils having offsetting edge portions. In one embodiment, a multiple tab cathode for a flat capacitor. A plurality of cathode tabs are portioned into a plurality of cathode tab groups positioned in different locations along the edge of the capacitor stack to reduce the amount of space required for connecting and routing the cathode tabs.<H constructing, capacitor, Method, of, const, 6763265.html, Patent, pto, 6763265

Title: Method of constructing a capacitor stack for a flat capacitor

Abstract: In one aspect, a method of manufacturing a capacitor includes disposing one or more conductive layers of a first electrode stack in a recess of an alignment mechanism, where the recess is positioned relative to two or more alignment elements. The method further includes placing a separator over the one or more conductive layers where an outer edge of the separator contacts the two or more alignment elements. In one embodiment, a capacitor includes anode and cathode foils having offsetting edge portions. In one embodiment, a multiple tab cathode for a flat capacitor. A plurality of cathode tabs are portioned into a plurality of cathode tab groups positioned in different locations along the edge of the capacitor stack to reduce the amount of space required for connecting and routing the cathode tabs.

Patent Number: 6,763,265 Issued on 07/13/2004 to O'Phelan, et al.

Inventors: O'Phelan; Michael J. (Oakdale, MN), Poplett; James M. (Plymouth, MN), Tong; Robert R. (Valencia, CA), Barr; A. Gordon (Burnsville, MN), Kavanagh; Richard J. (Brooklyn Park, MN), Waytashek; Brian V. (Lino Lakes, MN)
Assignee: Cardiac Pacemakers, Inc. (St. Paul, MN)

Appl. No.: 10/418,616

Filed: April 17, 2003

Related U.S. Patent Documents


Application Number	Filing Date	Patent Number	Issue Date
705994	Nov., 2000	6571126

Current U.S. Class: 607/5 ; 216/33; 216/6; 29/25.03

Current International Class: A61N 1/39 (20060101)

Field of Search: 607/5,9,17,36 361/502,503,517,520,523,535 29/25.01,25.02,25.03 429/30,94 216/6,33

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Primary Examiner: Wolfe; Willis R.
Attorney, Agent or Firm: Schwegman, Lundberg, Woessner & Kluth, P.A.

Parent Case Text

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 09/705,994, filed on Nov. 3, 2000, now U.S. Pat. No. 6,571,126, the specification of which is incorporated herein by reference.

This application is related to application Ser. No. 09/706,447, filed on Nov. 3, 2000, entitled FLAT CAPACITOR FOR AN IMPLANTABLE MEDICAL DEVICE, now U.S. Pat. No. 6,699,265, the specification of which is incorporated herein by reference in its entirety.

Claims

What is claimed is:

1. A method of manufacturing a flat capacitor stack, comprising: forming a plurality of capacitor layers, each capacitor layer including a separator layer attached to a capacitor foil layer; and placing each of the plurality of capacitor layers onto a capacitor stack by aligning each of the capacitor layers using an outer edge of the separator layer of the capacitor layer as an alignment means.

2. The method of claim 1, wherein aligning includes positioning the separator layer such that two or more points on an outer edge of the separator layer contact two or more corresponding alignment members.

3. The method of claim 1, further comprising pressing the capacitor stack to a specified, predetermined height after the capacitor stack has been formed.

4. The method of claim 1, further comprising annealing the capacitor stack after the capacitor stack has been formed.

5. The method of claim 1, wherein placing each of the plurality of capacitor layers includes: providing an alignment mechanism; and placing each capacitor layer within the alignment mechanism such that an outer edge of each separator layer contacts one or more alignment members of the alignment mechanism.

6. The method of claim 1, wherein forming a plurality of capacitor layers includes forming a first anode stack having or more anode layers and having a first surface area, and forming a second anode stack having or more anode layers and having a second surface area, wherein the first surface area is greater than the second surface area.

7. The method of claim 6, wherein the second anode stack has one or more less anode layers than the first anode stack.

8. A flat capacitor having a capacitor stack formed by a method including: forming a plurality of capacitor layers, each capacitor layer including a separator layer attached to a capacitor foil layer; and placing each of the plurality of capacitor layers onto a capacitor stack by aligning each of the capacitor layers using an outer edge of the separator layer of the capacitor layer as an alignment means.

9. The flat capacitor of claim 8, wherein aligning the separator layer includes positioning the separator layer such that two or more points on an outer edge of the separator layer contact two or more corresponding two or more alignment members.

10. The flat capacitor of claim 8, further comprising pressing the capacitor stack to a specified, predetermined height.

11. The flat capacitor of claim 8, further comprising annealing the capacitor stack.

12. The flat capacitor of claim 8, wherein aligning each of the plurality of capacitor layers includes: providing an alignment mechanism; and placing each capacitor layer within the alignment mechanism such that an outer edge of each separator layer contacts one or more alignment members of the alignment mechanism.

13. The flat capacitor of claim 8, wherein at least one of the plurality of capacitor layers includes a first anode stack having or more anode layers and having a first surface area, and wherein at least one of the plurality of capacitor layers includes a second anode stack having or more anode layers and having a second surface area, wherein the first surface area is greater than the second surface area.

14. The flat capacitor of claim 13, wherein the second anode stack has one or more less anode layers than the first anode stack.

Description

TECHNICAL FIELD

The present invention concerns implantable medical devices, such as defibrillators and cardioverters, and more specifically to a method of manufacturing a capacitor stack for a flat capacitor.

BACKGROUND

Since the early 1980s, thousands of patients prone to irregular and sometimes life-threatening heart rhythms have had miniature heart monitors, particularly defibrillators and cardioverters, implanted in their bodies. These devices detect onset of abnormal heart rhythms and automatically apply corrective electrical therapy, specifically one or more bursts of electric current to the heart. When the bursts of electric current are properly sized and timed, they restore normal heart function without human intervention, sparing patients considerable discomfort and often saving their lives.

The typical defibrillator or cardioverter includes a set of electrical leads, which extend from a sealed housing into the wall of a heart after implantation. Within the housing are a battery for supplying power, monitoring circuitry for detecting abnormal heart rhythms, and a capacitor for delivering bursts of electric current through the leads to the heart.

Flat capacitors generally include a stack of flat capacitor elements, with each element including a paper separator between two sheets of aluminum foil. One of the foils serves as the anode of the capacitor element, and the other serves as the cathode.

One or more of the capacitor elements are often die cut in a shape designed to conform to a capacitor case. The cutting results in undesired residual stresses, and in warpage of the capacitor element. Stacking a plurality of these types of capacitor elements may result in increased height to the assembly. Moreover, the foil strip used to produce the capacitor element may not have the desired flatness prior to processing. Undesired residual stress due to this factor may also result in warpage of the capacitor assembly, enough to add height to the assembly. Moreover, the foils are cut using high-precision dies which are not only expensive, but require repeated sharpening. Another problem that arises is that cutting the foils can produce burrs on the cut edges of the foils. When edge burrs on adjacent anode and cathode foils contact each other, a conductive path results that short circuits the capacitive element.

Each anode foil in the stack, and each cathode foil in the stack, is interconnected to the other anodes and cathodes respectively. The anodes and cathodes generally include tabs which are crimped or welded together. Connecting the anodes and cathodes in this way provides a total capacitance equal to the sum of the capacitances of all the capacitor elements. However, the anode and cathode interconnections cause designers to increase the size of the capacitor case to accommodate tabs or to remove a portion of the capacitive elements, which reduces total capacitance or increases the size of the capacitor.

Moreover, since defibrillators and cardioverters are typically implanted in the left region of the chest or in the abdomen, a smaller size device, which is still capable of delivering the required level of electrical energy, is desirable.

Accordingly, there is a need for capacitor structures and methods of manufacture which provide greater process control, less expensive manufacturing, provide for a design efficiently utilizing space within the capacitor case, and provide for a compact capacitor design capable of providing the required pulse of energy for use within the implantable device.

SUMMARY

In one embodiment, a method of manufacturing a capacitor includes disposing one or more conductive layers of a first electrode stack in a recess of an alignment mechanism, where the recess is positioned relative to two or more alignment elements. The method further includes placing a separator over the one or more conductive layers where an outer edge of the separator contacts the two or more alignment elements. In addition, the method includes securing the aligned separator and conductive layers to one another to form an anode or a cathode stack.

In one embodiment, a method of manufacturing a capacitor includes providing an alignment mechanism having a plurality of alignment elements and a recess, each alignment element having a position corresponding to a point on the outer edge of either a first electrode stack or second electrode stack. The method further comprises aligning a portion of at least one first electrode stack relative to the recess and the alignment elements, and removing the aligned first electrode stack. In addition, the method further includes aligning a portion of at least one second electrode stack relative to a second alignment mechanism including a second recess and second alignment elements. The method further includes removing the aligned second electrode stack.

One aspect provides a multi-tab base foil layer for a flat capacitor. The base tabs of the base foil layer are spaced laterally along a vertical face of the capacitor stack. In addition to the base layer, the capacitor stack of foil layers includes secondary layers. The secondary layers have matching tabs that overlay the base tabs of the base layer. In one embodiment, this arrangement reduces the space required for connecting and routing the tab groups and this allows a reduction in the size of the capacitor, or alternatively an increase in its capacitance, or energy-storage capacity.

One aspect provides a capacitor stack structure that is more tolerant of edge burrs in the cut foil layers. In one embodiment, a capacitor with anode and cathode layers having non-overlapping edge portions. The cathode and anode layers are shaped or positioned such that edge portions of the two layers are offset from one another in a layered structure.

In one or more embodiments, the above described methods and structures provide for a capacitor making efficient use of space within the case, increased anodic surface area and increased capacitance for a capacitor of a given set of dimensions. Variation in the outer dimensions of one capacitor stack to another capacitor stack is reduced because each is formed within alignment elements positioned the same manner. Dimensional variations in the capacitor stack resulting from variation in the reference points from case to case or alignment apparatus to alignment apparatus are eliminated. This provides improved dimensional consistency in production and allows for reduced tolerances between the capacitor stack and the capacitor case. This allows for more efficient use of space internal to the capacitor case.

These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims and their equivalents.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a perspective view of a flat capacitor according to one embodiment of the present invention.

FIG. 2 is an exploded perspective view of a capacitor stack constructed in accordance with one embodiment.

FIG. 3 is an exploded perspective view of an anode stack constructed in accordance with one embodiment.

FIG. 4 is a side view of an anode stack and edge connection member constructed in accordance with one embodiment.

FIG. 5 is a side view of a separator constructed in accordance with one embodiment;

FIG. 6 is an exploded perspective view of a cathode base layer stack constructed in accordance with one embodiment.

FIG. 7 is an exploded perspective view of a cathode stack constructed in accordance with one embodiment.

FIG. 8 is an exploded perspective view of a cathode stack constructed in accordance with one embodiment.

FIG. 9 is an exploded perspective view of a cathode stack constructed in accordance with one embodiment.

FIG. 10 is an exploded perspective view of a cathode stack constructed in accordance with one embodiment.

FIG. 11A is a perspective view of an alignment mechanism constructed in accordance with one embodiment.

FIG. 11B is a perspective view of an alignment mechanism constructed in accordance with one embodiment.

FIG. 12 is a perspective view of a capacitor stack in an alignment mechanism constructed in accordance with one embodiment.

FIG. 13 is a top view of an anode stack aligned within an external alignment mechanism constructed in accordance with one embodiment.

FIG. 14 is a top view of staking locations for a plurality of anode stacks constructed in accordance with one embodiment.

FIG. 15 is a cross-sectional view of the staking locations of FIG. 14.

FIG. 16 is a top view of a cathode stack within an alignment mechanism constructed in accordance with one embodiment.

FIG. 17 is a perspective view of a cathode stack in an alignment mechanism constructed in accordance with one embodiment.

FIG. 18 is a top view of a capacitor stack according to one embodiment.

FIG. 19 is a side schematic view of the capacitor stack of FIG. 18.

FIG. 20 is a side schematic view of a capacitor stack according to one embodiment.

FIG. 21 is a cross-sectional view of a capacitor stack constructed in accordance with one embodiment.

FIG. 22 is an exploded view of an anode stack constructed in accordance with one embodiment.

FIG. 23 is an exploded view of a modified anode stack constructed in accordance with one embodiment.

FIG. 24 is an exploded view of a mixed anode stack constructed in accordance with one embodiment.

FIG. 25 is a cross-sectional view of a capacitor stack constructed in accordance with one embodiment.

FIG. 26 is a perspective view of a capacitor stack according to one embodiment.

FIG. 27 is a perspective view of the capacitor stack of FIG. 26.

FIG. 28 is a perspective view of the capacitor stack of FIG. 26 with a plurality of tab groups positioned on the top surface of the capacitor stack.

FIG. 29 is a partial exploded side view of the capacitor stack of FIG. 26.

FIG. 30 is a partial side view of a capacitor stack according to one embodiment.

FIG. 31 is a flow chart of a method for manufacturing a capacitor in accordance with one embodiment.

FIG. 32 is a block diagram of a implantable medical device system constructed in accordance with one embodiment.

DESCRIPTION OF EMBODIMENTS

In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that structural changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims and their equivalents.

FIG. 1 shows a partially exploded view of an exemplary embodiment of capacitor 18. The present embodiment shows a D-shaped capacitor. In other embodiments, capacitor 18 may be designed in a variety of flat shapes to conform to various housing shapes. The capacitor includes a metallic case 20 defining a chamber 22, in which is placed a capacitor stack 24. In one embodiment, case 20 is manufactured from a conductive material, such as aluminum. In another option, the case 20 is manufactured using a nonconductive material, such as a ceramic or a plastic.

Case 20 includes a base 26 and a lid 28 overlying and resting on an upper rim of base 26. Stack 24 has a face 30 and a top surface 32. Stack 24 has a cutout region 34 at its periphery, with cutout region 34 being positioned when the stack 24 is installed in case 20 to provide space for electrical connections. An anode feedthrough post 36 passes through to stack 24 and is electrically insulated from case 20. The capacitor stack 24 is covered with insulating tape 38. A space 40 exists between the lid 28 and the top surface 32 of the stack 24 and between the face 30 of the stack 24 and a lateral wall of the base 26 of the case 20. In some embodiments, space 40 is a line-to-line interference fit between portions of stack 24 and case 20. In other embodiments, space 40 is a gap or opening within the case and between the stack and the case.

Capacitor stack 24 includes anode assemblies and cathode assemblies, with separator layers interposed therebetween.

FIG. 2 illustrates an exploded view of capacitor stack 24 according to one embodiment. Stack 24 includes a plurality of layers 120 which include at least one first electrode comprised of an anode stack 100, at least one separator 200, and at least one second electrode comprised of one of cathode stacks 300. The separator 200 separates each anode stack 100 from each cathode stack 300.

FIG. 3 illustrates an exploded view of one example of an anode stack 100. The anode stack 100 includes a plurality of anode layers including conductive layers 115 consisting of an upper conductive layer 110, a middle conductive layer 114, and a lower conductive layer 116 as well as an anode-separator layer 90. Each conductive anode layer has a first edge 111, 121, 131, and 141, respectively. Each anode layer also includes a clearance area defined by a second edge 112, 122, 132, 142. Each anode layer also includes an optional second edge 113, 123, 133, 143, respectively. The anode stack 100 further includes an edge connection member such as edge clip 150 for use in interconnecting the anode layers in adjacent layers of the capacitor stack 24.

FIG. 4 illustrates a portion of an assembled anode stack 100. The clearance area defined by the second edge 142 of the anode-separator 90 leaves the upper surface 154 of the edge clip 150 exposed for contact with an adjacent edge clip 150 of an adjacent layer 120.

FIG. 5 illustrates a separator 200 which separates the anode stack 100 from the cathode stack 300 (FIG. 2). The separator 200 includes a first edge 251 a clearance area defined by a second edge 252 and a flat edge 253. The clearance area of the separator 200 allows a side portion of the edge clip 150 (FIG. 3) to extend past the separator to reach an edge clip of an adjacent anode stack 100 (FIG. 2). The separator 200 is, in one option, made from a roll or sheet of separator material. Suitable materials for the separator material include, but are not limited to, pure cellulose or Kraft paper. Other chemically inert materials are suitable as well, such as porous polymeric materials. The separator 200 is cut slightly larger than the anode layers (or cathode layers) to accommodate misalignment during the stacking of layers, to prevent subsequent shorting between electrodes of opposite polarity, and to act as an outermost edge for alignment.

FIG. 6 illustrates an exploded view of an embodiment of a cathode base stack 50 including a cathode conductive layer 60 and a cathode-separator layer 70. In this embodiment, cathode conductive layer 60 includes one or more legs 54a, 54b, 54c, 54d extending from the flat edge 363. The cathode conductive layer 60 also includes a cathode extension member 62 for coupling the capacitor stack 24 to the case 20 (FIG. 1). Cathode legs 54a, 54b, 54c, 54d and cathode extension leg 62 extend beyond the dimensions defined by the inside of the case 20 during intermediate steps in the manufacturing process and are later formed to fit within the case. The cathode conductive layer 60 includes a first edge 361 inset from the first edges of the anode layers 110, 114, 116, and 90 (FIG. 3) and inset from the second edges of the anode layers 110, 114, 116, and 90. The conductive layer 60 also includes a flat edge 363 inset from the flat edges of the anode layers 110, 114, 116, and 90.

Cathode-separator layer 70 is also provided and includes a first edge 371, a clearance area defined by a second edge 372, a flat edge 373 and an extension edge 374. The cathode conductive layer 60 includes a first edge 361 inset from the first edge 371 of the cathode-separator and inset from the second edges of the cathode-separator layer 70. The cathode conductive layer 60 also includes a flat edge 363 inset from the flat edges of the cathode-separator layer 70. The inset edge 361 of the cathode conductive layer 60 and the clearance area of the cathode-separator layer 70 allows a portion of the edge clip 150 (FIG. 3) to extend past the cathode conductive layer 60 and the cathode-separator layer 70 to reach an edge clip 150 (FIG. 3) of an adjacent anode stack.

Referring to FIGS. 7-10, examples of cathode stacks 300 are shown. Cathode stacks 300 include in one embodiment, cathode stacks 301, 302, 303, 304. Each cathode stack 301, 302, 303, 304 includes cathode layers comprising a cathode conductive layer 60 and a cathode-separator layer 70. In this embodiment, each cathode stack 301, 302, 303, 304 conductive layer 60 includes an extension member such as a leg 60a, 60b, 60c, or 60d respectively. Cathode legs 60a-60d on each cathode stack 301, 302, 303, 304 extend beyond the dimensions defined by the case 20 (FIG. 1) during intermediate steps in the manufacturing process and are later formed to fit within the case. In one embodiment, each leg 60a-60d corresponds to leg 54a, 54b, 54c, 54d, respectively, on the cathode base layer stack 50, as will be discussed further below. Each cathode stack 301, 302, 303, 304 includes a cathode conductive layer 60 having a first edge 361, which when stacked, is inset from the first edge 141 of the anode separator 90 (FIG. 3) and inset from the second edge 142 of the anode separator. Further details of cathode stacks 300 will be described below.

In one embodiment of the present invention, the capacitor stack 24 described above is aligned to provide for optimal surface area of the capacitor.

FIGS. 11A, 11B, and 12 illustrate external alignment mechanisms 408, 406, 400 used to assemble anode stack 100, cathode stack 300, and capacitor stack 24, respectively, in accordance with one embodiment. Each of the external alignment mechanisms 408, 406, 400 includes a plurality of precisely placed alignment elements 500.

The alignment elements 500 in this embodiment, are vertically placed alignment elements 501, 502, 503, 504, which extend from a base 402. The base 402 supports components thereon, while the alignment elements 501, 502, 503, 504 align the components while the components are being stacked therein. The external alignment mechanism 400 optionally includes a first recess 520, which is sized and positioned to receive a clip, as further discussed below. In another option, the external alignment mechanisms 406, 408 each include a second recess 506, 508, respectively, in the base 402, as further discussed below.

Referring to FIG. 12, a capacitor stack 24 is assembled within the alignment apparatus 400. The capacitor stack 24 includes the plurality of layers 120. Each layer 122 of the plurality of layers 120 includes at least one first electrode stack, at least one separator 200 (FIG. 2) and at least one second electrode stack. Each first electrode stack, second electrode stack and each separator 200 is aligned relative to the position of the alignment elements 501, 502, 503, and 504. Optionally positioned within the optional channel 600 is a fastener 610, which is for wrapping around a portion of the capacitor stack 24 once the first electrode stacks, separators 200 and second electrode stacks have been stacked and aligned. Placing the fastener 610 in the channel 600 of the external alignment mechanism 400 positions the fastener 610 below the aligned capacitor stack 24 to maintain flatness of the capacitor stack 250, for example, for further processing. Alternatively, or in addition to, the optional channel 600 allows for a gripping device such as pliers to be slipped under the capacitor stack 250. In addition, precise alignment of the capacitor stack 250 is maintained by the alignment elements 500 when wrapping the capacitor stack 250.

FIG. 13 illustrates a top view of anode stack 100 within the anode external alignment mechanism 408, as described in FIG. 11A. To align the anode stack 100, each conductive layer 110, 114, 116, (FIG. 3) is placed in the recess 508. The anode separator 90 (FIG. 3) is placed over the conductive layers 110, 114, 116 and is aligned relative to the alignment elements 501, 502, 503, 504 by positioning the separator such that the first edge 141 and the flat edge 143 extend to contact each of the alignment elements 501, 502, 503, 504. The second recess 508 allows the anode separator 90 to be aligned relative to the conductive layers 110, 114, 116. The alignment elements 501, 502, 503, 504 concentrically align the separator 90 (FIG. 3) relative to the conductive layers 110, 114, 116 (FIG. 3).

In one embodiment, the anode external alignment mechanism 408 includes a recess 520. The recess 520 receives a portion of the edge clip 150 (FIG. 3) that extends beyond the anode stack 100 and allows the conductive layers 115 of the anode stack 100 to lay flat, one on top of the other within the anode external alignment mechanism 408. In one embodiment, the anode stack 100 is staked after being aligned in this manner.

FIG. 14 illustrates one embodiment in which the anode stack 100 is removed from the anode external alignment mechanism 408 (FIG. 13) and staked so that the conductive layers of the anode stack 100 form an anode chip. In one embodiment, the anode stack is staked as described in co-pending U.S. patent application Ser. No. 09/706,518, filed on Nov. 3, 2000, entitled FLAT CAPACITOR HAVING STAKED FOILS AND EDGE-CONNECTED CONNECTION MEMBERS, and incorporated herein by reference in its entirety.

In one embodiment, the staking locations 102 of the anode stacks 100 in the capacitor stack 24 (FIG. 1) are distributed so that anode stacks 100 in adjacent layers have staking locations that are offset from one another, as shown in FIG. 15 In one embodiment, the anode stack 100 is pressed after being staked to help reduce warpage and to reduce the overall height of the anode stack 100. In one embodiment, the anode stack 100 is pressed to a specific, predetermined height.

FIG. 16 illustrates a cathode stack 300 within a cathode external alignment mechanism 406. The same method is used to align the cathode conductive layer 60 and cathode separator layer 70 of the cathode stacks 50, 301, 302, 303 and 304, as was used to align the anode stack 100 (FIG. 13). The cathode conductive layer 60 is disposed within the recess 506, and the cathode separator layer 70 is aligned relative to the alignment elements 501, 502, 503, 504. Since the alignment elements 501, 502, 503, and 504 are placed in the same location for the anode external alignment mechanism 408, the cathode external alignment mechanism 406, and the external alignment mechanism 400 (FIG. 12), allows for the stacks 100, 300 to be better aligned to one another. This helps to reduce variances in alignment which may result from varying tolerance stack ups between layers of the assembly and the alignment mechanism used.

In one embodiment, the cathode separator layer 70 is aligned relative to the plurality of alignment elements 500 by stacking the cathode separator layer 70 so that edge 371 and flat edge 373 extend to contact each of the alignment elements 501, 502, 503, and 504. While aligned, the cathode separator layer 70 is coupled to the cathode conductive layer 60, for example, with adhesive. In one embodiment, each cathode stack 300 is pressed to help reduce warpage and thus to reduce the overall height of the capacitor stack 24 (FIG. 1).

FIG. 17 illustrates a capacitor stack 24 within an external alignment mechanism 400. In this embodiment, the capacitor stack 24 includes a plurality of layers 120, including anode stacks 100 (FIG. 3), and cathode stacks 300 (such as cathode stacks 50, 301-304 in FIGS. 6-10), which were each individually aligned with the anode external alignment mechanism 408 and the cathode external alignment mechanism 406, respectively. The anode stacks 100 and the cathode stacks 50, 301-304 are aligned relative to the alignment elements 500 using one or more outer edges of the cathode separators 70 (FIGS. 6-10) and one or more outer edges of the anode separators 90 (FIG. 3). In one embodiment, capacitor stack 24 includes separators 200 (FIG. 5) and the alignment elements 501, 502, 503, 504 further align each separator 200 relative to the anode stacks 100 and the capacitor stacks 300 using an outer edge of the separator 200 (FIG. 5). In some embodiments, separators 200 are omitted and capacitor stack 24 is aligned relative to the alignment elements 500 using only one or more outer edges of the cathode separators 70 (FIGS. 6-10) and one or more outer edges of the anode separators 90 (FIG. 3).

In one embodiment, a fastener 610 is wrapped around a portion of the stack 24 to retain the alignment of the layers 120 relative to one another. In one embodiment, fastener 610 comprises tape that is wrapped around a central portion of the capacitor stack 24. Optionally, the capacitor stack 24 is then clamped and annealed, with or without the fastener 610. The channel 600 optionally allows for a tool and/or a robot to be disposed under the stack 24.

In some embodiments, the anode stack 100 and the cathode stacks 50, 301-304 are aligned relative to one another within the case 20, instead of using the external alignment mechanism 400, and then are coupled to one another in the aligned position. For instance, an outer edge of a separator of the anode stack 100 (FIG. 3) and an outer edge of a separator of the cathode stacks 50, 301-304 (FIGS. 6-10) would contact an interior surface of the case 20, and would be aligned therein.

Among other advantages, one or more embodiments of the alignment mechanism described provide for a capacitor making efficient use of space within the case, permit increased anodic surface area, and increased capacitance for a capacitor of a given set of dimensions. Variation in the outer dimensions of one capacitor stack to another capacitor stack is reduced because each is formed within alignment elements positioned the same manner. Dimensional variations in the capacitor stack resulting from variation in the reference points from case to case or alignment apparatus to alignment apparatus are eliminated. This provides improved dimensional consistency in production and allows for reduced tolerances between the capacitor stack and the capacitor case. This allows for more efficient use of space internal to the capacitor case. Each first electrode stack, second electrode stack and each separator is aligned relative to the position of the alignment elements.

Moreover, the capacitor stack structure described above provides for greater anodic surface area since, by aligning to the separator, the anode surface area is optimized by not having to provide extraneous alignment notches or other alignment features on the anode foil itself which decrease the anode surface area.

Since the external alignment mechanism is exterior to the case, better visual observation of the alignment of each electrode stack and separator is provided. Furthermore, multiple points are used to make the alignment, reducing the effect of the tolerance stack up between the conductive layer or separator being aligned and the alignment element at any one position. This also facilitates for alignment of components which during certain steps in the manufacturing process have portions which extend beyond the dimensions defined by the case and are later formed to fit within the case.

In some embodiments, the edges of the cathodes and anodes described above are generally co-extensive or aligned with each other within stack 24. In other embodiments, capacitor stack 24 includes anode and cathode layers having at least partially offset edges.

FIG. 18 shows a planar view of a cathode stack 1800 according to one embodiment. The capacitor stack 1800 includes an anode layer 1801, a separator 1802, and a cathode layer 1803 that are configured in a layered structure analogous to capacitor stack 24 described above. The bottom surface in the figure is the anode layer, and the top surface is the cathode layer with the paper separator interposed therebetween. The separator includes two paper separators impregnated with an electrolyte that conducts current between the anode and cathode layers.

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