Method of designing semiconductor integrated circuit device and semiconductor integrated circuit device Number:6,611,943 from the United States Patent and Trademark Office (PTO) owispatent In a semiconductor integrated circuit device and a method of designing the same, design information about circuit cells each having a desired function are described as objects according to selected purposes. The pieces of design information are registered in a cell library as cell information capable of forming any of substrate potential fixed cells and substrate potential variable cells. Further, a data sheet common to the substrate potential fixed cell and the substrate potential variable cell is offered to a user, so that the user is able to make a selection according to the user's purposes. The substrate potential fixed cells and the substrate potential variable cells are mixed together on a semiconductor chip so as to be properly used according to the functions or the like of circuit portions in which the cells are used.<H semiconductor, integrated, Method, of, desig, 6611943.html, Patent, pto, 6611943

Title: Method of designing semiconductor integrated circuit device and semiconductor integrated circuit device

Abstract: In a semiconductor integrated circuit device and a method of designing the same, design information about circuit cells each having a desired function are described as objects according to selected purposes. The pieces of design information are registered in a cell library as cell information capable of forming any of substrate potential fixed cells and substrate potential variable cells. Further, a data sheet common to the substrate potential fixed cell and the substrate potential variable cell is offered to a user, so that the user is able to make a selection according to the user's purposes. The substrate potential fixed cells and the substrate potential variable cells are mixed together on a semiconductor chip so as to be properly used according to the functions or the like of circuit portions in which the cells are used.

Patent Number: 6,611,943 Issued on 08/26/2003 to Shibata, et al.

Inventors: Shibata; Ryuji (Higashiyamato, JP), Shimada; Shigeru (Hoya, JP)
Assignee: Hitachi, Ltd. (Tokyo, JP)

Appl. No.: 09/939,699

Filed: August 28, 2001

Related U.S. Patent Documents


Application Number	Filing Date	Patent Number	Issue Date
131393	Aug., 1998	6340825	Jan., 2002

Foreign Application Priority Data


Aug 21, 1997 [JP]			9-224560
Dec 09, 1997 [JP]			9-338337

Current U.S. Class: 716/1 ; 257/E27.108; 716/12; 716/18

Current International Class: H01L 27/02 (20060101); H01L 27/118 (20060101); G06F 017/50 ()

Field of Search: 716/1-18

References Cited [Referenced By]

U.S. Patent Documents


5105252	April 1992	Kim
5311048	May 1994	Takahashi
5376839	December 1994	Horiguchi
5434436	July 1995	Tamiguchi
5619420	April 1997	Breid
5663662	September 1997	Kurosawa
5763907	June 1998	Dallavalle et al.
5801407	September 1998	Yamada
5898595	April 1999	Bair et al.

Foreign Patent Documents


2269049	Jan., 1994	GB
63090847	Apr., 1988	JP
6-85200	Mar., 1994	JP
6120439	Apr., 1994	JP
6334010	Dec., 1994	JP
7235608	Sep., 1995	JP
6017183	Jan., 1996	JP
WO9721247	Jun., 1997	WO

Other References

Kuroda et al., "A 0.9V 150MHz 10mW 4mm.sup.2 2-D Discrete Cosine Transform Core Processor With Variable-Threshold-Voltage Scheme", ISSCC96. No Page Numbers. .
Kuroda et al., "A High-Speed Low-Power 0.3.mu.m CMOS Gate Array With Variable Threshold Voltage (VT) Scheme", IEEE 1996 Custom Integrated Circuits Conference. No Page Numbers. .
W. Murry, "Chapter 5: CMOS Technology", Zusetsu Cho Eruesuai Koqaku (Illustrated ULSI Engineering in English) pp. 167-191 (in Japanese with English translation)..

Primary Examiner: Garbowski; Leigh M.
Attorney, Agent or Firm: Antonelli, Terry, Stout & Kraus, LLP

Parent Case Text

This Application is a divisional application of U.S. Appln. Ser. No. 09/131,393, filed Aug. 7, 1998, now U.S. Pat. No. 6,340,825B1 issued Jan. 22, 2002, the entire disclosure of which is hereby incorporated by reference.

Claims

What is claimed is:

1. A method of designing a semiconductor integrated circuit device, comprising: defining information about the design of circuit cells, each having a desired function, as objects according to purposes; forming common cell information by a plurality objects; and forming a substrate potential fixed cell and a substrate potential variable cell by adding or deleting predetermined objects to or from the common cell information.

2. A method according to claim 1, wherein said common cell information includes design data about power supply wiring, and wherein said predetermined objects include design data about substrate potential supply wiring.

3. A method according to claim 1, wherein said common cell information includes design data about power supply wiring and substrate potential supply wiring, and wherein said predetermined objects include design data about a wiring pattern for connecting the power supply wiring and the substrate potential supply wiring.

4. A method according to claim 1, wherein said common cell information includes design data about power supply wiring and substrate potential supply wiring in a well region, and wherein said predetermined objects include an object having contact holes for electrically connecting the power supply wiring and the well region and an object having contact holes for electrically connecting the substrate potential supply wiring and the well region, said objects being formed separately from each other.

5. A method according to claim 1, wherein said common cell information includes design data about well regions, and wherein said power supply wiring or said substrate potential supply wiring is electrically connected to said each well region.

6. A method of designing a semiconductor integrated circuit device, comprising: defining design information about circuit cells, each having a desired function, as objects according to purposes; registering circuit-cell design information in a cell library as design resources together with other cell information in the form of cell information capable of forming any of substrate potential fixed cells and substrate potential variable cells by the deletion or addition of information about predetermined objects; and selecting desired circuit cell information from said cell library.

7. A method according to claim 6, further including: registering, in said cell library, cell information including (i) design information about well regions in which a p channel field effect transistor and an n channel field effect transistor are formed; (ii) design information about source-to-drain regions of the p channel field effect transistor and the n channel field effect transistor; (iii) design information about gate electrodes of the p channel field effect transistor and the n channel field effect transistor; (iv) design information about power supply wiring layers and substrate potential supply wiring layers; and (v) design information about through-holes for respectively connecting upper wiring to the source-to-drain regions, said cell information describing at least the design information about the power supply wiring layers and the design information about the substrate potential supply wiring layers as separate objects.

8. A method according to claim 7, wherein design information about buried well regions formed below the well regions of said p channel field effect transistor and said n channel field effect transistor is included in the inverter cell information.

9. A method according to claim 6, wherein said cell information has design information about contact holes for connecting power supply wiring layers to their corresponding well regions and design information about contact holes for connecting substrate potential supply wiring layers to their corresponding well regions, wherein said design information about the contact holes for connecting the power supply wiring layers to their corresponding well regions is described in said cell information as the same object as that for the design information about said power supply wiring layers, and wherein said design information about the contact holes for connecting the substrate potential supply wiring layers to their corresponding well regions is described in said cell information as the same object as that for the design information about said substrate potential supply wiring layers.

10. A method according to claim 6, wherein cell information about memory cell power supply portions, which includes (i) design information about a well region corresponding to a well region for each memory cell, (ii) design information about power supply wiring layers and substrate potential supply wiring layers for respectively supplying source voltages and substrate potentials to the well regions, and (iii) design information about contact holes for respectively connecting the power supply wiring layers and the substrate potential supply wiring layers to the well regions, and which describes at least the design information about the contact holes for the power supply wiring layers and the design information about the contact holes for the substrate potential supply wiring layers as separate objects, is registered in said cell library.

11. A method of designing a semiconductor integrated circuit device, comprising: designing a semiconductor integrated circuit device by using circuit cell information in a cell library, wherein design information about circuit cells is defined as objects, wherein common cell information is formed by said objects, wherein substrate potential fixed cells and substrate potential variable cells are designed by adding or deleting ones of said objects to or from said common cell information, and wherein said circuit cell information is registered in said cell library as design resources and includes said substrate potential fixed cells and said substrate potential variable cells.

12. A method of designing a semiconductor integrated circuit device according to claim 11, wherein said objects include design information about substrate potential supply wiring.

13. A method of designing a semiconductor integrated circuit device, comprising: designing a semiconductor integrated circuit device by using substrate potential fixed cells or substrate potential variable cells, wherein design information about circuit cells is defined as objects, wherein common cell information is formed by said objects, and wherein said substrate potential fixed cells and said substrate potential variable cells are designed by adding or deleting ones of said objects to or from said common cell information.

14. A method of designing a semiconductor integrated circuit device according to claim 13, wherein said objects include design information about substrate potential supply wiring.

15. A method of designing a semiconductor integrated circuit device, comprising: designing substrate potential variable cells, wherein design information about circuit cells is defined as objects, wherein common cell information is formed by said objects of substrate potential fixed cells, and wherein said substrate potential variable cells are designed by adding substrate potential supplying wiring lines to said common cell information, by using a script language.

16. A method of designing a semiconductor integrated circuit device, comprising: designing a semiconductor integrated circuit device by using circuit cell information in a cell library, wherein design information about circuit cells is defined as objects, wherein common cell information is formed by said objects of substrate potential fixed cells, wherein substrate potential variable cells are designed by adding substrate potential supplying wiring lines to said common cell information, by using a script language, and wherein said circuit cell information is registered in said cell library as design resources and includes said substrate potential fixed cells and said substrate potential variable cells.

17. A method of designing a semiconductor integrated circuit device, comprising: designing substrate potential fixed cells or substrate potential variable cells, wherein design information about circuit cells is defined as objects, wherein common cell information is formed by said objects, and wherein said substrate potential variable cells and said substrate potential fixed cells are designed by adding or deleting ones of said objects to or from said common cell information.

18. A method of designing a semiconductor integrated circuit device, comprising: providing a cell library having circuit cell information, wherein design information about circuit cells is defined as objects, wherein common cell information is formed by said objects, wherein substrate potential variable cells and substrate potential fixed cells are designed by adding or deleting ones of said objects to or from said common cell information, and wherein said cell information is registered in said cell library as design resources and includes said substrate potential fixed cells and said substrate potential variable cells.

19. A method of designing a semiconductor integrated circuit device, comprising: providing a cell library having circuit cell information, wherein design information about circuit cells is defined as objects, wherein common cell information is formed by said objects of substrate potential fixed cells, wherein said substrate potential variable cells are designed by adding substrate potential supplying wiring lines to said common cell information, by using a script language, and wherein said circuit cell information is registered in said cell library as design resources and includes said substrate potential fixed cells and said substrate potential variable cells.

20. A method of manufacturing a semiconductor integrated circuit device, comprising: forming a semiconductor integrated circuit device by using circuit cell information in a cell library, wherein design information about circuit cells is defined as objects, wherein common cell information is formed by said objects, wherein substrate potential fixed cells and substrate potential variable cells are designed by adding or deleting ones of said objects to or from said common cell information, and wherein said circuit cell information is registered in said cell library as design resources and includes said substrate potential fixed cells and said substrate potential variable cells.

21. A method of manufacturing a semiconductor integrated circuit device according to claim 20, wherein said objects include design information about substrate potential supply wiring.

22. A method of manufacturing a semiconductor integrated circuit device, comprising: forming a semiconductor integrated circuit device by using substrate potential fixed cells or substrate potential variable cells, wherein design information about circuit cells is defined as objects, wherein common cell information is formed by said objects, and wherein said substrate potential fixed cells and said substrate potential variable cells are designed by adding or deleting ones of said objects to or from said common cell information.

23. A method of manufacturing a semiconductor integrated circuit device according to claim 22, wherein said objects include design information about substrate potential supply wiring.

24. A method of manufacturing a semiconductor integrated circuit device, comprising: forming substrate potential variable cells, wherein design information about circuit cells is defined as objects, wherein common cell information is formed by said objects of substrate potential fixed cells, and wherein said substrate potential variable cells are designed by adding substrate potential supplying wiring lines to said common cell information, by using a script language.

25. A method of manufacturing a semiconductor integrated circuit device, comprising: forming a semiconductor integrated circuit device by using a circuit cell information in a cell library, wherein design information about circuit cells is defined as objects, wherein common cell information is formed by said objects of substrate potential fixed cells, wherein substrate potential variable cells are designed by adding substrate potential supplying wiring lines to said common cell information, by using a script language, and wherein said circuit cell information is registered in said cell library as design resources and includes said substrate potential fixed cells and said substrate potential variable cells.

26. A method of manufacturing a semiconductor integrated circuit device, comprising: forming substrate potential fixed cells or substrate potential variable cells, wherein design information about circuit cells is defined as objects, wherein common cell information is formed by said objects, and wherein said substrate potential variable cells and said substrate potential fixed cells are designed by adding or deleting ones of said objects to or from said common cell information.

27. A method of manufacturing a semiconductor integrated circuit device, comprising: forming a cell library having circuit cell information, wherein design information about circuit cells is defined as objects, wherein common cell information is formed by said objects, wherein substrate potential variable cells and substrate potential fixed cells are designed by adding or deleting ones of said objects to or from said common cell information, and wherein said circuit cell information is registered in said cell library as design resources and includes said substrate potential fixed cells and said substrate potential variable cells.

28. A method of manufacturing a semiconductor integrated circuit device, comprising: forming a cell library having circuit cell information, wherein design information about circuit cells is defined as objects, wherein common cell information is formed by said objects of substrate potential fixed cells, wherein said substrate potential variable cells are designed by adding substrate potential supplying wiring lines to said common cell information, by using a script language, and wherein said cell information is registered in said cell library as design resources and includes said substrate potential fixed cells and said substrate potential variable cells.

Description

BACKGROUND OF THE INVENTION

This invention relates to a method of designing a semiconductor integrated circuit device, and a technique effective in a case in which a plurality of circuits different in characteristic from each other are prepared as a cell library and a user selects a desired circuit from the cell library in the course of design of a semiconductor integrated circuit device. This invention also relates to a technique which is effective for use in the design of an ASIC (Application Specific Integrated Circuit), for example.

It has been known that a semiconductor logic integrated circuit device principally using field effect transistors like MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) is capable of operating at high speed as the threshold voltage of each MOSFET decreases; whereas, since a substantial leakage current is produced during its off state when the threshold voltage thereof is low, the use of a semiconductor logic integrated circuit device will lead to an increase in power consumption. As a characteristic of each MOSFET, a so-called substrate bias effect is known, wherein the threshold voltage thereof will go high as a reverse bias voltage between the source thereof and a base (substrate or well region) increases. Further, a technique for controlling a standby current has been described in Japanese Published Unexamined Patent Application No. Hei 7-235608, for example.

SUMMARY OF THE INVENTION

A technique, wherein an inverter circuit or an inverter INV, capable of switching the potentials of bases (n well and p well) to a source voltage Vcc and a reference voltage Vss, and base or substrate bias voltages Vbp (Vbp>Vcc) and Vbn (Vbn>Vcc), as shown in FIGS. 21(A) and 21(B), is used in place of an inverter INV wherein the potentials of bases (n well and p well) shown in FIGS. 2(A) and 20(B) are fixed to a source voltage Vcc and a reference voltage Vss (Vcc>Vss), respectively, has been described in, for example, "ISSCC Dig. of Tech. Papers", pp. 166-167, 437, February 1996, or IEEE CICC, pp. 53-56, May 1996.

According to this technique, the source voltages Vcc and Vss are applied to the bases (n well and p well) when the circuit is in operation (active), to thereby supply a low reverse bias voltage between the source and substrate or base, whereby each MOSFET is set to a low threshold so as to operate the circuit device at high speed. On the other hand, when the circuit is deactivated (at standby), the substrate bias voltages Vbp and Vbn are applied to the bases (n well and p well) to supply a high reverse bias voltage between the source and the base (well), thereby increasing the threshold of each MOSFET to reduce the leakage current, whereby low power consumption is provided. The present inventors have discussed the semiconductor integrated circuit device using MOSFETs capable of performing switching to the substrate bias voltages. As a result, it became evident that the following problems were inherent in such a device.

When the threshold of each MOSFET is controlled using the above described substrate bias effect in an attempt to realize an IC having desired characteristics, an inconvenience occurs in that wiring or wires for supplying the bias voltages to the well regions used as the bases of the respective MOSFETs are required in large numbers (Vcc line, Vbn/Vcc line, Vss line and Vbn/Vss line) and the area occupied by the circuit, and, in turn, the chip size of the IC, increases.

The development of an ASIC or the like will call for consideration of two cases: a first case where a user desires an IC having low power consumption or reduced chip size even if its operating speed is slow; and a second case where the user desires an IC capable of operating at high speed even if the power consumption increases more or less. When the reverse bias voltage between the source and base (well) is increased or decreased in an attempt to realize the above-described ICs which are different in characteristic from each other, a maker must separately design substrate potential fixed circuit cells and substrate potential variable circuit cells suitable for the respective ICs and prepare them as separate cell libraries. Therefore, the design effort increases, and the labor, such as the extraction of characteristics including delay times or the like of the circuit cells, required when the user designs and evaluates the chip using these circuit cells, the description thereof in the specifications (data sheet or data book), etc. also increases, i.e., the burden of preparing respective specifications for corresponding cell libraries increases.

An object of the present invention is to provide a design technique capable of implementing ICs which are different in cell type from each other without having to increase the burden on the designer.

Another object of the present invention is to provide a design technique capable of easily implementing a semiconductor integrated circuit device in which its chip size, power consumption and operating speed are optimized.

The above, other objects and novel features of this invention will become apparent from the description provided by the present specification and the accompanying drawings.

A summary of a typical one of the features disclosed in the present application will be described as follows:

Design information about circuit cells each having a desired function are described as objects according to desired purposes and are registered in a cell library registered with a plurality of circuit cells for forming ASIC or the like as design resources in the form of cell information capable of forming any of substrate potential fixed and variable cells by only the deletion or addition of information about predetermined objects. Incidentally, the present cell library is stored in a storage medium such as a magnetic disc, an optical disk, a printed material or the like.

As a typical one of the above-described circuit cells, a cell is known which comprises a pair consisting of a p channel MOSFET and an n channel MOSFET constituting a CMOS inverter which falls under the designation of a minimum unit in a circuit, for example. Others used as the circuit cells registered in the cell library may include a basic circuit cell,such as a flip-flop, a NOR gate, a NAND gate or the like, as frequently used in a logic LSI, a CPU peripheral circuit module, such as a CPU core used as a control circuit, a random access memory used as a memory circuit, a timer, a serial communication interface circuit or the like, and a macrocell like an A/D converter, a D/A converter or the like used as a signal processing circuit.

According to the above feature, since only one kind of cell may be designed for circuits having the same function, a maker can reduce the burden on the design and labor, such as the extraction of characteristics such as voltage dependency, temperature dependency, delay times or the like of each designed cell, the description thereof in the specifications, etc., and, in its turn, achieve a reduction in cost as well.

Further, a semiconductor integrated circuit device wherein the chip size, power consumption and operating speed are optimized, can easily be implemented by properly using substrate potential fixed and variable cells according to the functions or the like of circuit portions used with cells on one semiconductor chip and mixing them together in this condition.

Typical ones of various features of the present invention have been described in brief. However, the various embodiments of the present invention and specific configurations of these embodiments will be more fully set forth in the following description.

BRIEF DESCRIPTION OF THE DRAWINGS

While the specification concludes with claims particularly pointing out and distinctly claiming the subject matter which is regarded as the invention, it is believed that the invention, the objects and features of the invention and further objects, features and advantages thereof will be better understood from the following description taken in connection with the accompanying drawings in which:

FIG. 1 is a plan view showing one example of the layout pattern a common cell topology for a CMOS inverter to which the present invention is applied;

FIG. 2 is a cross-sectional view illustrating an example of a section taken along line II--II of FIG. 1;

FIG. 3(A) is a plan view of a layout pattern showing an object A;

FIG. 3(B) is a plan view of a layout pattern depicting an object B;

FIG. 3(C) is a plan view of an object CP;

FIG. 3(D) is a plan view of an object CN;

FIG. 3(E) is a plan view of an object DWL;

FIG. 3(F) is a plan view of an object DTH;

FIG. 3(G) is a plan view of an object E;

FIG. 3(H) is a plan view of an object F;

FIG. 3(I) is a plan view of an object G;

FIG. 3(J) is a plan view of an object H;

FIGS. 4(A) and 4(B) are,respectively,plan views showing layout patterns of a substrate potential fixed CMOS inverter and a substrate potential variable CMOS inverter each constructed using a common cell topology for a CMOS inverter;

FIG. 5(A) is a circuit diagram illustrating an example of a configuration of a substrate bias control circuit using substrate potential variable CMOS inverter cells;

FIG. 5(B) is a plan view showing a layout pattern of substrate potential variable logic cells;

FIG. 5(C) is a plan view illustrating a layout pattern of substrate potential fixed logic cells;

FIG. 6(A) is a circuit diagram depicting another example of a substrate bias control circuit using substrate potential variable CMOS inverter cells;

FIG. 6(B) is a plan view showing a layout pattern of a substrate potential fixed logic cell row;

FIG. 7(A) is a plan view of a layout pattern illustrating another example of a common cell topology for a CMOS inverter;

FIG. 7(B) is a plan view of a layout pattern depicting an object, B';

FIG. 8(A) is a plan view showing one example of a memory array to which the present invention is applied;

FIG. 8(B) is a plan view of a detail of FIG. 8(A);

FIG. 9 is a plan view illustrating a memory mat having memory cell power supply portions to which the present invention is applied;

FIG. 10(A) is a plan layout pattern view and FIGS. 10(B) and 10(C) are cross-sectional views showing an embodiment of a common cell topology for a memory cell power supply portion;

FIG. 11(A) through FIG. 11(D) are respective plan views illustrating the layout pattern of an example of each object configuration of a memory cell power supply portion;

FIG. 12(A) through FIG. 12(C) are respective plan views depicting the layout pattern of an embodiment of a cell topology of each memory cell;

FIG. 13 is a circuit diagram showing one embodiment of a memory cell;

FIG. 14 is a flowchart for describing a procedure for creating a library registered with cells;

FIG. 15 is a diagram showing a portion of an inverter cell part prepared in Step ST3 of the flowchart shown in FIG. 14;

FIG. 16 is a block diagram showing an example of an ASIC configuration used as one example of a semiconductor integrated circuit device constructed using a common cell topology according to the present invention;

FIG. 17 is a block diagram illustrating another embodiment of an LSI which can be designed using a common cell topology according to the present invention;

FIG. 18(A) to FIG. 18(C) are conceptual diagrams showing modifications of an LSI to which the present invention is applied.

FIG. 19(A) is a cross-sectional view showing a structure of an LSI having a well-separate configuration, which is used as another embodiment of the present invention, and FIGS. 19(B) and 19(C) are respective plan views showing an example of each object configuration;

FIG. 20(A) is a circuit diagram illustrating an equivalent circuit of a substrate potential fixed CMOS inverter;

FIG. 20(B) is a cross-sectional view depicting a structure of the circuit shown in FIG. 20(A);

FIG. 21(A) is a circuit diagram illustrating an equivalent circuit of a substrate potential variable CMOS inverter; and

FIG. 21(B) is a cross-sectional view showing a structure of the circuit shown in FIG. 21(A).

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the present invention will hereinafter be described with reference to the accompanying drawings.

A description will first be made of how to view common cell topology, using a CMOS (Complementary MOS) inverter cell INV as an illustrative example.

FIGS. 1 and 2 respectively show one example of a common cell topology for a CMOS inverter cell INV comprised of a pair of elements including a p channel MISFET (Metal Insulator Semiconductor FET) Qp and an n channel MISFET Qn. Of these, FIG. 1 illustrates an example of a layout pattern of a circuit cell and FIG. 2 shows an example of a sectional view taken along line II--II of FIG. 1.

In FIGS. 1 and 2, reference numeral 100 indicates a p-type single-crystal silicon substrate used as a base, for example Reference numeral 100i indicates a device or element separator, and reference numerals 101 and 102 indicate an n well region (101a, 101b) and a p well region (102a, 102b) defined as relatively low-density n-type and p-type semiconductor regions provided side by side in contact with each other, respectively Reference numerals 103 and 104 respectively indicate a Vcc line and a Vss line used as power wired layers, which are respectively provided along the upper and lower sides of the n well region 101 and p well region 102. Reference numerals 105 and 106 respectively indicate a VBP line and a VBN line used as substrate potential supply wired layers located on the further outer sides of the Vcc line 103 and Vss line 104 and arranged in parallel to these wired layers These power supply lines (103 through 106) are made up of a metal (aluminum) layer corresponding to a first layer, for example Further, the power supply lines (103 through 106) are constructed so as to extend in a cell row direction.

Reference numeral 107 indicates an active region in which the p channel MISFET Qp is formed. Reference numeral 108 indicates an active region in which the n channel MISFET Qn is formed. The active regions 107 and 108 are defined by the device separator 100i. Reference numerals 107a and 107b respectively indicate relatively low-density p-type semiconductor regions and relatively high-density p+type semiconductor regions provided in the n well region 101 and the active region 107. They serve as a source-to-drain region of the p channel MISFET Qp. Reference numerals 108a and 108b respectively indicate relatively low-density n-type semiconductor regions and relatively high-density n+type semiconductor regions provided in the p well region 102 and the active region 108. They serve as a source-to-drain region of the n channel MISFET Qn. Reference numeral 109 indicates a gate electrode comprised of a polysilicon film or the like, which is provided so as to extend in the direction normal to the power supply lines 103 and 104 across the p well region 101 and the n well region 102 The gate electrode 109 is formed integrally with a gate electrode 109p of the p channel MISFET Qp and a gate electrode 109n of the n channel MISFET Qn.

The gate electrodes 109n and 109p are respectively formed on the well regions 101 and 102 with gate insulating films 109i interposed therebetween. Further, a channel forming region of the p channel MISFET Qp is formed integrally with the n well region 101, whereas a channel forming region of the n channel MISFET Qn is formed integrally with the p well region 102.

Further, reference numeral 110 indicates a common drain electrode comprised of, for example; the metal (aluminum) layer or the like corresponding to the first layer, which is disposed in the direction orthogonal to the power supply lines 103 and 104 across the n well region 101 and the p well region 102. The common drain electrode 110 is designed so as to be electrically connected via contact holes CH1 and CH2 to the p-type semiconductor regions 107a and 107b and n-type semiconductor regions 108a and 108b respectively used as the source-to-drain regions at both ends.

Incidentally, symbols CH3 indicate contact holes for electrically connecting the Vcc line 103 to the n well region 101, symbols CH4 indicate contact holes for electrically connecting the Vss line 104 to the well region 102, symbols CH5 indicate contact holes for respectively electrically connecting the VBP line 105 to the n well region 101, symbols CH6 indicate contact holes for respectively electrically connecting the VBN line 106 to the p well region 102, symbol CH7 indicates a contact hole for electrically connecting the Vcc line 103 to the p-type semiconductor regions 107a and 107b serving as the source-to-drain region of the p channel MISFET Qp, and symbol CH8 indicates a contact hole for electrically connecting the Vss line 104 to the n-type semiconductor regions 108a and 108b serving as the source-to-drain region of the n channel MISFET Qn. Further, contact regions 111 through 114 comprised of high-density semiconductor regions for reducing contact resistance are respectively provided at substrate surface positions corresponding to the contact holes CH3 through CH6 of these contact holes, for supplying potentials to the well regions.

Incidentally, the contact regions 111 and 113 indicate n+type semiconductor regions, which are formed in the same process as that for the semiconductor region 108b, for example. The contact regions 111 through 114 and the active regions 107 and 108 are defined by the device separator 100i. The device separator 100i is formed by a structure in which an insulating film is embedded in a groove defined in the base 100.

Referring to FIGS. 1 and 2, symbol TH1 indicates a through hole used as an input terminal for electrically connecting the gate electrode 109 to a metal layer (upper wire or interconnection) 110' used as a first layer, which is located above the gate electrode 109 and is made up of an aluminum layer or the like Symbol TH2 indicates a through hole used as an output terminal for electrically connecting the drain electrode 110 to a metal layer (upper interconnection) 110" used as a first layer, which is located above the drain electrode 110 and is comprised of an aluminum layer or the like. CH1 through CH9 and TH1 are formed at the same height.

In FIG. 2, conductive layers 120 formed over the surfaces of the source-to-drain regions 107a and 107b and 108a and 108b and the contact regions 111 through 114 are formed of a metal silicide layer (CoSi, TiSi or the like) for providing low resistance as well as on the surface of the polysilicon gate electrode 109. The conductive layers 120 and the power supply lines 103 through 106 are respectively spaced away from one another by an interlayer insulating film 121 and are respectively electrically connected to one another by connecting bodies 122 comprised of a conductive material such as tungsten or the like charged into the contact holes CH1, CH2, CH3, CH4 and CH5 through CH8 defined in the interlayer insulating film 121.

In the present embodiment, design data constituting the CMOS inverter INV is divided into the following objects A, B, CP, CN, DWL, DTH, E, F, G and H. That is, the VBP line 105 and VBN line 106, the contact holes CH5, CH6, contact regions 113 and 114 for respectively connecting these to the n well region 101 and p well region 102, and the n well 101a and p well 102a corresponding to parts of the well regions 101 and 102 just below or under the VBP line 105 and VBN line 106, respectively, constitute design data. These design data are prepared as one united object A (see FIG. 3(A). Similarly, the contact holes CH3 and CH4 and contact regions 111 and 112 for electrically connecting the Vcc line 103 and the Vss line 104 to the n well region 101 and p well region 102, and protrusions 103a and 104a used for providing contact with the Vcc line 103 and the Vss line 104, respectively, constitute design data. These design data are prepared as one united object B (see FIG. 3(B).

The active region 107, p-type semiconductor regions 107a and 107b and gate electrode 109p constitute design data as the p channel MISFET Qp which constitutes the inverter cell. These design data are prepared as one united object CP (see FIG. 3(C). The active region 108, n-type semiconductor regions 108a and 108b and gate electrode 109n makeup design data as then channel MISFET Qn which constitutes the inverter cell These design data are prepared as one unified object CN (see FIG. 3(D).

As shown in FIGS. 3(C) through 3(J), other objects are also similarly configured as a unit of design data. That is, there are known, as other objects, an output contact structure (object DTH) comprising the drain electrode 110 (object DW) of the metal layer used as the first layer, and the through hole TH2 for connecting the drain electrode 110 to a wired layer (signal line) defined as an upper layer; an input contact structure (object E) comprising the through hole TH1 for connecting each gate electrode to an upper wired layer (signal line), and a buffer conductive layer BFM; a contact structure (object F) comprising the contact holes CH1, CH2, CH7 and CH8 for connecting the conductive layers such as the power supply lines 103 and 104, the drain electrode 110, etc. to the diffusion layers 107a, 107b, 108a and 108b, and high-density contact regions 107' and 108'; and a well structure (object H) for providing a conductive layer pattern (object G) constituting the power supply lines 103 and 104, and the well regions 101b and 102b.

Since the contact regions 107' and 108' are respectively substantially formed in the same process as that for the p-type semiconductor regions 107a and 107b and the n-type semiconductor regions 108a and 108b and formed integrally therewith, the illustration of these in FIG. 2 is omitted for ease in understanding the drawing. Incidentally, chain lines and two-dot chain lines in the objects, A, B, F and G shown in FIG. 3(A), FIG. 3(B), FIG. 3(H) and FIG. 3(I), respectively, indicate border lines indicative of the outside shapes of cells and do not indicate the components that constitute the respective objects.

The design data for the objects A through H are developed as hierarchical data called "plural layers" corresponding to a mask used in a production process For example, the removal of the object A means that information about the layer constituting the object A is removed. A mask used in the production process is created by synthesizing or combining together the same data (hierarchical data) divided into or distributed to the objects A through H. For example, the gate electrode 109p of the object CP and the gate electrode 109n of the object CN are placed under the same layer (hierarchical data). A mask pattern for forming the polysilicon gate electrode 109 is formed by combining these hierarchical data together.

Further, the wiring 110 of the object DWL, the Vcc line 103 and Vss line 104 of the object G, and the VBP line 105 and VBN line 106 of the object A are the same hierarchical data. A mask pattern for forming the metal layer corresponding to the first layer is created by combining these hierarchical data together. Thus, the design data for forming the same mask pattern constitutes the same hierarchical data. In regard to the inverter cell illustrated in the present embodiment, the same layer may be associated with components or elements of different objects other than the objects A and B.

When data obtained by eliminating the design data for the object A from the cell design data for forming the CMOS inverter cell shown in FIG. 1 are used (i.e., when the design data for the objects B through H are used), a substrate potential fixed CMOS inverter INV having a circuit configuration shown in FIG. 20(A) is constructed as shown in FIG. 4(A) wherein a Vcc line 103 and a Vss line 104 are electrically connected to the n well region 101 and the p well region 102 respectively. On the other hand, when data obtained by removing the design data for the object B from the design data for forming the CMOS inverter shown in FIG. 1 are used (i.e., when the design data for the objects A, CN and CP through H are used), a substrate potential variable CMOS inverter INV having a circuit configuration shown in FIG. 21(A) is constructed as shown FIG. 4(B) wherein a VBP line 105 and a VBN line 106 are electrically connected to the n well region 101 and the p well region 102 respectively.

That is, a library for a substrate potential fixed cell or a library for a substrate potential variable cell can be formed by preparing the design data having the objects A through H as a common cell layout and eliminating the object A or B from the common cell layout. Thus, the term common cell topology refers ti a method for forming two cell libraries using one common cell pattern and an approach therefor or the like.

That is, one common cell pattern is considered as an aggregate of objects. The two cell libraries can be formed from the common cell pattern by adding predetermined objects thereto.

Even in the case of NOR gate circuits, NAND gate circuits, switch circuits SW1 and SW2, RAM, etc. Silica to the inverter cell, a common layout for logic circuit cells respectively comprising the NOR gate circuits, NAND gate circuits, switch circuits SW1 and SW2, RAM, etc. can be configured by suitably forming the objects CP, CN, DW, DTW, E, F and H.

Each cell library can be formed from the common cell pattern as a substrate potential common cell library in a manner similar to the CMOS inverter cell INV.

Further, the common layout pattern for each logic circuit cell includes objects A and C each having cell heights Ha and Hb similar to those employed in the common layout pattern for the aforementioned CMOS inverter cell INV Thus, when the logic circuit cells CELL using the substrate potential variable cell library are arranged in a cell row direction as shown in FIGS. 5(A), 5(B) and 5(C), their corresponding power supply lines (103 through 106) are respectively integrally formed and configured so as to extend in a cell direction.

That is, the substrate potential common library and the substrate potential variable cell library are created from the common layout pattern for the logic circuit cells. A desired logic circuit can be configured by opening one library thereof and placing and connecting the logic circuit cells CELL. In this case, the logic circuit cells CELL are arranged so as to adjoin each other in the cell row direction. The power supply lines (103 through 106) are integrally formed in the cell direction as shown in FIGS. 5(A), 5(B) and 5(C) Similarly, when the logic circuit cells CELL are disposed using the substrate potential fixed cell library in a cell row direction, they are placed adjacent to each other in the cell row direction and the power supply lines (103 and 104) are integrally formed in the cell direction as illustrated in FIGS. 5(C) and 5(B).

When the substrate potential variable CMIS inverter cells CELL or the like are selected, a substrate bias control circuit BVC for supplying bias voltages Vbp and Vbn generated from a bias voltage generator BVC shown in FIG. 5(A) or power sources Vcc and Vss to each inverter cell INV are provided at a given position of a semiconductor chip and are controlled according to control signals stb1 and stb2 so as to apply bias voltages Vbp (=1.8V) and Vbn (=0V) so as to set a reverse bias voltage developed between the source of MISFET and the substrate smaller than base potentials Vbp (=3.3V) and Vbn (=-1.5V) at standby to each of the individual well regions through a VBP line 105 and a VBN line 106 upon an active state in place of the base potentials Vbp and Vbn as shown in Table 1, for example. As shown in FIG. 6(A), basic circuit cells CELL are connected to one another in their cell directions by using wires or interconnections of a metal layer defined as a first layer and a metal layer defined as a second layer so as to constitute a desired logic circuit.

In the aforementioned embodiment, the objects A and B may be prepared as an aggregate of much smaller objects. Similar to the inverter cells referred to above, cells comprised of basic logic circuits such as NAND gate circuits, NOR gate circuits, etc. are designed so as to be capable of constituting either a substrate potential fixed circuit or a substrate potential variable circuit and may be registered in a library Alternatively, cells capable of constituting both the substrate potential fixed circuit and the substrate potential variable circuit may be designed in a memory such as a RAM or the like so as to be registered in a library. Further, design information about the bias voltage generator BVG and substrate bias control circuit BVC may be registered in cell libraries as single circuit cells, respectively. In place of the mounting of the bias voltage generator BVG on the semiconductor chip, the bias voltages Vbp and Vbn may be supplied from the outside

As is apparent from a comparison between FIG. 4(A) and FIG. 4(B) or a comparison between FIG. 5(B) and FIG. 5(C), the substrate potential fixed CMOS inverter cell shown in 4(A) is reduced in cell area by the VBP line 105 and the VBN line 106 as compared with the substrate potential variable CMOS inverter cell shown in FIG. 4(B) Thus, when it is desired to form a circuit that needs a high-speed operation, the substrate potential fixed CMOS inverter cell is selected, whereby a reduction in chip size preferentially can be achieved.

That is, when the substrate potential fixed cells CELL each shown in FIG. 4(A) are utilized in combination to form logic as shown in FIG. 5(C), regions for the VBP line 105 and the VBN line 106 can be used as wiring regions because the cell height Ha shown in FIG. 4(A) is smaller than that shown in FIG. 4(B). It is therefore possible to reduce the chip size and provide high integration and high functioning. That is, since intervals defined between cell rows, which extend in the direction normal to a cell row direction can be reduced in FIGS. 5(C) and 6(B), a reduction in chip size and high integration can be achieved. The interval between the adjacent power supply lines (103 and 104) employed in the cells CELL is the same as that for the substrate potential fixed cell and the substrate potential variable cell.

The configuration and operation of the substrate bias control circuit BVC will next be described using FIG. 5(A) and Table 1.

The substrate bias control circuit BVC employed in the present embodiment comprises a first switch circuit SW1 comprised of a p channel MISFET Qp1 which is provided between the VBP line 105 employed in the embodiment shown in FIG. 1 as a substrate potential supply line and the bias voltage generator BVG and which is controlled by a control signal /stb1, and an n channel MISFET Qn1 provided between the VBN line 106 used as a substrate potential supply line and the bias voltage generator BVG and controlled by a control signal stb2, and a second switch circuit SW2 comprised of a p channel MISFET Qp2 provided between the Vcc line 103 and the VBP line 105 and controlled by a control signal stb1, and an n channel MISFET Qn2 provided between the Vss line 104 and the VBN line 106 and controlled by a control signal /stb2.

The second switch circuit SW2 is provided one by one per a predetermined number of basic circuit cells (inverter cells or NOR or NAND logic circuits (gates)), that is, a plurality of the second switch circuits SW2 are provided for each cell row CR. The first switch circuit SW1 is provided as a circuit common to the plurality of second switch circuits SW2 Thus, the MISFETs Qp1 and Qn1 constituting the first switch circuit SW1 are designed so as to be greater than the MISFETs Qp2 and Qn2 constituting the second switch circuit SW2 in device size. It is desirable for the pitch of placement of each second switch circuit SW2 to be reduced according to the operating frequency of an LSI and wiring resistances of the power supply Vcc and Vss lines 103 and 104 as the operating frequency increases and a voltage drop becomes great, thereby increasing the number of the second switch circuits SW2 provided within one cell row CR. It is thus possible to reduce a variation in substrate potential incident to a circuit operation and prevent the circuit from operating due to noise.

Thus, a desired logic circuit is configured by placing the basic circuit cells CELL and providing a connection between the basic circuit cells CELL using the wires or interconnections of the metal layers 110' and 110" corresponding to the first and second layers. Incidentally, the logic circuit may be configured by placing a plurality of cell rows CR as shown in FIG. 6(A). In this case, the first switch circuit SW1 may be provided every cell rows CR. Alternatively, one cell row CR may be provided for the logic circuit as shown in FIG. 6(A). As shown in FIGS. 6(A) and 6(B), the intervals defined between the adjacent cell rows CR are used as wiring regions and connections between the cell rows or within each cell are made by using the interconnections of the metal layers 110' and 110" corresponding to the first and second layers.

Further, the substrate bias control circuit BVC sets the control signals stb1, /stb1, stb2 and /stb2 to Vss (=0V), Vbp (=3.3V), Vbn (=-1.5V) and Vcc (=1.8V) respectively. Thus, the MISFETs Qp1 and Qn1 of the switch SW1 are turned off and the MISFETs Qp2 and Qn2 of the switch circuit SW2 are turned on so that the source voltages Vcc and Vss are respectively supplied to the VBP and VBN lines 105 and 106 connected to their corresponding inverter cells INV. Thus, each MISFET of the inverter cell INV undergoes or receives a low reverse bias voltage between the source thereof and the substrate to reduce its threshold, whereby it operates at high speed.

TABLE 1 Active Standby Power Vcc Voltage 1.8 V Source Vss Voltage 0.0 V Vbp Voltage -- 3.3 V Vbn Voltage -- -1.5 V Control stb1 L(0.0) H(3.3) Signal stb1 H(3.3) L(0.0) stb2 L(-1.5) H(1.8) stb2 H(1.8) L(-1.5) Controlled Power VBP line Vcc(1.8) Vbp(3.3) VBN line Vss(0.0) Vbn(-1.5)

On the other hand, the control signal stb1 is set to Vbp (=3.3V), the control signal /stb1 is set to Vss (=0V), the control signal stb2 is set to Vcc (=1.8V) and the control signal /stb2 is set to Vbn (=-1.5V), respectively upon non-operation of the circuit (at standby) as shown in Table 1. Thus, the MISFETs Qp1 and Qn1 of the switch circuit SW1 are turned on and the MISFETs Qp2 and Qn2 of the switch circuit SW2 are turned off so that the VBP line 105 and the VBN line 106 electrically connected to each inverter cell INV are supplied with bias voltages Vbp and Vbn generated from the bias voltage generator BVG. As a result, a high reverse bias voltage is applied between the source of each MISFET of the inverter cell INV and the substrate to thereby increase the threshold of each MISFET, whereby leakage current is reduced. Incidentally, Table 1 shows examples of bias voltages at the time that the source voltage Vcc supplied from the outside is 1.8V. If the source voltage Vcc varies, then the bias voltages Vbp (Vbp>Vcc) and Vbn (Vbn<Vss) suitably vary according to such variation.

Since the Vbn potential and the Vbp potential are potentials to be supplied to the well regions 101 and 102 respectively, less current variation is provided and the wiring widths of the VBP line 105 and VBN line 106 are formed so as to be thinner than those of the Vcc line 103 and Vss line 104 as shown in FIGS. 4(A) and 4(B). Thus, the provision of the VBP line 105 and VBN line 106 allows a reduction in the increase in each cell CELL size.

The aforementioned embodiment has been described for the case in which the design data constituting the VBP line 105 and VBN line 106, and the contact holes CH5, CH6 and contact regions 113 and 114 for respectively connecting these to the n well region 101 and p well region 102, and the parts of the well regions 101 and 102 just below or under the VBP line 105 and VBN line 106 are prepared as one unified object A, and the design data constituting the contact holes CH3 and CH4 and contact regions 111 and 112 for electrically connecting the Vcc line 103 and the Vss line 104 to the n well region 101 and p well region 102, and the protrusions 103a and 104a used for providing contact with the Vcc line 103 and the Vss line 104 are prepared as one united object B. However, the two objects A and B are set as one object A' and design information about such patterns FP1 and FP2 as to fill intervals between a VCC line 103 and a Vss line 104 and between a VBP line 105 and a VBN line 106 with the same conductive layer (corresponding to a metal (aluminum) layer corresponding to a first layer) is prepared as another object B' (see FIG. 7(B)) as indicated by hatching in FIG. 7(A) aside from the object A'. In this condition, either a substrate potential fixed cell or a substrate potential variable cell may be formed according to whether the object B' for the interval filling should be included in the object A'.

Further, either the substrate potential fixed cell or the substrate potential variable cell may be formed depending on whether in a state in which the objects A' and B' are prepared as one object A", the object B' is eliminated from the object A" or left as it is.

However, since any cell takes the same shape (outside shape) in such a case, the effect of reducing each cell area is not obtained even when the substrate potential fixed cell is selected. As an alternative to this, however, another effect can be obtained in that each logic circuit is improved in reliability and performance to stabilize a well potential due to a reduction in resistance incident to an increase in the width of each power supply line, the stabilization of the source potentials and an increase in the number of contacts.

Further, the aforementioned embodiment has described the case where the information about the contact holes CH3 through CH6 for connecting the Vcc line 103 and Vss line 104 and the VBP line 105 and VBN line 106 to their corresponding well regions 101 and 102 are contained in the same object as that for the information about their corresponding power supply lines. However, the information about the contact holes is omitted from the object including the information about the power supply lines, and substrate contact holes may be defined or produced in blank areas lying under the respective power supply lines by an automatic layout editor/program. That is, the objects constructive of the common layout pattern for the logic circuit cells are not necessarily limited to the above. It is needless to say that changes can be made thereto within a scope not changing the substance of the present invention.

A description will next be directed to a common cell topology at the time that a substrate potential applied to each of the memory cells constituting a RAM incorporated in an LSI is fixed or varied. In the present embodiment, the memory cells are the same and power supply portions,relative to well regions in which p channel MISFETs and n channel MISFETs constituting the memory cells are respectively formed, are formed by a common cell topology.

FIG. 8(A) shows the configuration of the entire memory array. In the memory array illustrated in accordance with the present embodiment, memory mats MATs respectively having 32.times.n memory cells MC placed in matrix form are arranged on both sides of an X decoder circuit X-DEC with the X decoder circuit interposed therebetween. Word drivers W-DRV for respectively driving word lines to select levels are disposed adjacent to the X decoder circuit X-DEC on both sides thereof. As indicated by the diagonally-shaded areas, word shunt areas W-SNT for coupling two-layered word lines at suitable pitches to thereby prevent level-down are formed between the memory mats extending in a word line direction (i.e., in a transverse direction in FIG. 8(A)). Precharge circuits PC and a column switch row YSW are disposed at one end of the memory mats. Further, sense amplifiers S-AMP and write amplifiers W-AMP for respectively amplifying signals on data lines are placed adjacent to the precharge circuits PC and the column switch row YSW.

FIG. 9 shows one memory mat MAT placed in a state in which word lines are omitted therefrom. As shown in FIG. 9, n well regions n-WELL and p well regions p-WELL are alternately arranged within the memory mat along a data line direction (i.e., in the longitudinal or vertical direction as seen in FIG. 9). In the present embodiment, power supply lines VDL and VSL and lines VBP and VBN for respectively supplying substrate potentials Vbp and Vbn are dispo