Method of forming insulating film and method of fabricating semiconductor device Number:6,800,512 from the United States Patent and Trademark Office (PTO) owispatent With keeping an atmosphere including oxygen within a chamber and with a wafer kept at a low temperature, plasma generated within the chamber is biased toward the wafer, and the wafer is subjected to the plasma. A semiconductor layer exposed on the wafer is oxidized into an oxide film. Thus, an oxide film can be formed even at room temperature differently from thermal oxidation. This oxidation is applicable to recovery of an implantation protection insulating film having been etched in cleaning a photoresist film, relaxation of a step formed between polysilicon films, relaxation of a step formed within trench and the like. Also, before removing a photoresist film used for forming a gate electrode including a metal, a contamination protection film can be formed by this oxidation with the photoresist film kept.<H semiconductor, fabricating, Method, of, formi, 6800512.html, Patent, pto, 6800512

Title: Method of forming insulating film and method of fabricating semiconductor device

Abstract: With keeping an atmosphere including oxygen within a chamber and with a wafer kept at a low temperature, plasma generated within the chamber is biased toward the wafer, and the wafer is subjected to the plasma. A semiconductor layer exposed on the wafer is oxidized into an oxide film. Thus, an oxide film can be formed even at room temperature differently from thermal oxidation. This oxidation is applicable to recovery of an implantation protection insulating film having been etched in cleaning a photoresist film, relaxation of a step formed between polysilicon films, relaxation of a step formed within trench and the like. Also, before removing a photoresist film used for forming a gate electrode including a metal, a contamination protection film can be formed by this oxidation with the photoresist film kept.

Patent Number: 6,800,512 Issued on 10/05/2004 to Itonaga, et al.

Inventors: Itonaga; Kazuichiro (Osaka, JP), Yamamoto; Akihiro (Kyoto, JP), Nakaoka; Hiroaki (Kyoto, JP), Miyanaga; Isao (Nara, JP), Harada; Yoshinao (Osaka, JP)
Assignee: Matsushita Electric Industrial Co., Ltd. (Osaka, JP)

Appl. No.: 09/662,004

Filed: September 14, 2000

Foreign Application Priority Data


Sep 16, 1999 [JP]			11-261876

Current U.S. Class: 438/154 ; 257/E21.258; 257/E21.285; 257/E21.301; 257/E21.546; 257/E21.637; 257/E21.639; 438/771; 438/788; 438/791

Field of Search: 438/154,788,791,771

References Cited [Referenced By]

U.S. Patent Documents


4442591	April 1984	Haken
4915777	April 1990	Jucha et al.
5366586	November 1994	Samukawa
5674783	October 1997	Jang et al.
5943565	August 1999	Ju
2001/0048980	December 2001	Kishimoto et al.

Foreign Patent Documents


661732	May., 1995	EP
63-90138	Apr., 1988	JP
5-19296	Jan., 1993	JP
7-115204	May., 1995	JP
7-131023	May., 1995	JP
11-121448	Apr., 1999	JP

Other References

Notice of Reasons of Rejection (Dated Apr. 1, 2003)..

Primary Examiner: Coleman; W. David
Assistant Examiner: Brewster; William M.
Attorney, Agent or Firm: Nixon Peabody LLP Studebaker; Donald R.

Claims

What is claimed is:

1. A method of forming an insulating film on a semiconductor layer, comprising the steps of: (a) loading a substrate including said semiconductor layer on a lower electrode in a processing chamber; and (b) generating, within the processing chamber, plasma biased toward said substrate by introducing only oxygen into the prosing chamber and with the substrate heated to a temperature of up to 300.degree. C., thereafter subjecting said semiconductor layer to the biased plasma, wherein an exposed surface of the semiconductor layer on the substrate is oxidized by the biased plasma in the step (b).

2. The method of forming an insulating film of claim 1, wherein a thickness of said insulating film is controlled by adjusting a degree of biasing the plasma in the step (b).

3. The method of forming an insulating film of claim 1, wherein the step (b) is carried out at a temperature of up to 200.degree..

4. The method of forming an insulating film of claim 3, wherein the step (b) is carried out with a photo resist film formed on said substrate.

5. The method of forming an insulating film of claim 1, wherein said insulating film is a gate insulating film of a MIS transistor.

6. The method of forming an insulating film of claim 5, further comprising, before at least the step (b), a step of forming a first active region doped with an impurity of a first conductivity type and a second active region doped with an impurity of a second conductivity type, wherein a first insulating film and a second insulating film are respectively formed on said first active region and said second active region in the step (b).

7. The method of forming an insulating film of claim 1, further comprising, after the step (b), a step of conducting a heat treatment on said insulating film.

8. The method of forming an insulating film of claim 1, wherein the insulating film is a silicon oxide film.

9. The method of forming an insulating film of claim 1, wherein the chamber includes the lower electrode serving as an anode, a bias electrode serving as a cathode and opposing the lower electrode, and a high frequency power supply for applying high frequency power to the lower electrode through a capacitor, the substrate is placed on the lower electrode in the step (a), and the biased plasma is generated by applying the high frequency power to the lower electrode in the step (b).

Description

BACKGROUND OF THE INVENTION

The present invention relates to a method of forming an insulating film in which a highly reliable oxide film can be formed at a low temperature and a method of fabricating a semiconductor device by utilizing the method of forming an insulating film.

In accordance with recent demands for high integration of semiconductor integrated circuits, for example, a very shallow junction structure is employed in forming a transistor and an STI (shallow trench isolation) structure is employed in forming an isolation. Since the very shallow junction structure and the STI are thus employed, dislocation defects are caused in an active region due to stress collected on the edge of the STI during formation of a gate oxide film (by thermal oxidation). As a result, junction leakage can be increased, or variation in the threshold voltage can be increased owing to change of junction profile caused in the formation of the gate oxide film. Therefore, in order to overcome these problems, it is very significant to conduct the process for forming an oxide film at a low temperature.

Also, in accordance with the demands for high integration of semiconductor integrated circuits, the gate length of a MOSFET is reduced, which makes it difficult to suppress the short channel effect. Therefore, the short channel effect is suppressed by employing a gate electrode structure designated as a dual gate electrode obtained by implanting phosphorus ions into a polysilicon film for a gate electrode of an NMOSFET and implanting boron ions into a polysilicon film for a gate electrode of a PMOSFET.

FIGS. 21(a) through 21(d) and 22(a) through 22(d) are sectional views for showing procedures in fabrication of a conventional CMOS device having a trench isolation structure and a dual gate electrode structure.

First, in the procedure shown in FIG. 21(a), a trench isolation region 101 is formed in a Si substrate 100, and then, a photoresist film 103 covering an NMOSFET formation region Rn and having an opening on a PMOSFET formation region Rp is formed on a protection oxide film 102 by photolithography. Thereafter, phosphorus ions (P.sup.+) for forming an N-type well region 104, phosphorus ions (P.sup.+) for controlling a threshold voltage and arsenic ions (As.sup.+) for stopping punch-through are implanted into a region of the Si substrate 100 within the opening of the photoresist film 103 (namely, the PMOSFET formation region Rp).

Then, in the procedure shown in FIG. 21(b), the photoresist film 103 is removed by ashing and RCA cleaning.

Next, in the procedure shown in FIG. 21(c), a photoresist film 105 covering the PMOSFET formation region Rp and having an opening on the NMOSFET formation region Rz is formed on the protection oxide film 102 by the photolithography. Thereafter, boron ions (B.sup.+) for forming a P-type well region 106, boron ions (B.sup.+) for controlling a threshold voltage and boron ions (B.sup.+) for stopping punch-through are implanted into a region of the Si substrate 100 within the opening of the photoresist film 105(namely, the NMOSFET formation region Rn).

Then, in the procedure shown in FIG. 21(d), the photoresist film 105 is removed by the ashing and the RCA cleaning, and the protection oxide film 102 is also removed. Thereafter, the Si substrate 100 is heated at approximately 800 through 1000.degree. C. in an oxygen atmosphere, thereby forming gate oxide films 107a and 107b on the N-type well region 104 and the P-type well region 106, respectively.

Subsequently, in the procedure shown in FIG. 22(a), after depositing a polysilicon film 108 for a gate electrode on the substrate, a photoresist film 109 covering the NMOSFET formation region Rn and having an opening on the PMOSFET formation region Rp is formed on the polysilicon film 108. Thereafter, boron ions (B.sup.+) are implanted into a region of the polysilicon film within the opening of the photoresist film 109 (namely, the PMOSFET formation region Rp).

Similarly, in the procedure shown in FIG. 22(b), after removing the photoresist film 109 by the ashing and the RCA cleaning, a photoresist film 110 covering the PMOSFET formation region Rp and having an opening on the NMOSFET formation region Rn is formed on the polysilicon film 108 by the photolithography. Thereafter, phosphorus ions (P.sup.+) are implanted into a region of the polysilicon film 108 within the opening of the photoresist film 110 (namely, the NMOSFET formation region Rn).

Next, in the procedure shown in FIG. 22(c), the photoresist film 110 is removed by the ashing and the RCA cleaning, and then, a heat treatment is carried out for activating the impurities implanted into the polysilicon film 108. In this manner, a P-type polysilicon film 108p is formed in the PMOSFET formation region Rp and an N-type polysilicon film 108n is formed in the NMOSFET formation region Rn.

Then, the P-type polysilicon film 108p and the N-type polysilicon film 108n are respectively patterned into a gate electrode 108a of the PMOSFET and a gate electrode 108b of the NMOSFET.

Furthermore, in order to cope with reduction in a chip area and high operation speed of a device, the resistance of the gate electrode of a MOSFET has recently been lowered. As one of promising means for lowering the resistance, the so-called polymetal gate structure or polycide gate structure in which part of the gate electrode is formed from a metal (refractory metal or its silicide) is known.

FIGS. 23(a) through 23(d) are sectional views for showing procedures in fabrication of a conventional CMOS device having the polymetal structure.

First, through the same procedures as those shown in FIGS. 21(a) through 21(d), a trench isolation region 101 for isolating a PMOSFET formation region Rp and an NMOSFET formation region Rn from each other, an N-type well region 104, a P-type well region 106 and gate oxide films 107a and 107b are formed in a Si substrate 100. Thereafter, as is shown in FIG. 23(a), a polysilicon film 120, a metal film 121 of titanium silicide or the like and an insulating film 122 of a silicon nitride film or the like are successively deposited on the substrate.

Next, in the procedure shown in FIG. 23(b), a photoresist film 115 covering a gate electrode formation region is formed by the photolithography, and then, dry etching (anisotropic etching) is carried out by using the photoresist film as a mask, thereby patterning the insulating film 122, the metal film 121 and the polysilicon film 120. In this manner, a gate electrode 125a including a bottom gate electrode 120a and a top gate electrode 121a, and an over-gate protection film 122aare formed in the PMOSFET formation region Rp. Also, a gate electrode 125b including a bottom gate electrode 120b and a top gate electrode 121b, and an over-gate protection film 122b are formed in the NMOSFET formation region Rn.

Then, in the procedure shown in FIG. 23(c), a photoresist film 116 covering the NMOSFET formation region Rn and having an opening on the PMOSFET formation region Rp is formed on the substrate. Thereafter, boron ions (B.sup.-) are implanted into the Si substrate 100 by using the photoresist film 116 and the gate electrode 125a as masks, thereby forming source/drain regions 126 of the PMOSFET.

Next, in the procedure shown in FIG. 23(d), the photoresist film 116 is removed by the ashing and the RCA cleaning, and then, a photoresist film (not shown) covering the PMOSFET formation region Rp and having an opening on the NMOSFET formation region Rn is formed on the substrate. Thereafter, arsenic ions (As.sup.+) are implanted into the Si substrate 100 by using the photoresist film and the gate electrode 125b as masks, thereby forming, source/drain regions 127 of the NMOSFET. Then, the photoresist film is removed by the ashing and the RCA cleaning.

The conventional semiconductor devices fabricated as described above have, however, the following problems:

First, as is shown in FIG. 22(d), the gate oxide film 107a of the PMOSFET and the gate oxide film 107b of the NMOSFET have different thicknesses. This is because, in the thermal oxidation for forming the gate oxide films in the procedure of FIG. 21(d), the oxidizing rate is higher in the portion of the protection oxide film 102 corresponding to the NMOSFET formation region Rn where the boron ions are implanted than in the portion thereof corresponding to the PMOSFET formation region Rp where the phosphorus (or arsenic) ions are implanted. Also, since the impurity concentration profile in the P-type well region 106 for controlling the threshold voltage of the NMOSFET and the impurity concentration profile in the N-type well region 104 for controlling the threshold voltage of the PMOSFET are changed in the heat treatment conducted at 850 through 1000.degree. C. the short channel effect of the MOSFETs are accelerated, variation in the threshold voltage of the NMOSFET and the PMOSFET Is increased, and an off leakage current is increased.

Secondly, the boron implanted into the P-type polysilicon film 108p of the polysilicon film 108 for the gate electrode is diffused into the N-type well region 104 through the gate oxide film 107a due to the heat treatment conducted at 900 through 1000.degree. C. for the thermal oxidation. As a result, the reliability of the gate oxide film is degraded, and variation in the threshold voltage of the PMOSFET is increased.

Thirdly, as is shown in FIG. 21(b), when the photoresist film 103 is removed by the ashing and the RCA cleaning after the ion implantation, the surface of the protection oxide film 102 becomes very rough. This is probably because the protection oxide film 102 is damaged by the ions during the ion implantation and is ununiformly etched by the RCA cleaning. When the ion implantation for forming the well region, namely, for controlling the threshold voltage, is carried out with the protection oxide film 102 having a very rough surface, the impurity concentration in a portion corresponding to a channel region within the well region is largely varied among MOSFETs. In this manner, variation in the threshold voltage among the MOSFETs is increased. Furthermore, the Si substrate 100 is also etched by the RCA cleaning. For example, when the RCA cleaning is carried out with the ion-implanted Si substrate exposed, a portion of the Si substrate 100 where the impurity ions have been implanted for controlling threshold voltage may also be etched by a thickness of several nm. As a result, the concentration profile of the implanted impurity is changed, so that the threshold voltage is largely varied in, particularly, a MOSFET having a buried transistor structure.

Fourthly, as is shown in FIG. 22(d), in patterning the polysilicon film 108 into the gate electrodes 108a and 108b, the surface of the active region of the Si substrate 100 can be roughened. Even when the etching end point of the polysilicon film is detected, the polysilicon film is not completely removed but partly remains as etching residues or sidewalls. Therefore, in order to remove the remaining portions of the polysilicon film, the polysilicon film is over-etched. Due to recent decrease in the thickness of a gate oxide film (to several nm), however, merely a portion of the gate oxide film not covered with the polysilicon film can be etched before completely removing the polysilicon film through the over-etching. Accordingly, when the Si substrate 100 below is partly etched. the surface of the active region is roughened. As a result, a good silicide layer cannot be formed in a salicidation process. Furthermore, the profile of the implanted ions for forming the source/drain regions cannot be uniform, resulting in increasing junction leakage.

Fifthly, as is shown in FIG. 23(d), in removing the photoresist film 116 by the ashing and the RCA cleaning after patterning the metal film 121, the top electrodes 121a and 121b, which are made from a metal in the gate electrodes 125a and 125b of the MOSFETS, are etched on their side faces. When metal ions dissolved in the etching solution (cleaning solution) enter the active region through the surface of the Si substrate 100, junction leakage is caused in the MOSFET. On the other hand, when a thermal oxide film for covering the substrate surface is formed to prevent this contamination, the top electrodes 121a and 121b formed from the metal are peeled.

Sixthly, as is shown in FIG. 22(b), in removing the photoresist films 109 and 110 by the ashing and the RCA cleaning or in conducting cleaning before loading the substrate in a furnace, the polysilicon film 108 is etched to some extent. Since the P-type polysilicon film 108p where the boron ions are implanted and the N-type polysilicon film 108n where the phosphorus (or arsenic) ions are implanted have different etch rates, there may be a step on the boundary between the P-type polysilicon film 108p and the N-type polysilicon film 108n. When this step is abrupt, although no problem can be observed in the sectional view shown in FIG. 22(d). the following problem may occur in a CMOS inverter having a silicide gate structure:

FIGS. 24(a) through 24(c) are sectional views in a silicidation process for showing the gate electrodes 108a and 108b alone taken on line perpendicular to the section of FIG. 22(d) (namely, line XXIV-XXIV of FIG. 25). Furthermore, FIG. 25 is a plan view of the gate electrodes and a portion below the gate electrodes of the CMOS inverter. In this manner, in the CMOS inverter, the gate electrodes of the PMOSFET and the NMOSFET are mutually connected in the section perpendicular to the section of FIG. 22(d).

In the case where the abrupt step as shown in FIG. 24(a) is present, even when, for example, a Co film is deposited on the gate electrodes 108a and 108b for forming a silicide film on the gate electrodes 108a and 108b in a later procedure, the Co film cannot be sufficiently deposited on the side face of the step.

As a result, as is shown in FIG. 24(c), merely a very thin silicide film of CoSi.sub.2 or the like is formed or no silicide film is formed on the step through the silicidation. Accordingly, even when a voltage is applied to the gate electrode 108b of the NMOSFET in the CMOS inverter, the resistance between the gate electrodes can be too large to transfer the electric field to the gate electrode 108a of the PMOSFET.

Seventhly, the following problem occurs in forming the STI structure (trench isolation region). FIG. 26 is a sectional view for showing the shape of a conventional trench isolation region. As is shown in FIG. 26, a pad oxide film 131 and a masking nitride film 132 are stacked on a Si substrate 100, and a portion of the Si substrate 100 below an opening of the masking nitride film 132 is etched so as to form a trench 134. Then, a thermal oxide film 135 is formed by thermally oxidizing a portion of the Si substrate 100 within the trench, and the trench is filled with a CVD oxide film, so as to form a trench isolation region 136.

The thickness of the thermal oxide film 135 is, however, varied at respective edges within the trench depending upon the thickness of the masking nitride film 132, the thickness of the pad oxide film 131 or the plane size of the masking nitride film 132. In particular, when a hone phenomenon in which the thermal oxide film 135 has a small thickness at an edge is caused, an abrupt edge is formed at the corresponding corner of the Si substrate 100 within the trench 134. As a result, the electric filed is collected on the edge so as to cause problems such as breakdown of a gate insulating film and a hump characteristic (actuation of an edge transistor). The hone characteristic is conspicuous particularly when the thermal oxide film 135 is formed at a low temperature of 900.degree. C. or less. Therefore, the temperature of the thermal oxidation can be set to 1000.degree. C. for avoiding the hone phenomenon, but as the temperature of the thermal oxidation increases, larger stress is caused in the nitride film 132, resulting in increasing defects occurring in the Si substrate 100.

SUMMARY OF THE INVENTION

An object of the invention is, in considering that the aforementioned problems are basically derived from a high temperature required for forming an oxide film through thermal oxidation, providing means for forming an oxide film through oxidation conducted at a low temperature, so as to provide a method of forming an insulating film and a method of fabricating a semiconductor device in which the aforementioned problems can be overcome.

In order to overcome the problems, an oxide film or a nitrided oxide film is formed at a low temperature by utilizing biased plasma in this invention.

The method of this invention of forming an insulating film for a semiconductor device for forming, on a semiconductor layer exposed on a substrate, the insulating film through a reaction between at least oxygen and a semiconductor, comprises the steps of (a) loading the substrate including the semiconductor layer in a processing chamber; and (b) generating, within the processing chamber, plasma biased toward the substrate with the processing chamber kept in an atmosphere including oxygen, and subjecting the semiconductor layer to the biased plasma.

In this method, an insulating film can be formed through oxidation of a semiconductor using plasma and conducted at a temperature lower than in thermal oxidation. Accordingly, by utilizing this characteristic, insulating films functioning as various members of a semiconductor device can be formed while avoiding the problems such as the characteristic degradation derived from subjecting the substrate to a high temperature.

In the method of forming an insulating film, a thickness of the insulating film can be controlled by adjusting magnitude of a degree of biasing the plasma in the step (b).

In the method of forming an insulating film, the step (b) is preferably carried out at a temperature of 300.degree. C. or less.

In the method of forming an insulating film, the step (b) is more preferably carried out at a temperature of 200.degree. C. or less.

In the method of forming an insulating film, the step (b) can be carried out with a photoresist film formed on the substrate.

In the method of forming an insulating film, the insulating film can be used as a gate insulating film of a MIS transistor.

The method of forming an insulating film can further comprise, before at least the step (b), a step of forming a first active region doped with an impurity of a first conductivity type and a second active region doped with an impurity of a second conductivity type, and a first insulating film and a second insulating film can be respectively formed on the first active region and the second active region in the step (b). In this manner, differently from the thermal oxidation, the first insulating film and the second insulating film can be formed in substantially the same thickness.

The method of forming an insulating film can further comprise, after the step (b), a step of conducting a heat treatment on the insulating film. In this manner, the insulating film can be made in uniform quality and carbon contamination thereon can be removed, resulting in improving the reliability of the insulating film.

In the method of forming an insulating film, the step (b) can be carried out in an atmosphere including nitrogen and oxygen, in an atmosphere including a NO gas (a nitriding oxidation atmosphere), or in an atmosphere including oxygen and N.sub.2 (a nitriding oxidation atmosphere). In this case, a nitrided oxide film is formed.

Alternatively, when the step (b) is carried out in an atmosphere including O.sub.2 but substantially no nitrogen, an oxide film is formed.

The first method of fabricating a semiconductor device of this invention comprises the steps of (a) forming an insulating film on first and second active regions of a semiconductor substrate; (b) forming a first photoresist film covering the second active region and having an opening on the first active region; (c) implanting impurity ions into the first active region through the first photoresist film; (d) removing the first photoresist film; (e) recovering a thickness of the insulating film by subjecting, in an atmosphere including oxygen, the semiconductor substrate to plasma biased toward the semiconductor substrate; (f) forming a second photoresist film covering the first active region and having an opening on the second active region; and (g) implanting impurity ions into the second active region through the second photoresist film.

In this method, although the insulating film is also etched to cause variation in its thickness by the ion implantation and the ashing and cleaning conducted for removing the first photoresist film in the step (d), the thickness of the insulating film is recovered to a substantially uniform thickness by the bias plasma oxidation conducted in the step (e). Accordingly. the distribution of the impurity ions implanted into the second active region in the following step (g) can be controlled with good reproducibility.

In the first method of fabricating a semiconductor device, when the step (c) corresponds to impurity ion implantation for controlling a threshold value of a MISFET, the variation in the threshold value of the MISFET can be suppressed.

The second method of fabricating a semiconductor device of this invention comprises the steps of (a) forming a semiconductor film on a semiconductor substrate; (b) forming, on the semiconductor film, a first photoresist film covering a first part of the semiconductor film and having an opening on a second part of the semiconductor film adjacent to the first part, and implanting impurity ions of a first conductivity type into the semiconductor film through the first photoresist film; (c) after removing the first photoresist film, forming a second photoresist film covering the second part of the semiconductor film and having an opening on the first part, and implanting impurity ions of a second conductivity type into the semiconductor film through the second photoresist film; (d) removing the second photoresist film; and (e) forming an insulating film on the semiconductor film through a reaction between at least oxygen and a semiconductor by subjecting, in an atmosphere including oxygen, the semiconductor substrate to plasma biased toward the semiconductor substrate.

In this method, although a step is formed on the top face of the semiconductor film in the ashing and the cleaning for removing the photoresist film in the step (d) owing to the difference in the conductivity type of the impurities implanted in the semiconductor film, a portion in the vicinity of the top face of the semiconductor film is oxidized in the process conducted at a low temperature in the step (e), so as to round the abrupt step. Accordingly, the harmful effect of the abrupt step on members formed on the semiconductor film afterward can be avoided without harmfully affecting the impurity distribution in the semiconductor film.

The second method of fabricating a semiconductor device can further comprise, before the step (a), a step of forming gate insulating films respectively on a first conductivity type MISFET formation region and a second conductivity type MISFET formation region of the semiconductor substrate, and the semiconductor film can be formed on the gate insulating films over the first and second conductivity type MISFET formation regions in the step (a), the first part may correspond to the second conductivity type MISFET formation region and the second part corresponds to the first conductivity type MISFET formation region in the steps (b) and (c), and the method can further include, after the step (d), a step of patterning the semiconductor film into a gate electrode of a dual gate type over the first conductivity type MISFET formation region and the second conductivity type MISFET formation region. In this case, an electric field can be well transferred between the gate electrodes of a CMIS inverter.

The second method of fabricating a semiconductor device can further comprise, after at least the step (d), a step of siliciding an upper portion of the semiconductor film after removing at least part of a thickness of the insulating film formed in the step (e). In this manner, an electric field can be well transferred between gate electrodes with low resistance.

The third method of fabricating a semiconductor device of this invention comprises the steps of (a) forming an insulating film on a semiconductor substrate; (b) forming a semiconductor film on the insulating film; (c) forming a gate electrode of a MISFET by patterning the semiconductor film by etching with a photoresist film used as a mask; and (d) oxidizing etching residues of the semiconductor film remaining on the exposed insulating film by subjecting, in an atmosphere including oxygen, the semiconductor substrate to plasma biased toward the semiconductor substrate, with keeping said photoresist film.

In this method, etching residues functioning as a conductor can be prevented from remaining around a member formed by patterning the semiconductor film, and the semiconductor substrate can be prevented from being roughened on its surface through ununiform etching in removing the insulating film afterward.

The third method of fabricating a semiconductor device can further comprise, after the step (d), steps of removing the oxidized etching residues and an exposed portion of the insulating film; and siliciding part of the semiconductor substrate exposed by removing the exposed portion of the insulating film. In this manner. a silicide layer with low resistance can be formed as part of a source/drain region of a MISFET.

When the step (d) is carried out at a temperature of 200.degree. C. or less, the step (d) can be carried out with the photoresist film kept. Thereafter, oxidized etching residues and an insulating film can be removed by etching using the photoresist film.

The fourth method of fabricating a semiconductor device of this invention comprises the steps of (a) successively depositing a first insulating film and a conducting film at least including a metal on a semiconductor substrate; (b) patterning the conducting film and the first insulating film by etching with a photoresist film used as a mask into a gate electrode and a gate insulating film; (c) forming a second insulating film on at least an exposed portion of the semiconductor substrate through a reaction between oxygen and a semiconductor by subjecting, in an atmosphere including oxygen, the semiconductor substrate to plasma biased toward the semiconductor substrate, with the photoresist film kept; (d) removing the photoresist film; and (e) forming source/drain regions by introducing an impurity into regions positioned on both sides of the gate electrode in the semiconductor substrate.

In this method, even if the metal of the conducting film included in the gate electrode is dissolved in the cleaning solution, the metal ions can be prevented from entering the semiconductor substrate because the second insulating film is present on the semiconductor substrate. In addition, since there is no need to conduct a high temperature treatment like the thermal oxidation, the metal of the conducting film can be avoided from being oxidized.

In the fourth method of fabricating a semiconductor device, a polysilicon film and a metal film stacked thereon can be formed as the conducting film in the step (a), a bottom electrode of a polysilicon film and a top electrode of a metal film can be formed as the gate electrode in the step (b), and the second insulating film can be formed also on side faces of the bottom electrode in the step (c). In this manner, a semiconductor device including a gate electrode having the polymetal structure or the polycide structure can be fabricated.

In the fourth method of fabricating a semiconductor device, a silicon nitride film can be further formed on the conducting film in the step (a), an over-gate protection film of a nitride film can be formed on the top electrode in the step (b), and the method can further include, after the step (d), steps of (f) forming nitride film sidewalls on side faces of the polysilicon film and the metal film; (g) depositing an interlayer insulating film of a silicon oxide film on the substrate; and (h) forming a contact hole penetrating through the interlayer insulating film and reaching the source/drain region in a self-alignment manner against the gate electrode. In this manner, a semiconductor device, suitable to refinement, having the polymetal structure or the polycide structure and the so-called SAC (self-aligned contact) structure can be fabricated.

In the fourth method of fabricating a semiconductor device, the step (c) is preferably carried out at a temperature of 200.degree. C. or less.

The fifth method of fabricating a semiconductor device of this invention comprises the steps of (a) forming a first gate electrode from a semiconductor film including an impurity of a first conductivity type on a first conductivity type MISFET formation region of a semiconductor substrate with a first gate insulating film sandwiched therebetween, and forming a second gate electrode from a semiconductor film including an impurity of a second conductivity type on a second conductivity type MISFET formation region of the semiconductor substrate with a second gate insulating film sandwiched therebetween; (b) forming a coat insulating film through a reaction between at least oxygen and a semiconductor on the semiconductor substrate and exposed portions of the first and second gate electrodes by subjecting, in an atmosphere including oxygen, the semiconductor substrate to plasma biased toward the semiconductor substrate; (c) forming source/drain regions of a first conductivity type MISFET through ion implantation of an impurity of the first conductivity type by using, as masks, a first photoresist film covering the second conductivity type MISFET formation region and having an opening on the first conductivity type MISFET formation region and the first gate electrode; (d) removing the first photoresist film; and (e) forming source/drain regions of a second conductivity type MISFET through ion implantation of an impurity of the second conductivity type by using, as masks, a second photoresist film covering the first conductivity type MISFET formation region and having an opening on the second conductivity type MISFET formation region and the second gate electrode.

In this method, since the coat insulating film can be formed at a low temperature in the step (b), punch-through of boron included in the gate electrode into the semiconductor substrate caused in the thermal oxidation can be avoided. Furthermore, since the surface of the semiconductor substrate can be protected by the coat insulating film, the surfaces of the source/drain regions can be prevented from being etched in removing the photoresist film in the following step (d) even when the gate insulating film has a small thickness, and hence, the sheet resistance of the source/drain regions can be kept small.

In the fifth method of fabricating a semiconductor device, the step (b) is preferably carried out at a temperature of 300.degree. C. or less.

Furthermore, the first photoresist film is preferably removed in the step (d) by ashing with a degree of biasing plasma smaller than a degree of biasing the plasma in the step (b). In this manner, the ashing can be carried out without increasing the thickness of the coat insulating film formed on the semiconductor substrate. As a result, the impurity profile in the surface portion of the semiconductor substrate is minimally changed, and hence, the leak characteristic and the like of the semiconductor device can be kept satisfactorily.

The sixth method of fabricating a semiconductor device of this invention comprises the steps of (a) successively depositing a pad oxide film and a masking nitride film on a semiconductor substrate; (b) forming an opening in the masking nitride film and the pad oxide film in a position corresponding to a trench formation region; (c) forming a trench in the semiconductor substrate by conducting etching with the masking nitride film used as a mask; (d) forming a rounding insulating film through a reaction between at least oxygen and a semiconductor on a portion of the semiconductor substrate exposed with in the trench by subjecting, in an atmosphere including oxygen, the semiconductor substrate to plasma biased toward the semiconductor substrate; and (e) forming a trench isolation region by filling the trench with an insulating film.

In this method, an abrupt edge of the semiconductor substrate exposed because the pad oxide film sinks in forming a trench by the etching in the step (b) can be rounded by forming the rounding insulating film in the step (d). Therefore, it is possible to suppress the degradation of the reliability of the gate insulating film derived from electric field collection in a MISFET formed therein and the occurrence of the hump characteristic in the MISFET.

The sixth method of fabricating a semiconductor device can further comprises. after the step (d) and before the step (e), a step of increasing a thickness of the rounding insulating film by thermal oxidation. In this manner, an underlying oxide film for a trench isolation region can be formed without causing the problem of the electric field collection and the like.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is across-sectional view for schematically showing the structure of a bias plasma generation system used in each embodiment of the invention;

FIGS. 2(a) and 2(b) show data of dependency, on processing time and bias, of the thickness of a silicon oxide film formed by bias plasma oxidation;

FIG. 3 is a diagram for showing dependency, on the thickness of an initial oxide film, of increase in the thickness of an oxide film formed by the bias plasma oxidation conducted on a wafer where the initial oxide film is previously formed;

FIGS. 4(a), 4(b), 4(c) and 4(d) are cross-sectional views for showing procedures in fabrication of a CMOS device having a trench isolation structure and a dual gate structure according to Embodiment 1 up to ion implantation for forming wells;

FIGS. 5(a), 5(b), 5(c) and 5(d) are cross-sectional views for showing other procedures in the fabrication of the CMOS device having the trench isolation structure and the dual gate structure of Embodiment 1 up to impurity ion implantation into a polysilicon film for gate electrodes;

FIGS. 6(a), 6(b), 6(c) and 6(d) are cross-sectional views for showing other procedures in the fabrication of the CMOS device having the trench isolation structure and the dual gate structure of Embodiment 1 up to formation of the gate electrodes;

FIGS. 7(a), 7(b), 7(c) and 7(d) are cross-sectional views for showing other procedures in the fabrication of the CMOS device having the trench isolation structure and the dual gate structure of Embodiment 1 up to formation of a salicide film;

FIGS. 8(a), 8(b), 8(c), 8(d) and 8(e) are TEM images of oxide films formed through the bias plasma oxidation on a channel region of an NMOSFET, a channel region of a PMOSFET, a substantially intrinsic substrate, an N-type polysilicon film and a P-type polysilicon film, respectively;

FIG. 9 is a diagram for showing the result of QBD evaluation of a PMOSFET including a gate insulating film formed through the bias plasma oxidation in Embodiment 1;

FIG. 10 is a diagram for showing the result of the QBD evaluation of a conventional PMOSFET including a gate insulating film of a thermal oxide film (pyrogenic oxidized at 900.degree. C.);

FIGS. 11(a), 11(b), 11(c), 11(d) and 11(e) are cross-sectional views of the structure of the gate electrodes alone in the bias plasma oxidation and silicidation taken on a section perpendicular to the section of FIG. 6(a);

FIGS. 12(a) and 12(b) are respectively a diagram obtained through three-dimensional observation with AFM of a step formed on the surfaces of N-type and P-type polysilicon films after ion implantation and a diagram of minute steps in a section of the N-type and P-type polysilicon films after the ion implantation;

FIG. 13 is a diagram for showing difference in an electric resistance value of a polycide layer resulting from the bias plasma oxidation;

FIGS. 14(a), 14(b), 14(c) and 14(d) are cross-sectional views for showing first half procedures in fabrication of a CMOS device having a polymetal gate structure and the like according to Embodiment 2;

FIGS. 15(a), 15(b) and 15(c) are cross-sectional views for showing second half procedures in the fabrication of the CMOS device having the polymetal gate structure and the like of Embodiment 2;

FIG. 16 is a cross-sectional view of a CMOS device having a SAC structure according to modification of Embodiment 2;

FIGS. 17(a), 17(b) and 17(c) are cross-sectional views for showing first half procedures in fabrication of a CMOS device having a salicide structure according to Embodiment 3;

FIGS. 18(a), 18(b) and 18(c) are cross-sectional views for showing second half procedures in the fabrication of the CMOS device having the salicide structure of Embodiment 3;

FIGS. 19(a) and 19(b) show data for comparison in the Ion-Ioff characteristic between MOSFETs formed in Embodiment 3 and MOSFETs formed without the plasma oxidation;

FIGS. 20(a), 20(b) and 20(c) are cross-sectional views for showing part of procedures for forming a trench isolation region of a semiconductor device according to Embodiment 4;

FIGS. 21(a), 21(b), 21(c) and 21(d) are cross-sectional views for showing first half procedures in fabrication of a conventional CMOS device having a trench isolation structure and a dual gate structure;

FIGS. 22(a), 22(b), 22(c) and 22(d) are cross-sectional views for showing second half procedures in the fabrication of the conventional CMOS device having the trench isolation structure and the dual gate structure;

FIGS. 23(a), 23(b), 23(c) and 23(d) are cross-sectional views for showing procedures in fabrication of a conventional CMOS device having a polymetal structure;

FIGS. 24(a), 24(b) and 24(c) are cross-sectional views of the structure of gate electrodes alone in silicidation taken on a section perpendicular to the section of FIG. 22(d);

FIG. 25 is a plan view of gate electrodes and a portion below in a conventional CMOS inverter, that is, a semiconductor device; and

FIG. 26 is a cross-sectional view for showing the shape of a conventional trench isolation region.

DETAILED DESCRIPTION OF THE INVENTION

Formation of Oxide Film by Bias Plasma Oxidation

Before describing preferred embodiments of the invention, a system employed for bias plasma oxidation of this invention and the characteristic of an oxide film formed by the bias plasma oxidation will be described.

FIG. 1 is a sectional view for schematically showing the structure of the bias plasma generation system employed in each it of the preferred embodiments. The bias plasma generation system includes a lower electrode 2 serving as an anode and disposed on the bottom of a chamber 1, a bias electrode 3 serving as a cathode and opposing the lower electrode 2, and a high frequency power supply 5 for applying high frequency power (of 13.56 MHz) to the lower electrode through a capacitor 6. A processing wafer 4 is placed on the lower electrode 2, plasma and a reaction gas (oxygen) are introduced through an upper portion of the chamber 1, and the reaction gas is vacuated through an exhaust port provided to the chamber 1 in the vicinity of the lower electrode 2. As the plasma generation system, any of various plasma generation systems, such as a capacity coupling plasma system, an induction coupling plasma system, an ECR plasma generation system and a helicon plasma generation system, can be employed by additionally providing a bias electrode.

In conducting processing by using bias plasma, for example, the temperature of the lower electrode 2 is set to 180.degree. C., an oxygen gas is introduced through the upper portion of the chamber at a flow rate of approximately 800 sccm, the gas pressure is set to 0.5 Torr (66.65 Pa) and high frequency power of 1000 W is applied by the high frequency power supply 5. Thus, a Si layer (monosilicon, polysilicon or amorphous silicon) exposed on the wafer 4 is oxidized into a silicon oxide film. The high frequency power can be replaced with a DC voltage. The experiment results described below are obtained by applying not the high frequency power but the DC voltage.

FIGS. 2(a) and 2(b) show data of dependency, on processing time and bias, of the thickness of a silicon oxide film formed by conducting the bias plasma oxidation on a processing wafer. FIG. 2(a), the abscissa indicates time (sec.) for applying the bias plasma, and the ordinate indicates the thickness (nm) of the formed silicon oxide film (SiO.sub.2 film). As is shown in FIG. 2(a), the bias plasma oxidation is found to have a characteristic form of oxidation as follows: As the bias plasma oxidation is proceeded, the thickness of the oxide film is abruptly increased to 3 nm at the initial stage, but thereafter, even though the bias plasma oxidation is further proceeded, the increasing rate of the thickness of the silicon oxide film is lowered. When the bias plasma oxidation is carried out for 10 min., the thickness of the oxide film is substantially saturated at approximately 6 nm.

FIG. 3 shows the dependency, on the thickness of an initial oxide film, of the increase in the thickness of an oxide film formed through the bias plasma oxidation conducted on a wafer where the initial oxide film is previously formed. In FIG. 3, the abscissa indicates the thickness of the initial oxide film formed on the wafer by thermal oxidation before conducting the bias plasma oxidation, and the ordinate indicates the increase (nm) in the thickness of the oxide film obtained by conducting the bias plasma oxidation for 5 min. under the aforementioned conditions (with the temperature of the lower electrode set to 108.degree. C.), namely, the thickness of a newly formed oxide film. As is shown in FIG. 3, in the case where the initial oxide film has a thickness of 6 nm or less, the newly oxide film is formed through the bias plasma oxidation conducted for 10 min., so that the total thickness of the oxide films can be approximately 6 nm. In other words, the total thickness of the oxide films is naturally controlled to be a constant value (of approximately 6 nm). On the other hand, when the initial oxide film has a thickness exceeding 6 nm, the total thickness of the oxide films is minimally increased through the bias plasma oxidation.

In FIG. 2(b), the abscissa indicates RF power (W) corresponding to the degree of biasing the plasma, and the ordinate indicates the thickness (run) of the formed silicon oxide film. As is shown in FIG. 2(b), the thickness of the oxide film is substantially linearly increased in accordance with the RF power (bias). Specifically, the saturation thickness of the oxide film is largely affected by the bias, and it is confirmed that as the bias increases, the saturation thickness of the oxide film increases, and that as the bias decreases, the saturation thickness. of the oxide film decreases. In other words, the total thickness of the oxide films can be controlled in accordance with the bias.

As a characteristic of the bias plasma oxidation, an oxide film can be sufficiently formed at a low temperature of 200.degree. C. or less (including room temperature). In conducting the bias plasma oxidation at such a low temperature, even when a photoresist film is formed on the wafer, the rate of removing the photoresist film is so low that it is minimally removed. This is because ashing for removing a photoresist film is generally conducted at approximately 250.degree. C. or more. Accordingly, when a photoresist film is present on the wafer, the bias plasma oxidation is preferably conducted at 200.degree. C. or less, whereas when no photoresist film is present, the temperature can be increased to approximately 300.degree. C.

Conventional plasma oxidation is carried out at 350 through 600.degree. C., and therefore, when a photoresist film is present on a wafer, the photoresist film is unavoidably damaged in forming an oxide film.

The frequency of the high frequency power may be varied in a range between 200 KHz and 20 MHz or the high frequency power may be a DC voltage as described above, whereas the plasma can be biased probably more effectively by using the high frequency power. In particular, radicals or ions included in the plasma can be more easily biased by using high frequency power with a comparative low frequency of 800 KHz or 400 KHz.

The reaction gas is not limited to oxygen but can be a mixture of nitrogen and oxygen. For example, the bias plasma oxidation can be conducted in a NO gas atmosphere or an atmosphere including oxygen and nitrogen. It goes without saying that it can be conducted in an atmosphere including oxygen but substantially no nitrogen.

Now, a method of forming a bias plasma oxide film and a method of fabricating a semiconductor device using the method will be described.

Embodiment 1

FIGS. 4(a) through 4(d), 5(a) through 5(d), 6(a) through 6(d) and 7(a) through 7(d) are sectional views for showing procedures in fabrication of a CMOS device having a trench isolation structure and a dual gate structure according to Embodiment 1.

First, in the procedure shown in FIG. 4(a), after forming a trench isolation region 12 in a Si substrate 11, a protection oxide film 13 with a thickness of approximately 10 nm is formed in an active region of the Si substrate 11 by thermal oxidation. Then, a photoresist film Pr1 covering an NMOSFET formation region Rn and having an opening on a PMOSFET formation region Rp is formed on the substrate by photolithography. Thereafter, phosphorus ions (P.sup.-) are implanted into a portion of the Si substrate 11 within the opening of the photoresist film Pr1 (namely, the PMOSFET formation region Rp) at implantation energy of 140 keV and a dose of 1.times.10.sup.12 cm.sup.-2, thereby forming an N-type well region 15. Also, boron ions (B.sup.30 ) for controlling a threshold voltage are implanted implantation energy of 20 keV and a dose of 6.times.10.sup.12 cm.sup.-2, and arsenic ions (As.sup.+) for stopping punch-through are implanted at implantation energy of 300 keV and a dose of 4.times.10.sup.12 cm.sup.-2. In this manner, the so-called buried channel region is formed. Alternatively, when a surface PMOSFET is desired, the ion implantation for controlling the threshold voltage is carried out by implanting phosphorus ions (P.sup.+) at implantation energy of 50 keV and a dose of 5.times.10.sup.12 cm.sup.-2.

Next, in the procedure shown in FIG. 4(b), the photoresist film Pr1 is removed by ashing and RCA cleaning. Specifically, the photoresist film is removed and the substrate is cleaned by ashing utilizing plasma in an oxygen atmosphere and by cleaning utilizing a mixed solution of sulfuric acid and hydrogen peroxide or hydrofluoric acid. At this point, the protection oxide film 13 is etched mainly by the RCA cleaning, and hence its thickness is reduced as a whole and becomes ununiform. Therefore, in the procedure shown in FIG. 4(c), the bias plasma oxidation is carried out for 5 minutes by using the plasma generation system of FIG. 1 in an atmosphere including oxygen at a substrate temperature of 180.degree. C. and bias power of 1000 W. Through this bias plasma oxidation, the protection oxide film 13 is recovered into a protection oxide film 13a with a substantially uniform thickness of approximately 10 nm. Specifically, as is understood from FIGS. 2(a), 2(b) and 3, since an oxide film formed through the bias plasma oxidation has a thickness corresponding to a constant saturation value determined depending upon the bias power, the damaged protection oxide film can be thus recovered into the protection oxide film 13a with a substantially uniform thickness. This bias plasma oxidation can be carried out at a high temperature of approximately 300.degree. C.

Next, in the procedure shown in FIG. 4(d), a photoresist film Pr2 covering the PMOSFET formation region Rp and having an opening on the NMOSFET formation region Rn is formed on the substrate by the photolithography. Thereafter, boron ions (B.sup.+) are implanted into a portion of the Si substrate 11 within the opening of the photoresist film Pr2 (namely, the NMOSFET formation region Rn) at implantation energy of 280 keV and a dose of 1.times.10.sup.13 cm.sup.-2, thereby forming a P-type well region 16. Also, boron ions (B.sup.+) for controlling a threshold value are implanted at implantation energy of 30 keV and a dose of 6.times.10.sup.12 cm.sup.-2. Thus, the so-called surface type channel region is formed.

Subsequently, in the procedure shown in FIG. 5(a), the photoresist film Pr2 is removed by the ashing and the RCA cleaning, and the protection oxide film 13a is also removed. Then, the bias plasma oxidation is carried out for 5 minutes in an atmosphere including oxygen (or oxygen and nitrogen) at a substrate temperature of 180.degree. C. and bias power of 1000 W. Thus, gate insulating films 17a and 17b of an oxide film (or a nitrided oxide film) with a thickness of approximately 6 nm are formed in the active region of the Si substrate 11. At this point, the insulating film formed through the bias plasma oxidation has a thickness saturated at a substantially constant value regardless of the kinds of impurities included in the Si layers (well regions 15 and 16) below. Accordingly, the gate insulating films 17a and 17b with an equivalent thickness of approximately 6 nm can be formed.

Next, in the procedure shown in FIG. 5(b), a polysilicon film 18 for gate electrodes with a thickness of approximately 200 nm is deposited on the substrate, and then, a photoresist film Pr3 covering the NMOSFET formation region Rn and having an opening on the PMOSFET formation region Rp is formed on the polysilicon film 18. Thereafter, boron ions (B.sup.-) are implanted into a portion of the polysilicon film 18 within the opening of the photoresist film Pr3 (namely, the PMOSFET formation region Rp) at implantation energy of 5 keV and a dose of 3.times.10.sup.15 cm-.sup.2.

Similarly, in the procedure shown in FIG. 5(a), the photoresist film Pr3 is removed by the ashing and the RCA cleaning, and a photoresist film Pr4 covering the PMOSFET formation region Rp and having an opening on the NMOFET formation region Rn is formed on the polysilicon film 18 by the photolithography. Then, phosphorus ions (P.sup.+) are implanted into a portion of the polysilicon film 18 within the opening of the photoresist film Pr4 (namely, the NMOSFET formation region Rn) at implantation energy of 15 keV and a dose of 5.times.10.sup.15 cm-.sup.2.

Then, in the procedure shown in FIG. 5(d), the photoresist film Pr4 is removed by the ashing and the RCA cleaning, and a heat treatment is carried out for activating the impurities implanted into the polysilicon film 18. In this manner, a P-type polysilicon film 18p is formed in the PMOSFET formation region Rp and an N-type polysilicon film 18n is formed in the NMOSFET formation region Rn. At this point, the P-type polysilicon film 18p and the N-type polysilicon film 18n are etched by the RCA cleaning and cleaning conducted before loading the substrate in a furnace, and due to a difference therebetween in the etch rate, an abrupt step is formed therebetween as described above.

Subsequently, in the procedure shown in FIG. 6(a), the bias plasma oxidation is carried out for 1 through 5 minutes in an atmosphere including oxygen at a substrate temperature of 180.degree. C. and bias power of 1800 W. Thus, the entire surfaces of the polysilicon films 18p and 18n are oxidized into an oxide film 19 with a thickness of approximately 10 nm. This bias plasma oxidation can be carried out at approximately 300.degree.C.

Next, in the procedure shown in FIG. 6(b), the oxide film 19 is removed by etching. As a result, the abrupt step having been present on the boundary between the P-type polysilicon film 18p and the H-type polysilicon film 18n is rounded and disappears.

Then, in the procedure shown in FIG. 6(c), a photoresist film Pr5 covering a gate formation region is formed by the photolithography, and the P-type polysilicon film 18p and the N-type polysilicon film 18n are patterned through dry etching using the photoresist film Pr5 as a mask, thereby forming a gate electrode 18a of the PMOSFET and a gate electrode 18b of the NMOSFET. At this point, when it is determined that removal of the polysilicon films 18p and 18n is completed, the gate insulating films 17a and 17b are dotted with etching residues 18x of the polysilicon films 18p and 18n. Therefore, with the photoresist film Pr5 kept, the bias plasma oxidation is carried out for 5 minutes in an atmosphere including oxygen (or oxygen and nitrogen) at a substrate temperature of 180.degree. C. and bias power of 1000 W, thereby changing the etching residues 18x into an oxide film (or a nitrided oxide film).

Next, in the procedure shown in FIG. 6(d), after removing the photoresist film Pr5, portions of the gate insulating films 17a and 17b not covered with the gate electrode 18a or 18b are removed through the dry etching. The etching residues 18x may be oxidized by the aforementioned bias plasma oxidation after removing the photoresist film Pr5.

Subsequently, in the procedure shown in FIG. 7(a), although not shown in the drawing, a photoresist film covering the NMOSFET information region Rn and having an opening on the PMOSFET formation region Rp is formed, and P-type impurity ions are implanted by using the photoresist film and the gate electrode 18a of the PMOSFET as masks, thereby forming low concentration source/drain regions 19 of the PMOSFET. Then, a photoresist film covering the PMOSFET formation region Rp and having an opening on the NMOSFET formation region Rn is formed, and N-type impurity ions are implanted by using the photoresist film and the gate electrode 18b of the NMOSFET as masks, thereby forming low concentration source/drain regions 20 of the NMOSFET. At this point, it is preferred that the bias plasma oxidation is carried out for forming a thin oxide film before forming the photoresist film and that the photoresist film is removed after the ion implantation.

Next, in the procedure shown in FIG. 7(b), a silicon oxide film is deposited on the substrate and is then etched back, thereby forming sidewalls 23a and 23b on the side faces of the gate electrodes 18a and 18b of the MOSFETs. Thereafter, although not shown in the drawing, a photoresist film covering the NMOSFET formation region Rn and having an opening on the PMOSFET formation region Rp is formed, and P-type impurity ions are implanted by using the photoresist film and the gate electrode 18a and the oxide film sidewalls 23a of