Method of forming gate of flash memory device Number:7,521,319 from the United States Patent and Trademark Office (PTO) owispatent A method of forming a gate of a flash memory device, including the steps of forming a gate on a semiconductor substrate and forming an oxide layer on the entire surface of the gate, forming a nitride layer on a sidewall of the oxide layer in a spacer form, performing a polishing process so that a top surface of the gate is exposed, and then stripping the nitride layer to form an opening, forming a barrier metal layer on a sidewall of the opening, and forming a tungsten layer in the opening.<H forming, device, Method, of, formi, 7521319.html, Patent, pto, 7521319

Title: Method of forming gate of flash memory device

Abstract: A method of forming a gate of a flash memory device, including the steps of forming a gate on a semiconductor substrate and forming an oxide layer on the entire surface of the gate, forming a nitride layer on a sidewall of the oxide layer in a spacer form, performing a polishing process so that a top surface of the gate is exposed, and then stripping the nitride layer to form an opening, forming a barrier metal layer on a sidewall of the opening, and forming a tungsten layer in the opening.

Patent Number: 7,521,319 Issued on 04/21/2009 to Jeong, et al.

Inventors: Jeong; Cheol Mo (Kyeongki-do, KR), Cho; Whee Won (Chungcheongbuk-do, KR), Kim; Jung Geun (Seoul, KR), Myung; Seong Hwan (Kyeongki-do, KR)
Assignee: Hynix Semiconductor Inc. (Gyeonggi-do, KR)

Appl. No.: 11/646,777

Filed: December 28, 2006

Foreign Application Priority Data


Jun 28, 2006 [KR]			10-2006-0058779

Current U.S. Class: 438/257 ; 438/266

Current International Class: H01L 21/336 (20060101)

References Cited [Referenced By]

U.S. Patent Documents


6873019	March 2005	Ida et al.
6884680	April 2005	Koh
7037784	May 2006	Hong
7052972	May 2006	Sandhu et al.
7262093	August 2007	Wang

Foreign Patent Documents


10-2002-0056141	Jul., 2002	KR
10-2003-057879	Jul., 2003	KR
10-2004-0098106	Nov., 2004	KR

Primary Examiner: Richards; N Drew
Assistant Examiner: Duong; Khanh B
Attorney, Agent or Firm: Marshall, Gerstein & Borun LLP

Claims

What is claimed is:

1. A method of forming a gate of a flash memory device, the method comprising: forming a gate including a first nitride layer on a semiconductor substrate; forming an oxide layer having a sidewall on the entire surface of the gate; forming a second nitride layer on the sidewall of the oxide layer in a spacer form; performing a polishing process so that a top surface of the first nitride layer is exposed; stripping the first nitride layer to form an opening having a sidewall; forming a barrier metal layer on the sidewall of the opening; and forming a tungsten layer in the opening.

2. The method of claim 1, wherein the forming of the gate comprises: sequentially laminating a tunnel oxide layer, a first polysilicon layer, a dielectric layer, a second polysilicon layer, the first nitride layer, a hard mask layer, an SiON layer, and a photoresist on the semiconductor substrate; patterning the photoresist; etching the SiON layer and the hard mask layer using the patterned photoresist as a mask; removing the patterned photoresist and the SiON layer, thereby forming a hard mask layer pattern; etching the first nitride layer, the second polysilicon layer, the dielectric layer, the first polysilicon layer, and the tunnel oxide layer using the hard mask layer pattern as a mask; and stripping the hard mask layer pattern.

3. The method of claim 2, comprising forming the first nitride layer to a thickness of 500 .ANG. to 2000 .ANG..

4. The method of claim 2, comprising forming the hard mask layer using .alpha.-carbon to a thickness of 500 .ANG. to 2000 .ANG..

5. The method of claim 2, comprising forming the SiON layer to a thickness of 100 .ANG. to 1000 .ANG..

6. The method of claim 1, wherein after the oxide layer is etched, a height between the second nitride layer and the oxide layer is 200 .ANG. to 500 .ANG..

7. The method of claim 1, comprising forming the second nitride layer to a thickness of 300 .ANG. to 1000 .ANG..

8. The method of claim 1, wherein a height between a top surface of the first nitride layer and a top surface of the second nitride layer is set within a range of 200 .ANG. to 500 .ANG..

9. The method of claim 2, wherein a height between a top surface of the first nitride layer and a top surface of the second nitride layer is set within a range of 200 .ANG. to 500 .ANG..

10. The method of claim 2, comprising performing a wet etch process using a phosphoric acid solution on the first nitride layer in order to form an opening.

11. The method of claim 1, comprising forming the barrier metal layer using one of W, Ti and TiN, Ta and TaN, and WN.

12. The method of claim 1, further comprising forming an oxide layer or a nitride layer on the sidewall of the opening before forming the barrier metal layer.

Description

BACKGROUND

1. Field of the Invention

The invention relates, in general, to flash memory devices and, more particularly, to a method of forming a gate of a flash memory device.

2. Discussion of Related Art

As the level of integration of flash memory devices increases, a metal line formation method using the damascene method instead of the conventional Reactive Ion Etching (RIE) method is increasingly used. This is because in memory devices of 60 nm or less, a tungsten gate has a narrow width of 60 nm or less and is difficult to pattern using the conventional RIE method. In the case where a tungsten silicide (WSi) gate is used, it is difficult to secure a gate line. In the case where a target is increased so as to secure resistance, it results in increased intra-capacitance. Furthermore, a hard mask layer, a tungsten silicide layer, a polysilicon layer, and an oxide layer must be etched at the same time even at the time of gate etch. In the case where a tungsten gate is formed using the RIE method, it is difficult to form a spacer because of tungsten oxidization and the reliability of the gate is low due to thermal budget. In addition, in the case where the conventional tungsten (W) single damascene method is used, a first polysilicon layer pattern must be formed at the ISO level and the coupling ratio is decreased due to misalignment.

SUMMARY OF THE INVENTION

Accordingly, the invention provides a method of forming a gate of a flash memory device, wherein gate pattern margin can be increased and capacitance between gates can be decreased.

According to one aspect, the invention provides a method of forming a gate of a flash memory device, including the steps of forming a gate on a semiconductor substrate and forming an oxide layer on the entire surface of the gate, forming a nitride layer on a sidewall of the oxide layer in a spacer form, performing a polishing process so that a top surface of the gate is exposed, and then stripping the nitride layer to form an opening, forming a barrier metal layer on a sidewall of the opening, and forming a tungsten layer in the opening.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 to 11 are cross-sectional views illustrating a method of forming a gate of a flash memory device according to an embodiment of the invention.

DETAILED DESCRIPTION OF EMBODIMENTS

Specific embodiments according to the invention are described below with reference to the accompanying drawings.

FIGS. 1 to 11 are cross-sectional views illustrating a method of forming a gate of a flash memory device according to an embodiment of the invention.

Referring to FIG. 1, a tunnel oxide layer 102, a first polysilicon layer 103 for a floating gate, a dielectric layer 104, a second polysilicon layer 105 for a control gate, a first nitride layer 106, a hard mask layer 107, a SiON layer 108, and a photoresist 109 are sequentially laminated on a semiconductor substrate 101 in which a cell region and a selection line region are defined. The photoresist 109 is patterned. The first nitride layer 106 is preferably formed to a thickness of 500 .ANG. to 2000 .ANG.. The hard mask layer 107 is preferably formed using .alpha.-carbon to a thickness of 500 .ANG. to 2000 .ANG.. The SiON layer 108 is preferably formed to a thickness of 100 .ANG. to 1000 .ANG..

Referring to FIG. 2, the SiON layer 108 and the hard mask layer 107 are etched using the patterned photoresist 109 as a mask. The patterned photoresist 109 and the SiON layer 108 are removed, thereby forming a hard mask layer pattern 107a.

Referring to FIG. 3, the first nitride layer 106, the second polysilicon layer 105, the dielectric layer 104, the first polysilicon layer 103, and the tunnel oxide layer 102 are sequentially etched using the hard mask layer pattern 107a as a mask, and the hard mask layer pattern 107a is then stripped. Accordingly, a gate pattern is formed.

Referring to FIG. 4, after a cleaning process and an ion implantation process is performed on the result, an oxide layer 110 is formed on the entire surface. Accordingly, an oxide layer spacer is formed between the gates.

Referring to FIG. 5, the oxide layer 110 is formed to a desired thickness through an etch process. It is preferred that the oxide layer 110 be etched such that the height between the first nitride layer 106 and the oxide layer 110 is 200 .ANG. to 500 .ANG..

Referring to FIG. 6, a second nitride layer 111 is formed on the entire surface. It is preferred that the second nitride layer 111 be formed to a thickness of 300 .ANG. to 1000 .ANG..

Referring to FIG. 7, if the second nitride layer 111 is etched, the second nitride layer 111 for a Self-Aligned Contact (SAC) remains on the sidewall of the oxide layer 110 of the selection line region in spacer form.

Referring to FIG. 8, if the second nitride layer 111 for the SAC remaining on the sidewall of the oxide layer 110 of the selection line region is located higher than the first nitride layer 106 of the gate pattern, there is a possibility that the second nitride layer 111 may be exposed in a subsequent etch process. Accordingly, the second nitride layer 111 is etched so that it is located lower than the first nitride layer 106. It is preferred that a height A between a top surface of the second nitride layer 111 and a top surface of the first nitride layer 106 be within a range of 200 .ANG. to 500 .ANG..

Referring to FIG. 9, an Inter-Layer Dielectric (ILD) 112 as an oxide layer is formed on the entire surface. After the ILD layer 112 is formed, Chemical Mechanical Polishing (CMP) is preferably performed on the resulting surface. At this time, the CMP process is performed until the first nitride layer 106 is exposed using the first nitride layer 106 as an etch-stop layer.

Referring to FIG. 10, the first nitride layer 106 is dipped out using a wet etch process. In this case, only the first nitride layer 106 is dipped out preferably using a phosphoric acid solution through the wet etch process. If an opening (CH) is formed by dipping out the first nitride layer 106, the Critical Dimension (CD) can be controlled by allowing the inside of the CH to remain or forming an oxide layer or a nitride layer on the sidewall of the CH as a spacer Ox. The spacer Ox is preferably formed to a thickness of 0 .ANG. to 300 .ANG.. (When the thickness of the spacer Ox is 0 .ANG., it means that the spacer Ox is not formed.)

Referring to FIG. 11, a barrier metal layer 113 is formed on the sidewall of the CH. Tungsten is deposited on the entire surface. The tungsten is polished using CMP until the barrier metal layer 113 is exposed, thereby forming a tungsten layer 114. The barrier metal layer 113 is preferably formed using any one of Ti and TiN, Ta and TaN, and WN. Aluminum (Al) or copper (Cu) may be used instead of the tungsten layer 114. A subsequent capping layer is formed, thereby completing the line process.

As described above, the method of forming the gate of the flash memory device according to the invention has the following advantages.

First, the tungsten layer is formed on the second polysilicon layer. Accordingly, gate pattern margin can be increased.

Second, a coupling ratio at the interface between the first and second polysilicon layers can be increased.

Third, the tungsten layer is not formed until the spacer is formed. Accordingly, subsequent thermal budget can be reduced.

Fourth, the resistance of the tungsten layer can be kept constant because .alpha.-carbon is used as the hard mask.

Fifth, since the SAC nitride layer is partially etched, the SAC nitride layer can be prevented from being opened.

Sixth, the CD between the gates can be controlled by forming the oxide layer or the nitride layer on the sidewall of the opening.

Seventh, capacitance between the gates can be controlled by lowering the height of the second polysilicon layer and the tungsten layer.

Eighth, etch process margin can be secured when forming the opening due to a reduction in the height of the gate.

Although the foregoing description has been made with reference to various embodiments, changes and modifications of the invention may be made by those of ordinary skill in the art without departing from the spirit and scope of the invention.

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