Method of making a semiconductor chip assembly with a bumped metal pillar Number:7,112,521 from the United States Patent and Trademark Office (PTO) owispatent A method of making a semiconductor chip assembly includes providing a metal base, a routing line and a bumped terminal, then mechanically attaching a semiconductor chip to the metal base, the routing line and the bumped terminal, then forming an encapsulant, and then etching the metal base to form a metal pillar that contacts the bumped terminal.<H semiconductor, assembly, Method, of, makin, 7112521.html, Patent, pto, 7112521

Title: Method of making a semiconductor chip assembly with a bumped metal pillar

Abstract: A method of making a semiconductor chip assembly includes providing a metal base, a routing line and a bumped terminal, then mechanically attaching a semiconductor chip to the metal base, the routing line and the bumped terminal, then forming an encapsulant, and then etching the metal base to form a metal pillar that contacts the bumped terminal.

Patent Number: 7,112,521 Issued on 09/26/2006 to Lin, et al.

Inventors: Lin; Charles W. C. (Singapore, SG), Chiang; Cheng-Lien (Taipei, TW)
Assignee: Bridge Semiconductor Corporation (Taipei, TW)

Appl. No.: 10/998,339

Filed: November 27, 2004

Related U.S. Patent Documents


Application Number	Filing Date	Patent Number	Issue Date
10994604	Nov., 2004
10922280	Aug., 2004
10307218	Nov., 2002	6809414
09997973	Nov., 2001	6492252
09917339	Jul., 2001	6537851
09878626	Jun., 2001	6653217
09687619	Oct., 2000	6440835
60523566	Nov., 2003
60497672	Aug., 2003
60497425	Aug., 2003

Current U.S. Class: 438/612 ; 257/738

Current International Class: H01L 21/44 (20060101)

Field of Search: 257/690,692,735-738 438/106,118,611-617

References Cited [Referenced By]

U.S. Patent Documents


4442967	April 1984	van de Pas et al.
4661192	April 1987	McShane
4717066	January 1988	Goldenberg et al.
4750666	June 1988	Neugebauer et al.
4807021	February 1989	Okumura
4925083	May 1990	Farassat et al.
4937653	June 1990	Blonder et al.
4955523	September 1990	Calomagno et al.
4970571	November 1990	Yamakawa et al.
4984358	January 1991	Nelson
5014111	May 1991	Tsuda et al.
5060843	October 1991	Yasuzato et al.
5074947	December 1991	Estes et al.
5090119	February 1992	Tsuda et al.
5106461	April 1992	Volfson et al.
5116463	May 1992	Lin et al.
5137845	August 1992	Lochon et al.
5167992	December 1992	Lin et al.
5172851	December 1992	Matsushita et al.
5196371	March 1993	Kulesza et al.
5209817	May 1993	Ahmad et al.
5237130	August 1993	Kulesza et al.
5260234	November 1993	Long
5261593	November 1993	Casson et al.
5275330	January 1994	Issacs et al.
5284796	February 1994	Nakanishi et al.
5293067	March 1994	Thompson et al.
5294038	March 1994	Nakano et al.
5327010	July 1994	Uenaka et al.
5334804	August 1994	Love et al.
5346750	September 1994	Hatakeyama et al.
5355283	October 1994	Marrs et al.
5358621	October 1994	Oyama
5364004	November 1994	Davidson
5397921	March 1995	Karnezos
5407864	April 1995	Kim
5424245	June 1995	Gurtler et al.
5438477	August 1995	Pasch
5439162	August 1995	George et al.
5447886	September 1995	Rai
5454161	October 1995	Beilin et al.
5454928	October 1995	Rogers et al.
5475236	December 1995	Yoshizaki
5477933	December 1995	Nguyen
5478007	December 1995	Marrs
5483421	January 1996	Gedney et al.
5484647	January 1996	Nakatani et al.
5485949	January 1996	Tomura et al.
5487218	January 1996	Bhatt et al.
5489804	February 1996	Pasch
5493096	February 1996	Koh
5508229	April 1996	Baker
5525065	June 1996	Sobhani
5536973	July 1996	Yamaji
5542601	August 1996	Fallon et al.
5547740	August 1996	Higdon et al.
5556810	September 1996	Fujitsu
5556814	September 1996	Inoue et al.
5564181	October 1996	Dineen et al.
5572069	November 1996	Schneider
5576052	November 1996	Arledge et al.
5583073	December 1996	Lin et al.
5595943	January 1997	Itabashi et al.
5599744	February 1997	Koh et al.
5611140	March 1997	Kulesza et al.
5611884	March 1997	Bearinger et al.
5613296	March 1997	Kurino et al.
5614114	March 1997	Owen
5615477	April 1997	Sweitzer
5619791	April 1997	Lambrecht, Jr. et al.
5627405	May 1997	Chillara
5627406	May 1997	Pace
5633204	May 1997	Tago et al.
5637920	June 1997	Loo
5641113	June 1997	Somaki et al.
5645628	July 1997	Endo et al.
5646067	July 1997	Gaul
5648686	July 1997	Hirano et al.
5654584	August 1997	Fujitsu
5656858	August 1997	Kondo et al.
5663598	September 1997	Lake et al.
5665652	September 1997	Shimizu
5666008	September 1997	Tomita et al.
5669545	September 1997	Pham et al.
5674785	October 1997	Akram et al.
5674787	October 1997	Zhao et al.
5682061	October 1997	Khandros et al.
5686353	November 1997	Yagi et al.
5691041	November 1997	Frankeny et al.
5722162	March 1998	Chou et al.
5723369	March 1998	Barber
5731223	March 1998	Padmanabhan
5736456	April 1998	Akram
5739585	April 1998	Akram et al.
5744827	April 1998	Jeong et al.
5744859	April 1998	Ouchida
5757071	May 1998	Bhansali
5757081	May 1998	Chang et al.
5764486	June 1998	Pendse
5774340	June 1998	Chang et al.
5789271	August 1998	Akram
5798285	August 1998	Bentlage et al.
5801072	September 1998	Barber
5801447	September 1998	Hirano et al.
5803340	September 1998	Yeh et al.
5804771	September 1998	McMahon et al.
5808360	September 1998	Akram
5811879	September 1998	Akram
5813115	September 1998	Misawa et al.
5817541	October 1998	Averkiou et al.
5822856	October 1998	Bhatt et al.
5834844	November 1998	Akagawa et al.
5854507	December 1998	Miremadi et al.
5861666	January 1999	Bellaar
5863816	January 1999	Cho
5870289	February 1999	Tokuda et al.
5883435	March 1999	Geffken et al.
5925931	July 1999	Yamamoto
5973393	October 1999	Chia et al.
5994222	November 1999	Smith et al.
6001671	December 1999	Fjelstad
6012224	January 2000	DiStefano et al.
6013877	January 2000	Degani et al.
6017812	January 2000	Yonezawa et al.
6018196	January 2000	Noddin
6020561	February 2000	Ishida et al.
6025650	February 2000	Tsuji et al.
6037665	March 2000	Miyazaki
6046909	April 2000	Joy
6072233	June 2000	Corisis et al.
6084297	July 2000	Brooks et al.
6084781	July 2000	Klein
6088236	July 2000	Tomura et al.
6103552	August 2000	Lin
6103992	August 2000	Noddin
6127204	October 2000	Isaacs et al.
6137164	October 2000	Yew et al.
6159770	December 2000	Tetaka et al.
6180881	January 2001	Isaak
6188127	February 2001	Senba et al.
6218728	April 2001	Kimura
6281568	August 2001	Glenn et al.
6303997	October 2001	Lee
6483718	November 2002	Hashimoto
6504241	January 2003	Yanagida
6608371	August 2003	Kurashima et al.
6630371	October 2003	Hembree

Foreign Patent Documents


0 718 882	Jun., 1996	EP
WO 97/38563	Oct., 1997	WO
WO 99/57762	Nov., 1999	WO

Other References

Markstein et al., "Controlling the Variables in Stencil Printing," Electronic Packaging & Production, Feb. 1997, pp. 48-56. cited by other .
Elenius, "Choosing a Flip Chip Bumping Supplier--Technology an IC Package contractor should look for," Advanced Packaging, Mar./Apr. 1998, pp. 70-73. cited by other .
Erickson, "Wafer Bumping: The Missing Link for DCA," Electronic Packaging & Production, Jul. 1998, pp. 43-46. cited by other .
Kuchenmeister et al., "Film Chip Interconnection Systems Prepared By Wet Chemical Metallization," IEEE publication 0-7803-4526-6/98, Jun. 1998, 5 pages. cited by other .
Ghaffarian, "Long Time BGA Assembly Reliability," Advancing Microelectronics, vol. 25, No. 6, Sep./Oct. 1998, pp. 20-23. cited by oth- er .
U.S. Appl. No. 09/465,024, filed Dec. 16, 1999, entitled "Bumpless Flip Chip Assembly With Solder Via". cited by other .
U.S. Appl. No. 09/464,562, filed Dec. 16, 1999, entitled "Bumpless Flip Chip Assembly With Strips And Via-Fill". cited by other .
U.S. Appl. No. 09/464,561, filed Dec. 16, 1999, entitled "Bumpless Flip Chip Assembly With Strips-In-Via And Plating". cited by other .
U.S. Appl. No. 09/120,408, filed Jul. 22, 1998, entitled "Flip Chip Assembly With Via Interconnection". cited by other .
U.S. Appl. No. 09/643,212, filed Aug. 22, 2000, entitled "Semiconductor Chip Assembly With Simultaneously Electroplated Contact Terminal and Connection Joint". cited by other .
U.S. Appl. No. 09/643,214, filed Aug. 22, 2000, entitled "Semiconductor Chip Assembly with Simultaneously Electrolessly Plated Contact Terminal and Connection Joint". cited by other .
U.S. Appl. No. 09/643,213, filed Aug. 22, 2000, entitled "Method Of Making A Support Circuit For A Semiconductor Chip Assembly". cited by other .
U.S. Appl. No. 09/643,445, filed Aug. 22, 2000, entitled "Method Of Making A Semiconductor Chip Assembly". cited by other .
U.S. Appl. No. 09/665,928, filed Sep. 20, 2000, entitled "Semiconductor Chip Assembly With Ball Bond Connection Joint". cited by other .
U.S. Appl. No. 09/665,931, filed Sep. 20, 2000, entitled "Method Of Making A Support Circuit With A Tapered Through-Hole For A Semiconductor Chip Assembly". cited by other .
U.S. Appl. No. 09/677,207, filed Oct. 2, 2000, entitled "Method Of Making A Semiconductor Chip Assembly With A Conductive Trace Subtractively Formed Before And After Chip Attachment". cited by other .
U.S. Appl. No. 09/865,367, filed May 24, 2001, entitled "Semiconductor Chip Assembly With Simultaneously Electroplated Contact Terminal and Connection Joint". cited by other .
U.S. Appl. No. 09/864,555, filed May 24, 2001, entitled "Semiconductor Chip Assembly with Simultaneously Electrolessly Plated Contact Terminal and Connection Joint". cited by other .
U.S. Appl. No. 09/864,773, filed May 24, 2001, entitled "Semiconductor Chip Assembly With Ball Bond Connection Joint". cited by other .
U.S. Appl. No. 10/714,794, filed Nov. 17, 2003, entitled "Semiconductor Chip Assembly With Embedded Metal Pillar". cited by other.

Primary Examiner: Nelms; David
Assistant Examiner: Lee; Calvin
Attorney, Agent or Firm: Sigmond; David M.

Parent Case Text

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No. 10/994,604 filed Nov. 22, 2004, which is a continuation-in-part of U.S. application Ser. No. 10/922,280 filed Aug. 19, 2004, which is a continuation-in-part of U.S. application Ser. No. 10/307,218 filed Nov. 29, 2002, and issued as U.S. Pat. No. 6,809,414 which is a divisional of U.S. application Ser. No. 09/997,973 filed Nov. 29, 2001, and issued as U.S. Pat. No. 6,492,252 which is a continuation-in-part of U.S. application Ser. No. 09/917,339 filed Jul. 27, 2001, U.S. Pat. No. 6,537,851 which is a continuation-in-part of U.S. application Ser. No. 09/878,626 filed Jun. 11, 2001, and issued as U.S. Pat. No. 6,653,217 which is a continuation-in-part of U.S. application Ser. No. 09/687,619 filed Oct. 13, 2000, and issued as U.S. Pat. No. 6,440,835 each of which is incorporated by reference.

U.S. application Ser. No. 10/994,604 filed Nov. 22, 2004 also claims the benefit of U.S. Provisional Application Ser. No. 60/523,566 filed Nov. 20, 2003, which is incorporated by reference.

U.S. application Ser. No. 10/922,280 filed Aug. 19, 2004 also claims the benefit of U.S. Provisional Application Ser. No. 60/497,672 filed Aug. 25, 2003, and U.S. Provisional Application Ser. No. 60/497,425 filed Aug. 22, 2003, each of which is incorporated by reference.

Claims

We claim:

1. A method of making a semiconductor chip assembly, comprising: providing a metal base, a routing line and a bumped terminal, wherein the routing line and the bumped terminal are contiguous with one another and contact the metal base, the routing line is disposed outside a recess in the metal base, and the bumped terminal extends into the recess and includes a cavity that extends into and faces away from the recess; then mechanically attaching a semiconductor chip to the metal base, the routing line and the bumped terminal, wherein the chip includes first and second opposing surfaces, and the first surface of the chip includes a conductive pad; forming a connection joint that electrically connects the routing line and the pad; forming an encapsulant after attaching the chip to the metal base, the routing line and the bumped terminal, wherein the encapsulant includes a first surface that faces in a first direction and a second surface that faces in a second direction opposite the first direction, the encapsulant covers the chip and extends vertically beyond the chip, the metal base, the routing line and the bumped terminal in the first direction, the chip is embedded in the encapsulant, the metal base extends vertically beyond the chip, the routing line and the bumped terminal in the second direction, the bumped terminal extends vertically beyond the routing line in the second direction and the cavity faces in the first direction; and etching the metal base after forming the encapsulant, thereby reducing contact area between the metal base and the routing line and forming a metal pillar from an unetched portion of the metal base that contacts the bumped terminal and extends vertically beyond the chip, the routing line, the bumped terminal and the encapsulant in the second direction.

2. The method of claim 1, wherein forming the routing line and the bumped terminal includes selectively depositing the routing line and the bumped terminal on the metal base.

3. The method of claim 2, wherein forming the routing line and the bumped terminal includes: forming a plating mask on the metal base, wherein the plating mask includes an opening that exposes a portion of the metal base; and then electroplating the routing line and the bumped terminal on the exposed portion of the metal base through the opening in the plating mask.

4. The method of claim 2, wherein forming the routing line and the bumped terminal includes the following steps in the sequence set forth: forming an etch mask on the metal base; etching the metal base using the etch mask to selectively expose the metal base, thereby forming the recess in the metal base; removing the etch mask; forming a plating mask on the metal base; electroplating the routing line and the bumped terminal on the metal base using the plating mask to selectively expose the metal base; and removing the plating mask.

5. The method of claim 1, wherein forming the routing line, the bumped terminal and the metal pillar includes selectively depositing the routing line, the bumped terminal and an etch mask on the metal base, and then etching the metal base using the etch mask to define the metal pillar.

6. The method of claim 5, wherein forming the routing line, the bumped terminal and the metal pillar includes: formng first and second plating masks on the metal base, wherein the first plating mask includes a first opening that exposes a first portion of the metal base and the second plating mask includes a second opening that exposes a second portion of the metal base; and then electroplating the routing line and the bumped terminal on the first exposed portion of the metal base through the first opening in the first plating mask and the etch mask on the second exposed portion of the metal base through the second opening in the second plating mask.

7. The method of claim 1, wherein forming the routing line, the bumped terminal and the metal pillar includes the following steps in the sequence set forth: forming a first etch mask on the metal base; etching the metal base using the first etch mask to selectively expose the metal base, thereby forming the recess in the metal base; removing the first etch mask; forming first and second plating masks on the metal base; electroplating the routing line, the bumped terminal and a second etch mask on the metal base using the plating masks to selectively expose the metal base; removing the plating masks; etching the metal base using the second etch mask to define the metal pillar; and removing the second etch mask.

8. The method of claim 1, wherein attaching the chip to the metal base, the routing line and the bumped terminal includes disposing an insulative adhesive between the chip and the metal base and then hardening the adhesive.

9. The method of claim 8, wherein the adhesive extends into the cavity.

10. The method of claim 8, wherein the adhesive fills the cavity.

11. The method of claim 8, wherein the adhesive is spaced from the cavity.

12. The method of claim 1, wherein forming the encapsulant includes transfer molding the encapsulant.

13. The method of claim 1, wherein forming the encapsulant includes curing the encapsulant.

14. The method of claim 1, wherein forming the connection joint includes electroplating the connection joint between the routing line and the pad.

15. The method of claim 1, wherein forming the connection joint includes electrolessly plating the connection joint between the routing line and the pad.

16. The method of claim 1, wherein forming the connection joint includes depositing a non-solidified material between the routing line and the pad and then hardening the non-solidified material.

17. The method of claim 1, wherein forming the connection joint includes providing a wire bond between the routing line and the pad.

18. The method of claim 1, wherein etching the metal base exposes the routing line.

19. The method of claim 1, wherein etching the metal base exposes the routing line and the bumped terminal.

20. The method of claim 1, wherein etching the metal base exposes the routing line without exposing the bumped terminal.

21. The method of claim 1, wherein etching the metal base removes most of the metal base.

22. The method of claim 1, wherein etching the metal base removes all of the metal base within a periphery of the pad.

23. The method of claim 1, wherein etching the metal base removes all of the metal base within a periphery of the chip.

24. The method of claim 1, wherein etching the metal base electrically isolates the routing line from other routing lines formed on the metal base.

25. The method of claim 1, wherein etching the metal base electrically isolates the pad from other conductive pads of the chip.

26. The method of claim 1, including attaching the chip to the metal base, the routing line and the bumped terminal and then forming the connection joint.

27. The method of claim 1, including forming the connection joint and then forming the encapsulant.

28. The method of claim 1, including forming the connection joint and then forming the metal pillar.

29. The method of claim 1, including forming the encapsulant, then forming connection joint and then forming the metal pillar.

30. The method of claim 1, including forming the encapsulant, then forming the metal pillar and then forming the connection joint.

31. The method of claim 1, including forming an insulative base that covers and extends vertically beyond the chip, the routing line and the encapsulant in the second direction.

32. The method of claim 31, wherein forming the insulative base includes depositing the insulative base such that the insulative base covers the metal pillar in the second direction and the metal pillar is not exposed, and after forming the insulative base, removing a portion of the insulative base thereby exposing the metal pillar.

33. The method of claim 32, wherein removing the portion of the insulative base includes applying a laser that ablates the insulative base.

34. The method of claim 32, wherein removing the portion of the insulative base includes applying a plasma that etches the insulative base.

35. The method of claim 32, wherein removing the portion of the insulative base includes grinding the insulative base.

36. The method of claim 32, wherein removing the portion of the insulative base includes grinding the insulative base without grinding the metal pillar, and then grinding the insulative base and the metal pillar.

37. The method of claim 32, wherein removing the portion of the insulative base includes grinding the insulative base without grinding the metal pillar, then grinding the insulative base and the metal pillar, and then applying a plasma that etches the insulative base.

38. The method of claim 32, wherein removing the portion of the insulative base laterally aligns the metal pillar and the insulative base at a surface that faces in the second direction.

39. The method of claim 32, including electrolessly plating a plated terminal on the metal pillar after removing the portion of the insulative base, wherein the plated terminal contacts the metal pillar and is spaced from the routing line, the bumped terminal and the connection joint and extends vertically beyond the chip, the routing line, the bumped terminal, the metal pillar, the connection joint, the encapsulant and the insulative base in the second direction.

40. The method of claim 31, wherein forming the insulative base includes depositing the insulative base such that the insulative base does not cover the metal pillar in the second direction and the metal pillar is exposed.

41. A method of making a semiconductor chip assembly, comprising: providing a metal base; then forming a recess in the metal base; then forming a routing line and a bumped terminal on the metal base, wherein the routing line and the bumped terminal are contiguous with one another and contact the metal base, the routing line is disposed outside the recess, and the bumped terminal extends into the recess and includes a cavity that extends into and faces away from the recess; then mechanically attaching a semiconductor chip to the metal base, the routing line and the bumped terminal, wherein the chip includes first and second opposing surfaces, and the first surface of the chip includes a conductive pad; forming a connection joint that electrically connects the routing line and the pad; forming an encapsulant after attaching the chip to the metal base, the routing line and the bumped terminal, wherein the encapsulant includes a first surface that faces in a first direction and a second surface that faces in a second direction opposite the first direction, the encapsulant covers the chip and extends vertically beyond the chip, the metal base, the routing line and the bumped terminal in the first direction, the chip is embedded in the encapsulant, the metal base extends vertically beyond the chip, the routing line and the bumped terminal in the second direction, the bumped terminal extends vertically beyond the routing line in the second direction and the cavity faces in the first direction; and etching the metal base after forming the encapsulant, thereby reducing contact area between the metal base and the routing line and form