Method of manufacturing a flash memory cell Number:6,759,296 from the United States Patent and Trademark Office (PTO) owispatent The present invention relates to a method of manufacturing a flash memory cell. The method includes forming a stack gate in which a floating gate and a control gate are stacked at a given region of a semiconductor substrate, and performing a rapid thermal nitrification process to form a nitride film at the side of the stack gate and over the semiconductor substrate. Therefore, the present invention can improve a retention characteristic and can prevent movement of threshold voltage control ions.<H manufacturing, memory, Method, of, manuf, 6759296.html, Patent, pto, 6759296

Title: Method of manufacturing a flash memory cell

Abstract: The present invention relates to a method of manufacturing a flash memory cell. The method includes forming a stack gate in which a floating gate and a control gate are stacked at a given region of a semiconductor substrate, and performing a rapid thermal nitrification process to form a nitride film at the side of the stack gate and over the semiconductor substrate. Therefore, the present invention can improve a retention characteristic and can prevent movement of threshold voltage control ions.

Patent Number: 6,759,296 Issued on 07/06/2004 to Kwak, et al.

Inventors: Kwak; Noh Yeal (Ichon-Shi, KR), Park; Sang Wook (Seoul, KR)
Assignee: Hynix Semiconductor Inc. (Ichon-shi, KR)

Appl. No.: 10/286,983

Filed: November 4, 2002

Foreign Application Priority Data


Dec 22, 2001 [KR]			2001-83500

Current U.S. Class: 438/257 ; 257/E21.209; 257/E21.268; 257/E21.279; 257/E21.282; 257/E21.293; 257/E21.422; 257/E21.576; 438/775

Current International Class: H01L 21/28 (20060101); H01L 21/70 (20060101); H01L 21/02 (20060101); H01L 21/336 (20060101); H01L 21/316 (20060101); H01L 21/318 (20060101); H01L 21/314 (20060101); H01L 21/768 (20060101)

Field of Search: 438/201,257,238,786,769,775

References Cited [Referenced By]

U.S. Patent Documents


5460992	October 1995	Hasegawa
2003/0003656	January 2003	Dong et al.

Foreign Patent Documents


2001-61403	Jul., 2001	KR

Primary Examiner: Le; Dung A.
Attorney, Agent or Firm: Jacobson Holman PLLC

Claims

What is claimed is:

1. A method of manufacturing a flash memory cell, comprising the steps of: stacking a tunnel oxide film, a first polysilicon film, a dielectric film, a second polysilicon film and a tungsten suicide film at a given region of a semiconductor substrate to form a stack gate in which a floating gate and a control gate are stacked; forming a nitride film at the side of said stack gate and on said semiconductor substrate by means of a rapid thermal nitrification process; and forming a junction region at a second given region of said semiconductor substrate by means of an impurity ion implantation process; said stacking step being performed prior to performing the step of forming the nitride film; and said step of step of forming the nitride film being performed urior to the step of forming the junction region.

2. The method as claimed in claim 1, wherein said tunnel oxide film is formed by performing a wet oxidization process at a temperature ranging from 750 to 800.degree. C. and then an annealing process using nitrogen at a temperature ranging from 900 to 910.degree. C. for 20.about.30 minutes.

3. The method as claimed in claim 1, wherein said first polysilicon film is formed using SiH.sub.4 gas and PH.sub.3 gas or Si.sub.2 H.sub.6 gas and PH.sub.3 gas at a temperature ranging from 500 to 620.degree. C. at a pressure of 0.1.about.1 Torr.

4. The method as claimed in claim 1, wherein said first polysilicon film is formed so that the concentration of phosphorous is 1.0E20.about.3.0E20 atoms/cc.

5. The method as claimed in claim 1, wherein said dielectric film is formed by stacking a lower oxide film, a nitride film and an upper oxide film.

6. The method as claimed in claim 5, wherein said lower oxide film is formed by a LPCVD method using DCS (SiH.sub.2 Cl.sub.2) gas and N.sub.2 O gas or DCS gas and NO gas as a source gas at a temperature ranging from 810 to 850.degree. C. at a pressure of 1.about.3 Torr.

7. The method as claimed in claim 5, wherein sad nitride film is formed by a LPCVD method using Si.sub.3 N.sub.4 gas and N.sub.2 O gas or Si.sub.3 N.sub.4 gas and NO gas as a source gas at a temperature ranging from 810 to 850.degree. C. at a pressure of 1.about.3 Torr.

8. The method as claimed in claim 5, wherein said upper oxide film is formed by a LPCVD method using DCS (SiH.sub.2 Cl.sub.2) gas and N.sub.2 O gas or DCS gas and NO gas as a source gas at a temperature ranging from 810 to 850.degree. C. at a pressure of 1.about.3 Torr.

9. The method as claimed in claim 1, wherein said second polysilicon film is formed by a LPCVD method using SiH.sub.4 gas or Si.sub.2 H.sub.6 and PH.sub.2 gas at a temperature ranging from 530 to 550.degree. C. at a pressure of below 1 Torr.

10. The method as claimed in claim 1, wherein said rapid thermal nitrification process is performed at a temperature ranging from 900 to 1000.degree. C. at a pressure of 1.about.5 Torr.

11. The method as claimed in claim 1, wherein said rapid thermal nitrification process is performed using a spike anneal of 100.about.150.degree. C./sec.

12. The method as claimed in claim 1, wherein said nitride film is formed in thickness of below 50 .ANG..

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates generally to a method of manufacturing a flash memory cell. More particularly, the invention relates to a method of manufacturing a flash memory cell capable of improving a retention characteristic and preventing movement of threshold voltage control ions, in a way that a stack gate in which a floating gate and a control gate are stacked is formed at a given region of a semiconductor substrate, and a rapid thermal nitrification process is then performed to form a nitride film at the side of the stack gate and over the semiconductor substrate.

2. Description of the Prior Art

In a flash memory device having a gate structure in which a floating gate and a control gate are isolated by a dielectric film, electric charges are stored at the floating gate using a hot carrier injection. The floating gate formed of a polysilicon film, however, has a retention fail problem by which the stored charges could not be retained due to variation in a wide range of temperature and the operating voltage.

The retention fail problem is usually generated by defective oxide film. The defective oxide film is mainly generated by the leakage of electrons due to reduction in the height of an interface barrier. Also, the leakage of the electrons is mainly generated by etching damage of an ONO film used as a dielectric film after the etch process for forming an electrode. In order to overcome this etch damage, an oxidization process using a high temperature thermal process is implemented. In addition, an ion implantation process for forming a junction region is implemented after the oxidization process.

However, during the ion implantation process, the quality of a gate oxide film is degraded by charged dopant since ions are implanted into the oxide film formed on the entire surfaces of the electrode. Further, as the junction region is increased by the oxidization process, the program speed and cell current are reduced in a flash memory device in which a program is performed through injection of large amount of hot carriers.

SUMMARY OF THE INVENTION

The present invention is contrived to solve the above problems and an object of the present invention is to provide a method of manufacturing a flash memory cell capable of improving a retention characteristic.

Another object of the present invention is to provide a method of manufacturing a flash memory cell by which the program speed and the cell current are not reduced.

Still another object of the present invention is to provide a method of manufacturing a flash memory cell in which the threshold voltage is not varied by preventing movement of threshold voltage control ions.

According to the present invention, in order to solve a problem that the quality of a dielectric film having a lower oxide film, a nitride film and an upper oxide film is degraded due to etching damage when an etch process for forming an electrode, a nitride film is formed by a rapid thermal nitrification process. Further, in order to solve a problem that the quality of the gate electrode is degraded due to implantation of an impurity ion into an oxide film that is formed around a gate electrode by a common oxidization process during an ion implantation process for forming a junction region, a thinly formed nitride film is used as a barrier layer.

In order to accomplish the above object, a method of manufacturing a flash memory cell according to the present invention, is characterized in that it comprises the steps of stacking a tunnel oxide film, a first polysilicon film, a dielectric film, a second polysilicon film and a tungsten silicide film at a given regions of a semiconductor substrate to form a stack gate in which a floating gate and a control gate are stacked; forming a nitride film at the side of the stack gate and on the semiconductor substrate by means of a rapid thermal nitrification process; and forming a junction region at a given region of the semiconductor substrate by means of an impurity ion implantation process.

BRIEF DESCRIPTION OF THE DRAWINGS

The aforementioned aspects and other features of the present invention will be explained in the following description, taken in conjunction with the accompanying drawings, wherein:

FIG. 1A.about.FIG. 1C are cross-sectional views of semiconductor devices explaining a method of manufacturing a flash memory cell according to the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The present invention will be described in detail by way of a preferred embodiment with reference to accompanying drawings.

FIG. 1A.about.FIG. 1C are cross-sectional views of semiconductor devices for explaining a method of manufacturing a flash memory cell according to the present invention.

Referring now to FIG. 1A, a device isolation film 12 is formed at a given region of a semiconductor substrate 11 to define an active region and a field region. After an impurity ion implantation process for forming a triple well in the semiconductor substrate 11 is performed, an impurity ion implantation process for controlling the threshold voltage is performed. Next, a tunnel oxide film 13 and a first polysilicon film 14 are sequentially formed on the entire structure. The first polysilicon film 14 and the tunnel oxide film 13 are then patterned by lithography process using the floating gate mask and etching process. After a dielectric film 15 is formed on the entire structure, a second polysilicon film 16 and a tungsten silicide film 17 are sequentially formed on the dielectric film 15. Thereafter, the tungsten suicide film 17, the second polysilicon film 16, the dielectric film 15, the first polysilicon film 14 and the tunnel oxide film 13 are patterned by lithography process using the control gate mask and etching process. Thereby, a stack gate in which the floating gate and the control gate are stacked is completed.

In the above, the tunnel oxide film 13 is formed by performing a wet oxidization process at a temperature ranging from 750 to 800.degree. C. and then an annealing process using nitrogen N.sub.2 at a temperature ranging from 900 to 910.degree. C. for 20.about.30 minutes. Further, the first polysilicon film 14 is formed using SiH.sub.4 gas and PH.sub.3 gas or Si.sub.2 H.sub.6 gas and PH.sub.3 gas at a temperature ranging from about 500 to 620.degree. C. at a pressure of 0.1.about.1 Torr. At this time, the concentration of phosphorous P is about 1.0E20.about.3.0E20 atoms/cc.

Further, the dielectric film 15 has an ONO structure in which a lower oxide film, a nitride film and an upper oxide film are stacked. At this time, the lower oxide film and the upper oxide film are deposited by a LPCVD method using DCS(SiH.sub.2 Cl.sub.2) gas and N.sub.2 O gas or DCS gas and NO gas as a source gas at a temperature ranging from 810 to 850.degree. C. at a pressure of 1.about.3 Torr. Also, the nitride film is deposited by a LPCVD method using Si.sub.3 N.sub.4 gas and N.sub.2 O gas or Si.sub.3 N.sub.4 gas and NO gas as a source gas at a temperature ranging from 810 to 850.degree. C. at a pressure of 1.about.3 Torr.

Meanwhile, the second polysilicon film 16 is deposited by a LPCVD method using silicon source gas such as SiH.sub.4, Si.sub.2 H.sub.6, etc. and PH.sub.2 gas at a temperature ranging from 530 to 550.degree. C. at a pressure of below 1 Torr.

Referring now to FIG. 1B, a rapid thermal nitrification process is performed to form a nitride film 18 at the side of the stack gate and on the semiconductor substrate 11. At this time, the nitride film 18 is not formed at and/or on the tungsten suicide film 17. The rapid thermal nitrification process is performed by flowing large amount of nitrogen so that the mean free pass can be minimized in order to minimize damage of the side of polysilicon due to nitrogen source at a temperature ranging from 900 to 1000.degree. C. at a pressure of 5.about.10 Torr. Meanwhile, the rapid thermal nitrification process is performed using a spike anneal of 100.about.150.degree. C./sec in order to minimize a thermal effect against a raised temperature ratio. At this time, it is preferred that the thickness of the nitride film is below 50 .ANG..

Referring now to FIG. 1C, an impurity ion implantation process is performed to form a junction region 19 at a given region of the semiconductor substrate 11. At this time, the impurity ion implantation process for forming the junction region 19 is performed using arsenic As or phosphorous P. Also, as a deep junction is required in order to obtain large amount of cell current, the ion implantation energy of 20.about.50 KeV is used in case of As and the ion implantation energy of 15.about.40 KeV is used in case of P. Further, an impurity ion of 1E14.about.1E16 is injected. At this time, the impurity ion implantation is performed with a slant of 0.degree. in order to prevent damage due to ion implantation of the side of the polysilicon film.

As mentioned above, according to the present invention, etch damage that is caused during an etch process for forming a gate electrode can be minimized by performing a rapid thermal nitrification process. A problem, that the ion for controlling the threshold voltage is changed by a heat generated in a subsequent thermal process such as a furnace thermal process for a long time, can be prevented by performing a rapid thermal nitrification process.

Further, according to the present invention, a nitride film at the side of a gate electrode and on a semiconductor substrate is formed by a rapid thermal nitrification process. Therefore, degradation in the quality of an oxide film at the side of polysilicon that is generated between upper and lower oxide films and re-oxide film constituting an existing dielectric film when an impurity ion implantation process is performed, can be prevented to improve a retention characteristic.

Meanwhile, according to the present invention, a thin nitride film used as a barrier layer is formed. Therefore, degradation of the quality of a gate electrode that is generated by implanting ions into the oxide film around the gate electrode by means of a common oxidization process when an impurity ion implantation process for forming a junction region is performed, can be prevented. In addition, the process time can be reduced by the rapid thermal nitrification process.

The present invention has been described with reference to a particular embodiment in connection with a particular application. Those having ordinary skill in the art and access to the teachings of the present invention will recognize additional modifications and applications within the scope thereof.

It is therefore intended by the appended claims to cover any and all such applications, modifications, and embodiments within the scope of the present invention.

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