Method of manufacturing a semiconductor device with self-aligned contacts Number:7,151,025 from the United States Patent and Trademark Office (PTO) owispatent A method of manufacturing a semiconductor device on a semiconductor substrate having a first region and a second region. This method beings by forming a transistor in the first region of said semiconductor substrate. This transistor includes a pair of impurity diffusion regions and a gate electrode. Then forming a first insulating film over the first and second regions with this first insulating film covering the transistor in the first region. Thereafter, patterning the first insulating film to selectively remove the first insulating film in the second region. Then forming a second insulating film over the first and second regions. Thereafter, forming at least one contact hole through the second and first insulating film. The contact hole reaches one of the impurity diffusion regions. Finally, forming a conductive layer in the contact hole.<H semiconductor, manufacturing, Method, of, manuf, 7151025.html, Patent, pto, 7151025

Title: Method of manufacturing a semiconductor device with self-aligned contacts

Abstract: A method of manufacturing a semiconductor device on a semiconductor substrate having a first region and a second region. This method beings by forming a transistor in the first region of said semiconductor substrate. This transistor includes a pair of impurity diffusion regions and a gate electrode. Then forming a first insulating film over the first and second regions with this first insulating film covering the transistor in the first region. Thereafter, patterning the first insulating film to selectively remove the first insulating film in the second region. Then forming a second insulating film over the first and second regions. Thereafter, forming at least one contact hole through the second and first insulating film. The contact hole reaches one of the impurity diffusion regions. Finally, forming a conductive layer in the contact hole.

Patent Number: 7,151,025 Issued on 12/19/2006 to Itabashi, et al.

Inventors: Itabashi; Kazuo (Kawasaki, JP), Tsuboi; Osamu (Kawasaki, JP), Yokoyama; Yuji (Kawasaki, JP), Inoue; Kenichi (Kawasaki, JP), Hashimoto; Koichi (Kawasaki, JP), Futo; Wataru (Kawasaki, JP)
Assignee: Fujitsu Limited (Kawasaki, JP)

Appl. No.: 10/388,447

Filed: March 17, 2003

Related U.S. Patent Documents


Application Number	Filing Date	Patent Number	Issue Date
09638139	Aug., 2000	6620674
08890991	Jul., 1997	6285045

Foreign Application Priority Data


Jul 10, 1996 [JP]			8-181057

Current U.S. Class: 438/253 ; 438/396; 438/637; 438/672

Current International Class: H01L 21/8242 (20060101)

Field of Search: 438/253,396

References Cited [Referenced By]

U.S. Patent Documents


4443932	April 1984	Mastrolanni et al.
4832789	May 1989	Cochran et al.
4958318	September 1990	Harai
5185282	February 1993	Lee et al.
5449634	September 1995	Inoue
5753551	May 1998	Sung
5818110	October 1998	Cronin
5835337	November 1998	Watanabe et al.
6251726	June 2001	Huang

Foreign Patent Documents


2-260453	Oct., 1990	JP
6-37272	Feb., 1994	JP
06-236972	Aug., 1994	JP
7-74275	Mar., 1995	JP
8-46173	Feb., 1996	JP
8-97378	Apr., 1996	JP
08-125138	May., 1996	JP
8-125138	May., 1996	JP
8-125141	May., 1996	JP
08-125141	May., 1996	JP

Other References

Japanese Office Action dated Dec. 20, 2005. cited by other .
Korean Office Action dated Jul. 30, 2001. cited by other.

Primary Examiner: Le; Dung A.
Attorney, Agent or Firm: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

Parent Case Text

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Divisional of Ser. No. 09/638,139 filed Aug. 15, 2000, now U.S. Pat. No. 6,620,674 which is a Divisional of Ser. No. 08/890,991 filed Jul. 10, 1997, now U.S. Pat. No. 6,285,045.

Claims

What is claimed is:

1. A method of manufacturing a semiconductor device on a semiconductor substrate having a first region and a second region, comprising the steps of: forming a transistor in said first region of said semiconductor substrate, said transistor including a pair of impurity diffusion regions and a gate electrode; forming a first insulating film over said first and second regions, said first insulating film covering said transistor in the first region; patterning said first insulating film to selectively remove said first insulating film in said second region; forming a second insulating film over said first and second regions; forming at least one contact hole through said second and first insulating film, said contact hole reaching one of said impurity diffusion regions; and forming a conductive layer in said contact hole, wherein said first region is a memory cell region, said second region is a peripheral circuit region, and said first insulating film is a silicon nitride film in which said silicon nitride film covers said memory cell region, but is removed in said peripheral circuit region.

2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of planarizing said second insulating film after forming said second insulating film.

3. The method of manufacturing a semiconductor device according to claim 1, wherein said second insulating film is an oxide film.

4. The method of manufacturing a semiconductor device according to claim 2, wherein said second insulating film is an oxide film.

5. A method of manufacturing a semiconductor device on a semiconductor substrate having a first region and a second region, comprising the steps of: forming a transistor in said first region of said semiconductor substrate, said transistor including a pair of impurity diffusion regions and a gate electrode; forming a first insulating film over said first and second regions, said first insulating film covering said transistor in the first region; patterning said first insulating film to selectively remove said first insulating film in said second region; forming a second insulating film over said first and second regions; forming at least one contact hold through said second and first insulating films, said contact holes reaching one of said impurity diffusion regions; embedding a conductive layer in said contact hole to form a conductive plug; forming a third insulating film over said second insulating film covering said conductive plug; and patterning said third insulating film, and forming a wiring layer electrically connected to said conductive plug.

6. The method of manufacturing a semiconductor device according to claim 5, further comprising the step of planarizing said second insulating film after forming said second insulating film.

7. The method of manufacturing a semiconductor device according to claim 5, wherein said second insulating film is an oxide film.

8. The method of manufacturing a semiconductor device according to claim 6, wherein said second insulating film is an oxide film.

9. A method of manufacturing a semiconductor device on a semiconductor substrate having a first region and a second region, comprising the steps of: forming a transistor in said first region of said semiconductor substrate, said transistor including a pair of impurity diffusion regions and a gate electrode; forming a first insulating film over said first and second regions, said first insulating film covering said transistor in the first region; patterning said first insulating film to selectively remove said first insulating film in said second region; forming a second insulating film over said first and second regions; forming at least one contact hole through said second and first insulating films, said contact hole reaching one of said impurity diffusion regions; embedding a conductive layer in said contact hole to form a conductive plug; forming a third insulating film over said second insulating film covering said conductive plug; patterning said third insulating film and forming a wiring layer electrically connected to said conductive plug; and etching said third and second insulating films in said second region and forming another wiring layer electrically connected to said semiconductor substrate in said second region.

10. The method of manufacturing a semiconductor device according to claim 9, further comprising the step of planarizing said second insulating film after forming said second insulating film.

11. The method of manufacturing a semiconductor device according to claim 9, wherein said second insulating film is an oxide film.

12. The method of manufacturing a semiconductor device according to claim 10, wherein said second insulating film is an oxide film.

Description

BACKGROUND OF THE INVENTION

a) Field of the Invention

The present invention relates to a semiconductor device and its manufacture, and more particularly to a semiconductor device and its manufacture suitable for highly integrated and reliable DRAMs (Dynamic Random Access Memories).

b) Description of the Related Art

It is essential to make a fundamental constituent, a memory cell of DRAM, more and more smaller or finer in order to realize high integration and low cost. A general DRAM cell is constituted of one MOS transistor and one capacitor.

In order to make a memory cell finer, it is therefore substantial that how a large capacitance is obtained from a small cell size.

As a method of procuring a capacitance of a memory cell, a trench type cell and a stack type cell have recently been proposed and adopted as the cell structure of current DRAMs. A trench type cell has a capacitor formed in a trench in the substrate. A stack type cell has a capacitor three-dimensionally stacked over the MOS transistor. More improved cell structures have also been proposed, particularly for stack type cells, such as a fin type cell and a cylinder type cell. A fin type cell has a plurality of storage electrodes disposed generally in parallel with the substrate and upper and lower surfaces of each storage electrode are used as a capacitor. A cylinder type cell has a cylindrical storage electrode disposed generally vertically to the substrate.

By using these cell structures and their manufacture processes, it becomes possible to realize DRAMs of 64 Mbit class.

However, a voltage applied to the capacitor electrode of a trench type capacitor forms a depletion layer near the trench so that the charge accumulating region broadens greatly. If trenches of adjacent capacitors are formed near to each other, leak of stored charges may occur and stored data may be lost. It is therefore necessary to broaden the width of an isolation area between cells, i.e., the width of a field oxide film area. This hinders high integration.

From this reason, stack type capacitors are promising devices which may contribute to high integration and high reliability of DRAMs.

A fine stack type capacitor is reported in "A 0.29-H.mu.m.sup.2 MIM-CROWN Cell and Process Technologies for 1-Gigabit DRAMs", 1994, pp. 927 929.

A cross sectional view of this memory cell is shown in FIG. 29.

In FIG. 28, reference numeral 100 represents a word line or gate electrode, reference numeral 101 represents a first polysilicon plug, reference numeral 102 represents a bit line, reference numeral 103 represents a second polysilicon plug, reference numeral 104 represents a storage electrode, reference numeral 105 represents a dielectric film, and reference numeral 106 represents an opposing electrode. Highly integrated DRAMs are provided by using cylinder type capacitors.

A height of the storage electrode of a cylinder type capacitor is required to be made greater in order to procure a sufficient capacitance even with a small cell area. Therefore, a height difference or step between a memory cell area and a peripheral circuit area becomes large, which becomes a critical issue. For example, in patterning a metal wiring layer on the memory cell area and peripheral circuit area, a size accuracy is lowered because of an insufficient depth of focus of photolithography to be caused by the step.

Although the step between the memory cell and peripheral circuit areas can be removed by filling the concaved peripheral circuit area with an insulating film, an aspect ratio of a contact hole in the peripheral circuit area becomes large, posing another problem of a difficulty of etching control.

As the distance between wiring patterns becomes short as the device becomes fine, a parasitic capacitance of wiring tends to increase.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a semiconductor device and its manufacture method capable of realizing highly integrated and stable DRAMs, e.g., 256 Mbit or higher, without degrading reliability.

According to one aspect of the present invention, there is provided a semiconductor device having a memory cell area and a peripheral circuit area on a semiconductor substrate, comprising: a transfer transistor in the memory cell area including a pair of impurity diffusion regions formed in the substrate and a gate electrode formed over a surface of the substrate between said pair of impurity diffusion regions; a first insulating film covering the upper and side surfaces of the gate electrode; a second insulating film formed on the substrate covering the first insulating film; a pair of contact holes formed through the second insulating film and reaching the pair of impurity diffusion regions; a conductive plug embedded in one of the contact holes and connected to one of the pair of impurity diffusion regions; a third insulating film formed on the second insulating film covering the conductive plug, and having a first aperture on the other of the pair of contact holes; a bit line formed on the third insulating film and connected to the other of the pair of impurity diffusion regions through the first aperture and the other of the pair of contact holes; a fourth insulating film covering the upper and side surfaces of the bit line; a second aperture formed through the third insulating film in alignment with the fourth insulating film covering the side surface of the bit line; a storage electrode formed to extend over the bit line, insulated from the bit line by the third and fourth insulating films, and electrically connected to the conductive plug through the second aperture; a dielectric film formed on a surface of the storage electrode; and an opposing electrode formed on a surface of the dielectric film.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a memory cell area and a peripheral circuit area on a semiconductor substrate, comprising the steps of: forming a transfer transistor in said memory cell area, the transfer transistor including a pair of impurity diffusion regions formed in the substrate and a gate electrode formed on the substrate between the pair of impurity diffusion regions; forming a first insulating film covering the upper and side surfaces of the gate electrode; forming a second insulating film covering the first insulating film and the transfer transistor; forming a contact hole through the second insulating film, the contact hole reaching one of the impurity diffusion regions; embedding a conductive layer in the contact hole to form a conductive plug for storage electrode contact; forming a third insulating film on the second insulating film covering the conductive plug; forming a bit line on the third insulating film; forming a fourth insulating film covering the upper and side surfaces of the bit line; forming an aperture through the third insulating film on the conductive plug, being aligned with the fourth insulating film; forming a storage electrode electrically connected to the conductive plug; forming a dielectric film on a surface of the storage electrode; and forming an opposing electrode on a surface of the dielectric film.

The plug made of the conductive layer produces a raised structure of the device. Namely, after the word line is formed, the plug for storage electrode contact is formed, the plug being used for the raised structure, and the storage electrode is formed through SAC (self aligned contact) technology between adjacent bit lines. Therefore, the height of the capacitor from the substrate surface can be lowered.

It is possible to reduce a height difference between the memory cell area and peripheral circuit area more than a conventional device structure and to easily form a contact hole in the peripheral circuit area.

The manufacture yield is prevented from being lowered while reducing the number of processes, and this contributes to high integration and high density of semiconductor devices.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are a plan view and a cross sectional view of a semiconductor device according to a first embodiment of the invention.

FIGS. 2A to 2H are cross sectional views illustrating the manufacture processes of a semiconductor device according to the first embodiment of the invention.

FIG. 3 is a plan view corresponding to the cross sectional view of FIG. 2D.

FIGS. 4A to 8B are plan views of a memory cell area and a peripheral circuit area of a semiconductor device according to a second embodiment of the invention, wherein drawings with character A illustrate a memory cell area and drawings with character B illustrate a peripheral circuit area.

FIGS. 9A to 9I are cross sectional views illustrating the manufacturing processes of a semiconductor device according to the second embodiment of the invention.

FIG. 10 is a cross sectional view of a semiconductor device according to a third embodiment of the invention.

FIG. 11 is a cross sectional view of a semiconductor device corresponding to FIG. 9I.

FIG. 12 is a cross sectional view of a semiconductor device according to a fourth embodiment of the invention.

FIG. 13 is a cross sectional view of a semiconductor device according to a fifth embodiment of the invention.

FIG. 14 is a cross sectional view of a semiconductor device according to a sixth embodiment of the invention.

FIG. 15 is a cross sectional view of a semiconductor device according to a seventh embodiment of the invention.

FIGS. 16A to 16I are cross sectional views illustrating the manufacture processes of a semiconductor device according to an eighth embodiment of the invention.

FIGS. 17A and 17B are a plan view of a memory cell area and a cross sectional view of a peripheral circuit area of a semiconductor device according to a ninth embodiment of the invention.

FIGS. 18A to 18L are cross sectional views illustrating the manufacture processes of a semiconductor device according to the ninth embodiment of the invention.

FIGS. 19 and 20 are cross sectional views of a semiconductor device illustrating some problems of the ninth embodiment.

FIGS. 21A to 21D are cross sectional views illustrating the manufacture processes of a semiconductor device according to a tenth embodiment of the invention.

FIG. 22 is a cross sectional view of a semiconductor device according to an eleventh embodiment of the invention.

FIG. 23 is a cross sectional view of a semiconductor device illustrating some problems of the eleventh embodiment.

FIG. 24 is a plan view of a memory cell area of a semiconductor device according to a twelfth embodiment of the invention.

FIGS. 25A and 25B are cross sectional views of a semiconductor device according to the twelfth embodiment of the invention.

FIG. 26 is a cross sectional view of a semiconductor device according to a thirteenth embodiment of the invention.

FIGS. 27A to 27C are cross sectional views of a substrate illustrating a semiconductor device according to a fourteenth embodiment of the invention.

FIG. 28 is a cross sectional view of a semiconductor device according to fifteenth embodiment of the invention.

FIG. 29 is a cross sectional view of a conventional semiconductor device.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the invention will be described with reference to the accompanying drawings.

The first embodiment of the invention is illustrated in FIGS. 1A to 2H.

In these Figures, reference numeral 1 represents a p-type silicon substrate, 2--a field SiO.sub.2 film, 3--a gate oxide film, 4--a silicon layer, 5--a tungsten silicide (WSi) layer, 6--an SiO.sub.2 film, 7--an SiO.sub.2 film , 8--a gate electrode (word line of first wiring layer), 9--an n.sup.-type impurity doped layer, 10--a side wall, 11--an SiO.sub.2 film, 12--an Si.sub.3N.sub.4 film, 13--a borophosphosilicate glass (BPSG) film, 14--an Si.sub.3N.sub.4 film, 15--a contact hole, 16--a conductive plug, 17--an SiO.sub.2 film, 18--a silicon layer, 19--a WSi layer, 20--an SiO.sub.2 layer, 21--an SiO.sub.2 film, 22--a bit line (second wiring layer), 23--a side wall, 24--an SiO.sub.2 film, 25--an Si.sub.3N.sub.4 film, 27--a storage electrode, 29--a Ta.sub.2O.sub.5 film as capacitor dielectric film, 30--a TiN film as a capacitor opposing electrode, 31--a BPSG film as an interlayer insulating film, and N1, P1, and P2 n-, p-, and p-wells. Representation of wells may be omitted in the following.

FIG. 1A is a plan view of a memory cell area of the semiconductor device of this embodiment. In FIG. 1A, a word line 8 is disposed vertically, a bit line 22 is disposed horizontally over the word line, and a capacitor C is disposed over the bit line.

FIG. 1B is a cross sectional view of the memory cell area corresponding to FIG. 1A. The cross sectional view taken along line A A' crosses the word and bit lines, and the cross sectional view taken along line B B' crosses the bit line and is parallel to the word line. For the sake of brevity, the A A' portion and the B B' portion are shown continuously.

FIGS. 2A to 6 are cross sectional views of a semiconductor substrate illustrating a semiconductor device manufacture method of this embodiment. The left side in these drawings corresponds to the memory cell area MC, and the right side corresponds to the peripheral circuit area PC. The memory cell area MC corresponds to the area of FIG. 1B. An n-well N2 is also formed in the peripheral circuit area PC. The memory cell area MC corresponds to the area of FIG. 1B. An n-well N2 is also formed in the peripheral circuit area PC. The semiconductor device manufacture method will be described with reference to these drawings.

As shown in FIG. 2A, on a p-type silicon substrate 1, a field SiO.sub.2 film 2 of 250 nm thick is formed by a well known technique, LOCOS isolation (selective oxidation). Thereafter, an SiO.sub.2 film 3 of 5 to 10 nm thick is formed by thermal oxidation, this film being a gate oxide film.

Next, a silicon layer 4 of 50 nm thick highly doped with n- or p-type impurities, a WSi layer 5 of 120 nm thick, and an SiO.sub.2 film 6 of 80 nm thick are sequentially formed over the whole surface of the substrate by CVD. The doped silicon layer 4 may be single crystal silicon, polysilicon, or amorphous silicon.

Next, an anti-reflection film 7 is formed by plasma CVD. This anti-reflection film 7 absorbs an exposure wavelength used by photolithography and is, for example, an SiON film of about 30 nm thick.

By using a resist mask pattern (not shown), the SiON film 7 and SiO.sub.2 film 6 are selectively etched, for example, by F containing etchant gas and the WSi layer 5 and polysilicon layer 4 are selectively etched, for example, by Cl containing etchant gas, to thereby form a gate electrode 8 which is connected to a word line.

As shown in FIG. 2B, by using the gate electrode 8 as a mask, P (phosphorous) ions are implanted into the silicon substrate 1 to form an n.sup.--type impurity diffusion region 9. The n.sup.--type impurity diffusion region 9 is the source/drain region of a transfer transistor in the memory cell area, and in the peripheral circuit area an LDD diffusion region of an n-channel transistor. Next, an SiO.sub.2 film of 60 nm thick is formed over the whole surface of the substrate by low pressure CVD, and a side wall 10 of SiO.sub.2 is formed by anisotropic etching.

In the peripheral circuit area, arsenic ions are implanted into the n-channel transistor region to form an n.sup.+-type diffusion region 55, and boron ions are implanted into a p-channel transistor region in the n-well N2 to form a p.sup.+-type diffusion region 57.

As shown in FIG. 2C, an SiO.sub.2 film 11 of 20 nm thick and an Si.sub.3N.sub.4 film 12 of 50 to 100 nm thick or preferably 80 nm thick are formed over the whole surface of the substrate by low pressure CVD.

Next, a BPSG film 13 of 300 to 400 nm thick is formed as a planarizing film over the whole surface of the substrate and is reflowed by heat treatment at about 800.degree. C. in a nitrogen atmosphere. For more complete planarization, the surface is preferably polished and planarized by CMP (Chemical Mechanical Polishing).

In place of the BPSG film, a phosphosilicate glass (PSG), spin on glass (SOG), insulating resin, or the like may be used.

The SiO.sub.2 film 11 serves as a stopper film when the Si.sub.3N.sub.4 film 12 is removed. If the Si.sub.3N.sub.4 film 12 is made thick, capacitance of wiring patterns increases because of its higher dielectric constant than SiO.sub.2. It is therefore preferable to make the Si.sub.3N.sub.4 film 12 thin, provided that it has sufficient function as an etching stopper.

As shown in FIG. 2D, an Si.sub.3N.sub.4 film 14 of 50 nm thick is formed by low pressure CVD over the whole surface of the substrate and selectively etched by using a resist mask pattern (not shown). Next, the BPSG film 13 is selectively etched until the Si.sub.3N.sub.4 film 12 is slightly etched, and then the Si.sub.3N.sub.4 film 12 and SiO.sub.2 film 11 are selectively removed. By the selective etching of the Si.sub.3N.sub.4 film 12, a hole is formed under the opening of the Si.sub.3N.sub.4 14, with the SiO.sub.2 film 11 being left on the bottom of the hole. By the selective etching of the SiO.sub.2 film, the substrate surface is exposed. The side wall 10 is hardly etched.

More detailed description will be given on the process in the region between adjacent word lines. In the state of FIG. 2C, the upper surface of the word lines is covered with the oxide film 6 and the SiON film 7. The side surface of the word lines is covered with a side wall (spacer) of silicon oxide. Covering such a word line structure, the oxide film 11 and the nitride film 12 are formed on the whole surface of the substrate. The BPSG film 13 is formed further thereon. Viewing the region between the adjacent word line structures from the above, the BPSG film 13, the nitride film 12 and the oxide film 11 exist in this order in a configuration projecting downwardly. These films can be respectively etched selectively from the above. When the BPSG film 13 is etched anisotropically and selectively using a photoresist mask, etching is stopped in a state where the nitride film 12 is exposed at the bottom surface. Since the nitride film 12 and the oxide film 11 are formed conformal to the side walls of the word line structure and the substrate surface, etching is terminated following the shape of these. When the nitride film 12 is selectively etched next, etching terminates in the state where the oxide film 11 is exposed. In this state, the region between the word line structures is occupied by the etched hole except the oxide film 11. When the thin oxide film 11 is removed, the substrate surface is exposed. The word line structures can be retained almost perfectly without any substantial deformation.

In this manner, contact holes 15 by SAC are formed. Next, a doped silicon layer of 300 nm thick is embedded in the contact holes 15 by low pressure CVD, and removed at the area on the Si.sub.3N.sub.4 film 14 by CMP. A plug 16b is used for bit line connection and a plug 16a is used for storage electrode connection. The plugs 16a and 16b are represented collectively by a plug 16 hereinafter.

The plug 16 may be formed by W, TiN, or the like instead of doped silicon. W or TiN layer may be deposited by CVD.

As shown in FIG. 2E, an SiO.sub.2 film 17 of 20 to 60 nm thick is formed over the whole surface of the substrate by low pressure CVD. It is preferable to form the oxide film of a dense high temperature oxide (HTO) film. Such a film is conformal. Since the underlying surface is planarized, a flat film having a flat surface is formed. This SiO.sub.2 film 17 insulates at necessary areas the plug 16 and the bit line of a second layer wiring. Next, by using a resist mask pattern (not shown), the SiO.sub.2 film 17 is selectively etched to form a contact hole HB of the bit line. In the right side area of the drawing, a contact hole for the plug and upper wiring layer is also formed. Next, a doped silicon layer 18 of 40 nm thick, a WSi layer 19 of 120 nm thick, and an SiO.sub.2 film 20 of 120 nm thick are sequentially formed over the whole surface of the substrate by low pressure CVD, and then an SiON film 21 as an anti-reflection film is formed on the SiO.sub.2 film 20 by plasma CVD. Next, by using a resist mask pattern (not shown), these layers are selectively removed to form a bit line 22. In the peripheral circuit, wiring is also formed which is connected to the lower plug according to necessity.

An SiO.sub.2 film of 60 nm thick is then formed over the whole surface of the substrate by low pressure CVD and anisotropically etched to form a side wall 23 of SiO.sub.2.

As shown in FIG. 2F, an SiO.sub.2 film 24 of 10 to 30 nm and an Si.sub.3N.sub.4 film 25 of 60 to 100 nm are sequentially formed over the whole surface of the substrate by low pressure CVD.

Next, as shown in FIG. 2G, a BPSG film 26 of 1000 to 1500 nm thick is formed as a planarizing film over the whole surface of the substrate and is reflowed by heat treatment at about 800.degree. C. in a nitrogen atmosphere. For more complete planarization, the surface is preferably polished and planarized by CMP.

The SiO.sub.2 film 24 serves as a stopper film when the Si.sub.3N.sub.4 film 25 is removed, and is formed in order to ensure a sufficient breakdown voltage. The Si.sub.3N.sub.4 film 25 serves as a stopper film when the BPSG film 26 is removed. If the Si.sub.3N.sub.4 film 25 is made thick, capacitance of wiring patterns increases because of its higher dielectric constant than SiO.sub.2. It is therefore preferable to make the Si.sub.3N.sub.4 film 25 thin provided that it can serve as an etching stopper.

Next, by using a resist mask pattern (not shown), the BPSG film 26, Si.sub.3N.sub.4 film 25, and SiO.sub.2 film 24 are sequentially and selectively etched to form a contact area HC for a storage electrode. Similar to forming the contact hole 15 for the plug 16, self alignment is realized by the SiO.sub.2 film 24 and Si.sub.3N.sub.4 film 25 covering the bit line structure.

A doped silicon layer of 60 nm thick is formed over the whole surface by low pressure CVD to form a storage electrode layer in the contact area HC. A resist film 28 is coated embedding the inner space of the contact area and polished by CMP to remove the silicon layer on the BPSG film 26 and form a storage electrode 27.

The resist 28 in the storage electrode 27 is removed. Next, by using the Si.sub.3N.sub.4 film 25 and silicon storage electrode 27 as an etching stopper, the BPSG film 26 is removed by using HF containing etchant gas to expose the outer side of the storage electrode 27.

As shown in FIG. 2H, the surface of the storage electrode 27 is nitrized by rapid thermal nitrization (RTN). Next, a Ta.sub.2O.sub.5 film 29 of 5 to 15 nm thick is formed by low pressure CVD, and thermal oxidation at about 800 to 850.degree. C. or oxygen plasma anneal is performed. In this manner, a capacitor dielectric film is formed.

A TiN film as an opposing electrode is formed on the whole surface by low pressure CVD and etched by using a resist mask pattern (not shown) to form an opposing electrode 30.

Thereafter, an interlayer insulating film is formed and contact holes are formed to obtain the structure shown in FIG. 1B. After the processes such as wiring pattern formation, a stack type capacitor can be manufactured.

This embodiment has a structure raised by the plug 16. Specifically, after the word line is formed, the plug 16 is formed to obtain the raised structure and the storage electrode 27 is formed between bit lines by SAC. It is therefore possible to lower the height of the capacitor by an amount corresponding to the bit line structure.

A height difference or step between the memory cell area and peripheral circuit area can be reduced, and contact holes in the peripheral circuit area can be easily formed.

In this embodiment, as shown in FIG. 1A, the contact hole of the storage electrode is opened in a lattice area surrounded by the word and bit lines.

FIG. 3 is a plan view of the substrate after the process of forming the plugs 16b in the bit line contact hole and the plug 16a in the storage electrode contact hole, and corresponds to FIG. 2D.

If 0.2 .mu.m design rule is used and an insulating film such as a side wall is formed to a thickness of 0.06 .mu.m on each side of a 0.2 .mu.m square contact hole surrounded in a 0.2 .mu.m square area, the actual contact hole is 0.08 .mu.m square. Such a fine and deep contact hole is very difficult to etch.

It is necessary to use an excimer stepper having a short wavelength in order to improve a resolution for the manufacture of highly integrated semiconductor devices, particularly 256 Mbit or larger DRAM devices (design rule of 0.22 .mu.m or shorter). However, such an excimer stepper only is insufficient when its resolution and manufacture margin are considered, and some ultra-high resolution approaches are required. Of these, the most leading approach is a method called a phase shift method. A Levenson type phase shift method is most effective and is highly expected, which method inverts the phases of adjacent patterns by 180 degrees.

However, only the pattern in conformity with the principle that the phases of adjacent patterns are inverted, can exhibit the effects of this method. In the layout of the plug shown in FIG. 3, one bit line contact 16b is adjacent to two storage electrode contacts in triangular shape. Three contacts which are adjacent to one another cannot be arranged to be opposite phase one another. Therefore, the layout of FIG. 3 is difficult to be applied to Levenson type phase shift.

The bit line is required to be connected also to an n-type diffusion region in the peripheral circuit area (particularly a sense amplifier). In this case, the plug 16 is also formed in the peripheral circuit area as shown in FIG. 2D. That is to say, the contact structure in the peripheral circuit area is constituted of the bit line, plug, n-type diffusion region and has two pairs of contact surfaces. Therefore, the contact resistance becomes large as compared to direct contact between the bit line and the diffusion region and a variation of contact resistances may occur.

The contacts are more dispersed in the peripheral circuit area than in the memory cell area, and have an isolated pattern. In this case, even if Levenson type phase shift is applied to patterning of the plug 16, this method is not effective for the isolated pattern. Rather, even if the exposure conditions (numerical aperture, .sigma. value, exposure time) are optimized to exhibit the effects of Levenson type phase shift, a contact hole cannot be opened if it hasn't a larger diameter.

2nd Embodiment

In the second embodiment, plugs 16 are formed only in the contact holes of storage electrodes in order to exhibit the effects of Levenson type phase shift.

The bit line is directly connected to the peripheral circuit area so that a variation of contact resistances can be suppressed.

The second embodiment will be described specifically with reference to FIGS. 4A to 9I in which similar reference numerals denote similar elements. The description of the processes corresponding to FIGS. 1A to 3 is omitted.

FIGS. 4A, 5A, . . . , 8A are plan views of memory cells of this embodiment. A word line 8 extends vertically in FIGS. 4A, 5A, . . . , 8A. FIGS. 4B, 5B, . . . , 8B are plan views of two MOS transistors in the peripheral circuit area of this embodiment.

FIGS. 9A to 9I are cross sectional views illustrating the manufacture processes of a semiconductor device of this embodiment. FIGS. 9A to 9I correspond to the cross sectional views of the memory cell area MC of FIGS. 4A, 5A, . . . , 8A taken along lines A A' and B B', and to the cross sectional views of the peripheral circuit area PC of FIGS. 4B, 5B, . . . , 8B taken along line C C'.

As shown in FIGS. 4A, 4B, and 9A, on a p-type silicon substrate 1, a field oxide film 2 is formed and thereafter, a gate oxide film 3 and a gate electrode 8 are formed, by using similar techniques described with FIG. 2A. The gate electrode is connected to a word line. Well structures are omitted, but may be similar to those of FIG. 1B.

As shown in FIG. 9B, by using similar techniques described with FIG. 2B, an n.sup.--type impurity diffusion region 9 is formed by using the gate electrode 8 as a mask. The n.sup.--type impurity diffusion region 9 becomes the source/drain region of a transfer transistor. Next, an SiO.sub.2 film of 60 nm thick is formed and anisotropically etched to form a side wall 10 of SiO.sub.2.

As shown in FIG. 9C, by using similar techniques described with FIG. 2C, an SiO.sub.2 film 11 and an Si.sub.3N.sub.4 film 12 are formed.

Next, a BPSG film 13 is formed as a planarizing film and reflowed by heat treatment. For more complete planarization, the surface of the BPSG film is preferably polished by CMP.

As shown in FIGS. 5A, 5B, and 9D, an Si.sub.3N.sub.4 film 14 is formed on the whole surface of the substrate by low pressure CVD. By using a resist mask (not shown) patterned in conformity with Levenson type phase shift, the Si.sub.3N.sub.4 film 14, BPSG film 13, Si.sub.3N.sub.4 film 12, and SiO.sub.2 film 11 are selectively removed to form only contact holes 15a via which storage electrodes contact the n.sup.--type impurity diffusion regions 9. At this stage, contact holes via which bit lines are connected to the n.sup.--type diffusion regions 9 and contact holes in the peripheral circuit area are not formed.

A doped silicon layer of 300 nm thick is embedded in the contact hole 15a by low pressure CVD and the doped silicon layer on the Si.sub.3N.sub.4 film 14 is removed by CMP to form a conductive plug 16a.

As shown in FIGS. 6A, 6B, and 9E, an SiO.sub.2 film 17 of 20 to 60 nm thick is formed over the whole surface of the substrate by low pressure CVD. This SiO.sub.2 film 17 covers the surface of the plug 16a, and electrically isolates the plug 16a and the bit line of the second wiring layer.

Next, by using a resist mask pattern (not shown), the SiO.sub.2 film 17, Si.sub.3N.sub.4 film 14, BPSG film 13, Si.sub.3N.sub.4 film 12, and SiO.sub.2 film 11 are selectively removed to form at the same time contact holes 15b for bit lines 22 and contact holes 15b in the peripheral circuit area.

As shown in FIGS. 7A, 7B, and 9E, a doped silicon layer 18 of 40 nm thick, a WSi layer 19 of 120 nm thick, and an SiO.sub.2 film 20 of 120 nm thick are sequentially formed by low pressure CVD, and then an SiON film 21 as an anti-reflection film is formed on the SiO.sub.2 film 20 by plasma CVD. Next, by using a resist mask pattern (not shown), these layers are selectively removed to form the bit line 22.

An SiO.sub.2 film is formed over the whole surface of the substrate, covering the bit line structure, by low pressure CVD and anisotropically etched to form a side wall 23 of SiO.sub.2.

As shown in FIG. 9F, by using similar techniques described with FIG. 2F, an SiO.sub.2 film 24 and an Si.sub.3N.sub.4 25 are sequentially formed over the whole surface of the substrate.

As shown in FIG. 9G, by using similar techniques described with FIG. 2G, a BPSG film 26 is formed and reflowed by heat treatment. For more complete planarization, the surface of the BPSG film 26 is preferably polished by CMP.

As shown in FIGS. 8A, 8B, and 9G, the BPSG film 26, Si.sub.3N.sub.4 film 25, and SiO.sub.2 film 24 are sequentially removed to form contact areas for the storage electrodes.

After a doped silicon layer is formed and a resist layer 28 is coated embedding the contact area of each storage electrode, the surface of the resist layer is polished by CMP to remove the silicon layer on the BPSG film 26 and form the storage electrodes 27.

As shown in FIG. 9H, by using similar techniques described with FIG. 2H, the resist 28 in the storage electrode is removed. Next, the BPSG film 26 is removed by wet etching using the Si.sub.3N.sub.4 film 25 as an etching stopper to expose the outer surface of the storage electrode. The surface of the storage electrode 27 is nitrized by RTN. Then, a Ta.sub.2O.sub.5 film 29 is formed, and heat treatment or oxygen plasma anneal is performed.

A TiN film is formed and patterned to form an opposing electrode 30. An interlayer insulating film 31 of, for example, BPSG is formed and its surface is planarized by reflow or CMP. Contact holes CH in the peripheral circuit area are formed by using a resist pattern (not shown).

As shown in FIG. 9I, after processes such as forming wiring including a barrier metal layer 32 and a main conductive layer 33, a DRAM device including stack type capacitors is completed.

In some case, even after the bit line 22 is formed, plugs for another raised structure may be formed. In this case, although the memory cell area becomes higher than the first embodiment, the contact holes 15a for the plugs 16 for storage electrode connection can be formed easily because of Levenson type phase shift.

In this embodiment, the contact hole 15b in the peripheral circuit area is opened at the same time when the contact hole 15b for the bit line is formed, separately from the formation of contact holes 15a for the storage electrode contacts. So, Levenson type phase shift is not necessary. Since the diameter of the contact hole in the peripheral circuit area can be reduced, the layout area can be made small.

Furthermore, since the contact hole 15b for the n-type diffusion region in the peripheral circuit area is directly formed on the substrate, the contact resistance in the peripheral circuit area can be stabilized and a variation of contact resistances can be suppressed.

3rd Embodiment

Next, the third embodiment will be described with reference to the accompanying drawings.

In the second embodiment, the silicon layer and WSi layer are used for the bit line. Therefore, if n-type doped silicon is used, contacts in the peripheral circuit area can be established only with n-type diffusion regions.

From this reason, in order to make contacts with p-type diffusion regions in the peripheral circuit area, it is necessary to use a higher level metal wiring layer. Furthermore, it is necessary to form a deep contact hole from the higher level wiring layer to the substrate surface. Therefore, this alignment margin makes the layout area broad. There is also a problem of a difficulty of etching control for such a deep contact hole.

In this embodiment, the bit line structure under the capacitor is formed by a metal wiring layer. It is therefore possible to contact both n- and p-type diffusion regions in the peripheral circuit area via shallow contact holes and the layout area can be reduced.

FIG. 10 is a cross sectional view of a semiconductor device of the third embodiment, and corresponds to the cross sectional view of FIG. 9I of the second embodiment. In FIG. 10, reference symbol 9a represents an n-type diffusion region, and reference symbol 9b represents a p-type diffusion region. A bit line 22 which is a second level conductive layer is formed of two metal layers 18a and 19a. Other reference numerals represent similar elements described with the second embodiment. Well structures are partly omitted from the drawing.

In this embodiment, at the same time when the contact hole 15b for the bit line is formed, contact holes 15b for both n- and p-channel transistor regions in the peripheral circuit area are formed.

It is therefore unnecessary to directly contact the substrate surface by using the higher level wiring layer as shown in FIG. 9I. The layout area of the peripheral circuit area can therefore be reduced.

4th Embodiment

The fourth embodiment of the invention will be described with reference to FIGS. 11 and 12.

This embodiment will be described mainly attending to the method of contacting a first layer conductive pattern with a second layer conductive pattern in the peripheral circuit area.

FIG. 11 is a cross sectional view of a semiconductor device corresponding to FIG. 9I of the second embodiment, showing a contact between the conductive patterns 4 and 5 of the first layer and the conductive patterns 18 and 19 of the second layer at the rightmost area in the peripheral circuit area.

FIG. 12 is a cross sectional view of a semiconductor device of the fourth embodiment, which device is an improvement of the device shown in FIG. 9I. The memory cell area corresponds to the memory cell area shown in FIG. 9I and the peripheral circuit area is similar to that shown in FIG. 9I. Similar elements to those of the second embodiment are represented by using identical reference numerals.

In this embodiment, after the Si.sub.3N.sub.4 12 to be used for SAC is formed, the Si.sub.3N.sub.4 film 12 in the peripheral circuit area is removed. For example, at the processes shown in FIGS. 2C and 9C, the Si.sub.3N.sub.4 film 12 is selectively removed at the area including the area where the conductive pattern of the first layer and the conductive pattern of the second layer are contacted together. In the memory cell area, there exists one Si.sub.3N.sub.4 film 12 between the n-type diffusion region 9 and the interlevel insulating layer 13. In the peripheral circuit area, there exists one SiON film 7 between the first level conductive pattern 45 and the interlevel insulating layer 13. The SiON film 7 and the SiN film 12 can be simultaneously etched in a single selective etching process.

Therefore, at the same time when the contact hole between the bit line and substrate is opened, the contact hole for the conductive pattern of the first layer and the conductive pattern of the second layer can be formed. As compared to the method illustrated in FIG. 11 which requires to open a fine contact hole to the first level conductive layer separately from the contact hole to the substrate, the method illustrated in FIG. 12 requires only to form additional pattern for removing the Si.sub.3N.sub.4 film at the area where a contact hole is formed. A separate fine pattern is therefore unnecessary so that yield and reliability can be improved.

5th Embodiment

The fifth embodiment of the invention will be described with reference to FIG. 13.

This embodiment is a combination of the third and fourth embodiments, uses the method of contacting the first layer conductive pattern with the second layer conductive pattern, and uses metal as the material of the second layer conductive pattern.

FIG. 13 is a cross sectional view of a semiconductor device of this embodiment, which device is an improvement of the device of the fourth embodiment shown in FIG. 12. Similar elements to those of the second embodiment are represented by using identical reference numerals.

With this embodiment, at the same time when the contact hole for the bit line is formed, contact holes for both the n- and p-channel transistors in the peripheral circuit area can be formed. Since a contact hole for the upper level wiring directly contacting the substrate is reduced, the layout area of the peripheral circuit area can be reduced.

After the Si.sub.3N.sub.4 film 12 used for SAC is formed, the Si.sub.3N.sub.4 film 12 in the peripheral circuit area is removed. Therefore, at the same time when the contact hole for the bit line and substrate is formed, a contact hole for the first layer conductive pattern and second layer conductive pattern can be formed so that the number of processes can be reduced.

6th Embodiment

The sixth embodiment of the invention will be described with reference to FIG. 14.

This embodiment pertains to forming a contact hole in the peripheral circuit area. If an interlayer insulating film is formed by a plurality of oxide films and nitride films, a process of etching the interlayer insulating film to form a contact hole to an impurity diffusion layer or a wiring layer becomes complicated.

This embodiment, therefore, aims to stabilize the process of forming a contact hole in the peripheral circuit area.

FIG. 14 is a cross sectional view of a semiconductor device of this embodiment, which device is an improvement of the device of the second embodiment. Identical reference numerals represent similar elements to those of the second embodiment.

The semiconductor device manufacture processes of this embodiment are generally the same as those described with FIGS. 9A to 9I. Different points will be described with reference to FIG. 14.

After the gate electrode of the first wiring layer is patterned, the SiON film 7 on the gate electrode 8 in the peripheral circuit area is removed, for example, by boiling phosphoric acid. Similarly, after the bit line of the second wiring layer is patterned, the SiON film 21 on the bit line in the peripheral circuit area is removed. Further, after the opposing electrode 30 is patterned, the Si.sub.3N.sub.4 film 25 in the peripheral circuit area is removed. The SiON films 7 and 21 are used as an anti-reflection film when the wiring layers are patterned. These SiON films 7 and 21 are not required to be removed if wiring layers are patterned without using these films.

In this embodiment, there is no SiON layer and only one SiN film on the first level wiring and the bit line in the peripheral circuit area. At the same time when the nitride film used for SAC in the memory cell area is selectively removed, the nitride film in the peripheral circuit area can be removed. Also, the underlying oxide films can be removed simultaneously. It becomes easy to form a contact hole in the peripheral circuit area without increasing the number of processes.

7th Embodiment

The seventh embodiment of the invention will be described with reference to FIG. 15.

In the sixth embodiment, the SiON film 7 on the first wiring layer (gate electrode) and the SiON film 21 on the second wiring layer (bit line) are removed and the Si.sub.3N.sub.4 film 25 under the opposing electrode is removed by using the opposing electrode as a mask. In this manner, forming a contact hole in the peripheral circuit area is made easy. In this embodiment, a method of forming a contact hole more easily is provided.

FIG. 15 is a cross sectional view of a semiconductor device of this embodiment, which device is an improvement of the device of the sixth embodiment. Identical reference numerals denote similar elements to those of the second embodiment. Different points will be described.

After the gate electrode of the first wiring layer is patterned, the SiON film 7 on the gate electrode 8 in the peripheral circuit area is removed, for example, by boiling phosphoric acid.

Next, after the Si.sub.3N.sub.4 film used for SAC is formed, the Si.sub.3N.sub.4 film 12 in the peripheral circuit area is selectively removed. Also, after the bit line of the second wiring layer is patterned, the SiON film 21 on the bit line in the peripheral circuit area is removed. Further, after the opposing electrode 30 is patterned, the Si.sub.3N.sub.4 film 25 for SAC, SiO.sub.2 interlayer insulating film 24, and Si.sub.3N.sub.4 film 14 in the peripheral circuit area are sequentially removed.

The SiON films 7 and 21 are used as an anti-reflection film when the wiring layers are patterned. These SiON films 7 and 21 are not required to be removed if wiring layers are patterned without using these films.

In this embodiment, since all the SiON films 7 and 21, Si.sub.3N.sub.4 films 12, 21, and 14 are removed, a contact hole in the peripheral circuit area can be formed more easily.

8th Embodiment

The eighth embodiment of the invention will be described with reference to FIGS. 16A to 16I.

This embodiment provides a method of contacting the conductive pattern of the first wiring layer with the conductive pattern of the second wiring layer in the peripheral circuit area, by using a different method from the fourth embodiment.

FIGS. 16A to 16I are cross sectional views of a semiconductor chip illustrating a semiconductor device manufacture method of this embodiment, in which similar elements to those of the second embodiment are represented by using identical reference numerals.

As shown in FIG. 16A, on a p-type silicon substrate 1, a field SiO.sub.2 film 2 of 250 nm thick is formed by a well known technique, LOCOS isolation (selective oxidation). Thereafter, an SiO.sub.2 film 3 of 5 to 10 nm thick is formed by thermal oxidation, this film being a gate oxide film.

Next, a silicon layer 4 of 50 nm thick highly doped with phosphorous (P) impurities, a WSi layer 5 of 120 nm thick, an SiO.sub.2 film 6 of 20 nm thick, and an Si.sub.3N.sub.4 layer 7' of 80 nm thick are sequentially formed by low pressure CVD.

By using a resist mask pattern (not shown), the SiON film 7' is selectively etched at the area where first layer conductive patterns and second layer conductive patterns are contacted together.

As shown in FIG. 16B, by using a resist mask pattern (not shown), the Si.sub.3N.sub.4 film 7', SiO.sub.2 film 6, WSi film 5, and silicon layer 4 are selectively removed to form a gate electrode (first wiring layer) which constitutes a word line.

As shown in FIG. 16C, by using the gate electrode 8 as a mask, P (phosphorous) ions are implanted into the silicon substrate 1 to form an n.sup.--type impurity diffusion region 9. The n.sup.--type impurity diffusion region 9 is the source/drain region of a transfer transistor in the memory cell area, and in the peripheral circuit area an LDD diffusion region of an n-channel transistor in the peripheral circuit area. Next, an SiO.sub.2 film of 60 nm thick is formed over the whole surface of the substrate by low pressure CVD, and a side-wall 10' of Si.sub.3N.sub.4 is formed by anisotropic etching.

As shown in FIG. 16D, in the peripheral circuit area, arsenic ions are implanted into the n-channel transistor region to form an n.sup.+-type diffusion region, and boron ions are implanted into a p-channel transistor region to form a p.sup.+-type diffusion region (not shown).

Next, an SiO.sub.2 film 11 of 20 nm thick and a BPSG film of 300 to 400 nm thick are formed over the whole surface of the substrate by low pressure CVD. The BPSG film 13 is reflowed by heat treatment at about 800.degree. C. in a nitrogen atmosphere. For more complete planarization, the surface is preferably polished and planarized by CMP.

Next, an Si.sub.3N.sub.4 film 14 of 50 nm thick is formed over the whole surface of the substrate by low pressure CVD, and by using a resist mask pattern (not shown). it is selectively removed at the area where the storage electrode is contacted. After the BPSG film 13 is removed in a self alignment manner using the nitride films 7' and 10', a contact hole 15a for SAC is formed.

A doped silicon layer of 300 nm thick is embedded in the contact holes 15a by low pressure CVD, and removed at the area on the Si.sub.3N.sub.4 film 14 by CMP to form a plug 16.

As shown in FIG. 16E, an SiO.sub.2 film 17 of 20 to 60 nm thick is formed over the whole surface of the substrate covering the plug 16 by low pressure CVD. This SiO.sub.2 film 17 insulates the plug 16 and the bit line of a second layer wiring. Next, by using a resist mask pattern (not shown), the SiO.sub.2 film 17, Si.sub.3N.sub.4 film 14, BPSG film 13, and SiO.sub.2 film 11 are selectively removed to form a contact hole 15b for the bit line 22 and a contact hole 15b in the peripheral circuit area at the same time. The contact hole 15b can be formed in a self alignment manner using the nitride films 7' and 10', similar to the formation of the contact hole 15a.

As shown in FIG. 16F, a silicon layer 18 of 40 nm thick highly doped with P, a WSi layer 19 of 120 nm thick, an SiO.sub.2 film 20 of 20 nm thick, and an Si.sub.3N.sub.4 film 21' are sequentially formed over the whole surface of the substrate by low pressure CVD. Next, by using a resist mask pattern (not shown), these layers are selectively removed to form a bit line 22.

An Si.sub.3N.sub.4 film of 60 nm thick is then formed over the whole surface of the substrate by low pressure CVD and anisotropically etched to form a side wall 23' of Si.sub.3N.sub.4.

As shown in FIG. 16G, an SiO.sub.2 film 24 of 10 to 30 nm is formed over the whole surface by low pressure CVD. Next, a BPSG film 26 of 1000 to 1500 thick as a planarizing film is formed over the whole surface and reflowed by heat treatment at 850.degree. C. in a nitrogen atmosphere. For more complete planarization, the surface is preferably polished and planarized by CMP.

Next, by using a resist mask pattern (not shown), the BPSG film 26 and SiO.sub.2 film 24 are sequentially and selectively removed in a self alignment manner utilizing the nitride films 21 and 23' to form a contact area HC for a storage electrode.

A silicon layer of 60 nm thick highly doped with phosphorous is formed over the whole surface by low pressure CVD. After resist 28 is embedded in the contact area for the storage electrode, the surface of the resist is polished to remove the silicon layer on the BPSG film 26 and form a storage electrode 27.

As shown in FIG. 16H, the resist 28 in the storage electrode is removed. Next, the BPSG film 26 is removed by wet etching using HF containing etchant gas to expose the outer side of the storage electrode 27. The figure shows the case where the BPSG film 26 is partly retained. The surface of the storage electrode 27 is nitrized by RTN. Next, a Ta.sub.2O.sub.5 film 29 of 5 to 15 nm thick is formed by low pressure CVD, and thermal oxidation at about 800 to 850.degree. C. or oxygen plasma anneal is performed.

A TiN film of 50 nm thick as an opposing electrode is formed on the whole surface by low pressure CVD and etched by using a resist mask pattern (not shown) to form an opposing electrode 30.

As shown in FIG. 16I,