Method of manufacturing multi-layer printed circuit board Number:7,178,234 from the United States Patent and Trademark Office (PTO) owispatent

Title: Method of manufacturing multi-layer printed circuit board

Abstract: Through holes 36 are formed to penetrate a core substrate 30 and lower interlayer resin insulating layers 50, and via holes 66 are formed right on the through holes 36, respectively. Due to this, the through holes 36 and the via holes 66 are arranged linearly, thereby making it possible to shorten wiring length and to accelerate signal transmission speed. Also, since the through holes 36 and the via holes 66 to be connected to solder bumps 76 (conductive connection pins 78), respectively, are directly connected to one another, excellent reliability in connection is ensured.

Patent Number: 7,178,234 Issued on 02/20/2007 to Kawasaki,   et al.

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Inventors:	Kawasaki; Yogo (Ogaki, JP), Satake; Hiroaki (Ogaki, JP), Iwata; Yutaka (Ogaki, JP), Tanabe; Tetsuya (Ogaki, JP)
Assignee:	Ibiden Co., Ltd. (Ogaki, JP)
Appl. No.:	11/106,642
Filed:	April 15, 2005

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Related U.S. Patent Documents

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	Application Number	Filing Date	Patent Number	Issue Date
	09830953		6930258
	PCT/JP00/07037	Oct., 2000

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Foreign Application Priority Data

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Oct 26, 1999 [JP]			11/303305
Oct 26, 1999 [JP]			11/303306
Oct 26, 1999 [JP]			11-303307
Feb 08, 2000 [JP]			2000-029988

Current U.S. Class:	29/852 ; 29/825; 29/830; 29/846; 427/97.7
Current International Class:	H01K 3/10 (20060101)
Field of Search:	29/825,830,846,852 427/97.7

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References Cited [Referenced By]

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U.S. Patent Documents

	4816323		March 1989		Inoue
	5004639		April 1991		Desai
	5153986		October 1992		Brauer et al.
	5450290		September 1995		Boyko et al.
	5487218		January 1996		Bhatt et al.
	5557844		September 1996		Bhatt et al.
	5590460		January 1997		DiStefano et al.
	5827604		October 1998		Uno et al.
	5837155		November 1998		Inagaki et al.
	5879568		March 1999		Urasaki et al.
	5906042		May 1999		Lan et al.
	6010768		January 2000		Yasue et al.
	6217988		April 2001		Yasue et al.
	6228511		May 2001		Sachdev et al.
	6251502		June 2001		Yasue et al.
	6266874		July 2001		DiStefano et al.
	6323439		November 2001		Kambe et al.
	6376052		April 2002		Asai et al.
	6729019		May 2004		Grube et al.
	6826830		December 2004		Egitto et al.
	6829823		December 2004		Downes et al.

Foreign Patent Documents

	06-283847		Oct., 1994		JP
	09-130050		May., 1997		JP
	09-181415		Jul., 1997		JP
	09-246732		Sep., 1997		JP
	09-260849		Oct., 1997		JP
	09-331152		Dec., 1997		JP
	11-087930		Mar., 1999		JP
	11-261216		Sep., 1999		JP
	11-266078		Sep., 1999		JP
	11-266079		Sep., 1999		JP

Primary Examiner: Arbes; Carl J.
Attorney, Agent or Firm: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.

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Claims

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What is claimed is:

1. A method of manufacturing a multi-layer printed circuit board comprising at least the following steps (a) to (f): (a) forming lower interlayer resin insulating layers on both sides of a core substrate, respectively; (b) forming through holes penetrating said core substrate and said lower interlayer resin insulating layers; (c) forming on sides of the through holes vertical electrical conductors extending between the lower interlayer resin insulating layers and extending at least along a length of the through holes; (d) forming conductor circuits on exposed surfaces of the lower interlayer resin insulating layers opposite the core substrate; (e) forming upper interlayer resin insulating layers on said lower interlayer resin insulating layers, respectively; and (f) forming via holes in said upper interlayer resin insulating layers, the via holes connected to external connection terminals and formed right on part of said through holes.

2. The method of claim 1, futher comprising: filling resin filler in said through holes prior to forming the upper interlayer resin insulating layers; polishing and flattening the resin filler pouring from said through holes; and forming conductor layers covering exposed surfaces of said resin filer from said through holes.

3. A method of manufacturing a multi-layer printed circuit board comprising at least the following steps (a) to (g): (a) forming lower interlayer resin insulating layers on both sides of a core substrate, respectively; (b) forming penetrating holes in said core substrate and said lower interlayer resin insulating layers, (c) forming openings in said lower interlayer resin insulating layers, (d) forming conductive films in said penetrating holes and said openings to thereby provide the through holes and the via holes, respectively; (e) filling resin filler in said through holes and said via holes; (f) polishing and flattening the resin filler pouring out of said through holes and said via holes; and (g) forming conductor layers covering exposed surfaces of said resin filler from said through holes and said via holes, respectively.

4. The method of claim 3, further comprising: (h) forming upper interlayer resin insulating layers on said lower interlayer resin insulating layers, respectively; and (i) forming via holes in said upper interlayer resin insulating layers and right on part of said via holes.

5. The method of claim 3, further comprising: (h) conducting a de-smear process to said penetrating holes by an oxidizer and conducting a roughing process to surfaces of the lower interlayer resin insulating layers;

6. The method according to claim 5, wherein said core substrate is made of one of a glass epoxy resin, an FR4 resin, an FR5 resin and a BT resin; each of said lower interlayer resin insulating layers contains at least one of an epoxy resin, a phenol resin, a polyimide resin, a polyphenylene resin, a polyolefin resin and a fluorocarbon resin; and said oxidizer contains one of a chromic acid and permanganate.

7. The method according to claim 5, wherein said oxidizer contains one of a chromic acid and permanganate.

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Description

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TECHNICAL FIELD

The present invention relates to a multi-layer printed circuit board having buildup layers formed on the both sides of a core substrate, the buildup layers each having interlayer resin insulating layers and conductor layers alternately provided, the conductor layers connected to one another by via holes. More particularly, the present invention relates to a multi-layer printed circuit board and a method of manufacturing a multi-layer printed circuit board which can be employed as a package substrate on which IC chips can be mounted.

BACKGROUND ART

Hitherto, a buildup multi-layer printed circuit board has been manufactured by a method disclosed by, for example, Japanese Patent Laid-Open No. 9-130050.

A rough layer is formed on the surface of the conductor circuit of a printed circuit board by electroless plating or etching. Then, an interlayer insulating resin is applied, exposed and developed by a roll coater or printing, via hole opening portions are formed for making layers continuous, and an interlayer resin insulating layer is formed through UV hardening, actual hardening and the like. Further, a catalyst such as palladium is applied onto the interlayer resin insulating layer on the rough surface which has been subjected to a roughing process with an acid or an oxidizer. A thin electroless plated film is formed, a pattern is formed on the plated film by a dry film and the thickness of the pattern is increased by electroplating. Thereafter, the dry film is separated and removed by an alkali and etched to thereby form a conductor circuit. By repeating the above processes, a buildup multi-layer printed circuit board is obtained.

At present, as the frequency of IC chips becomes higher, demand for accelerating the transmission speed of a multi-layer printed circuit board rises. To deal with such demand, the applicant of the present invention proposed Japanese Patent Laid-Open No. 10-334499. With this constitution, linear wirings are provided by arranging via holes 346 of a lower interlayer resin insulating layer 350 and via holes 366 of an upper interlayer resin insulating layer 360 right above through holes 336, thereby shortening wiring lengths and accelerating signal transmission speed.

It was discovered, however, that with the above constitution, the via holes 346 of the lower interlayer resin insulating layer 350 and the via holes 366 of the upper interlayer resin insulating layer 360 are separated from one another under heat cycle conditions. The inventor of the present invention investigated the cause of separation and discovered that the via holes 366 in the upper layer are influenced by the shapes of the surfaces of the via holes 346 of the lower layer and the connection characteristic of the via holes 366 deteriorates. Further, it is estimated that since the interlayer resin insulating layers 350 and 360 are not reinforced by core materials such as glass cloth, these layers tend to be separated in a heat cycle rather than a core substrate provided with a core material.

The present invention has been made to overcome the foregoing problems, and it is, therefore, an object of the present invention to provide a multi-layer printed circuit board and a method of manufacturing a multi-layer printed circuit board capable of shortening internal wiring lengths and having excellent connection reliability.

It is a still further object of the present invention to provide a manufacturing method capable of manufacturing a multi-layer printed circuit bard at low cost.

Meanwhile, a resin is filled in through holes so as to enhance reliability for a buildup multi-layer printed circuit board. When filling the resin, blackening-reduction processes are conducted to the surfaces of the through holes and rough layers are provided thereon so as to increase adhesiveness. In addition, as the density of the multi-layer printed circuit board increases, through holes are made smaller in size. Following this, resin filler having low viscosity is employed to be filled in the through holes.

As prior art for forming a rough layer on a through hole and filling the through hole with resin filler, it is described in Japanese Patent Laid-Open No. 9-181415 that a copper oxide layer is formed in a through hole, the through hole is filled with resin filler and then an interlayer insulating layer is formed. It is also described in Japanese Patent Laid-Open No. 9-260849 that after forming a rough layer in a through hole by etching, the through hole is filled with resin filler and then an interlayer insulating layer is formed.

If using resin filler having low viscosity, however, the resin filler is dented in the through hole, causing disconnection and the like during the formation of wirings on an upper layer. The inventor of the present invention investigated the cause of disconnection and discovered that this is because the resin out of filler and the resin which constitute resin filler flow along the rough layer (very small anchor) formed on the land of the through hole. As a result, the filler within the through hole is dented, making it impossible to flatten and smooth a core substrate. Due to this, it was discovered that if manufacturing a multi-layer printed circuit board by forming an interlayer resin insulating layer and wirings on a core substrate, the resultant multi-layer resin insulating layer is susceptible to disconnection and a probability of generating defects increases.

The present invention has been made to solve the foregoing problems and it is, therefore, a still further object of the present invention to provide a method of manufacturing a multi-layer printed circuit board having enhanced wiring reliability.

In the meantime, a substrate on which a resin film for the interlayer resin insulating layer of a resin substrate serving as a core material is bonded, is employed as a core substrate. Through holes for penetrating the substrate are filled with resin filler. Further, an interlayer resin insulating layer is formed and via holes are formed therein. The above-stated resin filler, however, had some defects.

First, if a reliability test such as a heat cycle is conducted to a printed circuit board filled with filler, conductors sometimes crack in the vicinity of the boundary between the resin substrate and the resin film. Second, after filling the filler, a resin film serving as an interlayer resin insulating layer cracks in a polishing step conducted to flatten the board. Third, if a plated cover is formed right on the through hole, the reaction of the plated film may stop. Thus, even if via holes are formed right above the through holes, electrical connection cannot be established.

As a result of these three defects, a printed circuit board with deteriorated reliability and reduced electrical connection characteristics is provided.

It is a still further object of the present invention to provide a printed circuit board and a method of manufacturing a printed circuit board capable of solving these defects.

DISCLOSURE OF THE INVENTION

In order to solve the above problems, a multi-layer printed circuit board according to the claim 1 is characterized by having buildup layers formed on both sides of a core substrate, the buildup layers each having interlayer resin insulating layers and conductive layers alternately provided, the conductor layers connected to one another by via holes, wherein

through holes are formed to penetrate said core substrate and the interlayer resin insulating layers formed on the both sides of the core substrate; and

the via holes are formed right on said through holes, the via holes connected to external connection terminals.

In claim 2, A multi-layer printed circuit board according to claim 1, wherein

resin filler is filled in said through holes and the conductor layers are formed to cover exposed surfaces of the resin filler from the through holes; and

the via holes right on said through holes are formed on said conductor layers of said through holes.

According to claim 3, a method of manufacturing a multi-layer printed circuit board comprising at least the following steps (a) to (d):

(a) forming lower interlayer resin insulating layers on both sides of a core substrate, respectively;

(b) forming through holes penetrating said core substrate and said lower interlayer resin insulating layers;

(c) forming upper interlayer resin insulating layers on said lower interlayer resin insulating layers, respectively; and

(d) forming via holes in said upper interlayer resin insulating layers, the via holes connected to external connection terminals and formed right on part of said through holes.

According to claim 4, a method of manufacturing a multi-layer printed circuit board comprising at least the following steps (a) to (g):

(a) forming lower interlayer resin insulating layers on both sides of a core substrate, respectively;

(b) forming through holes penetrating said core substrate and said lower interlayer resin insulating layers;

(c) filling resin filler in said through holes;

(d) polishing and flattening the resin filler pouring from said through holes;

(e) forming conductor layers covering exposed surfaces of said resin filer from said through holes;

(f) forming upper interlayer resin insulating layers on said lower interlayer resin insulating layers, respectively; and

(g) forming via holes in said upper interlayer resin insulating layers and forming the via holes right on part of said through holes so as to be connected to external connection terminals.

According to the multi-layer printed circuit board recited in claim 1 and the method of manufacturing the multi-layer printed circuit board recited in claim 3, the through holes are formed to penetrate the core substrate and the interlayer resin insulating layers formed on the both sides of the core substrate, and the via holes connected to external connection terminals are formed right on the through holes, respectively. Due to this, the through holes and the via holes are arranged linearly, thereby making it possible to shorten wiring length and accelerate signal transmission speed. Further, since the through holes and the via holes connected to the external connection terminals are directly connected to one another, connection reliability is excellent.

According to the multi-layer printed circuit board recited in claim 2 and the method of manufacturing the multi-layer printed circuit board recited in claim 4, the through holes are formed to penetrate the core substrate and the interlayer resin insulating layers formed on the both sides of the core substrate, and the via holes are formed right on the through holes, respectively. Due to this, the through holes and the via holes are arranged linearly, thereby making it possible to shorten wiring length and accelerate signal transmission speed. Further, since the through holes and the via holes connected to the external connection terminals are directly connected to one another and the via holes are formed on the respective conductor layers covering the resin filler in the through holes which filler has been flattened by polishing, connection reliability is excellent.

According to claim 5, a multi-layer printed circuit board having interlayer resin insulating layers on both sides of a core substrate, respectively, through holes provided to penetrate the core substrate and filled with resin filler, the interlayer resin insulating layers and conductor circuits provided, wherein

said resin filler contains an epoxy resin, a curing agent and 10 to 50% of inorganic particles.

According to claim 6, a multi-layer printed circuit board having interlayer resin insulating layers formed on both sides of a core substrate, respectively, through holes provided to penetrate the core substrate and filled with resin filler, plated covers provided, the interlayer resin insulating layers and conductor circuits provided, wherein

said resin filler contains an epoxy resin, a curing agent and 10 to 50% of inorganic particles.

According to claim 7, a multi-layer printed circuit board according to claim 5 or 6, wherein

said inorganic particles contain one type or more selected from a group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds and silicon compounds.

First, since the quantity of the mixed inorganic particles is set appropriately, the coefficient of thermal expansion of the resin filler, that of the resin substrate forming the core substrate and those of the resin films for the interlayer resin insulating layers are matched to one another. Due to this, even on heat cycle conditions, a stress caused by heat contraction does not occur. Thus, cracking does not occur. Further, the resin films are impregnated with soluble particles for forming rough surfaces by a roughing process. Due to this, it was discovered that if the quantity of mixed inorganic particles exceeds 50%, the matching cannot be ensured.

Second, it was discovered that in the polishing step conducted to flatten the filler after the filler is filled, the filler can be easily polished. It was discovered that if the quantity of mixed inorganic particles exceeds 50%, the filler can be flattened only by mechanical polishing using abrasive paper. The resin films on the surface layers of the core substrate are not impregnated with a reinforcing material such as glass epoxy and inferior, in strength, to the resin substrate. Due to this, if mechanical polishing with abrasive paper (such as belt sander polishing) is conducted, the resin films cannot resist the polishing. As a result, the resin films crack. Besides, the resin films are damaged, thereby detaching soluble particles. Consequently, even if the rough surfaces are formed, they are not what are desired. Considering this, if a polishing process is performed, the surface layers of the core substrate are traced with a nonwoven fabric containing a polishing material such as a buff, thereby removing and flattening the resin filler.

Third, it was discovered that in the formation of plated covers right on the respective through holes, if an inorganic particle content exceeds 50%, the quantity of added catalyst decreases and the reaction of the plated films stops. The coordinate bond between the inorganic particles and the catalyst does not occur. The quantity of added catalyst, therefore, decreases. Further, in the formation of the plated films, if the quantity of inorganic particles is excessive, a plating solution tends not to be contacted, thereby stopping the reaction of the plated films.

If the quantity of mixed inorganic particles is less than 10%, the effect of matching the coefficients of thermal expansion is not expected. As a result, if the resin filler is filled, the resin filler is not left in the through holes and flows away from the other side.

It is more preferable that the mixture ratio of inorganic particles is 20 to 40%. In that range, even if particles flocculate, the above-stated defects can be avoided.

According to claim 8, a multi-layer printed circuit board according to claim 5 or 6, wherein

a shape of said inorganic particles is one of a spherical shape, a circular shape, an ellipsoidal shape, a pulverized shape and a polygonal shape.

Preferably, the particles are circular, ellipsoidal or the like without angular surfaces. This is because cracks resulting from such particles do not occur. It is also preferable that the particle diameter of the inorganic particles is in a rage of 00.1 to 5 .mu.m. If the particle diameter is less than 0.01 .mu.m, the particles are offset one another when the resin filler is filled. If exceeding 5 .mu.m, it is often difficult to adjust the mixture ratio of the inorganic particles in the resin.

In claim 9, a multi-layer printed circuit board according to claim 5 and claim 6, wherein

rough layers are provided on the conductor layers of said through holes, respectively.

It is preferable that rough layers are provided on the conductor layers of the through holes, respectively. By doing so, it is possible to prevent the resin filler from expanding and contracting, whereby the interlayer resin insulating layers and the plated covers formed on the respective through holes are not pushed up. The rough layers are formed by an oxidization-reduction process, a blackening processor a plating process as well as by an etching process.

According to claim 10, a method of manufacturing a multi-layer printed circuit board having interlayer resin insulating layers provided on both sides of a core substrate, for forming the interlayer resin insulating layers through the following steps (a) to (e):

(a) a formation step of forming through holes penetrating the both sides of the printed circuit board;

(b) a filling step of filling resin filler containing an epoxy resin and 10 to 50% of inorganic particles;

(c) a drying step and a polishing step;

(d) a hardening step; and

(e) a cover plating step.

In claim 11, a method according to claim 10, wherein

in said polishing step (c), a buffing step is conducted at least once or a plurality of times.

In claim 12, a method according to claim 10 or 11, wherein

in said step (a), a step of forming rough layers is conducted.

In order to achieve the above problems, in claim 13, a multi-layer printed circuit board having buildup layers on both sides of a core substrate, respectively, said buildup layer having interlayer resin insulating layers and conductor layers alternately provided, the conductor layers connected to one another by via holes, wherein

through holes filled with resin filler are formed to penetrate said core substrate and lower interlayer resin insulating layers formed on the both sides of the core substrate; and

via holes filled with said resin filler are formed in said lower interlayer resin insulating layers.

In case of the multi-layer printed circuit board recited in claim 13, the through holes and the via holes are filled with the same resin filler. Due to this, the multi-layer printed circuit board can be manufactured at low cost and the strength within the through holes and that within the via holes can be kept uniform, thereby making it possible to enhance the reliability of the multi-layer printed circuit board.

The resin may be a thermosetting resin which means an epoxy resin, a phenol resin, a fluorocarbon resin, a triazine resin, a polyolefin resin, a polyphenylene ether resin and the like, a thermoplastic resin or a complex thereof. Inorganic filler, such as silica or alumina, may be contained in the resin to adjust the coefficient of thermal expansion of the resin. A paste mainly consisting of metal filler such as a conductive resin, gold or silver may be employed. The complexes thereof may be employed, as well.

In claim 14, a multi-layer printed circuit board according to claim 13, wherein

the conductor layers are formed to cover exposed surfaces of the resin filler filled in the via holes of said lower interlayer resin insulating layers; and

via holes are formed right on the via holes through the conductive layers, respectively.

According to claim 14, the conductor layers covering the exposed surfaces of the filler filled in the via holes of the lower interlayer resin insulating layers are formed and the via holes are formed right on the via holes through the conductor layers, respectively. Due to this, the lower via holes can be formed flat and the adhesiveness between the lower via holes and the via holes formed on the corresponding via holes can be enhanced to thereby enhance the reliability of the multi-layer printed circuit board.

According to claim 15, a method of manufacturing a multi-layer printed circuit board comprising at least the following steps (a) to (g):

(a) forming lower interlayer resin insulating layers on both sides of a core substrate, respectively;

(b) forming penetrating holes in said core substrate and said lower interlayer resin insulating layers, the penetrating holes becoming through holes;

(c) forming openings in said lower interlayer resin insulating layers, the openings becoming via holes;

(d) forming conductive films in said penetrating holes and said openings to thereby provide the through holes and the via holes, respectively;

(e) filling resin filler in said through holes and said via holes;

(f) polishing and flattening the resin filler pouring out of said through holes and said via holes; and

(g) forming conductor layers covering exposed surfaces of said resin filler from said through holes and said via holes, respectively.

According to claim 16, a method of manufacturing a multi-layer printed circuit board comprising at least the following steps (a) to (i):

(a) forming lower interlayer resin insulating layers on both sides of a core substrate, respectively;

(b) forming penetrating holes in said core substrate and said lower interlayer resin insulating layers, the penetrating holes becoming through holes;

(c) forming openings in said lower interlayer resin insulating layers, the openings becoming via holes;

(d) forming conductive films in said penetrating holes and said openings to provide the through holes and the via holes;

(e) filling resin filler in said through holes and said via holes;

(f) polishing and flattening the resin filler pouring out of said through holes and said via holes;

(g) forming conductor layers covering exposed surfaces of said resin filler from said through holes and said via holes;

(h) forming upper interlayer resin insulating layers on said lower interlayer resin insulating layers, respectively; and

(i) forming via holes in said upper interlayer resin insulating layers and right on part of said via holes.

According to the method of manufacturing the multi-layer printed circuit board recited in claims 15 and 16, the same resin filler is filled in the through holes and the via holes and polished simultaneously. Due to this, the multi-layer printed circuit board can be manufactured at low cost and the strength within the through holes and that within the via holes can be kept uniform, so that the reliability of the multi-layer printed circuit board can be enhanced. Further, since the upper via holes are formed on the conductor layers covering the filler within the via holes which filler has been polished and thereby flattened, respectively, connection reliability is excellent.

In order to achieve the above problems, according to claim 17, a method of manufacturing a multi-layer printed circuit board comprising at least the following steps (a) to (e):

(a) forming lower interlayer resin insulating layers on both sides of a core substrate, respectively;

(b) forming penetrating holes in said core substrate and said lower interlayer resin insulating layers, the penetrating holes becoming through holes;

(c) forming openings in said lower interlayer resin insulating layers, the openings becoming via holes;

(d) conducting a de-smear process to said penetrating holes by an acid or an oxidizer and conducting a roughing process to surfaces of the lower interlayer resin insulating layers; and

(e) forming conductive films on said penetrating holes and said openings to provide the through holes and the via holes, respectively.

According to the method of manufacturing the multi-layer printed circuit board recited in claim 17, the de-smear process for the penetrating holes by employing an oxidizer and the roughing process for the surfaces of the lower interlayer resin insulating layers are performed simultaneously. Due to this, it is possible to reduce the number of manufacturing steps and to manufacture the multi-layer printed circuit board at low cost.

In claim 18, a method according to claim 17, wherein

said core substrate is made of one of a glass epoxy resin, an FR4 resin, an FR5 resin and a BT resin;

each of said lower interlayer resin insulating layers contains at least one of an epoxy resin, a phenol resin, a polyimide resin, a polyphenylene resin, a polyolefin resin and a fluorocarbon resin; and

said oxidizer contains one of a chromic acid and permanganate.

According to claim 18, the core substrate is made of one of a glass epoxy resin, a FR4 resin, a FR5 resin and a BT resin. Each of the lower interlayer resin insulating layers contains at least one of an epoxy resin, a phenol resin, a polyimide resin, a polyphenylene resin, a polyolefin resin and a fluorocarbon resin. The oxidizer contains one of a chromic acid and permanganate. Due to this, it is possible to simultaneously perform the de-smear process for the penetrating holes for forming the lower interlayer resin insulating layers on the core substrate and the roughing process for the lower interlayer resin insulating layers.

In order to achieve the above problems, according to claim 21, a method of manufacturing a multi-layer printed circuit board comprising at least the following steps (a) to (d):

(a) forming through holes in a core substrate;

(b) forming rough layers on said through holes, respectively;

(c) polishing and flattening surfaces of lands of said through holes; and

(d) filling resin filler in said through holes and forming resin layers.

According to claim 21, after forming the rough layers on the through holes, respectively, the surfaces of the lands of the through holes are polished and flattened. By doing so, it is possible to prevent the resin filler from flowing out along the rough layers (anchors) formed on the lands of the through holes when filling the resin filler in the through holes. Thus, it is possible to smoothly form the filler in the through holes and to enhance the reliability of wirings formed above the through holes.

In claim 22, a method according to claim 21, wherein said rough layers are copper oxide layers.

In claim 23, a method according to claim 21, wherein said rough layers are formed by etching.

In claim 24, a method according to claim 21, wherein said rough layers are needle alloy layers made of copper-nickel-phosphorous.

According to claims 22, 23 and 24, the rough layer formed on each through hole is preferably formed by one of the formation of a copper oxide layer by a blackening-reduction process, the formation of a needle alloy layer consisting of copper-nickel-phosphorous and by etching. By doing so, it is possible to enhance the adhesiveness between the conductor layers on the inner walls of the through holes and the resin filler.

In claim 25, a method according to claims 21, wherein said resin filler is one selected from a group consisting of a mixture of an epoxy resin and organic filler, a mixture of an epoxy resin and inorganic filler and a mixture of an epoxy resin and inorganic fiber.

According to claim 25, the resin filler to be employed is preferably one selected from a group consisting of a mixture of an epoxy resin and organic filler, a mixture of an epoxy resin and inorganic filler and a mixture of an epoxy resin and inorganic filler. By doing so, it is possible to adjust the coefficients of thermal expansion between the resin filler and the core substrate.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagram showing a process for manufacturing a multi-layer printed circuit board according to the first embodiment of the present invention;

FIG. 2 is a diagram showing a process for manufacturing the multi-layer printed circuit board according to the first embodiment;

FIG. 3 is a diagram showing a process for manufacturing the multi-layer printed circuit board according to the first embodiment;

FIG. 4 is a diagram showing a process for manufacturing the multi-layer printed circuit board according to the first embodiment;

FIG. 5 is a diagram showing a process for manufacturing the multi-layer printed circuit board according to the first embodiment;

FIG. 6 is a cross-sectional view of the multi-layer printed circuit board according to the first embodiment;

FIG. 7 is a table showing the evaluation results of the first embodiment and Comparison;

FIG. 8 is a diagram showing a process for manufacturing a multi-layer printed circuit board according to the second embodiment of the present invention;

FIG. 9 is a diagram showing a process for manufacturing the multi-layer printed circuit board according to the second embodiment;

FIG. 10 is a diagram showing a process for manufacturing the multi-layer printed circuit board according to the second embodiment;

FIG. 11 is a diagram showing a process for manufacturing the multi-layer printed circuit board according to the second embodiment;

FIG. 12 is a diagram showing a process for manufacturing the multi-layer printed circuit board according to the second embodiment;

FIG. 13 is a cross-sectional view of the printed circuit board according to the second embodiment;

FIG. 14 is a diagram showing a process for manufacturing a multi-layer printed circuit board according to the first modification of the second embodiment;

FIG. 15 is a diagram showing a process for manufacturing the multi-layer printed circuit board according to the first modification of the second embodiment;

FIG. 16 is a diagram showing a process for manufacturing the multi-layer printed circuit board according to the first modification of the second embodiment;

FIG. 17 is a diagram showing a process for manufacturing the multi-layer printed circuit board according to the first modification of the second embodiment;

FIG. 18 is a diagram showing a process for manufacturing the multi-layer printed circuit board according to the first modification of the second embodiment;

FIG. 19 is a cross-sectional view of the multi-layer printed circuit board according to the first modification of the second embodiment;

FIG. 20 is a cross-sectional view of the multi-layer printed circuit board according to the second modification of the second embodiment;

FIG. 21 is a table showing the estimation result of the embodiments of the present invention and Comparisons; and

FIG. 22 is a cross-sectional view of a conventional multi-layer printed circuit board.

BEST MODE FOR CARRYING OUT THE INVENTION

First Embodiment

The embodiments of the present invention will be described hereinafter with reference to the accompanying drawings.

First, the constitution of a multi-layer printed circuit board according to the first embodiment of the present invention will be described with reference to FIG. 6 showing a longitudinal sectional view.

As shown in FIG. 6, a multi-layer printed circuit board 10 has a core substrate 30 having right and reverse sides on which buildup wiring layers 80U and 80D are formed, respectively. Each of the buildup wiring layers 80U and 80D consists of a lower interlayer resin insulating layer 50 in which via holes 46 are formed, an upper interlayer resin insulating layer 60 in which upper via holes 66 are formed, and a solder resist layer 70 formed on the upper interlayer resin insulating layer 60. A solder bump (external connection terminal) 76 for connecting the board 10 to an IC chip (not shown) is formed on each of the upper via holes 66 through the opening portion 71 of the solder resist 70. A conductive connection pin (external connection terminal) 78 for connecting the circuit board 10 to a daughter board (not shown) is connected to each of the lower via holes 66.

In the first embodiment, through holes 36 connecting the buildup wiring layers 80U and 80D to each other are formed to penetrate a core substrate 30 and the lower interlayer resin insulating layers 50. Resin filler 54 is filled in the through holes 36 and plated covers 58 are provided onto the opening portions of the holes 36. Likewise, resin filler 54 is filled in the via holes 46 formed in the lower interlayer resin insulating layer 50 and plated covers 58 are provided onto the opening portions of the via holes 46.

In the first embodiment, the through holes 36 are formed to penetrate the core substrate 30 and the lower interlayer resin insulating layers 50 and the via holes 66 are formed right on the through holes 36, respectively. Due to this, each through hole 36 and each via hole 66 are arranged linearly to thereby make it possible to shorten wiring length and to accelerate signal transmission speed. Further, since the through holes 36 are directly connected to the via holes 66 connected to the external connection terminals (solder bumps 76, conductive connection pins 78), excellent connection reliability is obtained. In the first embodiment, as will be described later, the filler 54 filled in the through holes 36 is flattened by polishing and then the plated covers (conductive layers) 58 covering the filler 54 are arranged and the via holes 66 are formed thereon. Due to this, the surfaces of the through holes 36 have high flatness and reliability in the connection between the through holes 36 and the corresponding via holes 66 is excellent.

Furthermore, in case of the multi-layer printed circuit board in the first embodiment, the through holes 36 and the lower via holes 46 are filled with the same resin filler 54 and the resin filler 54 is simultaneously polished and flattened as will be described later. Thus, the multi-layer printed circuit board can be manufactured at low cost and the strength of the interiors of the through holes and that of the interiors of the via holes can be kept uniform, so that the reliability of the multi-layer printed circuit board can be enhanced. Also, as will be described later, the filler 54 filled in the via holes 47 is flattened by polishing and then the plated covers (conductive layers) 58 covering the filler 54 are arranged and the upper via holes 66 are formed thereon. Due to this, the surfaces of the lower via holes 46 have high flatness and reliability in the connection between the lower via holes 46 and the upper via holes 66 is excellent.

Moreover, as will be described later, in case of the multi-layer printed circuit board in the first embodiment, a de-smear process for penetrating holes 35 which become the through holes 36 and a roughing process for the surface of the lower interlayer resin insulating layer 40 are performed simultaneously using an oxidizer, so that the number of manufacturing steps can be reduced and the multi-layer printed circuit board can be manufactured at low cost.

Next, description will be given to a method of manufacturing the multi-layer printed circuit board with reference to FIGS. 1 to 5. (1) A copper-clad laminated plate 30A having copper foils 32 each having a thickness of 18 .mu.m and laminated on both sides of a substrate 30 having a thickness of 0.8 mm and made of a glass epoxy resin, FR4, FR5 or BT (Bismaleimide-Triazine) resin, is employed as a starting material (FIG. 1(A)). First, this copper-clad laminated plate is etched in a pattern fashion, thereby forming inner-layer copper patterns 34 on the both sides of the substrate (FIG. 1(B)). (2) After washing the substrate 30 on which the inner-layer copper patterns 34 are formed, an etching solution containing a cupric complex and an organic acid is reacted under oxygen coexisting conditions such as spraying or bubbling. The copper conductor of a conductor circuit is dissolved to form voids. Through these processes, a rough layer 38 is provided on the surface of each inner-layer copper pattern 34 (FIG. 1(c)).

Alternatively, the rough layer may be provided by an oxidization-reduction process or by employing an electroless plated alloy. The rough layer thus formed has desirably a thickness in a range of 0.1 to 5 .mu.m. In such a range, the separation between the conductor circuit and the interlayer resin insulating layer less occurs.

The cupric complex is preferably a cupric complex of azoles. The cupric complex of azoles functions as an oxidizer for oxidizing metallic copper or the like. Azoles preferably involve diazole, triazole and tetrazole. Particularly, imidazole, 2-methylimidazole, 2-ethylimidazole, 2-ethyl-4-methylimidazole, 2-phenylimidazole, 2-undecylimidazole and the like are preferable. The quantity of added cupric complex of azoles is preferably 1 to 15 wt %. This is because the cupric complex of such a quantity is excellent in solubility and stability.

Further, to dissolve the copper oxide, an organic acid is mixed with the cupric complex of azoles. To be specific, the organic acid is preferably at least one selected from a group consisting of formic acid, acetic acid, propionic acid, butyric acid, valeric acid, caproic acid, acrylic acid, crotonic acid, oxalic acid, malonic acid, succinic acid, glutaric acid, maleic acid, benzoic acid, glycolic acid, lactic acid, malic acid and sulfamic acid. An organic acid content is preferably 0.1 to 30 wt %. With this content, it is possible to maintain the solubility of the oxidized copper and to secure stabile solubility.

The generated cuprous complex is dissolved by the acid, combined with oxygen into a cupric complex which contributes again to the oxidization of copper.

Furthermore, to assist in dissolving copper and oxidizing azoles, halogen ions, such as fluorine ions, chlorine ions and bromine ions, may be added to the etching solution. The present invention can supply halogen ions by adding hydrochloric acid, sodium chloride or the like. The quantity of halogen ions is preferably 0.01 to 20 wt %. Halogen ions of such a quantity ensures excellent adhesiveness between the generated rough surface and the interlayer resin insulating layer.

The cupric complex of azoles and the organic acid (or halogen ions according to necessity) are dissolved in water to thereby adjust the etching solution. Further, a commercially available etching solution, e.g., product name "MEC etch BOND" manufactured by Mec Co., Ltd., can be employed to form a rough surface according to the present invention. (3) A resin film 50 .alpha. which becomes a lower interlayer resin insulating layer is bonded on each surface of the substrate 30 by vacuum crimp lamination at a pressure of 5 kgf/cm.sup.2 while raising temperature to 50 to 150.degree. C. (FIG. 1(D)).

The resin film contains refractory resin, soluble particles, a curing agent and other components. The materials will now be described.

The resin film for use in the resin insulating layer in the manufacturing method according to the present invention has a structure that particles soluble in acid or an oxidizer (hereinafter called "soluble particles") are dispersed in resin which is refractory with respect to acid or an oxidizer (hereinafter called "refractory resin").

The expressions "refractory" and "soluble" will now be described. When materials are immersed in solution composed of the same acid or the same oxidizers for the same time, a material of a type which is dissolved at a relatively high dissolving rate is called a "soluble" material for convenience. A material of a type which is dissolved at a relatively slow dissolving rate is called a "refractory material" for convenience.

The soluble particles are exemplified by resin particles which are soluble in acid or an oxidizer (hereinafter called "soluble resin particles"), inorganic particles which are soluble in acid or an oxidizer (hereinafter called "inorganic soluble particles") and metal particles which are soluble in acid or an oxidizer (hereinafter called "soluble metal particles"). The foregoing soluble particles may be employed solely or two or more particles may be employed.

The shape of each of the soluble particles is not limited. The shape may be a spherical shape or a pulverized shape. It is preferable that the particles have a uniform shape. The reason for this lies in that a rough surface having uniformly rough pits and projections can be formed.

It is preferable that the mean particle size of the soluble particles is 0.1 .mu.m to 10 .mu.m. When the particles have the diameters satisfying the foregoing range, particles having two or more particle sizes may be employed. That is, soluble particles having a mean particle size of 0.1 .mu.m to 0.5 .mu.m and soluble particles having a mean particle size of 1 .mu.m to 3 .mu.mm may be mixed. Thus, a more complicated rough surface can be formed. Moreover, the adhesiveness with the conductor circuit can be improved. In the present invention, the particle size of the soluble particles is the length of a longest portion of each of the soluble particles.

The soluble resin particles may be particles constituted by thermosetting resin or thermoplastic resin. When the particles are immersed in solution composed of acid or an oxidizer, the particles must exhibit dissolving rate higher than that of the foregoing refractory resin.

Specifically, the soluble resin particles are exemplified by particles constituted by epoxy resin, phenol resin, polyimide resin, polyphenylene resin, polyolefin resin or fluorine resin. The foregoing material may be employed solely or two or more materials may be mixed.

The soluble resin particles may be resin particles constituted by rubber. Rubber above is exemplified by polybutadiene rubber, a variety of denatured polybutadiene rubber, such as denatured epoxy rubber, denatured urethane rubber or denatured (metha) acrylonitrile rubber, and (metha) acrylonitrile butadiene rubber containing a carboxylic group. When the foregoing rubber material is employed, the soluble resin particles can easily be dissolved in acid or an oxidizer. That is, when the soluble resin particles are dissolved with acid, dissolution is permitted with acid except for strong acid. When the soluble resin particles are dissolved, dissolution is permitted with permanganate which has a relatively weak oxidizing power. When chromic acid is employed, dissolution is permitted even at a low concentration. Therefore, retention of the acid or the oxidizer on the surface of the resin can be prevented. When a catalyst, such as palladium chloride, is supplied after the rough surface has been formed as described later, inhibition of supply of the catalyst and oxidation of the catalyst can be prevented.

The inorganic soluble particles are exemplified by particles made of at least a material selected from a group consisting of an aluminum compound, a calcium compound, a potassium compound, a magnesium compound and a silicon compound.

The aluminum compound is exemplified by alumina and aluminum hydroxide. The calcium compound is exemplified by calcium carbonate and calcium hydroxide. The potassium compound is exemplified by potassium carbonate. The magnesium compound is exemplified by magnesia, dolomite and basic magnesium carbonate. The silicon compound is exemplified by silica and zeolite. The foregoing material may be employed solely or two or more materials may be mixed.

The soluble metal particles are exemplified by particles constituted by at least one material selected from a group consisting of copper, nickel, iron, zinc, lead, gold, silver, aluminum, magnesium, potassium and silicon. The soluble metal particles may have surfaces coated with resin or the like in order to maintain an insulating characteristic.

When two or more types of the soluble particles are mixed, it is preferable that the combination of the two types of soluble particles is combination of resin particles and inorganic particles. Since each of the particles has low conductivity, an insulating characteristic with the resin film can be maintained. Moreover, the thermal expansion can easily be adjusted with the refractory resin. Thus, occurrence of a crack of the interlayer resin insulating layer constituted by the resin film can be prevented. Thus, separation between the interlayer resin insulating layer and the conductor circuit can be prevented.

The refractory resin is not limited when the resin is able to maintain the shape of the rough surface when the rough surface is formed on the interlayer resin insulating layer by using acid or oxidizer. The refractory resin is exemplified by thermosetting resin, thermoplastic resin and their composite material. As an alternative to this, the foregoing photosensitive resin of a type having photosensitive characteristic imparted thereto may be employed. When the photosensitive resin is employed, exposure and development processes of the interlayer resin insulating layers can be performed to form the openings for the via holes.

In particular, it is preferable that the resin containing thermosetting resin is employed. In the foregoing case, the shape of the rough surface can be maintained against plating solution and when a variety of heating processes are performed.

The refractory resin is exemplified by epoxy resin, phenol resin, phenoxy resin, polyimide resin, polyphenylene resin, polyolefin resin and fluorine resin. The foregoing material may be employed solely or two or more types of the materials may be mixed.

It is preferable that epoxy resin having two or more epoxy groups in one molecule thereof is employed. The reason for this lies in that the foregoing rough surface can be formed. Moreover, excellent heat resistance and the like can be obtained. Thus, concentration of stress onto the metal layer can be prevented even under a heat cycle condition. Thus, occurrence of separation of the metal layer can be prevented.

The epoxy resin is exemplified by cresol novolac epoxy resin, bisphenol-A epoxy resin, bisphenol-F epoxy resin, phenol novolac epoxy resin, alkylphenol novolac epoxy resin, biphenol-F epoxy resin, naphthalene epoxy resin, dicyclopentadiene epoxy resin, an epoxy material constituted by a condensation material of phenol and an aromatic aldehyde having a phenol hydroxyl group, triglycidyl isocyanurate and alicyclic epoxy resin. The foregoing material may be employed solely or two or more material may be mixed. Thus, excellent heat resistance can be realized.

It is preferable that the soluble particles in the resin film according to the present invention are substantially uniformly dispersed in the refractory resin. The reason for this lies in that a rough surface having uniform pits and projections can be formed. When via holes and through holes are formed in the resin film, adhesiveness with the metal layer of the conductor circuit can be maintained. As an alternative to this, a resin film containing soluble particles in only the surface on which the rough surface is formed may be employed. Thus, the portions of the resin film except for the surface is not exposed to acid or the oxidizer. Therefore, the insulating characteristic between conductor circuits through the interlayer resin insulating layer can reliably be maintained.

It is preferable that the amount of the soluble particles which are dispersed in the refractory resin is 3 wt % to 40 wt % with respect to the resin film. When the amount of mixture of the soluble particles is lower than 3 wt %, the rough surface having required pits and projections cannot be formed. When the amount is higher than 40 wt %, deep portions of the resin film are undesirably dissolved when the soluble particles are dissolved by using acid or the oxidizer. Thus, the insulating characteristic between the conductor circuits through the interlayer resin insulating layer constituted by the resin film cannot be maintained. Thus, short circuit is sometimes is caused to occur.

It is preferable that the resin film contains a curing agent and other components as well as the refractory resin.

The curing agent is exemplified by an imidazole curing agent, an amine curing agent, a guanidine curing agent, an epoxy adduct of each of the foregoing curing agents, a microcapsule of each of the foregoing curing agents and an organic phosphine compound, such as triphenylphosphine or tetraphenyl phosphonium tetraphenyl borate.

It is preferable that the content of the curing agent is 0.05 wt % to 10 wt % with respect to the resin film. When the content is lower than 0.05 wt %, the resin film cannot sufficiently be hardened. Thus, introduction of acid and the oxidizer into the resin film occurs greatly. In the foregoing case, the insulating characteristic of the resin film sometimes deteriorates. When the content is higher than 10 wt %, an excessively large quantity of the curing agent component sometimes denatures the composition of the resin. In the foregoing case, the reliability sometimes deteriorates.

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